Photolithography pattern stitching method and stitching error detection method
By dividing the chip layout into a splicing layout and reserving overlapping areas and splicing lines in the photomask splicing layout, the problem of missing circuit patterns in large-size chip photolithography is solved, achieving efficient and accurate photolithography pattern splicing and inspection, and ensuring product quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOI MICRO CO LTD
- Filing Date
- 2022-12-30
- Publication Date
- 2026-07-14
AI Technical Summary
When existing lithography machines etch large-size chips in a single process, the resulting circuit patterns are often missing or incomplete, affecting product quality.
The chip layout is divided into several spliced layouts, and exposure overlap areas and splicing lines are reserved in the photomask spliced layouts. Photolithography etching of the chip is achieved by overlapping the photomask spliced layouts. Combined with splicing error detection methods, the photomask layout is corrected to ensure the integrity of the circuit pattern.
It improves the accuracy and efficiency of photolithography pattern splicing, avoids errors in the splicing position of circuit patterns, and ensures product quality.
Smart Images
Figure CN116165849B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, specifically to a method for splicing photolithographic patterns and a method for detecting splicing errors. Background Technology
[0002] With the rapid development of semiconductor technology, the integration and complexity of chip systems have increased, the number of patterns in chips has increased, and the chip area has also increased. For example, for the largest image sensor chip, the size of the photomask used for etching the largest chip is four times the size of the actual chip. The maximum size of a single exposure of an image sensor chip is 26 mm * 33 mm, which seriously exceeds the image field of the photolithography machine. Furthermore, in the chip manufacturing process, the traditional chip etching method is one-time etching, that is, etching the corresponding circuit in the chip through a single photolithography process. Although this photolithography process is simple, due to the large size, the circuit patterns in the chip are missing or incomplete, which affects the smooth progress of the processing steps and the final product quality. Summary of the Invention
[0003] To address the problem that existing technologies, when using photolithography machines to etch circuit patterns on large-size chips, often result in missing or incomplete circuit patterns in a single etching process, thus reducing product quality, this invention provides a photolithography pattern splicing method and a splicing error detection method. This method can meet the photolithography requirements of large-size chip circuit patterns, prevent missing circuit patterns, ensure pattern integrity, and guarantee product quality.
[0004] To achieve the above objectives, the present invention adopts the following technical solution:
[0005] A photolithography pattern stitching method is used to perform photolithographic etching on chips larger than the maximum image field of a photolithography machine to obtain circuit patterns. The method is characterized by the following steps: S1, dividing the chip layout into at least two to obtain several chip stitching layouts; assuming that the maximum length of the chip layout is greater than length a and the maximum width is greater than width b, then the maximum length of the chip stitching layout is less than length a and the maximum width is less than width b.
[0006] S2. Design a photomask layout based on the chip layout, divide the photomask layout to obtain several photomask splicing layouts, the number of photomask splicing layouts being the same as the number of chip splicing layouts;
[0007] S3. Expose the chip sequentially using different photomask splicing patterns to obtain the circuit pattern;
[0008] In step S2, when dividing the photomask splicing pattern, at least one exposure overlap area is reserved in each of the divided photomask splicing patterns, and a splicing line is provided between each exposure overlap area and the light-shielding strip in the corresponding photomask splicing pattern.
[0009] In step S3, when the chip is sequentially exposed and etched using different photomask mosaic patterns, the mosaic lines of different photomask mosaic patterns used for exposing the same circuit pattern overlap to achieve the mosaicking of the photomask mosaic patterns; the chip is then exposed and etched using the mosaicked photomask mosaic pattern.
[0010] Its further feature is that,
[0011] In two photomask splicing layouts used for exposing the same circuit pattern, the splicing line in one photomask splicing layout is aligned and overlaps with the splicing line in the other photomask splicing layout to achieve splicing;
[0012] The length a is 33mm, and the width b is 26mm;
[0013] The shape of the circuit pattern obtained by exposure includes, but is not limited to, single strip, T-shape, first Z-shape, first combined shape, second Z-shape, second combined shape, and third combined shape. The shape of the photomask splicing pattern is consistent with and corresponds one-to-one with the shape of the circuit pattern to be etched. The first combined shape is a combined structure with a groove in the middle of the single strip circuit pattern. The second combined shape is a combined structure of a single strip and a double strip at one end of the single strip. The third combined shape is a combined structure of two groups of multiple strips connected by inclined connecting lines.
[0014] A splicing error detection method is used to detect errors in circuit patterns obtained by the above-described photolithographic pattern splicing method, wherein the error is the difference in spacing between two adjacent circuit patterns at the splicing position exceeding a standard threshold. The method is characterized by comprising the following steps:
[0015] A1. Provide several test patterns; the test patterns are circuit patterns of chips obtained by the above-mentioned photolithography pattern splicing method; divide the test patterns into a verification set and a test set;
[0016] A2. Collect test graphic data from the verification set. The test graphic data includes the first dimension data of the circuit graphic and the first shape of the circuit graphic, and establish corresponding dimension databases and shape databases respectively. The dimension database and the shape database correspond one-to-one.
[0017] A3. Collect the first spacing error caused by splicing exposure, and establish an error database. The error database corresponds one-to-one with the size database and the shape database.
[0018] A4. Establish a splicing effect judgment method based on the size database, shape database, and error database; the splicing effect judgment method is used to determine whether the first spacing error of the test pattern in the test set meets the standard. If yes, it indicates that the splicing exposure effect meets the requirements; if no, the photomask pattern is corrected.
[0019] Its further feature is that,
[0020] In step A4, the method for judging the splicing effect is as follows: A41, measure the second dimension data of the circuit pattern after splicing exposure, the second spacing error of adjacent circuit patterns, and obtain the second shape of the circuit pattern;
[0021] A42. Search the size database and shape database for data that are the same as the second size data and the second shape, and obtain the corresponding first spacing error in the error database based on the search results;
[0022] A43. Compare the second spacing error with the first spacing error. If they are the same, it indicates that the splicing exposure effect meets the requirements. Otherwise, it indicates that the splicing exposure effect does not meet the requirements, and the photomask pattern is corrected.
[0023] Furthermore, the method for correcting the photomask layout is as follows: an OPC correction model is established based on the size database, shape database, and error database; the photomask layout is corrected using the OPC correction model to obtain a corrected photomask; and the circuit pattern that does not meet the requirements is re-exposed using the corrected photomask until the error of the circuit pattern meets the standard.
[0024] The above-described structure of this invention achieves the following beneficial effects: Since each of the segmented photomask splicing layouts reserves at least one exposure overlap area, and a splicing line is provided between each exposure overlap area and the corresponding light-shielding strip, the photomask splicing layouts are spliced by aligning the splicing lines. The splicing lines not only simplify and expedite the splicing operation, improving efficiency, but also facilitate accurate alignment during splicing, avoiding poor exposure results due to inaccurate alignment and reducing errors at the splicing positions in the circuit pattern. Furthermore, the exposure overlap area ensures that the areas used for exposure in the two photomask splicing layouts are completely connected, preventing the circuit pattern to be spliced from being divided or incompletely connected due to loose connections during splicing exposure, thus improving the splicing effect.
[0025] This application also provides a splicing error detection method for judging the splicing effect of the photolithography pattern splicing method of this application. This splicing error detection method establishes a size database, a shape database, and an error database based on the collected size data, shape, and first spacing error of a test set. Based on the second size data, second shape data, and second spacing error of a certain circuit pattern in the test set, it searches the size database, shape database, and error database, and compares the second spacing error with the corresponding first spacing error in the error database. Based on the comparison result, it determines whether the second spacing error of the circuit pattern in the test set meets the standard threshold, i.e., whether the splicing effect of the circuit pattern in the test set meets the requirements. This achieves the detection of the splicing effect of the circuit pattern. The detection operation is simple and fast. This splicing error detection method establishes an effective pattern splicing technical specification, breaks through the image field limitation of the photolithography machine, and meets the photolithography etching requirements of circuit patterns in large-size chips. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the photomask layout.
[0027] Figure 2 These are schematic diagrams of the structure before and after the photomask layout is divided.
[0028] Figure 3 This is a schematic diagram of the circuit pattern before segmentation and the chip splicing layout after splicing.
[0029] Figure 4 These are schematic diagrams of the circuit diagram before and after segmentation.
[0030] Figure 5 This is a schematic diagram of the structure after the photomask splicing layout is divided and after the photomask splicing layout is spliced according to the present invention;
[0031] Figure 6 This is a schematic diagram of the structure after splicing different photomask layouts of the present invention;
[0032] Figure 7 This is a schematic diagram of the strip circuit graphic structure after splicing according to the present invention;
[0033] Figure 8 This is a schematic diagram of the structure of the T-shaped circuit pattern after splicing according to the present invention;
[0034] Figure 9 This is a schematic diagram of the structure of the two side end faces of the groove in the first combined pattern after splicing according to the present invention;
[0035] Figure 10 This is a schematic diagram showing the distance relationship between the end of the circuit pattern corresponding to the non-exposure area and the splicing line in a single horizontal strip circuit pattern in the third combined pattern of the present invention.
[0036] Figure 11 This is a schematic diagram of the structure of the strip photomask splicing layout, the first Z-shaped photomask splicing layout or the second Z-shaped photomask splicing layout, the unetched circuit pattern, and another strip photomask splicing layout of the present invention;
[0037] Figure 12 This is a flowchart of the photolithographic pattern splicing method of the present invention;
[0038] Figure 13 This is a flowchart of the splicing error detection method of the present invention. Detailed Implementation
[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It should be noted that the terms "comprising" and "having" or units in the specification, claims and the above-mentioned drawings of the present invention are not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or devices.
[0040] See Figure 12 A method for stitching photolithography patterns and a method for detecting stitching errors are used to perform photolithographic etching on chips with a field larger than the maximum image field of the photolithography machine to obtain circuit patterns. The method includes the following steps: S1, placing the chip substrate... Figure 1 Divide into at least two parts to obtain several chip splicing boards. Figure 2 If the maximum length of the chip layout in the x-direction is greater than length 'a', and the maximum width in the y-direction is greater than width 'b', then the chip splicing board... Figure 2 The maximum length of each component is less than length 'a', and the maximum width of each component is less than width 'b'. In this embodiment, length 'a' is 33mm and width 'b' is 26mm, meaning the chip's dimensions are greater than 33mm * 26mm. (See...) Figure 1 In this embodiment, the chip board Figure 1 See the structural diagram of the middle splicing line 3 (i.e., the cutting line). Figure 2 , Figure 2 The chip version is given in 2a. Figure 1 The position of the cutting line Figure 2 2b indicates that the chip board is cut using a cutting line. Figure 1 It is divided into two parts, each with a length of 20mm. The chip layout has a length of 40mm in the x-direction and 33mm in the y-direction.
[0041] S2, according to the chip board Figure 1 Design light mask version Figure 4 For the photomask Figure 4 The image is segmented to obtain several photomask splicing panels. Figure 5 Photomask splicing version Figure 5 Quantity and chip splicing board Figure 2 The quantities are consistent; in this embodiment, the chip board... Figure 1 Divide the chip into 2, 3, ..., n, where n is an integer. Let each chip be a separate piece. Figure 2 The maximum length in the x-direction does not exceed 26mm, ensuring that each chip splicing board after cutting is... Figure 2 The maximum width in the y-direction does not exceed 33mm. (Photomask) Figure 4 The structural diagram of the middle splicing line 3 (i.e., the cutting line) is shown below. Figure 3 , Figure 3 3a in the image provides the photomask version. Figure 4 The position of the cutting line Figure 3 3b indicates that the photomask is cut along the dicing lines. Figure 4 Divided into two parts. Photomask version. Figure 4 See the structural diagram before segmentation. Figure 4 4a in the image, the spliced version of the divided photomask. Figure 5 See the structural diagram Figure 4 4b in the middle.
[0042] In this step, on the photomask splicing plate Figure 5 During segmentation, in each of the segmented photomask splicing panels Figure 5 At least one exposure overlap area is reserved in the middle, see 51. Figure 5 In 5a, a splicing line 3 is provided between each exposure overlap area 51 and the corresponding light-shielding strip 52. In this embodiment, the photomask used for exposing the same circuit pattern is... Figure 4 Divided into two, two photomask splicing panels Figure 5 In the mirror setup, the end of the light-shielding strip 52 in one photomask splicing pattern is connected to the light-shielding strip of the other photomask splicing pattern in sequence through the overlapping exposure area 51 contained therein, the splicing line 3, the overlapping exposure area contained in the other photomask splicing pattern, and the other photomask splicing pattern.
[0043] S3. Use different photomask splicing plates in sequence. Figure 5 The chip is exposed and etched to obtain circuit pattern 50; in this step, different photomask splicing boards used for exposing the same circuit pattern 50 are used during exposure and etching. Figure 5 The splicing lines overlap 3 times to achieve a photomask splicing panel. Figure 5 The splicing, see Figure 5 5b in the middle.
[0044] See Figure 6 The shapes of the circuit patterns obtained by exposure include single stripes (reference). Figure 6 6a), T-type (reference) Figure 6 6b), First Z-shape (reference) Figure 6 6c), First combination form (reference) Figure 6 (Middle 6d), Second Z-shape (reference) Figure 6 6e), second combination form (reference) Figure 6 6f), the third combination form (reference) Figure 6 (6g) The shape of the photomask mosaic pattern is consistent with and corresponds one-to-one with the shape of the circuit pattern to be etched. Among them, the first combination shape is a combination structure with a groove in the middle of a single-strip circuit pattern. See Figure 6 In section 6d, the second combined shape is a combination structure of a single strip and a double strip located at one end of the single strip, see... Figure 6 In section 6f, the third combination is a combination structure consisting of two groups of multiple strips connected by an inclined connecting line, see... Figure 6 6g.
[0045] When a chip is exposed using a photolithography machine, the photoresist coated on the chip surface is illuminated, causing a photoreaction. The illuminated and unilluminated areas thus have different solubility. However, when light propagates in the photoresist on the chip surface, it is easily affected by the surface flatness, resulting in diffraction. For the splicing area, the height of the exposed and unexposed areas is different. Therefore, when the chip is exposed sequentially using a photomask splicing pattern, it is also easily affected by light diffraction, resulting in a large error at the splicing position of the final circuit pattern.
[0046] To address the issue that significant errors can easily occur at the splicing positions of circuit patterns obtained through splicing exposure methods, leading to products failing to meet standard requirements and potentially affecting circuit performance stability, this application also provides a splicing error detection method, see [link to relevant documentation]. Figure 13 This method is used to detect errors in circuit patterns obtained using the above-mentioned photolithographic pattern splicing method. The error is the difference between the spacing between two adjacent circuit patterns at the splicing position exceeding a standard threshold. The method includes the following steps:
[0047] A1. Provide several test patterns; the test patterns are the circuit patterns of the chip obtained by the above photolithography pattern splicing method; divide the test patterns into a verification set and a test set;
[0048] A2. Collect test graphic data from the verification set. The test graphic data includes the first dimension data of the circuit graphic and the first shape of the circuit graphic, and establish corresponding dimension databases and shape databases respectively; the dimension database and the shape database correspond one-to-one.
[0049] The first dimension data includes the minimum width of the light-shielding strip in the photomask layout corresponding to the circuit pattern (see...). Figure 11 W.1), the minimum width of the exposure overlap area in a single photomask mosaic pattern (see W.1). Figure 11 W.2), the minimum spacing between two adjacent photomask mosaic patterns (see W.2). Figure 11S.1), the minimum vertical distance from the vertical connecting line to the splicing line in the first or second Z-shaped photomask splicing layout (see S.1). Figure 11 S.2), the minimum distance from the splicing line to the via (i.e., VIA) that does not require etching of the circuit pattern (see S.2). Figure 11 S.3), the minimum length from the splicing line to the beginning of the light-shielding strip in a single photomask splicing layout (see S.3). Figure 11 OH.1).
[0050] A3. Collect the first spacing error caused by splicing exposure, establish an error database, and the error database corresponds one-to-one with the size database and shape database;
[0051] A4. Based on the size database, shape database, and error database, establish a splicing effect judgment method. The splicing effect judgment method is used to determine whether the corresponding first spacing error of the test pattern in the test set meets the standard. If yes, it indicates that the splicing exposure effect meets the requirements; if not, the photomask layout is corrected. In this step, the specific steps of the splicing effect judgment method are as follows: A41. Use EDA tools to collect the second size data of the circuit pattern after splicing exposure, the second spacing error of adjacent circuit patterns, and obtain the second shape of the circuit pattern.
[0052] A42. Search for data in the size database and shape database that are the same as the second size data and the second shape data. Based on the search results, obtain the corresponding first spacing error in the error database.
[0053] A43. Compare the second spacing error with the first spacing error. If they are the same, it means that the splicing exposure effect meets the requirements. Otherwise, it means that the splicing exposure effect does not meet the requirements. Then, the photomask pattern should be corrected.
[0054] The specific method for correcting the photomask layout is as follows: an OPC correction model is established based on the size database, shape database, and error database. The OPC correction model is used to correct the photomask layout to obtain a corrected photomask. The corrected photomask is then used to re-expose circuit patterns that do not meet the requirements until the errors of the circuit patterns meet the standards.
[0055] In this embodiment, taking single-strip circuit patterns, T-shaped circuit patterns, first combined circuit patterns, and third combined circuit patterns as examples, a shape database is established based on the shapes of these circuit patterns, and the size data of these circuit patterns is collected. Specifically, in the single-strip circuit pattern, the width of the circuit pattern corresponding to the non-exposure area ranges from 0.3 micrometers to 1.5 micrometers. In the spliced circuit pattern, the length from the end of the circuit pattern corresponding to the non-exposure area to the splicing line is greater than 1.5 micrometers (i.e., the minimum width of the exposure overlap area in a single photomask splicing layout). The structure of the single-strip circuit pattern is shown below. Figure 7The width of the lines in the dimensional data ranges from 0.36 micrometers to 1.5 micrometers. See Table 1 for detailed width data (unit: micrometers).
[0056] Table 1. Width data of single-strip circuit patterns
[0057] 0.36 0.38 0.40 0.44 0.48 0.52 0.56 0.60 0.80 1.00 1.10 1.20 1.30 1.40 1.50
[0058] The T-shaped circuit pattern includes a horizontal single-strip connecting line and a vertical single-strip connecting line perpendicular to the middle of the horizontal single-strip connecting line. The height of the vertical connecting line ranges from 0.4 micrometers to 1 micrometer, and the width of the vertical single-strip connecting line ranges from 0.36 micrometers to 1.2 micrometers. In the spliced circuit pattern, the length from the end of the circuit pattern in the non-exposed area to the splicing line is greater than 1.5 micrometers. See the T-shaped circuit pattern below. Figure 8 Detailed dimensional data are shown in Table 2.
[0059] Table 2. Height (V Height) and Width (V Width) data of vertical single-strip connecting lines in T-shaped circuit diagrams.
[0060]
[0061] In the first combination of circuit patterns, the width (V Width) of the groove is 0.36 micrometers to 1.2 micrometers, and the inner width of the groove ( Figure 9 The area indicated by "D" is 0.36 micrometers to 1.4 micrometers, and the height of the groove is 2 micrometers; the circuit diagram of the first combination is shown in [reference needed]. Figure 9 Detailed dimensional data are shown in Table 3.
[0062] Table 3 shows the width (V Width) and inner width (Distance) of the recess in the circuit diagram of the first combination shape.
[0063]
[0064] In the third type of circuit pattern, the minimum distance range between the end of the circuit pattern corresponding to the non-exposed area in a single horizontal strip circuit pattern and the splicing line (see...). Figure 10 The dimensions of "D1", "D2", and "D3" range from 0.36 micrometers to 1.40 micrometers. The width of a single horizontal strip circuit pattern ranges from 0.36 micrometers to 1 micrometer. The circuit pattern for the third combination is shown below. Figure 10 Detailed dimensional data are shown in Table 4.
[0065] Table 4 shows the width (V Width) of a single horizontal strip circuit pattern in the third combination circuit pattern, and the minimum distance (Distance, D1, D2, D3) between the end of the circuit pattern corresponding to the non-exposed area in a single horizontal strip circuit pattern and the splicing line.
[0066]
[0067] This invention provides a photolithography pattern stitching method for photolithographic etching of chips larger than the maximum image field of a photolithography machine. In this application, the width, height, length, and other data can be flexibly set according to the actual process node. In this photolithography pattern stitching method, the photomask layout is divided into at least two photomask stitching layouts based on the chip stitching layout. The chip is then exposed sequentially using these photomask stitching layouts. During the exposure process, the stitching lines of different photomask stitching layouts used for exposing the same circuit pattern overlap, thereby achieving the stitching of the photomask stitching layouts and the stitching photolithography of the circuit patterns in the chip. The resulting stitched circuit pattern is then measured, and a first spacing error in the stitched circuit pattern is measured to establish an error database.
[0068] A portion of test patterns are randomly selected as a test set. The chips in the test set are spliced and exposed using the aforementioned photolithography pattern splicing method to obtain a complete test set circuit pattern. Based on the size database, shape database, and error database established using the aforementioned size data and shape, the splicing error detection method of this application is used to judge the error of the test set circuit pattern. Specifically, the second spacing error of the test set circuit pattern is compared with the corresponding first error in the error database. The comparison shows that the second spacing error of the test set circuit pattern obtained by the photolithography pattern splicing method of this application is consistent with the corresponding first error in the error database, indicating that the splicing effect meets the standard requirements.
[0069] The above are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that are directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.
Claims
1. A method for detecting stitching error, used to detect errors in circuit patterns obtained by a photolithographic pattern stitching method, wherein the error is the difference in spacing between two adjacent circuit patterns at the stitching position exceeding a standard threshold, the photolithographic pattern stitching method being used to perform photolithographic etching on a chip larger than the maximum image field of a photolithography machine to obtain circuit patterns, the photolithographic pattern stitching method comprising the following steps: S1. Divide the chip layout into at least two parts to obtain a chip splicing layout; S2. Design a photomask layout based on the chip layout, divide the photomask layout to obtain several photomask splicing layouts, the number of photomask splicing layouts being the same as the number of chip splicing layouts; S3. The chip is exposed and etched using different photomask splicing patterns to obtain the circuit pattern; The splicing error detection method is characterized by the following steps: A1. Provide several test patterns; the test patterns are circuit patterns of chips obtained by the above-mentioned photolithography pattern splicing method; divide the test patterns into a verification set and a test set; A2. Collect test graphic data from the verification set. The test graphic data includes the first dimension data of the circuit graphic and the first shape of the circuit graphic, and establish corresponding dimension databases and shape databases respectively. The dimension database and the shape database correspond one-to-one. A3. Collect the first spacing error caused by splicing exposure, and establish an error database. The error database corresponds one-to-one with the size database and the shape database. A4. Establish a splicing effect judgment method based on the size database, shape database, and error database; the splicing effect judgment method is used to determine whether the first spacing error of the test pattern in the test set meets the standard. If yes, it indicates that the splicing exposure effect meets the requirements; if no, the photomask pattern is corrected.
2. The splicing error detection method according to claim 1, characterized in that, In step S1, let the maximum length of the chip layout be length a and the maximum width be width b. Then the maximum length of the chip splicing layout is less than length a and the maximum width is less than width b. In step S2, when dividing the photomask splicing pattern, at least one exposure overlap area is reserved in each divided photomask splicing pattern, and a splicing line is provided between each exposure overlap area and the light-shielding strip in the corresponding photomask splicing pattern. In step S3, when different photomask patterns are used to expose and etch the chip, the splicing lines of different photomask patterns used for exposing the same circuit pattern overlap to achieve the splicing of the photomask patterns. The spliced photomask pattern is then used to expose and etch the chip.
3. The splicing error detection method according to claim 1, characterized in that, In two photomask splicing layouts used for exposing the same circuit pattern, the splicing lines in one photomask splicing layout are aligned and overlapped with the splicing lines in the other photomask splicing layout to achieve splicing.
4. The splicing error detection method according to claim 2, characterized in that, The length a is 33mm and the width b is 26mm.
5. The splicing error detection method according to claim 4, characterized in that, The shape of the circuit pattern obtained by exposure includes, but is not limited to, single strip, T-shape, first Z-shape, first combined shape, second Z-shape, second combined shape, and third combined shape. The shape of the photomask splicing pattern is consistent with and corresponds one-to-one with the shape of the circuit pattern to be etched. The first combined shape is a combined structure with a groove in the middle of the single strip circuit pattern. The second combined shape is a combined structure of a single strip and a double strip at one end of the single strip. The third combined shape is a combined structure of two groups of multiple strips connected by inclined connecting lines.
6. The splicing error detection method according to claim 5, characterized in that, In step A4, the method for judging the splicing effect is as follows: A41, measure the second dimension data of the circuit pattern after splicing exposure, the second spacing error of adjacent circuit patterns, and obtain the second shape of the circuit pattern; A42. Search the size database and shape database for data that are the same as the second size data and the second shape, and obtain the corresponding first spacing error in the error database based on the search results; A43. Compare the second spacing error with the first spacing error. If they are the same, it indicates that the splicing exposure effect meets the requirements. Otherwise, it indicates that the splicing exposure effect does not meet the requirements, and the photomask pattern is corrected.
7. The splicing error detection method according to claim 6, characterized in that, In step A2, the first size data includes the minimum width of the light-shielding strip in the chip layout corresponding to the circuit pattern, the minimum width of the exposure overlap area in the single chip splicing layout, the minimum spacing between two adjacent chip splicing layouts, the minimum vertical distance from the vertical connecting line to the splicing line in the first Z-shaped photomask splicing layout or the second Z-shaped photomask splicing layout, the minimum distance from the splicing line to the via of the circuit pattern that does not need to be etched, and the minimum length from the splicing line to the beginning of the light-shielding strip in the single chip splicing layout.
8. The splicing error detection method according to claim 7, characterized in that, In the single-strip circuit pattern, the width of the circuit pattern corresponding to the non-exposure area ranges from 0.3 micrometers to 1.5 micrometers. In the spliced circuit pattern, the length from the end of the circuit pattern corresponding to the non-exposure area to the splicing line is greater than or equal to 1.5 micrometers.
9. The splicing error detection method according to claim 8, characterized in that, The T-shaped circuit pattern includes a horizontal single-strip connecting line and a vertical single-strip connecting line perpendicular to the middle of the horizontal single-strip connecting line. The height of the vertical single-strip connecting line ranges from 0.4 micrometers to 1 micrometer, and the width of the vertical single-strip connecting line ranges from 0.36 micrometers to 1.2 micrometers. In the spliced circuit pattern, the length from the end of the circuit pattern corresponding to the non-exposed area to the splicing line is greater than or equal to 1.5 micrometers.
10. The splicing error detection method according to claim 9, characterized in that, In the first combination of circuit patterns, the width of the connecting line of the groove is 0.36 micrometers to 1.2 micrometers, the inner width of the groove is 0.36 micrometers to 1.4 micrometers, and the height of the groove is 2 micrometers; in the third combination of circuit patterns, the minimum distance between the end of the circuit pattern corresponding to the non-exposure area in a single horizontal strip circuit pattern and the splicing line is 0.36 micrometers to 1.40 micrometers, and the width of a single horizontal strip circuit pattern is 0.36 micrometers to 1 micrometer.