A multi-fillet die schottky diode frequency doubler

By optimizing the spacing between adjacent rows of Schottky diodes in multiple rows, the performance degradation caused by thermal coupling and phase difference was solved, improving the operating efficiency and output power of the frequency multiplier and achieving higher driving capability in steady state.

CN116169957BActive Publication Date: 2026-06-12NAT SPACE SCI CENT CAS
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
NAT SPACE SCI CENT CAS
Filing Date
2022-12-27
Publication Date
2026-06-12

AI Technical Summary

Technical Problem

Existing multi-row Schottky diode frequency multipliers suffer from performance degradation due to thermal coupling and phase difference during actual operation, failing to effectively improve the power capacity of Schottky diodes and unable to provide drive for subsequent steady-state circuits.

Method used

By optimizing the spacing between adjacent rows of multi-row Schottky diodes to be set according to power dissipation, thermal coupling effects are reduced and phase differences are optimized to improve the overall efficiency of the frequency multiplier.

Benefits of technology

It reduces the thermal coupling effect between multiple chips, reduces the degradation of electrical performance caused by self-heating, improves the operating efficiency and output power of the frequency multiplier, and can better drive the subsequent circuits.

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    Figure CN116169957B_ABST
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Abstract

The application provides a multiple-row chip Schottky diode frequency doubler, and adjacent row spacing of the multiple-row chip is set according to dissipated power, so that total efficiency of the frequency doubler is maximized. The design method comprises the following steps: S1) according to a correlation between a chip temperature rise result and a size of the adjacent row spacing under a certain dissipated power, taking an inflection point and a plurality of point values after the inflection point as candidate values of the adjacent row spacing of the multiple-row chip; S2) determining peak efficiency of the frequency doubler under different chip temperature rise results according to the chip temperature rise results corresponding to the adjacent row spacing under different candidate values; S3) determining a multiple-row chip synthesis efficiency corresponding to the adjacent row spacing under different candidate values; and S4) taking a corresponding candidate value when the total efficiency of the frequency doubler is the highest as a final value of the adjacent row spacing. The application takes into account thermal coupling effect and phase difference of different rows of chips, reduces deterioration of electrical performance of the frequency doubler, and improves working efficiency of the frequency doubler.
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