Low phase noise signal source circuit and radar device

Abstract

This invention relates to the field of integrated circuits, and discloses a low phase noise signal source circuit and radar equipment. The low phase noise signal source circuit includes: a quad-core F... 23 A voltage-controlled oscillator (VCO) is used to generate the fundamental frequency, second harmonic, and third harmonic; a harmonic self-mixer is used with a quad-core F... 23 A voltage-controlled oscillator (VCO) is connected, and a harmonic self-mixer is used to mix the fundamental frequency and the third harmonic to obtain a fourth harmonic signal for output, and to mix the fundamental frequency and the third harmonic to obtain a second harmonic signal for output; an amplifier is connected to the harmonic self-mixer, and the amplifier is used to amplify the fourth harmonic signal for output. The signal source circuit of this invention can generate a fourth harmonic signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a low phase noise signal source circuit and radar equipment. Background Technology

[0002] With the rapid development of emerging fields such as millimeter-wave high-speed communication and high-precision radar, the demand for fully integrated millimeter-wave signal sources with low phase noise and wide bandwidth is increasing. The design of millimeter-wave signal sources faces several challenges, including low phase noise, wide tuning range, low power consumption, and high output power. Currently, one approach is to use a single quad-core F-series CPU. 23 While voltage-controlled oscillators (VCOs) provide output, at higher millimeter-wave frequencies, the limitations of passive component quality factors often result in poor phase noise and a narrow tuning range. Another approach is to cascade multiple frequency multipliers. While this method achieves better phase noise performance, it also introduces drawbacks such as excessive area, high power consumption, and the need for an external signal source. There is also the option of using a quad-core RF... 23 While cascading voltage-controlled oscillators (VCOs) and frequency multipliers can effectively increase the frequency, existing designs often require cascading multiple frequency multipliers, leading to excessive consumption of power and area.

[0003] The above solutions all use a fundamental frequency voltage-controlled oscillator. Since the impedance of the voltage-controlled oscillator needs to be matched with the corresponding harmonic frequency, the fourth harmonic cannot be generated, making it difficult to optimize the phase noise performance of the signal source. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a low phase noise signal source circuit and radar device, so that the signal source circuit can generate a signal of four times the frequency.

[0005] The technical solution of the present invention is as follows:

[0006] A low phase noise signal source circuit, comprising:

[0007] Quad-core F 23 A voltage-controlled oscillator-like device used to generate the fundamental frequency, second harmonic, and third harmonic;

[0008] Harmonic self-mixer, and the quad-core F 23 A voltage-controlled oscillator is connected, and the harmonic self-mixer is used to mix the fundamental frequency and the third harmonic into a fourth harmonic signal and output it, and to mix the fundamental frequency and the third harmonic into a second harmonic signal and output it.

[0009] An amplifier is connected to the harmonic self-mixer, and the amplifier is used to amplify the fourth harmonic signal before outputting it.

[0010] Optionally, the quad-core F23 The voltage-controlled oscillator includes four sets of oscillation cores, four sets of transformers, and four sets of head resonant cavities; each set of transformers is located between two sets of oscillation cores to form a closed-loop structure; the four sets of head resonant cavities are connected one-to-one with the four sets of transformers.

[0011] Optionally, the oscillation core includes a first NMOS transistor, a second NMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The first terminal of the first capacitor is connected to the drain of the first NMOS transistor and forms the first terminal of the oscillation core. The second terminal of the first capacitor is connected to the second terminal of the second capacitor. The first terminal of the second capacitor is connected to the drain of the second NMOS transistor and forms the second terminal of the oscillation core. The first terminal of the third capacitor is connected to the gate of the second NMOS transistor and forms the third terminal of the oscillation core. The second terminal of the third capacitor is connected to the second terminal of the fourth capacitor. The first terminal of the fourth capacitor is connected to the gate of the first NMOS transistor and forms the fourth terminal of the oscillation core. The first terminal of the fifth capacitor forms the fifth terminal of the oscillation core. The second terminal of the fifth capacitor is connected to the second terminal of the sixth capacitor and forms the sixth terminal of the oscillation core. The source of the first NMOS transistor is the seventh terminal of the oscillation core, and the source of the second NMOS transistor is the eighth terminal of the oscillation core.

[0012] Optionally, the oscillation core further includes a switched capacitor array, which includes a third NMOS transistor, a seventh capacitor, an eighth capacitor, a first resistor, a second resistor, a first inverter, and a second inverter. The input terminal of the first inverter is used to receive a control signal. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the gate of the third NMOS transistor. The source of the third NMOS transistor, the first end of the first resistor, and the first end of the seventh capacitor are interconnected. The second end of the seventh capacitor is connected to the third end of the oscillation core. The second end of the first resistor and the second end of the second resistor are connected. The drain of the third NMOS transistor, the first end of the second resistor, and the first end of the eighth capacitor are interconnected. The second end of the eighth capacitor is connected to the fourth end of the oscillation core.

[0013] Optionally, the transformer includes a first inductor, a second inductor, a third inductor, and a fourth inductor. A first end of the first inductor is connected to a first end of a set of oscillating cores, a second end of the first inductor is connected to a second end of another set of oscillating cores, a first end of the second inductor is connected to a third end of a set of oscillating cores, a second end of the second inductor is connected to a fourth end of another set of oscillating cores, a first end of the third inductor is connected to a fifth end of a set of oscillating cores, a second end of the third inductor is connected to a sixth end of another set of oscillating cores, a first end of the fourth inductor is connected to a seventh end of a set of oscillating cores, and a second end of the fourth inductor is connected to an eighth end of another set of oscillating cores.

[0014] Optionally, the head resonant cavity includes a ninth capacitor, a fifth inductor, and a sixth inductor. The first end of the fifth inductor and the first end of the sixth inductor are connected and connected to the middle end of the first inductor. The second end of the fifth inductor and the first end of the ninth capacitor are used to connect to the power supply voltage. The second end of the ninth capacitor and the second end of the sixth inductor are connected.

[0015] Optionally, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the first parasitic capacitor, the second parasitic capacitor, the first inductor, the second inductor, the third inductor, and the fourth inductor constitute a differential-mode resonant cavity, wherein the first parasitic capacitor is the source parasitic capacitor of the first NMOS transistor, and the second parasitic capacitor is the source parasitic capacitor of the second NMOS transistor;

[0016] The first capacitor, the second capacitor, the ninth capacitor, the first inductor, the fourth inductor, the fifth inductor, the sixth inductor, and the common-mode inductor constitute a common-mode resonant cavity, wherein the first end of the common-mode inductor is located at the middle end of the fourth inductor, and the second end of the common-mode inductor is grounded.

[0017] Optionally, the harmonic self-mixer includes a third resistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh inductor, an eighth inductor, and a tenth capacitor. The first terminal of the third resistor is used to connect to a first bias voltage. The second terminal of the third resistor, the first terminal of the tenth capacitor, and the gate of the fourth NMOS transistor are interconnected. The second terminal of the tenth capacitor and the source of the fourth NMOS transistor are grounded. The drain of the fourth NMOS transistor, the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor are interconnected. The gate of the fifth NMOS transistor is connected to the quad-core F... 23 A voltage-controlled oscillator-like connection is established, with the gate of the sixth NMOS transistor and the quad-core F... 23The circuit is connected in a voltage-controlled oscillator configuration. The drains of the fifth NMOS transistor, the sixth NMOS transistor, and the first terminal of the seventh inductor are interconnected. The second terminal of the seventh inductor is used to connect to the mixing voltage. The eighth inductor is connected to the amplifier.

[0018] Optionally, the amplifier includes a fourth resistor, a fifth resistor, a seventh NMOS transistor, an eighth NMOS transistor, an eleventh capacitor, a twelfth capacitor, a ninth inductor, and a tenth inductor. The first terminal of the fourth resistor, the gate of the seventh NMOS transistor, and the first terminal of the eleventh capacitor are interconnected and connected to the first output terminal of the harmonic self-mixer. The first terminal of the fifth resistor, the gate of the eighth NMOS transistor, and the first terminal of the twelfth capacitor are interconnected and connected to the second output terminal of the harmonic self-mixer. The second terminal of the fourth resistor and the second terminal of the fifth resistor are connected and used to connect to a second bias voltage. The sources of the seventh NMOS transistor and the eighth NMOS transistor are grounded. The drain of the seventh NMOS transistor, the first terminal of the ninth inductor, and the second terminal of the twelfth capacitor are interconnected. The drain of the eighth NMOS transistor, the second terminal of the ninth inductor, and the second terminal of the eleventh capacitor are interconnected. The middle terminal of the ninth inductor is used to connect to the amplifier voltage. The first and second terminals of the tenth inductor are the output terminals of the amplifier.

[0019] The present invention also proposes a radar device, including the low phase noise signal source circuit described above.

[0020] The technical solution of this invention uses a quad-core F 23 A low-phase-noise signal source circuit is composed of a voltage-controlled oscillator, a harmonic self-mixer, and an amplifier. Among them, a quad-core F... 23 A voltage-controlled oscillator (VCO) can generate a fundamental frequency, second harmonic, and third harmonic, which are output to a harmonic self-mixer. The harmonic self-mixer then mixes the fundamental frequency and third harmonic to a fourth harmonic signal before outputting it to an amplifier, and mixes the fundamental frequency with another fundamental frequency to a second harmonic signal before outputting it to an amplifier. The second harmonic cancels out each other. The amplifier then amplifies the fourth harmonic signal before outputting it. Thus, the low-phase-noise signal source circuit of this scheme can generate a fourth harmonic signal without being interfered with by the second harmonic, optimizing the phase noise performance of the signal source. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0022] Figure 1 This is a functional module schematic diagram of an embodiment of the low phase noise signal source circuit of the present invention.

[0023] Figure 2 The quad-core F in the low phase noise signal source circuit of this invention 23 A schematic diagram of the circuit structure of an embodiment of a voltage-controlled oscillator.

[0024] Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the oscillation core in the low phase noise signal source circuit of the present invention.

[0025] Figure 4 This is a schematic diagram of the circuit structure of a switched capacitor array in the low phase noise signal source circuit of the present invention.

[0026] Figure 5 This is a schematic diagram of the circuit structure of a differential-mode resonant cavity in the low-phase-noise signal source circuit of the present invention.

[0027] Figure 6 This is an impedance schematic diagram of an embodiment of the differential-mode resonant cavity in the low-phase-noise signal source circuit of the present invention.

[0028] Figure 7 This is a schematic diagram of the circuit structure of a common-mode resonant cavity in the low-phase-noise signal source circuit of the present invention.

[0029] Figure 8 This is an impedance schematic diagram of an embodiment of the common-mode resonant cavity in the low-phase-noise signal source circuit of the present invention.

[0030] Figure 9 This is a schematic diagram of the circuit structure of a harmonic self-mixer in the low phase noise signal source circuit of the present invention.

[0031] Figure 10 This is a schematic diagram of the circuit structure of an amplifier in an embodiment of the low phase noise signal source circuit of the present invention.

[0032] Figure 11 This is a schematic diagram of the circuit structure of an embodiment of the low phase noise signal source circuit of the present invention.

[0033] Figure 12 The quad-core F in the low phase noise signal source circuit of this invention 23 A schematic diagram showing the relationship between the fundamental oscillation frequency and the tuning voltage of a voltage-controlled oscillator.

[0034] Figure 13 The quad-core F in the low phase noise signal source circuit of this invention 23 A schematic diagram showing the relationship between the fundamental frequency phase noise and frequency of a voltage-controlled oscillator.

[0035] Figure 14The quad-core F in the low phase noise signal source circuit of this invention 23 A schematic diagram showing the relationship between the fourth harmonic frequency and the tuning voltage of a voltage-controlled oscillator.

[0036] Figure 15 The quad-core F in the low phase noise signal source circuit of this invention 23 A schematic diagram showing the relationship between the fourth harmonic phase noise and frequency of a voltage-controlled oscillator.

[0037] Figure label explanation: 10, Quad-core F 23 Voltage-controlled oscillator (VCO); 11. Oscillator core; 20. Harmonic self-mixer; 30. Amplifier; V, Power supply voltage; VG, Oscillator gate voltage; VB1, First bias voltage; VB2, Second bias voltage; V20, Mixer voltage; V30, Amplifier voltage; INV1, First inverter; INV2, Second inverter; R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; R5, Fifth resistor; M1, First NMOS transistor; M2, Second NMOS transistor; M3, Third NMOS transistor; M4, Fourth NMOS transistor; M5, Fifth NMOS transistor; M6, Sixth NMOS transistor; M7, Seventh NMOS transistor. OS transistor; M8, eighth NMOS transistor; L1, first inductor; L2, second inductor; L3, third inductor; L4, fourth inductor; L5, fifth inductor; L6, sixth inductor; L7, seventh inductor; L8, eighth inductor; L9, ninth inductor; L10, tenth inductor; LC, common-mode inductor; CS1, first parasitic capacitance; CS2, second parasitic capacitance; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; C7, seventh capacitor; C8, eighth capacitor; C9, ninth capacitor; C10, tenth capacitor; C11, eleventh capacitor; C12, twelfth capacitor. Detailed Implementation

[0038] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0039] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0040] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0041] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0042] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0043] With the rapid development of emerging fields such as millimeter-wave high-speed communication and high-precision radar, the demand for fully integrated millimeter-wave signal sources with low phase noise and wide bandwidth is increasing. The design of millimeter-wave signal sources faces several challenges, including low phase noise, wide tuning range, low power consumption, and high output power. Currently, one approach is to use a single quad-core F-series CPU. 23 While voltage-controlled oscillators (VCOs) provide output, at higher millimeter-wave frequencies, the limitations of passive component quality factors often result in poor phase noise and a narrow tuning range. Another approach is to cascade multiple frequency multipliers. While this method achieves better phase noise performance, it also introduces drawbacks such as excessive area, high power consumption, and the need for an external signal source. There is also the option of using a quad-core RF... 23 While cascading voltage-controlled oscillators (VCOs) and frequency multipliers can effectively increase the frequency, existing designs often require cascading multiple frequency multipliers, leading to excessive consumption of power and area.

[0044] Employing a quad-core F with rich harmonics 23This technology utilizes voltage-controlled oscillators (VCOs) and amplifiers to extract and amplify second, third, and even fourth harmonics, achieving excellent performance and low power consumption. However, when extracting the second or third harmonic alone, the quad-core F... 23 The impedance of a voltage-controlled oscillator (VCO) needs to be matched with the corresponding harmonic frequency, which makes it impossible to generate the fourth harmonic. When extracting the fourth harmonic, the second and third harmonics also cannot be effectively generated due to impedance issues, resulting in the inability to achieve harmonic shaping and making it difficult to further optimize the phase noise performance of the signal source.

[0045] To address the above problems, this invention proposes a low phase noise signal source circuit.

[0046] Reference Figure 1 In one embodiment, the low phase noise signal source circuit includes:

[0047] Quad-core F 23 A voltage-controlled oscillator 10 is used to generate the fundamental frequency, second harmonic, and third harmonic;

[0048] Harmonic self-mixer 20, and the quad-core F 23 A voltage-controlled oscillator 10 is connected, and the harmonic self-mixer 20 is used to mix the fundamental frequency and the third harmonic into a fourth harmonic signal and output it, and to mix the fundamental frequency and the third harmonic into a second harmonic signal and output it.

[0049] Amplifier 30 is connected to the harmonic self-mixer 20, and amplifier 30 is used to amplify the fourth harmonic signal and output it.

[0050] In this embodiment, the quad-core F 23 A voltage-controlled oscillator (VCO) 10 is an electronic oscillator circuit whose output signal frequency can be adjusted by an input control voltage. In this solution, a quad-core F... 23 A voltage-controlled oscillator (VCO) 10 is used as the fundamental frequency signal source to achieve lower phase noise. Quad-core F... 23The fundamental frequency output by the voltage-controlled oscillator 10 is the inherent oscillation frequency of the output signal and also the frequency component with the strongest energy; its frequency value is determined by the control voltage. The second harmonic is a harmonic component with a frequency twice that of the fundamental frequency, and the third harmonic is a harmonic component with a frequency three times that of the fundamental frequency. The harmonic self-mixer 20 is a circuit that can mix the harmonic components of the input signal with the fundamental frequency (or other harmonics). It is commonly used for signal reception and frequency conversion in high-frequency bands such as millimeter waves and terahertz. Self-mixing utilizes the harmonic components of the signal itself to participate in the mixing, or the harmonics of the local oscillator replace the high-frequency local oscillator, without the need to provide an additional high-frequency local oscillator source. The amplifier 30 can compensate for the inherent losses of the harmonic self-mixer 20. The amplifier 30 can provide sufficient gain to amplify the weak intermediate frequency signal to a detectable level for subsequent circuits (such as ADCs), preventing the signal from being overwhelmed by circuit noise. In addition, the signal output by the harmonic self-mixer 20 contains not only the target intermediate frequency signal but also stray interference such as local oscillator leakage and redundant harmonic components. In practical applications, spurious signals are first filtered out using a filter, and then the target signal is amplified using amplifier 30. The amplified target signal amplitude increases relative to the interference, which indirectly enhances the signal's anti-interference capability and reduces the bit error rate in subsequent demodulation and sampling processes. Compared with traditional millimeter-wave signal source solutions, this invention fully utilizes multiple harmonics to generate high-frequency signals through self-mixing, which not only effectively reduces the overall circuit size but also improves the reliability of the design.

[0051] The technical solution of this invention uses a quad-core F 23 A voltage-controlled oscillator 10, a harmonic self-mixer 20, and an amplifier 30 constitute a low-phase-noise signal source circuit, wherein the quad-core F 23 A voltage-controlled oscillator 10 generates a fundamental frequency, a second harmonic, and a third harmonic, which are output to a harmonic self-mixer 20. The harmonic self-mixer 20 mixes the fundamental frequency and the third harmonic into a fourth harmonic signal and outputs it to an amplifier 30, and mixes the fundamental frequency with another fundamental frequency into a second harmonic signal and outputs it to an amplifier 30. The second harmonics cancel each other out. The amplifier 30 then amplifies the fourth harmonic signal and outputs it. Thus, the low phase noise signal source circuit of this scheme can generate a fourth harmonic signal without being interfered with by the second harmonic and the second harmonic, optimizing the phase noise performance of the signal source.

[0052] In one embodiment, the quad-core F 23 The voltage-controlled oscillator 10 includes four sets of oscillation cores 11, four sets of transformers, and four sets of head resonant cavities; each set of transformers is disposed between two sets of oscillation cores 11 to form a closed-loop structure; the four sets of head resonant cavities are connected one-to-one with the four sets of transformers.

[0053] In this embodiment, compared with the traditional quad-core F... 23Compared to the voltage-controlled oscillator 10, the quad-core F-type oscillator proposed in this scheme consists of four oscillation cores 11, four transformers, and four head resonant cavities. 23 The voltage-controlled oscillator 10 features second and third harmonic extension and out-of-band enhancement, enabling it to generate high-amplitude second and third harmonic signals without requiring an additional low-quality-factor capacitor tuning array for harmonic alignment. This simplifies layout design and further reduces phase noise. Meanwhile, the quad-core F... 23 The voltage-controlled oscillator 10 significantly reduces phase noise, and the subsequently cascaded low-power, small-area amplifier 30 further improves the output amplitude. This invention provides a feasible millimeter-wave signal source solution for fields such as high-speed wireless communication, high-precision autonomous driving, and high-resolution imaging. It should be noted that the quad-core F... 23 The voltage-controlled oscillator 10 uses a multi-core architecture, and even with a single core, it offers high second-harmonic impedance, high third-harmonic impedance, harmonic impedance extension, low phase noise, wide tuning range, high tuning accuracy, and high output frequency. The quad-core F... 23 If the voltage-controlled oscillator 10 has no second harmonic output, the fourth harmonic can be generated after the fundamental frequency and third harmonic are mixed.

[0054] Reference Figures 2 to 4 In one embodiment, the oscillation core 11 includes a first NMOS transistor M1, a second NMOS transistor M2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The first terminal of the first capacitor C1 is connected to the drain of the first NMOS transistor M1 and serves as the first terminal of the oscillation core 11. The second terminal of the first capacitor C1 is connected to the second terminal of the second capacitor C2. The first terminal of the second capacitor C2 is connected to the drain of the second NMOS transistor M2 and serves as the second terminal of the oscillation core 11. The first terminal of the third capacitor C3 is connected to the gate of the second NMOS transistor M2. The third capacitor C3 is connected to the second terminal of the fourth capacitor C4. The first terminal of the fourth capacitor C4 is connected to the gate of the first NMOS transistor M1 and is the fourth terminal of the oscillation core 11. The first terminal of the fifth capacitor C5 is the fifth terminal of the oscillation core 11. The second terminal of the fifth capacitor C5 is connected to the second terminal of the sixth capacitor C6 and is the sixth terminal of the oscillation core 11. The source of the first NMOS transistor M1 is the seventh terminal of the oscillation core 11, and the source of the second NMOS transistor M2 is the eighth terminal of the oscillation core 11.

[0055] The oscillation core 11 further includes a switched capacitor array, which includes a third NMOS transistor M3, a seventh capacitor C7, an eighth capacitor C8, a first resistor R1, a second resistor R2, a first inverter INV1, and a second inverter INV2. The input terminal of the first inverter INV1 is used to receive a control signal. The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2. The output terminal of the second inverter INV2 is connected to the gate of the third NMOS transistor M3. The source of the third NMOS transistor M3, the first terminal of the first resistor R1, and the first terminal of the seventh capacitor C7 are interconnected. The second terminal of the seventh capacitor C7 is connected to the third terminal of the oscillation core 11. The second terminal of the first resistor R1 and the second terminal of the second resistor R2 are connected. The drain of the third NMOS transistor M3, the first terminal of the second resistor R2, and the first terminal of the eighth capacitor C8 are interconnected. The second terminal of the eighth capacitor C8 is connected to the fourth terminal of the oscillation core 11.

[0056] The transformer includes a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4. The first end of the first inductor L1 is connected to the first end of a set of oscillation cores 11, and the second end of the first inductor L1 is connected to the second end of another set of oscillation cores 11. The first end of the second inductor L2 is connected to the third end of a set of oscillation cores 11, and the second end of the second inductor L2 is connected to the fourth end of another set of oscillation cores 11. The first end of the third inductor L3 is connected to the fifth end of a set of oscillation cores 11, and the second end of the third inductor L3 is connected to the sixth end of another set of oscillation cores 11. The first end of the fourth inductor L4 is connected to the seventh end of a set of oscillation cores 11, and the second end of the fourth inductor L4 is connected to the eighth end of another set of oscillation cores 11.

[0057] The head resonant cavity includes a ninth capacitor C9, a fifth inductor L5, and a sixth inductor L6. The first end of the fifth inductor L5 is connected to the first end of the sixth inductor L6 and is connected to the middle end of the first inductor L1. The second end of the fifth inductor L5 and the first end of the ninth capacitor C9 are used to connect to the power supply voltage V. The second end of the ninth capacitor C9 and the second end of the sixth inductor L6 are connected.

[0058] In this embodiment, a set of oscillation cores 11 is used as an example. The drains of the first NMOS transistor M1 and the second NMOS transistor M2 are connected to the positive and negative terminals of the first inductor L1 in the two sets of transformers, respectively, as well as the first capacitor C1 and the second capacitor C2. The middle port of the first inductor L1 is connected to the sixth inductor L6 and the fifth inductor L5. The sixth inductor L6 is connected to the ninth capacitor C9. The ninth capacitor C9 and the fifth inductor L5 are connected together to the power supply voltage V, which provides oscillation energy for the oscillation core 11. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 in the single set of oscillation cores 11 are connected to the positive and negative terminals of the fourth inductor L4 in the two sets of transformers. The middle port of the fourth inductor L4 is connected to the VSS potential (ground terminal). The gates of the first NMOS transistor M1 and the second NMOS transistor M2 in the single-group oscillation core 11 are connected to the seventh capacitor C7, the third capacitor C3, and the fourth capacitor C4, respectively, and to the positive and negative terminals of the second inductor L2 in the two transformers, respectively. The middle port of the second inductor L2 is connected to the oscillator gate voltage VG. The fifth capacitor C5 and the sixth capacitor C6 are connected to the positive and negative terminals of the third inductor L3 in the two transformers, respectively. It features second harmonic extension and third harmonic extension with out-of-band enhancement. The input terminal of the first inverter INV1 in the switched capacitor array is connected to the control signal, and the output terminal is connected to the input terminal of the second inverter INV2 and to the positive terminals of the first resistor R1 and the second resistor R2. The output terminal of the second inverter INV2 is connected to the gate of the third NMOS transistor M3. The source of the third NMOS transistor M3 is connected to the negative terminals of the seventh capacitor C7 and the first resistor R1, and the drain of the third NMOS transistor M3 is connected to the negative terminals of the eighth capacitor C8 and the second resistor R2.

[0059] In the four oscillation cores 11, the dimensions of all first NMOS transistors M1 and all second NMOS transistors M2 are the same; the capacitance values ​​of all third capacitors C3 and all fourth capacitors C4 are the same; the capacitance values ​​of all first capacitors C1 and all second capacitors C2 are the same; and the capacitance values ​​of all fifth capacitors C5 and all sixth capacitors C6 are the same. In the switched capacitor array, the dimensions of the first inverter INV1 and the second inverter INV2 are the same; the dimensions of the first resistor R1 and the second resistor R2 are the same. In the same oscillation core 11, the capacitance values ​​of the seventh capacitor C7 under the same control word are the same; the capacitance values ​​of the seventh capacitor C7 under different control words are designed proportionally; and the dimensions of the third NMOS transistors M3 are designed proportionally. In the four transformers, the inductance and quality factor of all second inductors L2 are the same; the inductance and quality factor of all first inductors L1 are the same; the inductance and quality factor of all fourth inductors L4 are the same; and the inductance and quality factor of all third inductors L3 are the same. In the four sets of head resonant cavities, all sixth inductors L6 have the same inductance and quality factor, all fifth inductors L5 have the same inductance and quality factor, and all ninth capacitors C9 have the same capacitance. The coupling coefficient between the first inductor L1 and the second inductor L2 is K. DG The coupling coefficient between the first inductor L1 and the third inductor L3 is K. DT The coupling coefficient between the first inductor L1 and the fourth inductor L4 is K. DS The coupling coefficient between the second inductor L2 and the third inductor L3 is K. GT The coupling coefficient between the second inductor L2 and the fourth inductor L4 is K. GS The coupling coefficient between the third inductor L3 and the fourth inductor L4 is K. TS .

[0060] It should be noted that the traditional quad-core F 23 The voltage-controlled oscillator 10 has a transformer between its drain and gate that provides voltage gain. The addition of a fourth inductor L4 to couple with the first inductor L1 in this structure allows the source signal (VS) of the NMOS transistor to oscillate around a low DC level and generate a voltage swing opposite to the oscillator gate voltage VG, thereby increasing the gate-source voltage VGS and improving phase noise.

[0061] Reference Figure 5 and Figure 6In one embodiment, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the first parasitic capacitor CS1, the second parasitic capacitor CS2, the first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 constitute a differential-mode resonant cavity, wherein the first parasitic capacitor CS1 is the source parasitic capacitance of the first NMOS transistor M1, and the second parasitic capacitor CS2 is the source parasitic capacitance of the second NMOS transistor M2;

[0062] The first capacitor C1, the second capacitor C2, the ninth capacitor C9, the first inductor L1, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, and the common-mode inductor LC constitute a common-mode resonant cavity, wherein the first end of the common-mode inductor LC is located at the middle end of the fourth inductor L4, and the second end of the common-mode inductor LC is grounded.

[0063] In this embodiment, the introduction of third harmonic injection source shaping technology can further improve phase noise. Secondly, adding a fourth inductor L4 can increase the third harmonic impedance through out-of-band extension, further enhancing the third harmonic. The third capacitor C3, fourth capacitor C4, first capacitor C1, second capacitor C2, fifth capacitor C5, sixth capacitor C6, first parasitic capacitor CS1, second parasitic capacitor CS2, and four mutually coupled inductors L2, L1, L4, and L3 form a differential-mode resonant cavity. This differential-mode resonant cavity can generate four resonant points, providing impedance at the fundamental frequency and the third harmonic, and providing impedance extension and out-of-band impedance enhancement at the third harmonic. Figure 5 and Figure 6 As shown.

[0064] The first capacitor C1, the second capacitor C2, the first inductor L1, the fourth inductor L4, the ninth capacitor C9, the common-mode inductor LC, the sixth inductor L6, and the fifth inductor L5 form a common-mode resonant cavity. This common-mode resonant cavity can generate two resonant points, providing impedance extension at the second harmonic. For example... Figure 7 and Figure 8 As shown.

[0065] By employing differential-mode multi-coil technology, the impedance at the third harmonic is broadened and enhanced. Furthermore, the impedance at the second harmonic is widened through common-mode top resonant cavity extension technology. This allows the proposed quad-core F... 23 The voltage-controlled oscillator 10 can generate high-amplitude second and third harmonics without additional tuning, synchronized with the fundamental frequency local oscillator. The abundant harmonics can shape the voltage and current, thereby improving the ISF function, increasing voltage and current efficiency, and thus optimizing phase noise. Furthermore, the second harmonic signal generated by the mixer 20 can be suppressed by the resonant cavity.

[0066] Reference Figure 9 In one embodiment, the harmonic self-mixer 20 includes a third resistor R3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh inductor L7, an eighth inductor L8, and a tenth capacitor C10. The first terminal of the third resistor R3 is connected to a first bias voltage VB1. The second terminal of the third resistor R3, the first terminal of the tenth capacitor C10, and the gate of the fourth NMOS transistor M4 are interconnected. The second terminal of the tenth capacitor C10 and the source of the fourth NMOS transistor M4 are grounded. The drain of the fourth NMOS transistor M4, the source of the fifth NMOS transistor M5, and the source of the sixth NMOS transistor M6 are interconnected. The gate of the fifth NMOS transistor M5 is connected to the quad-core F... 23 The voltage-controlled oscillator 10 is connected, and the gate of the sixth NMOS transistor M6 and the quad-core F are connected. 23 A voltage-controlled oscillator 10 is connected, the drain of the fifth NMOS transistor M5, the drain of the sixth NMOS transistor M6, and the first terminal of the seventh inductor L7 are interconnected, the second terminal of the seventh inductor L7 is used to connect to the mixing voltage V20, and the eighth inductor L8 is connected to the amplifier 30.

[0067] In this embodiment, the harmonic self-mixer 20 is as follows: Figure 10 As shown, the third resistor R3 and the tenth capacitor C10 form a filter module to filter out noise at the first bias voltage VB1. One end of the third resistor R3 is connected to the first bias voltage VB1, and the other end is connected to the gate of the tenth capacitor C10 and the fourth NMOS transistor M4. The source of the tenth capacitor C10 and the fourth NMOS transistor M4 are both connected to the VSS potential (ground). The fourth NMOS transistor M4 is a biased NMOS transistor, and the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are mixer MOS transistors with the same size. The drain of the mixer MOS transistor is connected to the seventh inductor L7, and the coupling coefficient between the seventh inductor L7 and the eighth inductor L8 is K. M The seventh inductor, L7, is connected to the mixing voltage V20, which provides the mixing power to the mixer. The mixer input is connected to a quad-core F... 23 The single-core drain output of the voltage-controlled oscillator 10 has an input signal containing a fundamental frequency signal f0, a second harmonic 2f0, and a third harmonic 3f0. The input signal is output as a fourth harmonic 4f0 signal from both ends of the eighth inductor L8 via the harmonic self-mixer 20.

[0068] Reference Figure 10In one embodiment, the amplifier 30 includes a fourth resistor R4, a fifth resistor R5, a seventh NMOS transistor M7, an eighth NMOS transistor M8, an eleventh capacitor C11, a twelfth capacitor C12, a ninth inductor L9, and a tenth inductor L10. The first terminal of the fourth resistor R4, the gate of the seventh NMOS transistor M7, and the first terminal of the eleventh capacitor C11 are interconnected and connected to the first output terminal of the harmonic self-mixer 20. The first terminal of the fifth resistor R5, the gate of the eighth NMOS transistor M8, and the first terminal of the twelfth capacitor C12 are interconnected and connected to the second output terminal of the harmonic self-mixer 20. The second end of the fourth resistor R4 is connected to the second end of the fifth resistor R5 and is used to connect to the second bias voltage VB2. The source of the seventh NMOS transistor M7 and the source of the eighth NMOS transistor M8 are grounded. The drain of the seventh NMOS transistor M7, the first end of the ninth inductor L9 and the second end of the twelfth capacitor C12 are interconnected. The drain of the eighth NMOS transistor M8, the second end of the ninth inductor L9 and the second end of the eleventh capacitor C11 are interconnected. The middle end of the ninth inductor L9 is used to connect to the amplifier voltage V30. The first and second ends of the tenth inductor L10 are the output terminals of the amplifier 30.

[0069] In this embodiment, the amplifier 30 circuit is as follows: Figure 11 As shown, the fifth resistor R5 and the fourth resistor R4 are bias resistors. One end of the fifth resistor R5 is connected to the input signal of the harmonic self-mixer 20, and the other end is connected to the gate of the eighth NMOS transistor M8. One end of the fourth resistor R4 is connected to the input signal of the harmonic self-mixer 20, and the other end is connected to the gate of the seventh NMOS transistor M7. The drains of the eighth NMOS transistor M8 and the seventh NMOS transistor M7 are respectively connected to the two ends of the ninth inductor L9. The two ends of the twelfth capacitor C12 are respectively connected to the gate of the eighth NMOS transistor M8 and the drain of the seventh NMOS transistor M7. The two ends of the eleventh capacitor C11 are respectively connected to the gate of the seventh NMOS transistor M7 and the drain of the eighth NMOS transistor M8. The coupling coefficient between the ninth inductor L9 and the tenth inductor L10 is K. B The eighth NMOS transistor M8 and the seventh NMOS transistor M7 have the same dimensions; the twelfth capacitor C12 and the eleventh capacitor C11 have the same dimensions. The second bias voltage VB2 is connected to the common node of the fourth resistor R4 and the fifth resistor R5, providing the turn-on bias voltage for the NMOS transistors. The sources of the eighth NMOS transistor M8 and the seventh NMOS transistor M7 are connected to the VSS potential (ground). The middle port of the ninth inductor L9 is connected to the amplifier voltage V30, which provides amplification power to the amplifier 30. The amplifier 30 amplifies the input signal of the harmonic self-mixer 20 and outputs the fourth harmonic 4f0 signal through the two OUT terminals of the tenth inductor L10.

[0070] To illustrate the technical effects of this invention, please refer to... Figures 11 to 15 . Figure 11 This is the overall circuit structure diagram of a low phase noise signal source circuit.

[0071] refer to Figure 12 Quad-core F 23 The schematic diagram showing the relationship between the fundamental oscillation frequency and the tuning voltage of the voltage-controlled oscillator 10 shows that the quad-core F... 23 The voltage-controlled oscillator 10, under the control of a variable capacitor and a capacitor array, can adjust its fundamental frequency between 18.05 GHz and 21.7 GHz. A change in the tuning voltage from 0 to 1 V will only cause a change of about 1.7% in the oscillation frequency, which demonstrates the wide tuning range and high tuning accuracy of the present invention.

[0072] refer to Figure 13 Quad-core F 23 The schematic diagram showing the relationship between the fundamental frequency phase noise and frequency of a voltage-controlled oscillator 10 shows that the quad-core F... 23 The phase noise of the voltage-controlled oscillator 10 ranges from -94.1 dBc / Hz to -100.2 dBc / Hz at a frequency offset of 100 kHz from the carrier, and from -140.1 dBc / Hz to -141.2 dBc / Hz at a frequency offset of 10 MHz from the carrier. These results show that the phase noise of the present invention is low.

[0073] refer to Figure 14 Quad-core F 23 The schematic diagram showing the relationship between the fourth harmonic frequency and the tuning voltage of the voltage-controlled oscillator 10 shows that the quad-core F... 23 A voltage-controlled oscillator 10, under the control of a variable capacitor and a capacitor array, produces a quad-core F... 23 The output signal of the voltage-controlled oscillator 10 is output after passing through a mixer and amplifier 30. Its output frequency can be adjusted between 72.2 GHz and 86.8 GHz. The change of the tuning voltage from 0 to 1V will only cause a change of about 1.7% in the oscillation frequency. The results show that the present invention has a wide tuning range, high tuning accuracy and high output frequency.

[0074] refer to Figure 15 Quad-core F 23 The schematic diagram showing the relationship between the fourth harmonic phase noise and frequency of a voltage-controlled oscillator 10 shows that the quad-core F... 23The phase noise of the voltage-controlled oscillator 10 output signal after passing through the mixer and amplifier 30 ranges from -82.1dBc / Hz to -88.2dBc / Hz at a frequency offset of 100kHz from the carrier, and from -127.9dBc / Hz to -129.1dBc / Hz at a frequency offset of 10MHz from the carrier. The results show that the phase noise of the present invention is low.

[0075] It should be noted that the quad-core F 23 The voltage-controlled oscillator 10, under the control of a variable capacitor and a capacitor array, can adjust its fundamental oscillation frequency between 18.05 GHz and 21.7 GHz. A change in the tuning voltage from 0 to 1 V only causes a change of approximately 1.7% in the oscillation frequency. This scheme uses four capacitor arrays, resulting in 2^4 = 16 curves. The tuning capacitor is a variable capacitor whose voltage is controlled from 0 to 1 V. Therefore... Figure 12 and Figure 15 The lines in the diagram correspond to 16 lines.

[0076] In summary, this solution can extend the harmonic impedance bandwidth. The inductors at the beginning and end of the solution extend the second harmonic impedance bandwidth, and the third harmonic impedance bandwidth is extended through a four-coil resonant cavity. Therefore, this solution does not require manual tuning to maximize the common-mode impedance.

[0077] The head and tail inductor units of this design not only increase the impedance value of the second harmonic but also suppress the influence of the second harmonic component on the resonant circuit, thereby suppressing the quad-core F 23 The phase noise of the voltage-controlled oscillator 10 deteriorates. Using a four-coil resonant cavity can increase the impedance of the third harmonic, thereby increasing the third harmonic component and suppressing the quad-core F... 23 The phase noise of the voltage-controlled oscillator 10 deteriorates. (Using a quad-core F...) 23 The parallel structure of the voltage-controlled oscillator (VCO) reduces the resonant cavity loss resistance and optimizes the phase noise.

[0078] In this design, both the variable capacitor and the capacitor array can adjust the resonant frequency of the resonant unit. The array capacitor unit allows for coarse frequency adjustment, while the variable capacitor unit allows for fine frequency adjustment. (Quad-core F) 23 The output signal of the voltage-controlled oscillator 10 is output after passing through a mixer and amplifier 30, and its output frequency can be precisely tuned between 72.2 GHz and 86.8 GHz.

[0079] The present invention also proposes a radar device.

[0080] In one embodiment, the radar device includes a low phase noise signal source circuit as described above.

[0081] It is understood that, since the radar device of the present invention uses the above-mentioned low phase noise signal source circuit, the embodiments of the radar device of the present invention include all the technical solutions of all the embodiments of the above-mentioned low phase noise signal source circuit, and the technical effects achieved are exactly the same, so they will not be repeated here.

[0082] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A low phase noise signal source circuit, characterized by, include: Quaternary F 23 Class C voltage controlled oscillator for generating fundamental, second harmonic and third harmonic; a harmonic self-mixer, connected to the four-core F 23 a voltage-controlled oscillator connection, the harmonic self-mixer being configured to output a four-fold frequency signal after mixing the base frequency and the third harmonic, and a two-fold frequency signal after mixing the base frequency and the base frequency; An amplifier, connected to the harmonic self-mixer, is used to amplify the fourth harmonic signal before outputting it. The four-core F 23 The class voltage-controlled oscillator comprises four sets of oscillation cores, four sets of transformers and four sets of head resonant cavities. The oscillation core includes a first NMOS transistor, a second NMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The first terminal of the first capacitor is connected to the drain of the first NMOS transistor and forms the first terminal of the oscillation core. The second terminal of the first capacitor is connected to the second terminal of the second capacitor. The first terminal of the second capacitor is connected to the drain of the second NMOS transistor and forms the second terminal of the oscillation core. The first terminal of the third capacitor is connected to the gate of the second NMOS transistor and forms the third terminal of the oscillation core. The second terminal of the third capacitor is connected to the second terminal of the fourth capacitor. The first terminal of the fourth capacitor is connected to the gate of the first NMOS transistor and forms the fourth terminal of the oscillation core. The first terminal of the fifth capacitor forms the fifth terminal of the oscillation core. The second terminal of the fifth capacitor is connected to the second terminal of the sixth capacitor and forms the sixth terminal of the oscillation core. The source of the first NMOS transistor is the seventh terminal of the oscillation core, and the source of the second NMOS transistor is the eighth terminal of the oscillation core.

2. The low phase noise signal source circuit of claim 1, wherein, Each set of transformers is positioned between the two sets of oscillation cores, forming a closed-loop structure; the four sets of head resonant cavities are connected one-to-one with the four sets of transformers.

3. The low phase noise signal source circuit of claim 1, wherein, The oscillation core further includes a switched capacitor array, which includes a third NMOS transistor, a seventh capacitor, an eighth capacitor, a first resistor, a second resistor, a first inverter, and a second inverter. The input terminal of the first inverter is used to receive a control signal. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the gate of the third NMOS transistor. The source of the third NMOS transistor, the first end of the first resistor, and the first end of the seventh capacitor are interconnected. The second end of the seventh capacitor is connected to the third end of the oscillation core. The second end of the first resistor and the second end of the second resistor are connected. The drain of the third NMOS transistor, the first end of the second resistor, and the first end of the eighth capacitor are interconnected. The second end of the eighth capacitor is connected to the fourth end of the oscillation core.

4. The low phase noise signal source circuit of claim 1, wherein, The transformer includes a first inductor, a second inductor, a third inductor, and a fourth inductor. A first end of the first inductor is connected to a first end of a set of oscillating cores. A second end of the first inductor is connected to a second end of another set of oscillating cores. A first end of the second inductor is connected to a third end of a set of oscillating cores. A second end of the second inductor is connected to a fourth end of another set of oscillating cores. A first end of the third inductor is connected to a fifth end of a set of oscillating cores. A second end of the third inductor is connected to a sixth end of another set of oscillating cores. A first end of the fourth inductor is connected to a seventh end of a set of oscillating cores. A second end of the fourth inductor is connected to an eighth end of another set of oscillating cores.

5. The low phase noise signal source circuit of claim 4, wherein, The head resonant cavity includes a ninth capacitor, a fifth inductor, and a sixth inductor. The first end of the fifth inductor is connected to the first end of the sixth inductor and is connected to the middle end of the first inductor. The second end of the fifth inductor and the first end of the ninth capacitor are used to connect to the power supply voltage. The second end of the ninth capacitor and the second end of the sixth inductor are connected.

6. The low phase noise signal source circuit of claim 5, wherein, The first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the first parasitic capacitor, the second parasitic capacitor, the first inductor, the second inductor, the third inductor, and the fourth inductor constitute a differential-mode resonant cavity, wherein the first parasitic capacitor is the source parasitic capacitor of the first NMOS transistor, and the second parasitic capacitor is the source parasitic capacitor of the second NMOS transistor; The first capacitor, the second capacitor, the ninth capacitor, the first inductor, the fourth inductor, the fifth inductor, the sixth inductor, and the common-mode inductor constitute a common-mode resonant cavity, wherein the first end of the common-mode inductor is located at the middle end of the fourth inductor, and the second end of the common-mode inductor is grounded.

7. The low phase noise signal source circuit of claim 1, wherein, The harmonic self-mixer includes a third resistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh inductor, an eighth inductor, and a tenth capacitor. The first terminal of the third resistor is connected to a first bias voltage. The second terminal of the third resistor, the first terminal of the tenth capacitor, and the gate of the fourth NMOS transistor are interconnected. The second terminal of the tenth capacitor and the source of the fourth NMOS transistor are grounded. The drain of the fourth NMOS transistor, the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor are interconnected. The gate of the fifth NMOS transistor is connected to the quad-core F... 23 A voltage-controlled oscillator-like connection is established, with the gate of the sixth NMOS transistor and the quad-core F... 23 The circuit is connected in a voltage-controlled oscillator configuration. The drains of the fifth NMOS transistor, the sixth NMOS transistor, and the first terminal of the seventh inductor are interconnected. The second terminal of the seventh inductor is used to input the mixing voltage. The eighth inductor is connected to the amplifier, and the seventh and eighth inductors are coupled to each other.

8. The low phase noise signal source circuit of claim 1, wherein, The amplifier includes a fourth resistor, a fifth resistor, a seventh NMOS transistor, an eighth NMOS transistor, an eleventh capacitor, a twelfth capacitor, a ninth inductor, and a tenth inductor. The first terminal of the fourth resistor, the gate of the seventh NMOS transistor, and the first terminal of the eleventh capacitor are interconnected and connected to the first output terminal of the harmonic self-mixer. The first terminal of the fifth resistor, the gate of the eighth NMOS transistor, and the first terminal of the twelfth capacitor are interconnected and connected to the second output terminal of the harmonic self-mixer. The second terminal of the fourth resistor and the second terminal of the fifth resistor are connected and used to connect a second bias voltage. The sources of the seventh NMOS transistor and the eighth NMOS transistor are grounded. The drain of the seventh NMOS transistor, the first terminal of the ninth inductor, and the second terminal of the twelfth capacitor are interconnected. The drain of the eighth NMOS transistor, the second terminal of the ninth inductor, and the second terminal of the eleventh capacitor are interconnected. The middle terminal of the ninth inductor is used to connect the amplifier voltage. The first and second terminals of the tenth inductor are the output terminals of the amplifier.

9. A radar device, characterized by Includes the low phase noise signal source circuit as described in any one of claims 1-8.

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