A three-dimensional memory device having an isolation structure for a source-select gate line and a method for forming the same.

Abstract

Embodiments of a three-dimensional (3D) memory device and a method for forming the same are disclosed. In one example, a 3D memory device includes: a substrate; a memory stack layer located on the substrate; a plurality of channel structures, each extending perpendicularly through the memory stack layer; an isolation structure; and alignment marks. The memory stack layer includes a plurality of interleaved conductor layers and dielectric layers. The outermost conductor layer among the conductor layers facing the substrate is a source select gate line (SSG). The isolation structure extends perpendicularly into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG from the at least one channel structure. The alignment marks extend perpendicularly into the substrate and are coplanar with the isolation structure.

Description

[0001] This application is a divisional application of Chinese patent application No. 202080002341.6, filed on September 4, 2020, entitled "Three-dimensional memory device having an isolation structure for source select gate lines and a method for forming the thereof". Technical Field

[0002] Embodiments of this disclosure relate to three-dimensional (3D) storage devices and methods of manufacturing the same. Background Technology

[0003] Flattened memory cells can be scaled to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, flattening processes and manufacturing technologies become challenging and costly. Therefore, the storage density of flattened memory cells approaches its upper limit.

[0004] 3D memory architecture can address the density limits of flat memory cells. A 3D memory architecture includes memory arrays and peripheral devices for controlling signals to and from the memory arrays. Summary of the Invention

[0005] This article discloses embodiments of 3D storage devices and methods for manufacturing the same.

[0006] In one example, a 3D memory device includes: a substrate; a memory stack layer on the substrate; a plurality of channel structures, each extending vertically through the memory stack layer; an isolation structure; and alignment marks. The memory stack layer includes a plurality of interleaved conductor layers and dielectric layers. The outermost conductor layer facing the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG from the at least one channel structure. The alignment marks extend vertically into the substrate and are coplanar with the isolation structure.

[0007] In another example, a 3D memory device includes: a substrate; a laterally extending SSG; an isolation structure extending vertically through the SSG into the substrate; a first channel structure extending vertically through the SSG into the substrate; and a second channel structure extending vertically through the isolation structure into the substrate and separated from the SSG by the isolation structure.

[0008] In yet another example, a method for forming a 3D memory device is disclosed. An SSG sacrificial layer is formed on a substrate. Simultaneously, isolation structures and alignment marks, each passing through the SSG sacrificial layer, are formed. A plurality of interleaved word line dielectric layers and word line sacrificial layers are formed on the SSG sacrificial layer, the isolation structures, and the alignment marks. A first channel structure is formed, extending vertically through the interleaved word line dielectric layers, word line sacrificial layers, and the isolation structures. The word line sacrificial layer and the SSG sacrificial layer are replaced with a plurality of conductor layers to form a plurality of word lines and SSGs, such that the first channel structure is separated from the SSGs by the isolation structures. Attached Figure Description

[0009] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate embodiments of the disclosure and, together with this specification, further serve to illustrate the principles of the disclosure and enable those skilled in the art to make and use the disclosure.

[0010] Figure 1 A side view of the cross-section of the intermediate structure during the formation of a 3D storage device is shown.

[0011] Figure 2A-2C The plan view and side view of the cross-section of the intermediate structure during the formation of the 3D storage device are illustrated.

[0012] Figure 3 A side view of a cross-section of an intermediate structure is shown when forming a 3D storage device having an isolation structure for an SSG according to some embodiments of the present disclosure.

[0013] Figure 4A A side view of a cross-section of an exemplary 3D storage device having an isolation structure for an SSG, according to some embodiments of the present disclosure, is shown.

[0014] Figure 4B A plan view illustrating a cross-section of an exemplary 3D storage device having an isolation structure for an SSG, according to some embodiments of the present disclosure.

[0015] Figure 5A-5J An exemplary manufacturing process is described for forming a 3D storage device having an isolation structure for SSG according to some embodiments of this disclosure.

[0016] Figure 6 This is a flowchart of an exemplary method for forming a 3D storage device having an isolation structure for an SSG according to some embodiments.

[0017] Figure 7This is a flowchart of an exemplary method for forming an isolation structure for an SSG in a 3D storage device according to some embodiments of the present disclosure.

[0018] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0019] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0020] It should be noted that references to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., in this specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will understand that such a feature, structure, or characteristic arises in conjunction with other embodiments, whether or not explicitly described.

[0021] In general, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," or "that" can again be understood to convey either singular or plural usage. Furthermore, again depending at least in part on the context, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that do not necessarily need to be explicitly described.

[0022] It should be obvious that the meanings of “above,” “on top of,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “above” means not only “directly on something,” but also “on something” with an intermediate feature or layer in between, and that “on top of” or “above” means not only “on something” or “above something,” but may also mean “on something” or “above something” without any intermediate feature or layer in between (i.e., directly on something).

[0023] Furthermore, for ease of description, spatial relative terms (such as "below," "under," "lower," "above," "higher," etc.) may be used herein to describe the relationship between one element or feature and another element(s) as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to also include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or oriented in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0024] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials (such as silicon, germanium, gallium arsenide, indium phosphide, etc.). Alternatively, the substrate may be made of a non-conductive material (such as glass, plastic, or sapphire wafer).

[0025] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or may have a width less than that of the underlying or overlying structure. Further, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may lie between or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers above, on, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnects are formed and / or vertical interconnects are accessed via contacts) and one or more dielectric layers.

[0026] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process operation set during the design phase of a product or process, and the range of values ​​above and / or below the expected value. The range of values ​​may result from minor variations or tolerances during the manufacturing process. As used herein, the term "about" indicates a value of a given quantity that can be varied based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a value of a given quantity that can be varied, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0027] As used herein, the term "3D memory device" refers to a semiconductor device having strings (referred to herein as "memory strings," such as NAND memory strings) of vertically oriented memory cell transistors located on a laterally oriented substrate, such that the memory strings extend in a vertical direction with respect to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0028] In some 3D memory devices, during the formation of the channel structure, selective epitaxial growth (hence the term SEG) is first used to form semiconductor plugs, such as those used for channel metering, in the bottom of the channel vias. However, for a given device design, the quality or uniformity of the SEG in some channel vias may not be met; the SEG may even fail in some channel vias. Therefore, the SEG and substrate may be short-circuited, causing leakage current (SEG leakage) in the final 3D memory device, thus leading to device failure.

[0029] In one example, during a stage of manufacturing a 3D memory device having a core array region 108, an edge region 110, and a stepped region 112, such as in Figure 1 As shown, a dielectric stack layer 104 is formed on substrate 102. Channel vias 114 extending vertically through the dielectric stack layer 104 into substrate 102 are formed in the core array region 108 and the edge region 110, but not in the stepped region 112, wherein a stepped structure will be formed in the stepped region 112 in the final 3D memory device. Channel plugs 116 are selectively formed at the bottom of each channel via 114 using epitaxial growth. However, because the edge region 110 is laterally located between the core array region 108, which is filled with channel vias 114, and the stepped region 112, which has no channel vias 114, etch load effects may cause unsatisfied etching of the channel vias 114 in the edge region 110, particularly in one or more of the outermost columns of the stepped region 112 (e.g., with difficult-to-clean polymer residues), which in turn jeopardizes the formation of semiconductor plugs 116 in those channel vias 114. Therefore, during the gate replacement process, when the bottommost sacrificial layer 106 (also referred to as the SSG sacrificial layer) of the dielectric stack 104 is replaced with a conductor layer (SSG), conductive material may leak into the channel vias 114 that do not have semiconductor plugs 116 or have defective semiconductor plugs 116, causing the SSG to short-circuit with the substrate 102.

[0030] For example, in Figure 2AIn the image, semiconductor plugs (shown in light colors) failed to form in some of the vias (shown in dark colors) in the outermost column (shown in dashed boxes) of the core region. Short circuits between the SSG and the substrate could therefore occur in those vias in the final device. Even if semiconductor plugs could be formed, the quality or uniformity of the semiconductor plugs in those vias might be compromised. (As shown in...) Figure 2B As shown in the image, although a semiconductor plug 202 is formed in the bottom of the channel hole 204, the quality of the semiconductor plug 202 is not satisfied because it leaves a void between the SSG sacrificial layer 206 and the substrate 208, which may also cause a short circuit between the SSG and the substrate 208 in the final device.

[0031] Furthermore, before forming the dielectric stack layer 104, one or more alignment marks 118 are formed into the substrate 102. These alignment marks 118 can be used for alignment in later processes, such as when forming a stepped structure after forming a channel structure. However, as in Figure 2C As shown in the left-hand image, the trenches entering the alignment mark 210 of the substrate 208 may cause a recess (represented by dashed ellipses) at the top surface of the stacked structure (e.g., the lower dielectric layer of a double-layer dielectric stack) to the upper right of the alignment mark 210. Therefore, in Figure 2C In the right-hand image, residue 212 that has entered the depression (e.g., polymer residue between the low and high dielectric layers of a double dielectric stack) can be captured, which hinders the alignment of the alignment marks 210 on the underlying layer in a later process (e.g., when forming a stepped structure). Therefore, the yield may be reduced due to alignment failure.

[0032] According to various embodiments of this disclosure, a 3D memory device with an isolation structure for SSG that can prevent SSG leakage is provided. During the manufacturing process, by using one or more isolation structures to separate the SSG sacrificial layer from the channel via in the edge region where growth failure or defects of the semiconductor plug are likely to occur before the gate replacement process, even if growth failure or voids in the semiconductor plug become SSG leakage in the final 3D memory device.

[0033] Figure 3 A side view of a cross-section of an intermediate structure 300 is illustrated when forming a 3D memory device having an isolation structure for an SSG according to some embodiments of the present disclosure. (See also...) Figure 3As shown, a dielectric stack 304, including an SSG sacrificial layer 306 (e.g., the lowest sacrificial layer), can be formed on a substrate 302. An array of channel vias 312, each extending vertically through the dielectric stack 304 into the substrate 302, can be formed, and semiconductor plugs 314 can be selectively formed at the bottom of each channel via 312. Each channel via 114 (including one channel via 114 in the edge region 110) extends through the SSG sacrificial layer 306 such that the SSG sacrificial layer 306 contacts the channel via 114 in the edge region 110. Figure 1 The examples shown are different, such as in Figure 3 The channel via 312 in the edge region shown extends through the isolation structure 316 and is thus separated from the SSG sacrificial layer 306 by the isolation structure 316 therebetween. Therefore, even if the semiconductor plug 314 fails to form in the channel via 312 or has a void therein, SSG leakage will not occur due to the presence of the isolation structure 316 laterally located between the SSG (replacing the SSG sacrificial layer 306) and the substrate 302 exposed in the channel via 312. In some embodiments, the isolation structure 316, such as a shallow trench isolation (STI), extends through the SSG sacrificial layer 306 into the substrate 302 such that the bottom surface of the isolation structure 316 is below the top surface of the substrate 302.

[0034] Furthermore, the isolation structure can be formed in the same process as the formation of the alignment marks and SSG notches, without introducing additional manufacturing processes and costs. Therefore, the isolation structure, alignment marks, and SSG notches can be coplanar. In some embodiments, the top surfaces of the isolation structure, alignment marks, and SSG notches are planarized before forming the dielectric pair stack. The flat surface of the alignment marks thus prevents depressions at the top surface of the dielectric pair stack, thereby avoiding residues in depressions that could cause alignment failures in later processes.

[0035] In some embodiments, the final 3D memory device after fabrication thus includes an isolation structure that extends vertically into the substrate and surrounds at least one of the channel structures in the edge core to separate the SSG from the channel structure, and an alignment mark that extends vertically into the substrate and is coplanar with the isolation structure.

[0036] Figure 4A A side view of a cross-section of an exemplary 3D storage device 400 having an isolation structure for an SSG, according to some embodiments of this disclosure, is illustrated. The 3D storage device 400 may be manufactured post-processed. Figure 3 An example of the final 3D storage device of the intermediate structure 300 in the middle. Figure 4BA plan view of a cross-section of a 3D storage device 400 having an isolation structure for an SSG, according to some embodiments of the present disclosure, is shown. Figure 4B This can explain Figure 4A An example of a plan view of a cross section in the AA plane of a 3D storage device 400.

[0037] 3D memory device 400 may include a substrate 402, which may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, substrate 402 is a thin substrate (e.g., a semiconductor layer) that has been thinned from its normal thickness by grinding, dry / wet etching, chemical mechanical polishing (CMP), or any combination thereof. It should be noted that in Figure 4A The x, y, and z axes are included to illustrate the spatial relationships of components in the 3D memory device 400. The substrate 402 includes two lateral surfaces extending laterally in the xy plane: a front surface located on the front side of the wafer, and a rear surface located on the back side opposite the front side of the wafer. The x and y directions are two orthogonal directions in the wafer plane: the x direction is the word line direction, and the y direction is the bit line direction. The z axis is perpendicular to both the x and y axes. As used herein, when the substrate is positioned in the z direction in the lowest plane of the semiconductor device, the z direction (i.e., the direction perpendicular to the xy plane) determines whether one component (e.g., layer or device) of the semiconductor device (e.g., 3D memory device 400) is "above," "on top of," or "below" another component (e.g., layer or device) relative to the substrate (e.g., substrate 402) of the semiconductor device. The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0038] 3D memory device 400 may include a memory stack layer 404 located on a substrate 402. The memory stack layer 404 may be a stacked memory structure through which NAND memory strings (e.g., in the form of a channel structure 412) are formed. In some embodiments, the memory stack layer 404 includes a plurality of conductor / dielectric layer pairs vertically stacked on the substrate 402. Each conductor / dielectric layer pair may include a conductor layer 403 and a dielectric layer 405. That is, the memory stack layer 404 may include vertically stacked, interleaved conductor layers 403 and dielectric layers 405. The number of conductor / dielectric layer pairs in the memory stack layer 404 (e.g., 32, 64, 96, 128, 144, 160, 176, 192, 256, etc.) can set the number of memory cells in the 3D memory device 400. It should be understood that in some embodiments, the memory stack layer 404 may have a multi-layer architecture (not shown), which includes a plurality of memory layers stacked on top of each other. The number of conductor layer 403 and dielectric layer 405 pairs in each storage layer can be the same or different.

[0039] Conductor layers 403 may each have the same thickness or different thicknesses. Similarly, dielectric layers 405 may each have the same thickness or different thicknesses. Conductor layers 403 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof. Dielectric layers 405 may include insulating materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, conductor layers 403 include metals (such as W), and dielectric layers 405 include silicon oxide. It should be understood that, according to some embodiments, a thin film of silicon oxide, such as in-situ vapor-generated (ISSG) silicon oxide (not shown), is formed between substrate 402 (e.g., a silicon substrate) and memory stack layer 404.

[0040] In some embodiments, the outermost conductor layer 403 of the conductor layers 403 of the memory stack 404 serves as a select gate line for controlling the source and / or drain of each NAND memory string (e.g., in the form of a channel structure 412). The outermost conductor layer 403 of the conductor layers 403 facing the substrate 402 (i.e., Figure 4A The bottommost conductor layer in the NAND flash memory string can be the SSG 406 (also known as the bottom select gate line (BSG)) used to control the source of the NAND flash memory string, and the outermost conductor layer 403 in the conductor layer 403 away from the substrate 402 (i.e., Figure 4AThe topmost conductor layer in the NAND flash memory string can be a drain select gate line 407 (DSG, also known as a top select gate line (TSG)) used to control the drain of the NAND flash memory string. It should be understood that the number of conductor layers 403 acting as SSG 406 or DSG 407 is not limited to one, and in some examples may be greater than one. It should also be understood that although SSG 406 and DSG 407 are each referred to as "lines," their shapes are not limited to one-dimensional line segments in the x or y direction, and can extend laterally in a two-dimensional plane (e.g., ...). Figure 4B (SSG 406 in the xy plane). According to some embodiments, the remaining conductor layer 403 of the storage stack layer 404 (e.g., conductor layer 403 located vertically between SSG 406 and DSG 407) is a gate line / word line for controlling the memory cells in the NAND memory string.

[0041] As in Figure 4A As shown, the 3D memory device 400 may include a plurality of channel structures 412, each extending vertically through the memory stack layer 404 into the substrate 402. The channel structure 412 may include channel holes filled with a semiconductor material (e.g., forming a semiconductor channel 413) and an insulating material (e.g., forming a memory film 417). In some embodiments, the semiconductor channel 413 comprises silicon (such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon). In some examples, the memory film 417 is a composite layer comprising a tunneling layer, a memory layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The remaining space of the channel holes 412 may be partially or completely filled with a protective layer comprising an insulating material (such as silicon oxide) and / or air gaps. The channel structure 412 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the protective layer, semiconductor channel 413, tunneling layer of memory film 417, memory layer, and barrier layer are arranged radially from the center of the column to its outer surface in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the storage film 417 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0042] In some embodiments, the channel structure 412 includes two plugs 414 and 415 located at their respective ends in the vertical direction. (As in...) Figure 4AAs shown, the channel structure 412 may include a semiconductor plug 414 located at one end (i.e., the lower end) facing the substrate 402. As used herein, when the substrate 402 is positioned in the lowermost plane of the 3D memory device 400, the “upper end” of the component (e.g., semiconductor channel 412) is the end further away from the substrate 402 in the z-direction, and the “lower end” of the component (e.g., semiconductor channel 412) is the end further towards the substrate 402 in the z-direction. The semiconductor plug 414 may include a semiconductor material (such as single-crystal silicon) epitaxially grown from the substrate 402. The semiconductor plug 414 may act as a controller for the source selection gate of the NAND memory string together with the SSG 406. The channel plug 415 may be located at the upper end of the channel structure 412 and may include a semiconductor material (e.g., polysilicon). By covering the upper end of the channel structure 412 during the fabrication of the 3D memory device 400, the channel plug 415 can act as an etch stop layer to prevent etching of the dielectric (such as silicon oxide and silicon nitride) filled in the channel structure 412. In some embodiments, the channel plug 415 acts as the drain of a NAND memory string.

[0043] As in Figure 4B As further shown, the 3D memory device 400 may include a core array region 408 and an edge region 410 in a plan view. In some embodiments, the 3D memory device 400 further includes a stepped region 411 such that the edge region 410 is located laterally, for example, in the x-direction (word line direction), between the stepped region 411 and the core array region 408. That is, the edge region 410 may be a transition region between the core array region 408 and the stepped region 411. The memory stack layer 404 may include a stepped structure (not shown) located in the stepped region 411, where the word lines terminate for landing word line contacts (not shown). Each “level” of the stepped structure may include one or more conductor / dielectric layer pairs, each conductor / dielectric layer pair including a conductor layer 403 and a dielectric layer 405. In some embodiments, every two adjacent levels of the stepped structure are offset by a nominally equal distance in the vertical direction and by a nominally equal distance in the lateral direction. For each two adjacent layers of the stepped structure, the first layer, which is more towards the substrate 402, can extend laterally further than the second layer, thus forming a "landing area" on the first layer for vertical interconnection. In some embodiments, the channel structure 412 is arranged in the core array region 408 and the edge region 410, but not in the stepped region 411. It should be understood that in some examples, a dummy channel structure (not shown) can be formed in the stepped region 411 in the final device of the 3D memory device 400. However, compared with... Figure 1 Similar examples exist, occurring at specific stages during the manufacturing process, such as in... Figure 4B As shown, the stepped area 411 may have no channel structure or a pseudo-channel structure.

[0044] To alleviate the situation described above Figure 1 The challenges described are due to etch load effects and the resulting growth failures or defects in the semiconductor plugs 414 in the edge region 410. In some embodiments, the channel structure 412 has different lateral dimensions (e.g., diameters) in the core array region 408 and the edge region 410. According to some embodiments, such as in Figure 4B As shown, the lateral dimensions (e.g., diameter or side length) of the edge channel structure 412B (i.e., the channel structure 412 arranged in the edge region 410) are larger than the lateral dimensions (e.g., diameter or side length) of the core channel structure 412A (i.e., the channel structure 412 arranged in the core array region 408). By increasing the size of the channel holes in the edge region 410, post-etching polymer residues can be removed much more easily by cleaning before forming the semiconductor plug 414, thus improving the growth quality of the semiconductor plug 414. It should be understood that in some examples, the dimensions of the edge channel structure 412B and the core channel structure 412A may be the same. In any case, in some embodiments, as described above with respect to the channel structure 412, the structures of the edge channel structure 412B and the core channel structure 412A are identical. In some embodiments, the edge channel structures 412B are not used as NAND memory strings for storage, although they are electrically connected to other components in a similar manner to the core channel structure 412A, which is used as a NAND memory string for storage.

[0045] and Figure 1 Unlike the examples in [the previous example], the 3D memory device 400 may include an isolation structure 416 in the edge region 410 for the SSG 406 to prevent SSG leakage due to growth failure or defects in the semiconductor plug 414 in the edge channel structure 412B. (See also...) Figure 4B As shown, the isolation structure 416 surrounds the edge channel structure 412B in a plan view to separate the SSG 406 from the edge channel structure 412B in the edge region 410. However, according to some embodiments, the isolation structure 416 does not extend to the core array region 408 or the step region 411. The isolation structure 416 may include a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the isolation structure 416 includes the same insulating material (such as silicon oxide) as the dielectric layer 405 of the memory stack layer 404. Figure 4BAs shown, the SSG 406 can extend laterally across the core array region 408 and the edge region 410, and the core channel structure 412A in the core array region 408 can contact the SSG 406. Conversely, according to some embodiments, utilizing the isolation structure 416 in the edge region 410, the edge channel structure 412B in the edge region 410 is separated from the SSG 406 by the isolation structure 416. It should be understood that, although Figure 4B The isolation structure 416 surrounds all the edge channel structures 412B in the edge region 410. However, it should be understood that in other examples, the isolation structure 416 may surround one or some of the edge channel structures 412B so that the remaining edge channel structures 412B can still contact the SSG 406. In some embodiments, since the etch load effect has the greatest impact on the channel holes in the outermost column adjacent to the step region 411 in the plan view and gradually decreases in the other columns toward the core array region 408, the isolation structure 416 surrounds the edge channel structures 412B in the outermost column adjacent to the step region 411, but not the edge channel structures 412B in other columns. It should be understood that in some examples, the number of outermost columns surrounded by the isolation structure 416 is not limited to 1, and can be any number less than the total number of columns in the edge region 410.

[0046] As in Figure 4A As shown in the side view, the isolation structure 416 extends vertically through the SSG 406 into the substrate 402 in the edge region 410, such that at least one channel structure 412 in the edge region 410 contacts the isolation structure 416 instead of the SSG 406. In some embodiments, the isolation structure 416 is an STI such that the bottom surface of the isolation structure 416 is below the top surface of the substrate 402. According to some embodiments, each channel structure 412 in the core array region 408 extends vertically through the DSG 407, the gate line / word line of the conductor layer 403, and the SSG 406, while at least one channel structure 412 in the edge region 410 extends vertically through the DSG 407, the gate line / word line of the conductor layer 403, and the isolation structure 416 (replacing the SSG 406). According to some embodiments, because the isolation structure 416 extends further into the substrate 402, the channel structure 412 surrounded by the isolation structure 416 in the edge region 410 extends further into the substrate than the channel structure 412 not surrounded by the isolation structure 416 (such as the channel structure 412 in the core array region 408). That is, in some embodiments, the lower end (semiconductor plug 414) of the channel structure 412 surrounded by the isolation structure 416 in the edge region 410 is located below the lower end of the channel structure 412 not surrounded by the isolation structure 416 (such as the channel structure 412 in the core array region 408).

[0047] In some embodiments, the upper end of the semiconductor plug 414 of each channel structure 412 is located above the SSG 406, such that the semiconductor plug 414 of the channel structure 412 in the core array region 408 contacts the SSG 406, and the semiconductor plug 414 of at least one channel structure 412 in the edge region 410 contacts the isolation structure 416. The SSG 406 contacts at least one channel structure 412 in the edge region 410 (e.g., Figure 4B The lateral distance between the outermost edge channel structure 412B in the edge region 410, for example, the minimum distance between the SSG 406 and the semiconductor plug 414 surrounded by the isolation structure 416 is between approximately 40 nm and approximately 80 nm, such as, between 40 nm and 80 nm (e.g., 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, any range with any of these values ​​as a lower limit or any range defined by any two of these values). That is, according to some embodiments, the channel structure 412 surrounded by the isolation structure 416 in the edge region 410 is spaced at least 40 nm to 80 nm from the SSG 406 to avoid SSG leakage.

[0048] In some embodiments, the 3D storage device 400 further includes a structure that can divide the storage stack layer 404 and the channel structure 412 into different regions that can be individually controlled by various memory operations (such as read, write, program, or erase). Figure 4B As shown, the 3D memory device 400 may include a plurality of parallel slot structures 418 (e.g., gate slots (GLS)) arranged in the y-direction and each extending in the x-direction to divide the memory stack layer 404 and the channel structure 412 into a plurality of block memory regions 401 arranged in the y-direction. Although not shown in Figure 4B As shown, however, within each block storage area 401, additional structures (such as DSG cutouts or SSG cutouts) can further divide the block storage area 401 into multiple pointer storage areas. For example, as in Figure 4A As shown in the side view, the 3D memory device 400 may further include an SSG cutout 409 extending vertically through the SSG 406 into the substrate 402 to cut off the SSG 406. According to some embodiments, as described below with respect to the manufacturing process, the SSG cutout 409 is coplanar with the isolation structure 416 because the SSG cutout 409 and the isolation structure 416 can be formed in the same process. It should be understood that, although in Figure 4AThe SSG cutout 409 can be arranged in the stepped area 411, but it can also be arranged in other areas (such as the core array area 408 and / or the edge area 410). For example, the SSG cutout 409 can extend laterally across the core array area 408, the edge area 410, and the stepped area 411 to divide the SSG 406 into different parts of the block storage area 401.

[0049] In some embodiments, the 3D memory device 400 further includes one or more alignment marks 419, each extending vertically through the SSG 406 into the substrate 402. According to some embodiments, as described below with respect to the manufacturing process, the alignment marks 419 are coplanar with the SSG cutout 409 and the isolation structure 416 because the alignment marks 419, SSG cutout 409, and isolation structure 416 can be formed in the same process. It should be understood that the alignment marks 419 can be used for alignment during the fabrication of the 3D memory device 400 (e.g., forming the stepped structure in the stepped region 411 after forming the channel structure 412) and can be retained in the final product of the 3D memory device 400 (although not functional). It should be understood that, although in Figure 4A and 4B The alignment mark 419 can be arranged in the step area 411, but it can also be arranged in other areas (such as the core array area 408 and / or the edge area 410).

[0050] It should be understood that the 3D storage device 400 may include Figure 4A and 4B Additional components and structures not shown include, but are not limited to, local contacts and interconnects in one or more mid-process (MEOL) and back-process (BEOL) interconnect layers, as well as peripheral circuitry.

[0051] It should be understood that the layout design of the isolation structure is not subject to Figure 4A and 4B The example of isolation structure 416 is limited, and may include any other suitable layout design, such as square, rectangle, circle, cross, annular, ring, etc. It should also be understood that the number of isolation structures 416 is not limited. Figure 4A and 4B The example of a single isolation structure 416 is limited, but there can be multiple isolation structures. For example, instead of sharing a single isolation structure, each of one or more channel structures in the edge region can be surrounded by a single isolation structure.

[0052] Figure 5A-5J An exemplary manufacturing process is described for forming a 3D storage device having an isolation structure for SSG according to some embodiments of this disclosure. Figure 6 This is a flowchart of an exemplary method for forming a 3D storage device having an isolation structure for an SSG according to some embodiments. Figure 5A-5J Examples of 3D storage devices depicted in 6 include Figure 4A and 4B The 3D storage device 400 depicted in the image will be described together. Figure 4A and 4B 5A-5J and 6. It should be understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations described. Furthermore, operations may be performed simultaneously or in accordance with... Figure 6 The order shown in the diagram represents the different orders in which some of these operations are performed.

[0053] In some embodiments, a dielectric stack layer comprising multiple interlaced dielectric layers and sacrificial layers is formed on a substrate. According to some embodiments, the lowest sacrificial layer is penetrated by an isolation structure. (As in...) Figure 3 As shown, a dielectric stack layer 304 is formed on substrate 302, and an SSG sacrificial layer 306 (the lowest sacrificial layer) is penetrated by an isolation structure 316. As described in detail below, the formation of the dielectric stack layer may include the formation of an isolation structure that penetrates the SSG sacrificial layer into the substrate and the formation of interlaced word line dielectric layers and word line sacrificial layers located above the SSG sacrificial layer and the isolation structure.

[0054] refer to Figure 6 Method 600 begins at operation 602, in which an SSG sacrificial layer is formed on the substrate. Method 600 continues to operation 604, as in... Figure 6 As described herein, in this operation, respective isolation structures and alignment marks passing through the SSG sacrificial layer are formed simultaneously. In some embodiments, an SSG cut through the SSG sacrificial layer is formed in the same process as forming the isolation structures and alignment marks. Figure 7 This is a flowchart of an exemplary method for forming an isolation structure for an SSG in a 3D memory device according to some embodiments of the present disclosure. To simultaneously form the isolation structure and alignment marks, each passing through the SSG sacrificial layer, an SSG sacrificial layer, a buffer layer, and a stop layer are sequentially formed on a substrate at operation 702. In some embodiments, an SSG dielectric layer is formed on the substrate prior to forming the SSG sacrificial layer. In some embodiments, a protective layer is formed on the stop layer after forming the stop layer. In some embodiments, the SSG sacrificial layer and the stop layer comprise silicon nitride, and the SSG dielectric layer, the buffer layer, and the protective layer comprise silicon oxide. The substrate may be a silicon substrate.

[0055] As in Figure 5AAs described, an SSG dielectric layer 504, an SSG sacrificial layer 506, a buffer layer 508, a stop layer 510, a protective layer 512, and a hard mask 514 are sequentially formed on a silicon substrate 502. In some embodiments, layers of silicon oxide and silicon nitride are alternately deposited on the silicon substrate 502 using one or more thin film deposition processes, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof, such that the SSG sacrificial layer 506 and the stop layer 510 comprise silicon nitride, and the SSG dielectric layer 504, the buffer layer 508, and the protective layer 512 comprise silicon oxide. In some embodiments, the hard mask 514 comprises one or more layers (such as spin coating on carbon (SOC) and silicon oxynitride) as a planarization layer and an anti-reflection layer, which may be formed using spin coating or any other thin film deposition process, including but not limited to PVD, CVD, ALD, or any combination thereof. The hard mask 514 may also be used as an etching mask in a later process.

[0056] Return to reference Figure 7 At operation 704, isolation trenches and alignment trenches, each penetrating through the stop layer, buffer layer, and SSG sacrificial layer into the substrate, are simultaneously etched. In some embodiments, SSG notch trenches, also penetrating through the stop layer, buffer layer, and SSG sacrificial layer into the substrate, are etched in the same process. Figure 5B As described herein, isolation trench 516, SSG notch trench 518, and alignment trench 519 are etched through protective layer 512, stop layer 510, buffer layer 508, SSG sacrificial layer 506, and SSG dielectric layer 504 into silicon substrate 502. It should be understood that isolation trench 516 can be patterned using photolithography to any suitable isolation structure layout design (such as the examples disclosed herein). Hard mask 514 can be patterned according to the layout design of isolation trench 516, SSG notch trench 518, and alignment trench 519. In some embodiments, the exposed portions of protective layer 512, stop layer 510, buffer layer 508, SSG sacrificial layer 506, and SSG dielectric layer 504 located beneath the patterned hard mask 514 are then etched using dry etching and / or wet etching processes (such as reactive ion etching (RIE)) until reaching silicon substrate 502. According to some embodiments, in order to form alignment marks, the top of the silicon substrate 502 is also etched so that the alignment trench 519, SSG notch trench 518, and isolation trench 516 extend further into the silicon substrate 502. Since they are formed using the same process, the alignment trench 519, SSG notch trench 518, and isolation trench 516 can be coplanar with each other.

[0057] Return to reference Figure 7At operation 706, a dielectric layer is deposited to fill the isolation trench and alignment trench. In some embodiments, the SSG notch trench is also filled with a dielectric layer in the same process. Figure 5C As described herein, a dielectric layer 520 (such as a silicon oxide layer of the same material as the SSG dielectric layer 504, buffer layer 508, and protective layer 512) is deposited using one or more thin film deposition processes, including but not limited to PVD, CVD, ALD, or any combination thereof, to fill the isolation trench 516, SSG notch trench 518, and alignment trench 519 (in Figure 5B (As shown in the figure). According to some embodiments, the thickness of the dielectric layer 520 is large enough to ensure that the isolation trench 516, the SSG notch trench 518, and the alignment trench 519 are completely filled.

[0058] Return to reference Figure 7 At operation 708, the dielectric layer is planarized at the stop layer. For example, in... Figure 5D As described, the dielectric layer 520 is planarized using wet etching and / or CMP until the stop layer 510. In some embodiments, since both the dielectric layer 520 and the protective layer 512 have the same material (such as silicon oxide), which is different from the stop layer 510 (such as a silicon nitride layer), the stop layer 510 acts as a CMP stop layer and / or an etching stop layer to control the planarization process and avoid damaging the underlying SSG sacrificial layer 506.

[0059] Return to reference Figure 7 At operation 710, remove the stop layer. (As in...) Figure 5E As described, stop layer 510 is removed using wet etching (in... Figure 5D (as shown in the figure). In some embodiments in which the stop layer 510 comprises silicon nitride and the dielectric layer 520 and the buffer layer 508 comprise silicon oxide, phosphoric acid is used as an etchant to selectively etch the stop layer 510, leaving the dielectric layer 520 and the buffer layer 508 undamaged.

[0060] Return to reference Figure 7 At operation 712, the dielectric layer and buffer layer are planarized to form an isolation structure and alignment marks. In some embodiments, SSG notches are also formed in the same process. Figure 5F As described, another planarization process is applied using wet etching and / or CMP to make the dielectric layer 520 (in) Figure 5E(As shown in the diagram) and buffer layer 508 are planarized to form isolation structures 522, SSG notches 524, and alignment marks 525, respectively, that pass through the SSG sacrificial layer 506 into the silicon substrate 502. In some embodiments, the SSG sacrificial layer 506 is cut by the SSG notch 524. It should be understood that the buffer layer 508 can be completely removed by the planarization process, or in different examples, partially left on the SSG sacrificial layer 506. Thus, the isolation structures 522, SSG notches 524, and alignment marks 525 can be coplanar with each other. The planarization process also ensures flat surfaces of the isolation structures 522, SSG notches 524, and alignment marks 525 to avoid any depressions in the upper structure later in the process, such as those caused by alignment trenches 519.

[0061] Method 600 continues to operation 606, such as in Figure 6 As described, in this operation, multiple interlaced word line dielectric layers and word line sacrificial layers are formed on the SSG sacrificial layer, the isolation structure, and the alignment marks. Therefore, a dielectric stack layer including interlaced word line dielectric layers and word line sacrificial layers, as well as the SSG sacrificial layer, can be formed on the substrate.

[0062] As in Figure 5G As described, a dielectric stack layer 526 comprising multiple dielectric / sacrificial layer pairs is formed on a silicon substrate 502. In some embodiments, word line sacrificial layers 527 and word line dielectric layers 529 are alternately deposited on the SSG sacrificial layer 506, the isolation structure 522, and the alignment marks 525 (and in some examples, SSG notches 524) using one or more thin-film deposition processes, including but not limited to PVD, CVD, ALD, or any combination thereof. In some embodiments, the word line sacrificial layer 527 comprises silicon nitride (the same material as the SSG sacrificial layer 506), and the word line dielectric layer 529 comprises silicon oxide. It should be understood that the order in which the word line sacrificial layer 527 and the word line dielectric layer 529 are deposited is not limiting. For example, depending on whether a buffer layer 508 (in) is used (in) Figure 5F (As shown in the diagram) an SSG sacrificial layer 506 is covered, and deposition may begin with a word line sacrificial layer 527 or a word line dielectric layer 529. Therefore, according to some embodiments, a dielectric stack 526 comprising interlaced word line dielectric layers 529 and word line sacrificial layers 527, and an SSG sacrificial layer 506, is formed on the silicon substrate 502. According to some embodiments, the lowermost sacrificial layer of the dielectric stack 526 (i.e., the SSG sacrificial layer 506) is penetrated by an isolation structure 522 and an alignment mark 525, and is cut by an SSG notch 524. Due to the flat surface of the alignment mark 525, a depression directly above the alignment mark 525 and any residue trapped therein can be avoided on the top surface of the dielectric stack 526.

[0063] In some embodiments, after forming a dielectric stack, a plurality of channel structures are formed, each extending vertically through the dielectric stack into the substrate, such that at least one of the channel structures extends through an isolation structure. As described in detail below, the formation of the channel structures may include the formation of channel vias and semiconductor plugs.

[0064] Method 600 continues to operation 608, such as in Figure 6 As described, in this operation, a first channel structure (i) extending vertically through the interwoven word line dielectric layer, word line sacrificial layer, and SSG sacrificial layer, and a second channel structure extending vertically through the interwoven word line dielectric layer, word line sacrificial layer, and isolation structure are simultaneously formed. The lateral dimension of the second channel structure may be larger than the lateral dimension of the first channel structure. In some embodiments, in order to simultaneously form the first and second channel structures, a first channel via extending vertically through the interwoven word line dielectric layer, word line sacrificial layer, and SSG sacrificial layer into the substrate and a second channel via extending vertically through the interwoven word line dielectric layer, word line sacrificial layer, and isolation structure into the substrate are simultaneously formed, and a first semiconductor plug located at the bottom of the first channel via and in contact with the SSG sacrificial layer and a second semiconductor plug located at the bottom of the second channel via and spaced apart from the SSG sacrificial layer are simultaneously formed. In some embodiments, in order to simultaneously form the first and second semiconductor plugs, the first and second semiconductor plugs are epitaxially grown from the substrate in the first and second channel vias, respectively. In some embodiments, the second semiconductor plug is separated from the SSG sacrificial layer by an isolation structure.

[0065] As in Figure 5HAs described, an array of interlaced word line dielectric layers 529 and word line sacrificial layers 527, each extending vertically through the dielectric stack layer 526, are formed. The channel holes 528 in the core array region 531 may further extend through the SSG sacrificial layer 506 into the silicon substrate 502. The channel holes 528 in the edge region 533 aligned with the isolation structure 522 may further extend through the isolation structure 522 (replacing the SSG sacrificial layer 506) into the silicon substrate 502. In some embodiments, the channel holes 528 extending through the isolation structure 522 extend further into the silicon substrate 502 than the channel holes 528 extending through the SSG sacrificial layer 506. That is, the lower end of the channel holes 528 extending through the isolation structure 522 may be lower than the lower end of the channel holes 528 extending through the SSG sacrificial layer 506. The channel via 528 can be patterned using photolithography, and the channel via 528 can be etched through the interlaced silicon oxide and silicon nitride layers using dry etching and / or wet etching processes (such as deep RIE (DRIE)). In some embodiments, the channel via 528 further extends through the top of the silicon substrate 502. It should be understood that the etching process through the dielectric stack layer 526 can continue to etch portions of the silicon substrate 502. In some embodiments, after etching through the dielectric stack layer 526, a separate etching process is used to etch portions of the silicon substrate 502. In some embodiments, the lateral dimension (e.g., diameter) of the channel via 528 in the edge region 533 is larger than the lateral dimension of the channel via 528 in the core array region 531 to facilitate the cleaning of etching residues in the channel via 528 in the edge region 533, because more etching residues can form in the channel via 528 in the edge region 533 due to the etching load effect than in the core array region 531.

[0066] As in Figure 5H As described, a semiconductor plug 530 is formed in the lower portion of each channel hole 528 by filling the lower portion of the channel hole 528 with a semiconductor material (e.g., single-crystal silicon epitaxially grown from a silicon substrate 502) in any suitable direction (e.g., starting from the bottom and / or side). The fabrication process for epitaxially growing the semiconductor plug 530 may include, but is not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or any combination thereof, followed by a cleaning process to remove etching residues from the channel hole 528. Figure 1 Compared to the example in the previous example, by forming an isolation structure 522 through the SSG sacrificial layer 506 in the edge region 533, even if the semiconductor plug 530 fails to grow in the edge region 533 or has a void located in the channel hole 528, the SSG sacrificial layer 506 will be separated from the channel hole 528 to avoid SSG leakage in later processes, thus improving the yield.

[0067] As in Figure 5I As described in the text, in channel hole 528 (in Figure 5H A channel structure 538 is formed in the (shown in the figure). A memory film 532 (including a barrier layer, a memory layer, and a tunneling layer) and a semiconductor channel 534 are formed sequentially along the sidewalls of each channel hole 528 and on the respective semiconductor plug 530. In some embodiments, the memory film 532 is first deposited along the sidewalls of the channel hole 528 and on the semiconductor plug 530, and then the semiconductor channel 534 is deposited on the memory film 532. The barrier layer, memory layer, and tunneling layer can be deposited sequentially in this order using one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the memory film 532. The semiconductor channel 534 can then be formed by depositing a semiconductor material (such as polysilicon) on the tunneling layer of the memory film 532 using one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are sequentially deposited to form a storage thin film 532 and a semiconductor channel 534.

[0068] As in Figure 5I As described in the text, in channel hole 528 (in Figure 5H (As shown in the diagram) and a protective layer is formed on the semiconductor channel 534 to completely or partially fill the channel hole 528 (e.g., with or without an air gap). An insulating material (such as silicon oxide) can be deposited to form the protective layer using one or more thin-film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof). A channel plug 536 can then be formed in the top of the channel hole 528. A groove can then be formed in the top of the channel hole 528 by wet etching and / or dry etching of portions of the storage film 532, the semiconductor channel 534, and the protective layer. The channel plug 536 can then be formed by depositing a semiconductor material (such as polysilicon) into the groove using one or more thin-film deposition processes (such as CVD, PVD, ALD, or any combination thereof). According to some embodiments, a channel structure 538 is thus formed, each comprising a semiconductor plug 530, a storage film 532, a semiconductor channel 534, and a channel plug 536. In some embodiments, the channel structure 538 in the core array region 531 extends vertically through the dielectric stack 526 having the SSG sacrificial layer 506 into the silicon substrate 502, while the channel structure 538 in the edge region 533 extends vertically through the isolation structure 522 and the dielectric stack 526 without the SSG sacrificial layer 506 into the silicon substrate 502.

[0069] In some embodiments, a stepped structure (not shown) may be formed, for example, on the edge of the dielectric stack 526. The stepped structure can be formed by performing multiple so-called “trimming etch” cycles on the dielectric layer pairs of the dielectric stack 526 facing the silicon substrate 502. Due to the repeated trimming etch cycles applied to the dielectric layer pairs of the dielectric stack 526, the dielectric stack 526 may have one or more sloping edges and a top dielectric layer pair shorter than the bottom dielectric layer pair. In some embodiments, alignment marks 525 are used for alignment during the formation of the stepped structure. Due to the flat surface of the alignment marks 525, recesses on the top surface of the dielectric stack 526 and residues trapped therein can be avoided, thus preventing obstruction of the alignment marks 525.

[0070] In some embodiments, as described in detail below, the dielectric stack is replaced with a storage stack by replacing the sacrificial layer with a plurality of conductor layers, such that at least one channel structure is separated from the lowermost conductor layer of the conductor layers by an isolation structure.

[0071] Method 600 continues to operation 610, such as in Figure 6 As explained, in this operation, multiple conductor layers are used to replace the word line sacrificial layer and the SSG sacrificial layer to form multiple word lines and SSGs respectively, so that the first channel structure is in contact with the SSG and the second channel structure is separated from the SSG by an isolation structure.

[0072] As in Figure 5J As explained in the text, by replacing the word line sacrificial layer 527 with word line 542 (in... Figure 5H (as shown in the image) and replacing the SSG sacrificial layer 506 with SSG544 (in...) Figure 5I (As shown in the diagram) to replace the dielectric stack layer 526 with a memory stack layer 540 including interleaved word lines 542 and word line dielectric layer 529 and SSG 544. Figure 5I (As shown in the figure). In some embodiments, wet etching and / or dry etching (such as DRIE) of the dielectric (e.g., silicon oxide and silicon nitride) can be used to etch a gap (gap) through the dielectric stack layer 526. The gap can be replaced by a so-called gate replacement process in which the sacrificial layers (e.g., word line sacrificial layer 527 and SSG sacrificial layer 506) are replaced with active conductor layers (e.g., word lines 542 and SSG 544). Replacement of the sacrificial layer with a conductor layer can be performed by selective wet etching of the sacrificial layer (e.g., silicon nitride) on the dielectric layer 529 (e.g., silicon oxide) and filling the grooves created by the etching with a conductor layer (e.g., W). The conductor layer can be deposited by PVD, CVD, ALD, electrochemical deposition, or any combination thereof.

[0073] According to some embodiments, since the SSG sacrificial layer 506 is replaced by the SSG 544 (i.e., the bottommost conductor layer of the storage stack 540), the channel structure 538 in the core array region 531 extends through and contacts the SSG 544. Conversely, the channel structure 538 in the edge region 533 remains separated from the SSG 544 by the isolation structure 522. During the gate replacement process, since the channel structure 536 in the edge region 533 is separated from the SSG sacrificial layer 506 by the isolation structure 522, even if the semiconductor plug 530 fails to grow in the channel via 528 or has voids, the conductive material forming the SSG 544 will not leak from the recess into the silicon substrate 502 to cause a short circuit after the removal of the SSG sacrificial layer 506.

[0074] According to one aspect of this disclosure, a 3D memory device includes: a substrate, a memory stack layer on the substrate, a plurality of channel structures each extending perpendicularly through the memory stack layer, an isolation structure, and an alignment mark. The memory stack layer includes a plurality of interleaved conductor layers and dielectric layers. The outermost conductor layer among the conductor layers facing the substrate is a source select gate line (SSG). The isolation structure extends perpendicularly into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG from the at least one channel structure. The alignment mark extends perpendicularly into the substrate and is coplanar with the isolation structure.

[0075] In some embodiments, the plurality of channel structures are arranged in a core array region and an edge region in a plan view, and at least one channel structure is arranged in the edge region.

[0076] In some embodiments, the storage stack layer includes a stepped structure, the edge region being laterally located between the stepped structure and the core array region, and the at least one channel structure being arranged in the outermost column adjacent to the stepped structure in the plan view.

[0077] In some embodiments, the lateral dimension of the at least one channel structure is larger than the lateral dimension of the channel structure arranged in the core array region.

[0078] In some embodiments, the lateral distance between the SSG and the at least one channel structure is between approximately 40 nm and approximately 80 nm.

[0079] In some embodiments, each of the channel structures includes a semiconductor plug located at one end facing the substrate.

[0080] In some embodiments, the isolation structure is located laterally between the SSG and the semiconductor plug of the at least one channel structure.

[0081] In some embodiments, the semiconductor plug of the at least one channel structure extends further into the substrate than the semiconductor plug of another channel structure in the channel structure.

[0082] In some embodiments, the isolation structure and the alignment mark each include a dielectric.

[0083] In some embodiments, the alignment mark extends vertically through the SSG.

[0084] In some embodiments, the 3D memory device further includes an SSG cutout that extends vertically into the substrate and is coplanar with the isolation structure and the alignment mark.

[0085] According to another aspect of this disclosure, a 3D memory device includes: a substrate, a laterally extending SSG, an isolation structure extending vertically through the SSG into the substrate, a first channel structure extending vertically through the SSG into the substrate, and a second channel structure extending vertically through the isolation structure into the substrate and separated from the SSG by the isolation structure.

[0086] In some embodiments, in a plan view, the first channel structure is arranged in the core array region, and the second channel structure is arranged in the edge region.

[0087] In some embodiments, the 3D memory device further includes a memory stack layer comprising a plurality of interwoven conductor layers and dielectric layers. According to some embodiments, the SSG is the outermost conductor layer facing the substrate.

[0088] In some embodiments, the storage stack layer includes a stepped structure, the edge region is located laterally between the stepped structure and the core array region, and the second channel structure in the edge region is arranged in the outermost column adjacent to the stepped structure in the plan view.

[0089] In some embodiments, each of the first and second channel structures includes a semiconductor plug located at one end thereto, the semiconductor plug of the first channel structure contacting the SSG, and the semiconductor plug of the second channel structure contacting the isolation structure.

[0090] In some embodiments, the second channel structure extends further into the substrate than the first channel structure.

[0091] In some embodiments, the 3D memory device further includes alignment marks that extend vertically through the SSG into the substrate and are coplanar with the isolation structure.

[0092] In some embodiments, the isolation structure and the alignment mark each include a dielectric.

[0093] In some embodiments, the 3D memory device further includes an SSG cutout that extends vertically through the SSG into the substrate and is coplanar with the isolation structure and the alignment mark.

[0094] In some embodiments, the lateral dimension of the second channel structure is larger than the lateral dimension of the first channel structure.

[0095] In some embodiments, the lateral distance between the SSG and the second channel structure is between approximately 40 nm and approximately 80 nm.

[0096] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. An SSG sacrificial layer is formed on a substrate. Simultaneously, isolation structures and alignment marks, each passing through the SSG sacrificial layer, are formed. A plurality of interleaved word line dielectric layers and word line sacrificial layers are formed on the SSG sacrificial layer, the isolation structures, and the alignment marks. A first channel structure is formed, extending vertically through the interleaved word line dielectric layers, the word line sacrificial layers, and the isolation structures. The word line sacrificial layer and the SSG sacrificial layer are replaced with a plurality of conductor layers to form a plurality of word lines and SSGs, such that the first channel structure is separated from the SSGs by the isolation structures.

[0097] In some embodiments, a second channel structure is formed in the same process as that used to form the first channel structure, extending vertically through the interlaced word line dielectric layer, word line sacrificial layer, and SSG sacrificial layer. In some embodiments, the second channel structure contacts the SSG by replacing the word line sacrificial layer and the SSG sacrificial layer with the plurality of conductor layers to form the plurality of word lines and the SSG.

[0098] In some embodiments, a buffer layer and a stop layer are sequentially formed on the SSG sacrifice layer.

[0099] In some embodiments, in order to form the isolation structure, isolation trenches and alignment marks are formed, each passing through the stop layer, the buffer layer and the SSG sacrificial layer into the substrate; a dielectric layer is deposited to fill the isolation trenches and the alignment trenches; the dielectric layer is planarized at the stop layer; and the stop layer is removed.

[0100] In some embodiments, after the stop layer is removed, the dielectric layer and the buffer layer are planarized to form the isolation structure and the alignment mark.

[0101] In some embodiments, an SSG cut through the SSG sacrificial layer is formed in the same process as forming the isolation structure and the alignment mark.

[0102] In some embodiments, the SSG sacrificial layer comprises silicon nitride, and the isolation structure and the alignment mark comprise silicon oxide.

[0103] In some embodiments, in order to form the first and second channel structures in the same process, a first channel via extending vertically through the interwoven word line dielectric layer and word line sacrificial layer and the isolation structure into the substrate, and a second channel via extending vertically through the interwoven word line dielectric layer and word line sacrificial layer and the SSG sacrificial layer into the substrate are formed simultaneously; and a first semiconductor plug located at the bottom of the first channel via and spaced apart from the SSG sacrificial layer, and a second semiconductor plug located at the bottom of the second channel via and contacting the SSG sacrificial layer are formed simultaneously.

[0104] In some embodiments, in order to simultaneously form the first and second semiconductor plugs, the first and second semiconductor plugs are epitaxially grown from the substrate in the first and second channel holes, respectively.

[0105] In some embodiments, the first channel hole extends further into the substrate than the second channel hole.

[0106] In some embodiments, the lateral dimension of the first channel structure is larger than the lateral dimension of the second channel structure.

[0107] The foregoing description of specific embodiments is intended to reveal the general nature of this disclosure so that others, by applying knowledge of the art, can easily modify and / or adapt such specific embodiments to various applications without excessive experimentation and without departing from the general conception of this disclosure. Therefore, based on the teachings and guidelines presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that phrases or terms in this document are for descriptive and not limiting purposes, and that the terminology or phrases in this specification should be interpreted by those skilled in the art based on the teachings and guidelines presented.

[0108] Embodiments of this disclosure have been described above using functional building blocks to illustrate the implementation schemes of the specified functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for ease of description. Alternative boundaries may be defined, provided that the specified functions and their relationships are properly performed.

[0109] The abstract may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0110] The scope and extent of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A three-dimensional (3D) storage device, comprising: Substrate; A memory stack layer located on the substrate, the memory stack layer comprising overlapping conductor layers and dielectric layers, wherein at least one conductor layer in the memory stack layer closest to the substrate is a source select gate line (SSG), wherein the dielectric layer of the memory stack layer includes an SSG dielectric layer between the substrate and the source select gate line; the memory stack layer comprises a core array region, an edge region, and a stepped region, wherein the edge region is laterally located between the stepped region and the core array region; Multiple channel structures, each extending vertically through the storage stack layer, including multiple edge channel structures located within the edge region; and An isolation structure extends vertically through the SSG and the SSG dielectric layer and into the substrate, wherein the bottom surface of the isolation structure is below the top surface of the substrate and the top surface of the isolation structure is above the SSG, and wherein the isolation structure is located in the edge region, and at least one of the plurality of edge channel structures extends vertically through the isolation structure and is separated from the SSG and the SSG dielectric layer by the isolation structure.

2. The 3D storage device according to claim 1, wherein, The at least one edge channel structure is located in at least one column within the edge region, closest to the outermost column of the stepped region.

3. The 3D storage device according to claim 2, wherein, The plurality of channel structures also include a plurality of core channel structures located within the core array region, wherein the lateral dimension of the edge channel structure is larger than the lateral dimension of the core channel structure.

4. The 3D storage device according to claim 1, wherein, The minimum lateral distance between the SSG and the at least one edge channel structure is between approximately 40 nm and approximately 80 nm.

5. The 3D storage device according to claim 3, wherein, Each of the plurality of channel structures includes a semiconductor plug located at one end facing the substrate.

6. The 3D storage device according to claim 5, wherein, The isolation structure is located in the lateral direction between the SSG and the semiconductor plug of the at least one edge channel structure.

7. The 3D storage device according to claim 5, wherein, The semiconductor plug of the at least one edge channel structure extends further into the substrate than the semiconductor plug of the core channel structure.

8. The 3D storage device according to claim 1, wherein, It also includes an SSG cut that extends vertically through the SSG and into the substrate to cut off the SSG.

9. The 3D storage device according to claim 8, wherein, The SSG cut is coplanar with the isolation structure.

10. The 3D storage device according to claim 8, wherein, Both the SSG cutout and the isolation structure are in direct contact with the dielectric layer on the SSG in the storage stack.

11. The 3D storage device according to claim 8, wherein, The SSG cut extends laterally and crosses the core array region, the edge region, and the stepped region.

12. The 3D storage device according to claim 1, wherein, The edge region has an isolation structure, and the edge channel structures located in the edge region all extend vertically through the isolation structure and into the substrate.

13. The 3D storage device according to claim 1, wherein, It also includes alignment marks that extend vertically into the substrate.

14. The 3D storage device according to claim 13, wherein, The alignment mark extends vertically through the SSG.

15. The 3D storage device of claim 14, wherein the alignment mark is coplanar with the isolation structure.

16. A three-dimensional (3D) storage device, comprising: Substrate; Laterally extended source-select gate line (SSG). The SSG dielectric layer between the substrate and the source-select gate line; An isolation structure extends vertically through the SSG and the SSG dielectric layer into the substrate, wherein the bottom surface of the isolation structure is below the top surface of the substrate and the top surface of the isolation structure is above the SSG; A first channel structure extending vertically through the SSG into the substrate; and A second channel structure that extends vertically through the isolation structure into the substrate and is separated from the SSG and the SSG dielectric layer by the isolation structure.

17. The 3D storage device according to claim 16, wherein, In the plan view, the first channel structure is located in the core array region, and the second channel structure is located in the edge region.

18. The 3D storage device of claim 17, further comprising a storage stack layer, the storage stack layer comprising a plurality of interleaved conductor layers and dielectric layers, wherein, The SSG includes at least one conductor layer that faces the outermost part of the substrate.

19. The 3D storage device according to claim 18, wherein, The storage stack layer includes a stepped area, the edge area is located laterally between the stepped area and the core array area, and the second channel structure is located at least in the outermost column adjacent to the stepped area in the plan view.

20. The 3D storage device according to claim 16, wherein, Each of the first channel structure and the second channel structure includes a semiconductor plug located at one end thereof; The semiconductor plug of the first channel structure contacts the SSG; and The semiconductor plug of the second channel structure is in contact with the isolation structure.

21. The 3D storage device according to claim 16, wherein, The second channel structure extends further into the substrate than the first channel structure.

22. The 3D storage device according to claim 19, wherein, It also includes an SSG cut that extends vertically through the SSG and into the substrate to cut off the SSG.

23. The 3D storage device according to claim 22, wherein, The SSG cut is coplanar with the isolation structure.

24. The 3D storage device according to claim 22, wherein, The SSG cut extends laterally and crosses the core array region, the edge region, and the stepped region.

25. The 3D storage device according to claim 16, wherein, It also includes alignment marks that extend vertically into the substrate.

26. The 3D storage device of claim 25, wherein the alignment mark extends vertically through the SSG.

27. The 3D storage device of claim 25, wherein the alignment mark is coplanar with the isolation structure.

28. The 3D storage device according to claim 16, wherein, The lateral dimension of the second channel structure is larger than that of the first channel structure.

29. The 3D storage device according to claim 16, wherein, The minimum lateral distance between the SSG and the second channel structure is between approximately 40 nm and approximately 80 nm.

30. A method for forming a three-dimensional (3D) storage device, comprising: A source-select gate line dielectric layer is formed on the substrate; A source select gate line (SSG) sacrificial layer is formed on the source select gate line dielectric layer; An isolation structure is formed that penetrates the SSG sacrificial layer and the source select gate line dielectric layer into the substrate, wherein the bottom surface of the isolation structure is below the top surface of the substrate and the top surface of the isolation structure is above the SSG sacrificial layer; Multiple interleaved word line dielectric layers and word line sacrificial layers are formed on the SSG sacrificial layer and the isolation structure; A first channel structure is formed that extends vertically through the interlaced word line dielectric layer and word line sacrificial layer, as well as the isolation structure; and The word line sacrificial layer and the SSG sacrificial layer are replaced with multiple conductor layers to form multiple word lines and SSGs, respectively, such that the first channel structure is separated from the SSG and the source select gate line dielectric layer by the isolation structure.

31. The method of claim 30, further comprising: A second channel structure is formed in the same process as that used to form the first channel structure, extending vertically through the interwoven word line dielectric layer, word line sacrificial layer, and SSG sacrificial layer, wherein the second channel structure contacts the SSG by replacing the word line sacrificial layer and the SSG sacrificial layer with the plurality of conductor layers to form the plurality of word lines and the SSG.

32. The method of claim 30, further comprising: A buffer layer and a stop layer are formed sequentially on the SSG sacrificial layer.

33. The method according to claim 32, wherein, The SSG cut is formed in the same process as the process of forming the isolation structure; The formation of the isolation structure and the SSG cut includes: The etching passes through the stop layer, the buffer layer, and the SSG sacrificial layer into the isolation trench and SSG notch trench in the substrate; Deposit a dielectric layer to fill the isolation trench and the SSG cut trench; Planarization of the dielectric layer stops at the stop layer; and Remove the stop layer.

34. The method of claim 33, further comprising: After removing the stop layer, the dielectric layer and the buffer layer are planarized to form the isolation structure and the SSG cutout.

35. The method of claim 33, further comprising: Alignment marks are formed in the same process as forming the isolation structure and the SSG notch, extending through the SSG sacrificial layer into the substrate.

36. The method according to claim 31, wherein, The formation of the first channel structure and the second channel structure in the same process includes: Simultaneously forming (i) a first channel via extending vertically through the interwoven word line dielectric layer and word line sacrificial layer and the isolation structure into the substrate, and (ii) a second channel via extending vertically through the interwoven word line dielectric layer and word line sacrificial layer and the SSG sacrificial layer into the substrate; and Simultaneously, a first semiconductor plug is formed in the bottom of the first channel hole, which is separated from the SSG sacrificial layer, and a second semiconductor plug is formed in the bottom of the second channel hole, which is in contact with the SSG sacrificial layer.

37. The method according to claim 36, wherein, Simultaneously forming the first semiconductor plug and the second semiconductor plug includes: epitaxially growing the first semiconductor plug and the second semiconductor plug from the substrate in the first channel hole and the second channel hole, respectively.

38. The method according to claim 36, wherein, The first channel hole extends further into the substrate than the second channel hole.

39. The method according to claim 31, wherein, The lateral dimension of the first channel structure is larger than the lateral dimension of the second channel structure.

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