Algan / gan vertical high electron mobility transistor and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING CHIP IDENTIFICATION TECH CO LTD
- Filing Date
- 2022-09-07
- Publication Date
- 2026-06-12
Smart Images
Figure CN116190438B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to AlGaN / GaN vertical bulk field-effect transistors, and more specifically to an AlGaN / GaN vertical high electron mobility transistor and its fabrication method. Background Technology
[0002] GaN (gallium nitride) materials possess characteristics such as a large bandgap, high critical breakdown electric field, and high electron saturation drift velocity, thus showing great promise for applications in high-power, high-temperature, and high-frequency power electronics. Currently, among GaN-based transistors, AlGaN (aluminum gallium nitride) / GaN vertical high electron mobility transistors are among the most widely studied. In 2001, UmeshK reported the successful fabrication and testing of the first AlGaN / GaN vertical device, marking the first successful fabrication of a GaN-based vertical device and opening a new chapter in vertical device research, which is of great significance.
[0003] Field plate technology is a commonly used terminal technology that is widely used in high-voltage power semiconductor devices. Field plate technology can effectively improve the electric field distribution in the device, thereby increasing the breakdown voltage of the device.
[0004] Depending on the manufacturing process, field plates can be divided into metal field plates and resistive field plates. Resistive field plates generally employ semi-insulating polycrystalline silicon (SIPOS) technology. This is because resistive field plates are non-equipotential field plates, meaning there is a uniform potential voltage drop on the field plate, resulting in a uniform potential difference between the field plate and the device surface. Consequently, majority carriers accumulate in the drift region, and the accumulated electrons can reduce the specific on-resistance (R0) of the device. on,sp At the same time, the field plate will also uniformly distribute the electric field in the drift region, improving the device's withstand voltage. However, when the field plate technology is applied to devices with vertical drift regions, the vertical drift regions are easily affected by charge imbalance, which in turn affects the conduction current.
[0005] To address the issue of charge imbalance affecting the vertical drift region, devices with superjunction and semi-superjunction structures have been proposed. However, devices with superjunction and semi-superjunction structures suffer from high cost and low conduction current. Summary of the Invention
[0006] The purpose of this invention is to address the problem that when field plate technology is applied to devices with vertical drift regions, the vertical drift regions are easily affected by charge imbalance, thus affecting the conduction current. The invention provides an AlGaN / GaN vertical high electron mobility transistor and its fabrication method.
[0007] The technical solution adopted in this invention is:
[0008] An AlGaN / GaN vertical high electron mobility transistor, comprising:
[0009] GaN material substrate;
[0010] Drain region formed by ion implantation at the lower end of the substrate;
[0011] A drain electrode is located on the lower surface of the drain region;
[0012] An N-type drift region, a GaN channel layer, and an AlGaN barrier layer are grown sequentially on the substrate.
[0013] Its special feature is that it also includes:
[0014] N identical P-type floating buried layers are formed on the left and right sides of the N-type drift region by ion implantation and annealing, respectively, and a P-type barrier layer is formed on the upper part of the N-type drift region by doping, wherein N≥1; the P-type floating buried layers on the left and right sides are symmetrically arranged.
[0015] A multi-layered stepped dielectric trench is formed by etching through the middle of the N-type drift region, P-type barrier layer, GaN channel layer and AlGaN barrier layer, reaching the substrate. The large diameter end of the dielectric trench is located at the top. A multi-layered stepped oxide layer is provided on the inner wall of each side of the dielectric trench. A SIPOS field plate is deposited between the two oxide layers. Polysilicon is deposited above the SIPOS field plate. A gate and passivation layer are sequentially disposed above the polysilicon.
[0016] The steps of the dielectric trench are located between the N-type drift regions on both sides, and / or between the GaN channel layers on both sides, and / or between the AlGaN barrier layers on both sides.
[0017] The source region is formed by ion implantation on the surface of the AlGaN barrier layer on both sides of the dielectric trench.
[0018] Each source region is equipped with a source electrode, and the two source electrodes on both sides of the dielectric trench are connected together.
[0019] Furthermore, the thickness of the N-type drift region is 4 μm to 10 μm;
[0020] The thickness of the P-type floating buried layer is 0.5μm to 2μm;
[0021] The thickness of the P-type barrier layer is 0.5 μm to 1 μm;
[0022] The thickness of the GaN channel layer is 0.04 μm to 0.08 μm;
[0023] The thickness of the AlGaN barrier layer is 0.01 μm to 0.05 μm;
[0024] The thickness of the oxide layer is 0.05 μm to 0.5 μm.
[0025] Furthermore, a groove is provided in the middle of the upper end of the SIPOS field plate, and the polycrystalline silicon is deposited in the groove from bottom to top.
[0026] Furthermore, the number of steps in the oxide layer is the same as the number of steps in the medium trench, which is 2 to 5.
[0027] Furthermore, the number of steps in the oxide layer is the same as the number of steps in the medium trench, which is 2.
[0028] Furthermore, the substrate doping concentration is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 ;
[0029] The doping concentration of the N-type drift region is 1×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 ;
[0030] The doping concentration of the P-type floating buried layer is 1×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 ;
[0031] The doping concentration of the P-type barrier layer is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 .
[0032] Furthermore, in the AlGaN barrier layer, the Al component accounts for 15% to 30%.
[0033] Furthermore, the oxygen doping ratio of the SIPOS field plate is 15% to 35%;
[0034] The resistivity of the SIPOS field plate is 10. 6 Ω·cm~10 12 Ω·cm.
[0035] Furthermore, the doping concentration of the drain region is 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 .
[0036] This invention also proposes a method for fabricating the aforementioned AlGaN / GaN vertical high electron mobility transistor, characterized by the following steps:
[0037] 1) In gallium nitride material N +A gallium nitride epitaxial layer is grown on the substrate as an N-type drift region;
[0038] 2) At least one mutually symmetrical P-type floating buried layer is formed by P-type ion implantation and annealing on the left and right sides of the N-type drift region, respectively;
[0039] 3) A P-type barrier layer is formed on the upper part of the N-type drift region by P-type ion implantation and annealing;
[0040] 4) A GaN channel layer and an AlGaN barrier layer are grown sequentially from bottom to top above the P-type barrier layer;
[0041] 5) Etch the N-type drift region, P-type barrier layer, GaN channel layer and AlGaN barrier layer to form a multi-layered stepped dielectric trench that runs through the substrate.
[0042] 6) The source region is formed on the surface of the AlGaN barrier layer on both sides of the dielectric trench by ion implantation;
[0043] 7) Etch contact holes on the upper surface of the AlGaN barrier layer, deposit metal in the contact holes and etch to form the source, and connect the source on both sides of the dielectric trench together.
[0044] 8) A multi-layered, stepped oxide layer is formed on both sides of the medium trench;
[0045] 9) Deposit SIPOS field plates between the two oxide layers;
[0046] 10) Polysilicon is deposited above the SIPOS field plate, and a gate is formed on the upper surface of the polysilicon.
[0047] 11) Deposit a passivation layer on the upper surface of the gate;
[0048] 12) A drain region is formed on the lower surface of the substrate by ion implantation, and a drain electrode is set below the drain region.
[0049] The beneficial effects of this invention are:
[0050] 1. This invention utilizes P-type ion implantation and annealing to form a P-type floating buried layer within the N-type drift region. Multiple stepped dielectric trenches are formed between the N-type drift region, the P-type barrier layer, the GaN channel layer, and the AlGaN barrier layer through etching. Multiple stepped oxide layers and SIPOS field plates are deposited within these trenches. When the transistor is turned off, the oxide layer and SIPOS field plates significantly increase the lateral electric field of the N-type drift region, even with minimal change in the longitudinal electric field. This further optimizes the electric field distribution in the middle of the N-type drift region, thus significantly increasing the device's breakdown voltage (BV). Furthermore, the presence of the P-type floating buried layer greatly increases the doping concentration of the N-type drift region, resulting in lower conduction losses when the device is turned on, thereby increasing the conduction current.
[0051] In summary, SIPOS field plate transistors based on P-type floating buried layers and multi-layer stepped structures exhibit higher breakdown voltage and lower conduction loss compared to existing vertical GaN devices, with the same drift region length, resulting in better performance.
[0052] 2. By forming the same number of P-type floating buried layers on both the left and right sides and symmetrically arranging the P-type floating buried layers on both the left and right sides, the present invention ensures the consistency of conduction loss on the N-type drift region on both the left and right sides of the medium trench, thereby ensuring the consistency of conduction current on the N-type drift region on both the left and right sides of the medium trench.
[0053] 3. In this invention, the steps of the dielectric trench are located between the N-type drift regions on both sides, and / or between the GaN channel layers on both sides, and / or between the AlGaN barrier layers on both sides, thereby enabling a uniform lateral electric field distribution between the drift regions when the device is turned off.
[0054] 4. By setting a groove in the middle of the upper part of the SIPOS field plate and depositing polycrystalline silicon from bottom to top inside the groove, the present invention can further reduce conduction loss and increase conduction current through the sidewall current induced by the polycrystalline silicon.
[0055] 5. In this invention, the number of steps in the oxide layer is the same as the number of steps in the dielectric trench, which is 2 to 5. This can further reduce the peak electric field in the drift region. At the same time, 2 to 5 steps are also conducive to the realization of the process and reduce the manufacturing complexity. Attached Figure Description
[0056] Figure 1 This is a schematic diagram of the structural principle of an embodiment of the present invention;
[0057] Figure 2 This is a comparison diagram of the on-resistance of the present invention and existing structures;
[0058] In the figure, 1 is the source; 2 is the oxide layer; 3 is the gate; 4 is the passivation layer; 5 is the AlGaN barrier layer; 6 is the GaN channel layer; 7 is the P-type barrier layer; 8 is the N-type drift region; 9 is the P-type floating buried layer; 10 is the polysilicon; 11 is the SIPOS field plate; 12 is the substrate; and 13 is the drain. Detailed Implementation
[0059] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0060] like Figure 1 As shown, the present invention proposes an AlGaN / GaN vertical high electron mobility transistor, comprising: a gallium nitride substrate 12, wherein the substrate 12 is doped with a concentration of 1×10⁻⁶. 17 cm -3 ~1×1018 cm -3 A drain region is formed in the lower part of substrate 12 by doping, with a doping concentration of 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 A drain electrode 13 is provided on the lower surface of the drain area.
[0061] In gallium nitride material N + An N-type drift region 8 of gallium nitride material is epitaxially grown on substrate 12. The thickness of the N-type drift region 8 is determined according to the device breakdown voltage requirement, ranging from 4 μm to 10 μm, and the doping concentration is 1 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 ;
[0062] Two P-type floating buried layers 9 are formed on both sides of the N-type drift region 8 by ion implantation and annealing, and the P-type floating buried layers 9 on the left and right sides are symmetrically arranged. The thickness of the P-type floating buried layers 9 is 0.5 μm to 2 μm; the doping concentration is 1 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 ;
[0063] A P-type barrier layer 7 is formed on the upper part of the N-type drift region 8 by P-type ion implantation and annealing. The thickness of the P-type barrier layer 7 is 0.5 μm to 1 μm, and the doping concentration is determined according to the device breakdown voltage requirement, ranging from 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 ;
[0064] A GaN channel layer 6 and an AlGaN barrier layer 5 are sequentially grown above the N-type drift region 8. The thickness of the GaN channel layer 6 is 0.04 μm to 0.08 μm; the thickness of the AlGaN barrier layer 5 is 0.01 μm to 0.05 μm, and the Al component ratio in the AlGaN barrier layer 5 is 15% to 30%.
[0065] Multiple etching processes with increasing depth are performed in the middle region of the N-type drift region 8, the P-type barrier layer 7, the GaN channel layer 6, and the Al GaN barrier layer 5 to form a stepped dielectric trench that extends to the substrate 12. The radial dimensions of the stepped dielectric trench decrease sequentially, and there are two steps in the dielectric trench. Both steps are located between the N-type drift regions 8 on both sides of the dielectric trench. An oxide layer 2 with the same number of steps as the dielectric trench is grown on the surface of the dielectric trench on both sides. The thickness of the oxide layer 2 is determined according to the device breakdown voltage requirement and ranges from 0.05 μm to 0.5 μm.
[0066] A SIPOS field plate 11 is deposited from bottom to top in the region between the oxide layers 2 on both sides. The two sides of the SIPOS field plate 11 are stepped, and a groove is provided in the middle of the upper end of the SIPOS field plate 11. The oxygen doping ratio and resistivity of the SIPOS field plate 11 are determined according to the device breakdown voltage. The oxygen doping ratio is 15% to 35%, and the resistivity is 10. 6 Ω·cm~10 12 Ω·cm;
[0067] Polysilicon 10 is deposited from bottom to top in the groove, and a gate 3 and a passivation layer 4 are deposited sequentially from bottom to top above the polysilicon 10.
[0068] Contact holes are etched on the upper surface of the AlGaN barrier layer 5 on both sides of the dielectric trench. Metal is deposited in the contact holes and etched to form source 1. The source 1 on both sides of the dielectric trench is connected together.
[0069] The present invention proposes an AlGaN / GaN vertical high electron mobility transistor with a trench gate structure. It mainly introduces a stepped oxide layer 2 and a SIPOS field plate 11 in the middle of the N-type drift region 8. The stepped SIPOS field plate 11 is connected to the gate electrode of the device above and passes through the entire drift region below to connect to the substrate 12 of the device. P-type doping is performed on both sides of the N-type drift region 8 to form multiple P-type floating buried layers 9.
[0070] When the device is turned on, a conductive channel is formed on the surface of oxide layer 2 and N-type drift region 8. The forward specific on-resistance of the device (R) on,sp The current is significantly reduced, resulting in a stronger current conduction capacity per unit area;
[0071] When the device is turned off, the electric field modulation effect of the stepped SIPOS field plate 11 can optimize the internal electric field and make the electric field distribution more uniform. A relatively balanced PN junction structure is formed in the N-type drift region 8 around the floating P-type buried layer. By taking advantage of the breakdown voltage principle of the PN junction, the combination of the two can significantly improve the breakdown voltage (BV) of the device.
[0072] Combining the above advantages, the present invention has higher withstand voltage and lower conduction loss.
[0073] The present invention also proposes a method for manufacturing the above-mentioned transistor, comprising the following steps:
[0074] 1) At a doping concentration of 1×10 17 cm -3 ~1×10 18 cm -3 gallium nitride material N + The doping concentration grown on substrate 12 is 1×10⁻⁶. 16 cm -3 ~1×10 17 cm-3 A gallium nitride epitaxial layer with a thickness of 4μm to 10μm serves as the N-type drift region.
[0075] 2) P-type ion implantation and annealing were performed on the left and right sides of the N-type drift region 8 to form a doping layer with a thickness of 0.5 μm to 2 μm and a doping concentration of 1 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 And four P-shaped floating buried layers 9 that are symmetrical to each other;
[0076] 3) A doping concentration of 1×10⁻⁶ is formed in the upper part of the N-type drift region 8 by P-type ion implantation and annealing. 17 cm -3 ~1×10 18 cm -3 7. A P-type barrier layer with a thickness of 0.5μm to 1μm;
[0077] 4) Above the P-type barrier layer 7, a GaN channel layer 6 with a thickness of 0.04 μm to 0.08 μm and an AlGaN barrier layer 5 with a thickness of 0.01 μm to 0.05 μm are grown sequentially from bottom to top.
[0078] 5. Etch the N-type drift region 8, the P-type barrier layer 7, the GaN channel layer 6, and the AlGaN barrier layer 5 to form two stepped dielectric trenches that run vertically through the substrate 12.
[0079] 6) A source region is formed on the upper surface of the AlGaN barrier layer 5 on both sides of the dielectric trench by ion implantation;
[0080] 7) Etch contact holes on the upper surface of AlGaN barrier layer 5, deposit metal in the contact holes and etch to form source 1, and connect source 1 on both sides of the dielectric trench.
[0081] 8) A multi-layered stepped oxide layer 2 is formed on both sides of the medium trench;
[0082] 9) An oxygen-doped layer with a resistivity of 10⁻⁵ is deposited between the two oxide layers 2. 6 Ω·cm~10 12 SIPOS field plate 11 with Ω·cm;
[0083] 10) Polysilicon 10 is deposited in the groove of SIPOS field plate 11, and a gate 3 is deposited on the upper surface of polysilicon 10;
[0084] 11) A passivation layer 4 is deposited on the upper surface of the gate 3;
[0085] 12) The lower surface of substrate 12 is doped with a concentration of 1×10⁻⁶ by ion implantation. 18 cm-3 ~1×10 19 cm -3 The drain area is located below the drain electrode 13.
[0086] like Figure 2 As shown in the ISE-TCAD simulation, the performance of the novel device proposed in this invention is significantly improved compared to the traditional AlGaN / GaN vertical device. When both devices have an equal N-type drift region length of 7μm, the novel device has 2 steps and a drain doping concentration of 1×10⁸. 18 cm -3 There are two P-type floating buried layers 9, and the doping concentration of the substrate 12 is 1×10⁻⁶. 17 cm -3 The thickness of the P-type floating buried layer 9 is 1 μm, and the doping concentration is 1 × 10⁻⁶. 16 cm -3 The doping concentration of the N-type drift region 8 is 1.5 × 10⁸. 16 cm -3 The thickness of the P-type barrier layer 7 is 7 μm, the thickness of the P-type barrier layer 7 is 0.5 μm, and the doping concentration of the P-type barrier layer 7 is 3 × 10⁻⁶. 17 cm -3 The GaN channel layer 6 has a thickness of 0.04 μm, the AlGaN barrier layer 5 has a thickness of 0.02 μm, and the Al composition ratio is 15%. The oxide layer 2 has a thickness of 0.05 μm, and the resistivity of the SIPOS field plate 11 is 10⁻⁶. 10 Ω·cm; As shown in the figure, the breakdown voltage of the traditional device is only about 1253V, while the breakdown voltage of the new device is 1928V, which is an improvement of about 53.8%.
[0087] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions also fall within the protection scope of the present invention.
Claims
1. An AlGaN / GaN vertical high electron mobility transistor, comprising: GaN substrate (12); The drain region formed by ion implantation at the lower end of the substrate (12); Drain electrode (13) is set on the lower surface of the drain region; An N-type drift region (8), a GaN channel layer (6), and an AlGaN barrier layer (5) are sequentially grown on the substrate (12). Its characteristic is that it further includes: N identical P-type floating buried layers (9) are formed on the left and right sides of the N-type drift region (8) by ion implantation and annealing, and a P-type barrier layer (7) is formed on the upper part of the N-type drift region (8) by doping, wherein N≥1; the P-type floating buried layers (9) on the left and right sides are symmetrically arranged. A multi-layered stepped dielectric trench extending to the substrate (12) is formed by etching through the middle of the N-type drift region (8), the P-type barrier layer (7), the GaN channel layer (6), and the AlGaN barrier layer (5), with the large-diameter end of the dielectric trench located at the top. A multi-layered stepped oxide layer (2) is provided on the inner wall of each side of the dielectric trench. An SIPOS field plate (11) is deposited between the two oxide layers (2). Polysilicon (10) is deposited above the SIPOS field plate (11), and a gate (3) and a passivation layer (4) are sequentially provided above the polysilicon (10). The steps of the dielectric trench are located between the N-type drift regions (8) on both sides, and / or between the GaN channel layers (6) on both sides, and / or between the AlGaN barrier layers (5) on both sides. Source regions are formed on the surface of the AlGaN barrier layer (5) on both sides of the dielectric trench by ion implantation; a source electrode (1) is provided in each source region, and the two source electrodes (1) on both sides of the dielectric trench are connected together.
2. The AlGaN / GaN vertical high electron mobility transistor according to claim 1, characterized in that: The thickness of the N-type drift region (8) is 4 μm to 10 μm; The thickness of the P-type floating buried layer (9) is 0.5μm to 2μm; The thickness of the P-type barrier layer (7) is 0.5 μm to 1 μm; The thickness of the GaN channel layer (6) is 0.04 μm to 0.08 μm; The thickness of the AlGaN barrier layer (5) is 0.01 μm to 0.05 μm; The thickness of the oxide layer (2) is 0.05 μm to 0.5 μm.
3. The AlGaN / GaN vertical high electron mobility transistor according to claim 2, characterized in that: A groove is provided in the middle of the upper end of the SIPOS field plate (11), and the polycrystalline silicon (10) is deposited in the groove from bottom to top.
4. The AlGaN / GaN vertical high electron mobility transistor according to claim 3, characterized in that: The number of steps in the oxide layer (2) is the same as the number of steps in the medium trench, which is 2 to 5.
5. The AlGaN / GaN vertical high electron mobility transistor according to claim 4, characterized in that: The number of steps in the oxide layer (2) is the same as the number of steps in the medium trench, which is 2.
6. An AlGaN / GaN vertical high electron mobility transistor according to any one of claims 1-5, characterized in that: The doping concentration of the substrate (12) is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 ; The doping concentration of the N-type drift region (8) is 1×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 ; The doping concentration of the P-type floating buried layer (9) is 1×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 ; The doping concentration of the P-type barrier layer (7) is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 .
7. The AlGaN / GaN vertical high electron mobility transistor according to claim 6, characterized in that: In the AlGaN barrier layer (5), the Al component accounts for 15% to 30%.
8. The AlGaN / GaN vertical high electron mobility transistor according to claim 7, characterized in that: The oxygen doping ratio of the SIPOS field plate (11) is 15% to 35%; The resistivity of the SIPOS field plate (11) is 10. 6 Ω·cm~10 12 Ω·cm.
9. The AlGaN / GaN vertical high electron mobility transistor according to claim 8, characterized in that: The doping concentration of the drain region is 1×10 18 cm -3 ~1×10 19 cm -3 .
10. A method for fabricating an AlGaN / GaN vertical high electron mobility transistor according to any one of claims 1-9, characterized in that, Includes the following steps: 1) In gallium nitride material N + A gallium nitride epitaxial layer is grown on the substrate (12) as an N-type drift region (8); 2) At least one P-type floating buried layer (9) is formed on the left and right sides of the N-type drift region (8) by P-type ion implantation and annealing respectively; 3) A P-type barrier layer (7) is formed on the upper part of the N-type drift region (8) by P-type ion implantation and annealing; 4) A GaN channel layer (6) and an AlGaN barrier layer (5) are grown sequentially from bottom to top above the P-type barrier layer (7); 5) Etch the N-type drift region (8), P-type barrier layer (7), GaN channel layer (6) and AlGaN barrier layer (5) to form a multi-layer stepped dielectric trench that runs through the top and bottom and reaches the substrate (12). 6) A source region is formed on the upper surface of the AlGaN barrier layer (5) on both sides of the dielectric trench by ion implantation; 7) Etch contact holes on the upper surface of the AlGaN barrier layer (5), deposit metal in the contact holes and etch to form source (1), and connect the source (1) on both sides of the dielectric trench. 8) A multi-layered stepped oxide layer (2) is formed on both sides of the medium trench; 9) Deposit SIPOS field plate (11) between the two oxide layers (2); 10) Polysilicon (10) is deposited above the SIPOS field plate (11), and a gate (3) is deposited on the upper surface of the polysilicon (10); 11) A passivation layer (4) is deposited on the upper surface of the gate (3); 12) A drain region is formed on the lower surface of the substrate (12) by ion implantation, and a drain electrode (13) is disposed below the drain region.