Algan / gan vertical high electron mobility transistor and manufacturing method thereof

By introducing a P-type floating buried layer and a multi-layer stepped SIPOS field plate into GaN-based transistors, the electric field distribution is optimized, the charge imbalance problem in the vertical drift region is solved, the breakdown voltage and conduction current are improved, and the conduction loss is reduced.

CN116190438BActive Publication Date: 2026-06-12BEIJING CHIP IDENTIFICATION TECH CO LTD +2
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
BEIJING CHIP IDENTIFICATION TECH CO LTD
Filing Date
2022-09-07
Publication Date
2026-06-12

AI Technical Summary

⚠Technical Problem

When field plate technology is applied to GaN-based transistors with vertical drift regions, charge imbalance is likely to occur, affecting the conduction current.

⚗Method used

Symmetrical P-type floating buried layers are formed on both sides of the N-type drift region, and multiple stepped oxide layers and SIPOS field plates are set in the dielectric trench. The electric field distribution is optimized by combining the P-type floating buried layers and the multiple stepped SIPOS field plates.

🎯Benefits of technology

This improved the device's breakdown voltage and conduction current, reduced conduction losses, and achieved higher withstand voltage and lower conduction losses.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application relates to an AlGaN / GaN vertical high electron mobility transistor and a manufacturing method thereof; solves the problem that when the field plate technology is applied to a device with a vertical drift region, the vertical drift region is easily affected by charge imbalance, thereby affecting the on-current; comprises a substrate of a GaN material; an N-type drift region, a GaN channel layer and an AlGaN barrier layer are sequentially grown above the substrate; a source region is formed on the upper surface of the AlGaN barrier layer, and a source electrode is arranged in the source region; the same number of P-type floating buried layers are formed on the left and right sides of the N-type drift region, and a P-type blocking layer is formed on the upper portion of the N-type drift region; a multilayer stepped dielectric groove is formed by etching through the middle portions of the N-type drift region, the P-type blocking layer, the GaN channel layer and the AlGaN barrier layer; a multilayer stepped oxide layer is arranged on the inner wall of each side of the dielectric groove; an SIPOS field plate is deposited between the oxide layers on the two sides; polycrystalline silicon is deposited above the SIPOS field plate; a gate electrode and a passivation layer are arranged above the polycrystalline silicon; and the two source electrodes are connected in common.
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