A data transmission circuit, constant current drive chip and display system

Abstract

The application provides a data transmission circuit, a constant current driving chip and a display system. The data transmission circuit comprises a receiving end configured to receive a first input sequence and a sending end configured to output a first output sequence. The first input sequence and the first output sequence both satisfy: sequentially comprising a frame header sequence and a data sequence; when the length of the data sequence is greater than M, any continuous M-bit data in the data sequence is different from the frame header sequence, and the length of the frame header sequence is M. Through the data transmission circuit, the reliability of transceiving data can be ensured.

Description

[0001] This application is a divisional application of the invention patent application with application number 202211241998.5, entitled "A data transmission circuit, constant current driving chip and display system", filed on October 11, 2022. Technical Field

[0002] This application relates to the field of data transmission, and more particularly to a data transmission circuit, a constant current drive chip, and a display system. Background Technology

[0003] In an LED (Light Emitting Diode) display system, a single constant current source driver chip can drive several LED beads. To achieve large-scale displays, the conventional approach is to cascade multiple constant current driver chips. The output of the previous stage driver chip is electrically connected to the input of the next stage driver chip to send display data to the next stage driver chip. Once each cascaded driver chip receives the display data, it controls the connected LED beads to emit light according to the data.

[0004] Existing driver chips often require multiple data lines to achieve data transmission between various driver chips in a cascaded system. For example, a separate data line is needed for transmitting data signals, and another separate data line is needed for transmitting clock signals. LED driver systems using this multi-line transmission method suffer from large size, high material consumption, and wasted circuit resources, failing to meet current requirements for miniaturization and lightweight display systems. Furthermore, this multi-line transmission method necessitates strict timing coordination between data and clock signals; otherwise, correct data transmission and reception cannot be guaranteed, leading to unpredictable display malfunctions.

[0005] Furthermore, unpredictable interference during data transmission can lead to incomplete data received by the receiver, resulting in discrepancies between the received and transmitted data. For example, the data signal might originally be 0, but due to some reason, the received data might be flipped to 1. Digital signals are often transmitted in the form of a frame header + data + frame trailer. When the aforementioned interference exists, the receiver may identify a portion that is not part of the frame header as the "frame header." In this case, the receiver will consider the data following this misidentified "frame header" as the actual data, leading to data transmission errors, which in turn affects the LED display effect and may even directly cause display malfunctions.

[0006] Therefore, existing technologies suffer from problems such as low data transmission accuracy and reliability, waste of line resources, poor display effects, and even display failures.

[0007] The aforementioned problems have become urgent issues that need to be addressed. Summary of the Invention

[0008] This application addresses the problems of low data transmission accuracy, potential data transmission and reception errors, waste of line resources, poor display effects, and even display failures by proposing a data transmission circuit, a driver chip, and a display system.

[0009] To achieve the above objectives, this application adopts the following technical solution:

[0010] On one hand, this application provides a data transmission circuit, which includes:

[0011] The receiving end is used to receive the first input sequence;

[0012] The sending end is used to output the first output sequence;

[0013] The first input sequence and the first output sequence both satisfy the following conditions: they include a frame header sequence and a data sequence in sequence; when the length of the data sequence is greater than M, any consecutive M bits of data in the data sequence are different from the frame header sequence, wherein the length of the frame header sequence is M.

[0014] The data transmission circuit of this application has a unified data structure for both the sequence received by the receiving end and the sequence sent by the sending end. This ensures that the actual data received by the data transmission circuit and the actual data output by the data transmission circuit received by other receivers are complete and accurate. That is, the receiver will not misidentify the frame header sequence from the data sequence portion of the received sequence, thus ensuring that the acquired data portion is accurate and not truncated or subject to other abnormalities, thereby improving the reliability of data transmission.

[0015] Optionally, the data sequence of the first input sequence and / or the data sequence of the first output sequence include: a basic data group and an identification data group; each basic data group and each identification data group are distributed at intervals; and satisfy: M>X, where X is the length of each basic data group.

[0016] In this application, a set of identifier data is inserted between each group of basic data to ensure that the receiver does not misidentify the frame header from the data sequence during decoding, and to ensure that the received data is not truncated (truncation refers to considering the data sequence after a certain position as the real data sequence, resulting in an incomplete data sequence). The frame header sequence length M is greater than X, ensuring that any M bits extracted from the data sequence will necessarily include at least one bit from the identifier data. By appropriately setting the identifier data and frame header, it can be guaranteed that any M bits extracted from the data sequence will not be the same as the frame header.

[0017] Optionally, the frame header sequence is determined based on the identification data.

[0018] Optionally, each set of identifier data in the first input sequence and / or the first output sequence is entirely composed of first code values, and the frame header sequence is entirely composed of second code values.

[0019] Optionally, the data sequence of the first input sequence and / or the data sequence of the first output sequence includes: a basic data group; each basic data group may be selected as any X-bit sequence excluding one or more X-bit special sequences; wherein, the one or more X-bit special sequences are related to the frame header sequence.

[0020] In this embodiment, by sacrificing the amount of data information that the basic data can represent, the identification data used in the aforementioned embodiments can be avoided, thus reducing the complexity of data processing.

[0021] Optionally, the first input sequence and / or the first output sequence further includes: a P-bit frame tail sequence located at the end of the data sequence;

[0022] The first input sequence and / or the first output sequence satisfy the following condition: when the data sequence length is greater than P, any consecutive P bits of data in the data sequence are not the same as the frame tail sequence.

[0023] The frame header sequence and frame tail sequence are used to characterize the beginning and end of data in a data frame, respectively. In this application, any consecutive P bits of data in the data sequence are different from the frame tail sequence, that is, the frame tail sequence will not be mistakenly identified from the data sequence portion in the first input / output sequence, and the problem of data being truncated (read prematurely) will not occur, thus improving the reliability of data transmission.

[0024] Optionally, the data sequence of the first input sequence and / or the data sequence of the first output sequence further includes: a configuration sequence, which serves as functional configuration data and / or instruction data. The configuration sequence, as functional configuration data and / or instruction data, configures the functions of subsequent receivers or controls subsequent receivers.

[0025] If the configuration sequence is included in the data sequence, then the data sequence containing it also satisfies the following conditions: any consecutive M bits of data in the data sequence are not the same as the frame header sequence and / or any consecutive P bits of data in the data sequence are not the same as the frame tail sequence.

[0026] Optionally, when the transmitting end has no first output sequence to send, the transmitting end outputs a second output sequence until the transmitting end starts sending the first output sequence; or, when the transmitting end needs to send the first output sequence, the transmitting end outputs the second output sequence and then sends the first output sequence; wherein, any consecutive M bits of data in the second output sequence are different from the frame header sequence.

[0027] When idle (i.e., when no data, function configuration data, or instruction data is being sent), the data transmission circuit can adopt the following two operating modes: (1) It continues to output data uninterruptedly. This data can be any data, as long as any consecutive M bits of data are different from the frame header sequence. This can prevent the receiver from misidentifying the data sent by the sender when idle as the frame header, thus causing incorrect data transmission and reception; (2) When the first output sequence needs to be sent, irrelevant data is first output to the outside through the sender for a period of time before sending the first output sequence (this data can be any data, as long as any consecutive M bits of data are different from the frame header sequence), and then the first output sequence is sent. Both modes can ensure the stability of the receiver's internal decoding circuit, thereby ensuring the reliability and stability of data reception.

[0028] Optionally, the data transmission circuit uses return-to-zero (RZ) code to transmit data, and distinguishes whether each bit in the first input sequence and / or the first output sequence belongs to a first code value or a second code value based on the duty cycle. In this application, distinguishing the first code value and the second code value by the length of the high / low level can increase the accuracy of data transmission.

[0029] Optionally, the frame tail sequence consists entirely of second code values.

[0030] In a second aspect, this application provides a constant current driving chip, which includes the data transmission circuit as described in the first aspect;

[0031] The constant current drive chip obtains a set of basic data corresponding to the constant current drive chip based on the first input sequence received by the data transmission circuit; the constant current drive chip outputs a constant current based on the corresponding set of basic data.

[0032] The constant current driver chip provided in this embodiment, after receiving the first input sequence at its input terminal, needs to acquire the data it requires (including a set of basic data) corresponding to itself. This set of basic data can be display data. The constant current driver chip can generate a PWM signal based on the display data to control the constant current output, thereby lighting up the LED beads.

[0033] Optionally, the constant current driving chip truncates the first input sequence to obtain a set of basic data corresponding to the constant current driving chip;

[0034] When the first input sequence after truncation still contains basic data groups, the data transmission circuit outputs the remaining basic data groups through the transmitting end.

[0035] In this application, the constant current drive chip obtains a set of display data corresponding to itself by truncating the first input sequence received by the receiving end. If there are still other sets of display data after the truncated first input sequence, they are processed and reconstructed into data structure of the first output sequence as described in the first aspect above, and then output by the transmitting end.

[0036] Thirdly, this application provides a display system including K constant current driving chips as described in the second aspect; the K constant current driving chips are cascaded; the upper-level constant current driving chip outputs a first output sequence to the lower-level constant current driving chip, and the first output sequence serves as the first input sequence of the lower-level constant current driving chip.

[0037] In the display system of this application, the output terminal of the first driver chip (outputting the first output sequence) is connected to the input terminal of the second driver chip (receiving the first output sequence as the first input sequence), the output terminal of the second driver chip is connected to the input terminal of the third driver chip, and so on, until the output terminal of the (K-1)th driver chip is connected to the input terminal of the Kth driver chip. The first output sequence sent by the previous constant current driver chip includes at least one set of basic data, the number of basic data sets being consistent with the number of subsequent constant current driver chips, and each set of basic data corresponds one-to-one with each constant current driver chip. After receiving the first input sequence, the next constant current driver chip truncates it to obtain a set of basic data corresponding to that driver chip. At the same time, after the first input sequence is truncated, the driver chip will determine whether there are one or more sets of basic data corresponding to other driver chips in the truncated first input sequence. If not, the first output sequence will not be sent; if it does exist, the constant current driver chip will reconstruct it to obtain a new first output sequence that meets the requirements of the first aspect. The new first output sequence serves as the first input sequence for the next driver chip. In this way, each driver chip can obtain its corresponding set of basic data and output constant current based on this to control the display.

[0038] Optionally, the constant current drive chip determines its own position based on the received first input sequence, and determines the time to use the corresponding set of basic data for display based on its own position.

[0039] The constant current source driver chip in this application can determine its position in a series system based solely on the received data, and determine when to display based on this position. For the display system, display synchronization of multiple constant current source driver chips can be achieved without the use of an additional clock line.

[0040] Optionally, after the constant current driving chip identifies the frame header sequence, it starts counting the number of basic data groups in the first input sequence to obtain a first count value; after identifying the frame tail sequence, the constant current driving chip determines the time for displaying the basic data corresponding to the constant current driving chip based on the first count value.

[0041] The frame end sequence not only indicates the end of the data sequence but also serves for delay synchronization. The driver chip can determine the number of subsequent driver chips and its own position in the cascaded chip sequence (which position it is from the end of the cascade sequence) based on the number of basic data sets in the received first input sequence. Accordingly, the driver chip can decide how long to delay before starting display after recognizing the frame end sequence. After this delay, it is considered that the last driver chip has received its corresponding basic data (all cascaded driver chips have received their respective display data). At this point, all driver chips display based on their respective sets of basic data, achieving synchronized display.

[0042] Beneficial effects:

[0043] The data transmission circuit provided in this application ensures the accuracy of data transmission and reception through special data processing and data transmission methods;

[0044] The constant current driver chip and display system of this application can obtain accurate display data and ensure display effect;

[0045] The driver chip and display system of this application only require a single data cable to achieve data transmission, reception and synchronization, with low material consumption and small size, which can meet the requirements of miniaturization and lightweight design. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 Schematic diagrams of data transmission circuits provided for some embodiments of this application;

[0048] Figure 2 This application provides a schematic diagram of the data structure of a first input sequence / first output sequence in some embodiments.

[0049] Figure 3a Case 1, illustrating the data sequence of the first input sequence / first output sequence provided in some embodiments of this application;

[0050] Figure 3bCase 2, which is a schematic diagram of the data sequence of the first input sequence / first output sequence provided in some embodiments of this application;

[0051] Figure 3c Case 3, a schematic diagram of the data sequence of the first input sequence / first output sequence provided in some embodiments of this application;

[0052] Figure 3d Case 4, a schematic diagram of the data sequence of the first input sequence / first output sequence provided in some embodiments of this application;

[0053] Figure 4 Case 5, a schematic diagram of the data sequence of the first input sequence / first output sequence provided in some embodiments of this application;

[0054] Figure 5 Case six, a schematic diagram of the data sequence of the first input sequence / first output sequence provided in some embodiments of this application;

[0055] Figure 6 A schematic diagram of the zeroing code provided for some embodiments of this application;

[0056] Figure 7 Schematic diagrams of display systems provided for some embodiments of this application;

[0057] Figure 8 A schematic diagram of a first input sequence / first output sequence provided for some embodiments of this application;

[0058] Figure label: 100 - Data transmission circuit. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0061] Hereinafter, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. Furthermore, the term "electrical connection" can refer to a direct electrical connection or an indirect electrical connection via an intermediate medium.

[0062] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0063] It should be noted that the sequence mentioned in this application refers to elements or objects arranged in a column, with the elements or objects arranged in a certain order, such as the binary sequence 01001.

[0064] In this application, the first input sequence, the first output sequence, the data sequence, the frame header sequence, the frame tail sequence, the configuration sequence, the special sequence, etc., can all be understood as data arranged in a certain order.

[0065] like Figure 1 As shown, the first aspect of this application provides a data transmission circuit 100. The data transmission circuit 100 includes:

[0066] The receiving end is used to receive the first input sequence;

[0067] The sending end is used to output the first output sequence;

[0068] Wherein, both the first input sequence and the first output sequence satisfy:

[0069] It consists of a frame header sequence and a data sequence, in that order.

[0070] When the length of the data sequence is greater than M, any consecutive M bits of data in the data sequence are different from the frame header sequence, wherein the length of the frame header sequence is M.

[0071] The first input sequence received by the receiving end of the data transmission circuit 100 and the first output sequence transmitted by the transmitting end have the same data structure and meet the same requirements. Meeting the same requirements means that when the data sequence length is greater than M, any consecutive M bits of data in the data sequence are not the same as the frame header sequence. Figure 2 The data structures for the first input sequence and the first output sequence of this application are provided, each consisting of a sequence of at least two parts (a frame header sequence and a data sequence).

[0072] The first input sequence and the first output sequence have the same frame header sequence, meaning the frame header sequence has the same number of bits (e.g., M bits) and each bit of data corresponds to the same value. For example, the frame header sequence is 112 bits of 1.

[0073] The data sequences of the first input sequence and the first output sequence can be the same or different. For example, the data portion of the first output sequence can be a segment of the data portion of the first input sequence. In this case, the first output sequence is related to the first input sequence, for example, it can be generated based on the first input sequence. For instance, generating the first output sequence based on the first input sequence can include, but is not limited to, a series of operations such as adding and / or deleting and / or reconstructing and / or reshaping the first input sequence to reconstruct the first output sequence into a sequence that conforms to the aforementioned requirements / standards, thereby improving the accuracy of data transmission.

[0074] It should be noted that regardless of whether the data sequences of the first input sequence and the first output sequence are the same, they both satisfy a certain condition, namely, when the length of the data sequence is greater than M, any consecutive M bits of data in the data sequence are different from the frame header sequence.

[0075] This condition ensures that the data transmission circuit 100 will not identify any consecutive M bits of the data sequence portion of the received first input sequence as a frame header, and similarly, the data transmission circuit 100 will not identify any consecutive M bits of the data sequence portion of the received first output sequence as a frame header when transmitting the first output sequence to the target receiver. In other words, for both the data transmission circuit 100 itself and its corresponding receiver, the received data is not truncated or incomplete, ensuring the accuracy and reliability of data transmission.

[0076] It should also be noted that the data sequence may include the data transmission circuit 100 itself and / or the data actually needed by the subsequent receiver, or it may include data in other formats containing this actually needed data. The specific form or structure of the data is not limited herein. For example, when the data transmission circuit 100 is applied to an LED constant current driver chip, the actually needed data may be at least one set of display data. The constant current driver chip can generate a PWM (Pulse Width Modulation) signal based on the display data and output a constant current based on the PWM signal to drive the LED display screen for display. Of course, when applied to other scenarios, the actually needed data may be other types of data.

[0077] In some optional implementations, the data sequence of the first input sequence and / or the data sequence of the first output sequence includes:

[0078] Basic data group and identification data group;

[0079] Each set of basic data and each set of identifier data are distributed at intervals; and, satisfying: M>X, where X is the length of each set of basic data.

[0080] As mentioned earlier, the first input sequence and the first output sequence have the same data structure, not only in that they both include a frame header sequence and a data sequence, but also in that their data sequence includes a basic data group and an identifier data group. There is at least one basic data group, the number of which depends on the specific application. Optionally, each basic data group has the same data length (e.g., X bits), and each identifier data group (e.g., Z bits) is identical. In this case, not only are the frame header sequences identical in the first input sequence and the first output sequence, but the identifier data is also identical. For example, the frame header sequences are both 112 bits of 1, and the identifier data are both 16 bits of 0.

[0081] When there are groups of identification data, each group of basic data and each group of identification data are distributed at intervals. That is, there will not be two consecutive groups of basic data and / or two consecutive groups of identification data.

[0082] Preferably, in this application, M>=X+Z, where Z is the length of each group of identifier data.

[0083] Figures 3a-3d This application provides various implementations of the data structure for the first input sequence and the first output sequence. It is assumed in this application that the data sequence in the first input sequence or the first output sequence includes N sets of basic data (N>=1), then the number of identifier data sets can be N, N-1, or N+1.

[0084] Figure 3a In the provided implementation, the number of basic data groups and the number of identification data groups are the same. The first basic data group follows the frame header sequence, followed by the first identification data group, then the second basic data group, and so on, until the last identification data group.

[0085] Of course, it can also be like... Figure 3b As shown, the frame header sequence is followed by the first set of identification data, followed by the first set of basic data, and so on, until the last set of basic data.

[0086] Of course, the number of basic data sets and the number of identifier data sets can be different. Figure 3c In the provided implementation, the number of basic data groups is one more than the number of identification data groups. Figure 3d In the provided implementation, the number of basic data groups is one less than the number of identification data groups.

[0087] It should be noted that in this application, Figure 3a For example, suppose Figure 3aAs the first input sequence, when the data transmission circuit 100 receives the first input sequence, it first receives the frame header sequence, then the first set of basic data following the frame header sequence, then the first set of identification data following the first set of basic data, and so on. Similarly, assuming... Figure 3a If the first output sequence is the first output sequence, then other receivers receive this first output sequence, firstly the frame header sequence, then the first set of basic data following the frame header sequence, then the first set of identification data following the first set of basic data, and so on. In other words, the sequence in this application (such as...) Figures 3a-3d The data is distributed from left to right along the timeline, with the first set of basic data received first, followed by the subsequent sets.

[0088] In this application, the identification data, used as interpolation data, is employed to prevent the receiver from misreading the frame header data from the data sequence portion when receiving the first input sequence or when subsequently receiving the first output sequence (which serves as the receiver's first input sequence) from the data transmission circuit, thereby ensuring the correctness of the received basic data. It is understandable that, assuming the identification data is absent, if the length of multiple sets of basic data exceeds the length of the frame header sequence, since the values ​​of each set of basic data can be arbitrary, arbitrarily truncating a continuous M-bit sequence has the same possibility of being mistaken for the frame header sequence. Furthermore, if the basic data is flipped for some reason, the receiver may also mistakenly identify the data portion as frame header data. Incorrect identification of the frame header sequence will undoubtedly lead to data decoding errors and the acquisition of truncated data.

[0089] In this application, the length M of the frame header sequence of the first input sequence and the first output sequence is greater than the length X of each group of basic data. Based on the foregoing, there must be an identifier data set between the two groups of basic data. This ensures that any M bits extracted from the data sequence will include at least one identifier data bit. By reasonably setting the identifier data and the frame header sequence, any consecutive M bits in the first input sequence and / or the first output sequence can be different from the frame header sequence, thereby preventing the frame header from being misidentified in the data sequence of the first input sequence and / or the first output sequence, which includes the actual data to be transmitted.

[0090] For example, each set of identifier data consists entirely of the first code value, and the frame header sequence consists entirely of the second code value. In this application, the first code value and the second code value can be represented using binary 0 and 1. When the first code value is 1, the second code value is 0; when the first code value is 0, the second code value is 1.

[0091] When the frame header sequence is all 1s, each group of identifier data is all 0s. Since the length M of the frame header sequence is greater than the length of each group of basic data, any M consecutive subsequences extracted from the data sequence must include at least one identifier data bit, meaning the extracted M bits must include 0s. However, the frame header sequence consists of M bits of 1s. Therefore, it is impossible to identify any M consecutive bits in the first subsequence as the frame header.

[0092] For example, suppose each set of basic data is 96 bits, the frame header sequence is 112 bits of 1s, and the identification data is 16 bits of 0s. Then, if 112 bits are arbitrarily extracted from the first input sequence and / or the first output sequence, 16 bits will necessarily belong to the identification data and be 0s. The extracted 112 bits will not be recognized as the 112-bit all-1s frame header.

[0093] For example, consider a 17-bit frame header sequence, 16-bit basic data per group, and 3-bit identifier data per group. Assume the identifier data is 010. Then, by properly configuring the frame header sequence, the condition that any consecutive M bits in the first input sequence and / or the first output sequence are different from the frame header sequence can be satisfied. For instance, any three consecutive bits in the frame header sequence must not be 010, and the last bit of the frame header sequence must not be 0, the last two bits must not be 01, the first bit must not be 0, and the first two bits must not be 10. Examples include 11000000000000011, 11111111111110111, etc.

[0094] As can be seen, the frame header sequence is related to the identification data. Once the identification data is determined, one or more frame header sequences that meet the conditions can be derived from it. Of course, feasible identification data can also be derived from a pre-determined frame header sequence. For a simple example, if the frame header sequence is all 1s, then the identification data can be all 0s. Of course, there are countless other feasible methods, which are more complex than the former, and will not be elaborated here.

[0095] Optionally, the number of data groups in the first input sequence and the first output sequence are different. For example, the basic data in the first input sequence is K1 groups (K1>=1), and the basic data in the first output sequence is K1-1 groups. Preferably, the basic data in the first output sequence is the last K1-1 groups of basic data in the first input sequence. It can be understood that when K1=1, the data transmission circuit will not output the first output sequence.

[0096] In some optional implementations, the data sequence of the first input sequence and / or the data sequence of the first output sequence includes:

[0097] Basic data set;

[0098] Each set of basic data can be selected as any X-bit sequence excluding one or more X-bit special sequences; wherein, the one or more X-bit special sequences are related to the frame header sequence. Preferably, M>=X.

[0099] Please see Figure 4 , Figure 4This application provides a data sequence for the first input sequence and / or a data structure for the first output sequence. Unlike the aforementioned embodiments, it does not include specially inserted identifier data. For example... Figure 4 As shown, multiple sets of basic data are arranged sequentially.

[0100] In the above embodiments, the data actually needed by the receiver is a set of basic data, namely X bits of data. Theoretically, this basic data can represent 2X numbers, which is 0 to 2X-1 in decimal. Another method provided in this embodiment, which makes any consecutive M bits of data in the data sequence different from the frame header sequence, differs from the aforementioned method of setting identifier data. Instead, it does not use identifier data and causes the basic data to discard some values. For example, assuming X=4, the frame header sequence is 0000000, and M=7, the basic data cannot be 0000, but can only be 0001-1111, that is, it can only represent the 15 integers from 1 to 15; or, assuming X=4, the frame header sequence is 1111111, and M=7, the basic data cannot be 1111, but can only be 0000-1110, that is, it can only represent the 15 integers from 0 to 14. When the frame header sequence is other values, one or more values ​​that the basic data needs to discard can be calculated. However, the shorter the frame header sequence, the more values ​​the underlying data needs to discard, meaning there are more special sequences, and the less information the underlying data can convey or represent. For example, suppose X = 4, and the underlying data only takes the values ​​0001, 0101, 1001, and 1101, then only the frame header sequence 1111 is needed.

[0101] In this embodiment, M is preferably greater than or equal to X. However, in practice, M can be less than X. For example, when M = 4 and X = 5, if the frame header is 1111 and the basic data is in the form of zzz00, then there will be no possibility of recognizing any consecutive 4-bit data sequence as the frame header. However, it uses 5 bits to represent 8 data (i.e. 8 pieces of information), resulting in a loss of 24 pieces of information.

[0102] Of course, the values ​​of the frame header sequence can also be calculated by setting the values ​​to be discarded in the basic data. For example, the values ​​of N bits in each group of basic data can be fixed. It should be noted that these N bits are in the same position and have the same value in each group of basic data. For example, each group of basic data is in the form of zzzz01zz, where the value of z is not fixed and is related to the specific data required; the N bits in the first input sequence and the first output sequence are in the same position and have the same value, that is, each group of basic data in the first input sequence and the first output sequence is in the form of zzzz01zz. Preferably, N = 1. For example, the basic data is 3 bits and is in the form of zz0. Then, the original 3 bits of data can represent 8 pieces of information from 0 to 7, but when 1 bit is occupied, it can only represent 4 pieces of information, 0, 2, 4, and 6.

[0103] In other words, the receiver actually needs a set of basic data, i.e., Mbit of data. Theoretically, this basic data can represent 2M numbers, i.e., 0 to 2M-1. Since its N bits of data are the same fixed data, this set of basic data can only represent 2(MN) numbers.

[0104] Taking the format zzz01 as an example, the basic data can only represent a 5-digit sequence ending with 0 or 1, which can only represent 2(5-2) = 8 pieces of information. In this case, if the frame header sequence is 11111 or 00000, since every 5 bits in the data sequence must contain one 1 and one 0, the frame header will definitely be different from any consecutive 5 bits in the data sequence. Of course, the frame header sequence can take other values ​​besides the two possibilities mentioned above. For example, the frame header sequence can also take more than 5 bits, such as 111110, 1111100, etc.

[0105] In this embodiment, by sacrificing the amount of data information that the basic data can represent, the identification data used in the aforementioned embodiments can be avoided, thus reducing the complexity of data processing.

[0106] In some optional implementations, the first input sequence and / or the first output sequence further includes: a P-bit frame tail sequence located at the end of the data sequence;

[0107] The first input sequence and / or the first output sequence satisfy the following condition: when the data sequence length is greater than P, any consecutive P bits of data in the data sequence are not the same as the frame tail sequence.

[0108] The frame header sequence and frame tail sequence are used to characterize the beginning and end of data in a data frame, respectively. In this application, any consecutive P bits of data in the first input sequence and / or the first output sequence are different from the frame tail sequence. That is, when receiving the first input sequence and / or the first output sequence, the data sequence in the sequence will not be mistakenly identified as the frame tail sequence, and the problem of prematurely ending the reception of data and causing the data sequence to be partially truncated will not occur, thus further improving the reliability of data transmission.

[0109] Optionally, the frame tail sequence consists entirely of second code values. For example, all 1s or all 0s.

[0110] For the aforementioned embodiments with identifier sequences, such as Figure 5 As shown, the number of bits (length X) in each group of basic data is less than the number of bits P in the frame tail sequence. Preferably, in this application, P >= X + Z.

[0111] Understandably, there must be an identifier between two sets of basic data. Therefore, any consecutive P bits extracted from the data sequence will necessarily include at least one identifier bit. By properly configuring the identifier and the frame tail sequence, any consecutive P bits in the data sequence can be different from the frame tail sequence, thus preventing the frame tail from being mistakenly identified in the data sequence that actually needs to be transmitted. Understandably, when a frame tail is identified in the data sequence, the reception of the data portion will prematurely end, data reception will be interrupted, and the data received by the receiving end will be incomplete.

[0112] For embodiments without an identifier sequence, preferably, X <= P. Of course, P can also be less than X, in which case the amount of information that the X-bit data sequence can represent will be greatly reduced. The specific selection of identifier data and frame tail sequence follows the same principle as the selection of identifier data and frame header sequence in the aforementioned embodiments without an identifier sequence. This will not be elaborated upon here.

[0113] It should be emphasized again that in this application, the method or means used to ensure that any consecutive P bits of data in the data sequence are different from the frame tail sequence is the same as the method used to ensure that any consecutive M bits of data in the data sequence are different from the frame header sequence.

[0114] When the data sequence uses identifier data, the identifier data and frame tail sequence are configured. For example, the frame header sequence takes the second code value (e.g., 112 bits of 1), the identifier sequence takes the first code value (e.g., 16 bits of 0), and the frame tail sequence takes the second code value (e.g., 144 bits - 160 bits of 1). One set of basic sequences can be selected as 96 bits. In this application, the first and second code values ​​can be represented using binary 0 and 1. When the first code value is 1, the second code value is 0; when the first code value is 0, the second code value is 1.

[0115] It is understandable that the frame tail sequence is related to the identification data. Once the identification data is determined, one or more frame tail sequences that meet the conditions can be derived from it. Of course, feasible identification data can also be derived from a predetermined frame tail sequence, which is more complex than the former and will not be elaborated here.

[0116] When the data sequence does not use an identifier sequence, i.e., some basic data is discarded, the frame tail sequence can be configured according to the configuration method for the frame header sequence mentioned above, which will not be elaborated here.

[0117] Furthermore, in this application, upon receiving the data structure sequence of the first input sequence and / or the first output sequence, after identifying the frame header sequence, the data sequence is read to obtain its corresponding basic data. Once the frame tail sequence is identified, the data sequence is considered read completely. Generally, the frame header and frame tail sequences need to be distinguished, ideally by setting special feature sequences for differentiation. Alternatively, the frame tail sequence can be the same as the frame header sequence, taking all the second code values ​​(for easy distinction, the two should have different bit lengths). For example, the frame header sequence is 112 bits of 1, and the frame tail sequence is 144 bits of 1. In this case, the method for distinguishing the frame header and frame tail varies depending on the selected frame header, frame tail, or the transmission protocol used. For example, when there is no data sequence to send and the first code value is continuously output by the transmitting end, counting can begin when the first code value changes to the second code value and stop when the first code value is received again. The frame tail or frame tail can be determined based on the count value. A count value of M indicates a frame header, and a count value of P indicates a frame tail. This method is particularly suitable for cases where M>=X+Z, P>=X+Z, and P is not equal to M. Furthermore, the greater the difference between P and M, the better, as it indicates higher fault tolerance. Taking the case of continuously outputting 0s from the transmitter when there is no data sequence as an example, a counting method can be used: starting to count when the received data changes from 0 to 1, stopping counting when another 0 is received, and using this counting to determine the frame header and frame tail. Figure 8 For example, when there is no first output sequence to send, and the output is continuously 0, with a frame header of 112 bits, a frame trailer of 144 bits, and an identifier sequence of 16 bits, counting begins when the received data changes from 0 to 1. If 0 is received again, counting stops. When the count reaches 112, it is considered the frame header; if it reaches 144, it is considered the frame trailer. It should be noted that the frame header, frame trailer, and identifier sequence can actually take other values ​​and have different bit lengths. For these different frame headers, frame trailers, and identifier sequences, appropriate methods can be used to identify the frame header and frame trailer. Of course, depending on the transmission method, there are many ways to distinguish the frame header and frame trailer, which will not be elaborated upon here.

[0118] In some optional implementations, the data transmission circuit 100 uses return-to-zero code to transmit data, and distinguishes each bit of data in the first input sequence and / or the first output sequence according to the duty cycle, i.e., whether it belongs to the first code value or the second code value.

[0119] Return-to-zero code refers to an encoding method where the signal level returns to zero within one symbol. Duty cycle refers to the ratio of the high level to the duration of one symbol. When the symbol time is fixed, different duty cycles, i.e., different high level durations / lengths, mean that this application actually distinguishes the first code value and the second code value based on the length of the high / low level within one symbol time.

[0120] For example, Figure 6 The form of the data transmitted by the data transmission circuit of this application is given. Within one symbol (within one period T), the high voltage level recovers to zero. Figure 6 In the provided embodiments, a duty cycle of 3 / 4 represents data 1, and a duty cycle of 1 / 4 represents data 0. That is, this application distinguishes between 0 and 1 codes based on the length of the high / low level time within a symbol. It should be noted that the duty cycle representing 1 and the duty cycle representing 0 are not necessarily 3 / 4 and 1 / 4 respectively as described above, but can be set as needed.

[0121] In some optional implementations, the data sequence of the first input sequence and / or the data sequence of the first output sequence further includes:

[0122] A configuration sequence, which serves as functional configuration data and / or instruction data.

[0123] When data transmission circuits are applied in different scenarios, different application scenarios require different configuration data and / or instructions to complete the functions under various application scenarios using basic data. That is, the data sequence also includes a configuration sequence, which can serve as functional configuration data and / or instruction data to configure or control the functions of the subsequent receiver.

[0124] Since the configuration sequence is included in the data sequence, the data sequence containing it also satisfies the aforementioned conditions, namely, the data sequence satisfies that: any consecutive M bits of data in the data sequence are not the same as the frame header sequence and / or any consecutive P bits of data in the data sequence are not the same as the frame tail sequence.

[0125] Optionally, the sequence can be configured as Q bits, which can be located at the beginning or end of the data sequence. For example... Figure 8 As shown, the configuration sequence is located at the beginning of the data sequence, that is, immediately following the frame header sequence. This configuration sequence is register data. Figure 8 The system contains three registers, each containing 16 bits of data. Optionally, regardless of the actual number of base data sets, the data sequences of both the first input sequence and / or the first output sequence include the same Q-bit configuration sequence.

[0126] In some possible implementations, when the transmitting end has no first output sequence to send, the transmitting end outputs a second output sequence until the transmitting end starts sending the first output sequence, wherein any consecutive M bits of data in the second output sequence are different from the frame header sequence; or, when the transmitting end needs to send the first output sequence, the transmitting end outputs the second output sequence first and then sends the first output sequence; wherein any consecutive M bits of data in the second output sequence are different from the frame header sequence.

[0127] In this application, when idle (i.e. when no data, function configuration data, or instruction data is being sent), the data transmission circuit can adopt the following two working modes: (1) It continues to output data (second output sequence) without interruption. This data can be any data, as long as any consecutive M bits of data are not the same as the frame header sequence (of course, any consecutive P bits of data can also be different from the frame tail sequence at the same time, but this is not a necessary condition); this can prevent the receiver from misidentifying the data sent during idle time as the frame header, thereby performing incorrect data transmission and reception; (2) When the first output sequence needs to be sent (i.e. when data, function configuration data, and instruction data are being sent), data (second output sequence, which can be any data, as long as any consecutive M bits of data are not the same as the frame header sequence, of course, any consecutive P bits of data can also be different from the frame tail sequence at the same time, but this is not a necessary condition) is output to the outside through the output terminal a certain time before the first output sequence is sent, and then the first output sequence is sent.

[0128] Both of these modes ensure that the receiver's decoding circuit can operate for a period of time or remain in a continuous operating state before receiving the actual data (the data sequence in the first output sequence), thus ensuring a stable and reliable operating phase and guaranteeing the reliability of the received data when receiving the actual data.

[0129] For example, in the first mode, when the frame header sequence is M bits 0, it is necessary to ensure that no consecutive M bits of data in the second output sequence are all 0. For instance, when there is no data to be sent (basic data group), the sending module continuously outputs 1. Or, when the frame header sequence is M bits 1, it is necessary to ensure that no consecutive M bits of data in the second output sequence are all 1. For instance, when there is no data to be sent, the sending module continuously outputs 0. Of course, the form of the second output sequence is not limited to the above examples, and this application does not limit it here.

[0130] For example, in the second mode, irrelevant data (the second output sequence) is sent before the first output sequence is sent, after which the first output sequence is sent. It should be noted that the irrelevant data can be sent before the first output sequence is sent, or the timing can be omitted, and the irrelevant data is a fixed sequence, which is sent first, followed by the first output sequence.

[0131] In this application, the aforementioned irrelevant data (second output sequence) can be any data, as long as any consecutive M bits of data are not the same as the frame header sequence.

[0132] Secondly, this application also provides a constant current driving chip, which includes the data transmission circuit 100 described in the first aspect. The constant current driving chip obtains a set of basic data corresponding to the constant current driving chip based on a first input sequence received by the data transmission circuit 100; the constant current driving chip outputs a constant current based on the corresponding set of basic data.

[0133] The constant current driver chip provided in this embodiment can be used to generate a PWM signal based on display data, thereby outputting a constant current to drive the connected LED beads to emit light. It can be applied to the driving of LED displays.

[0134] After receiving the first input sequence at the input terminal of its data transmission circuit 100, the constant current driver chip needs to acquire its own required data (including a set of basic data). This acquired set of basic data is the display data, which can be considered as data used to control multiple channels of the constant current driver chip. Assuming a constant current driver chip has 6 channels and a set of basic data is 96 bits, then each channel corresponds to 16 bits of data (high-order bits first, low-order bits last). The PWM generation module of the constant current driver chip generates a PWM signal based on the display data (16 bits of data corresponding to each channel), thereby controlling the output constant current of each channel to control the lighting of an LED bead electrically connected to that channel. More specifically, this 16-bit data can be used to control the lighting time of the LED bead corresponding to that channel.

[0135] Understandably, by using the aforementioned data transmission circuit 100, it can be ensured that the data received by the constant current drive chip is complete, thereby further ensuring that the set of basic data (i.e. display data) it obtains is accurate, and thus guaranteeing the LED display effect.

[0136] Please continue to explain. Figure 3a For example, when the constant current drive chip receives the first input sequence, the first set of basic data after the frame header sequence is its corresponding display data.

[0137] In some optional implementations, the constant current driving chip truncates the first input sequence to obtain a set of basic data corresponding to the constant current driving chip;

[0138] When the first input sequence after truncation still contains basic data groups, the data transmission circuit outputs the remaining basic data groups through the transmitting end.

[0139] After receiving the first input sequence, the constant current driver chip decodes it. After recognizing the frame header, it begins to read the data sequence. The first set of basic data after the frame header is the corresponding display data. The constant current driver chip truncates the first input sequence to obtain the corresponding set of display data.

[0140] Let Series represent the first input sequence that has not been truncated. When the truncated first input sequence Series* still contains basic data groups, it indicates that there are subsequent receivers (specifically, other constant current driver chips) that need the aforementioned basic data groups for display. At this time, the constant current driver chip processes the truncated first input sequence Series* (processed by the constant current driver chip's data processing module), including deleting certain sequences (e.g., identifier sequences) and / or adding certain sequences (e.g., identifier sequences) and / or reconstructing sequences, reconstructing it into the aforementioned first output sequence that conforms to certain standards, to ensure the accuracy and completeness of the data received by subsequent receivers. For example, such as... Figure 8 As shown, after extracting the first set of basic data (96 bits), the subsequent set of identifier data (16 bits) is deleted. The sequence preceding the first set of basic data in the Series (e.g., the frame header sequence and configuration sequence (Q bits), for example...) Figure 8 The 48-bit configuration sequence of the three registers is recombined with the original first data group after removing one set of identifier data to form the first output sequence. In other words, the first output sequence transmitted by the output transmission circuit also includes the aforementioned configuration sequence, the remaining basic data group, and identifier data (not necessarily required).

[0141] The following is a brief description of the operation of the constant current driver chip in this application. Each driver chip (LED constant current driver chip) can generate a PWM signal based on its corresponding set of display data to drive the LED display screen for display. Specifically, after extracting the corresponding set of basic data (display data) from the first input sequence received by the receiving end (the data processing module of the constant current driver chip extracts the data), the data processing module sends the data to the PWM generation module of the constant current driver chip to generate a PWM signal. The constant current source output channel outputs a constant current according to the PWM signal, thereby controlling the LED beads electrically connected to each channel to light up (the lighting time is related to the high level time of the PWM signal, that is, the LED lights up when the PWM is high).

[0142] Optionally, each group of basic data has the same number of bits, which is 8 / 16 / 24 / 32 / 64 / 96 bits. Preferably, each group of basic data (each group of display data) is 96 bits, corresponding to the display data of 6 constant current channels (16 bits per channel). The 16 bits of display data corresponding to each channel are used to control the constant current output of that channel, so as to control the lighting of the LED beads electrically connected to that output channel. The 16 bits of display data can be in the order of most significant digits first and least significant digits last.

[0143] Thirdly, this application provides a display system including K constant current driving chips as described in the second aspect above;

[0144] K constant current driver chips are cascaded together; the transmitting end of the previous constant current driver chip outputs a first output sequence to the next level driver chip, and the first output sequence serves as the first input sequence of the next level constant current driver chip.

[0145] These multiple constant current driver chips are cascaded together, that is, they use a single-wire serial cascading method for data transmission and configuration commands, such as... Figure 7 As shown.

[0146] Figure 7 This is a display system using K LED driver chips. Each chip drives two groups of RGB LEDs, totaling six LEDs.

[0147] The receiving card receives the raw display data, processes it, and then sends the aforementioned first input sequence to the first constant current driver chip CHIP0 (the receiving card has a data processing module that can encode the raw display data, thereby transforming it into the initial first input sequence that meets the aforementioned first aspect requirements). See also Figure 8 The first input sequence includes K sets of basic data corresponding to K (K>=2) cascaded constant current driver chips, namely S0, S1, ..., SK-1, corresponding to CHIP0 to CHIPK-1 respectively. The first input sequence contains K sets of identifier data, all of which are 16 bits of all zeros. After receiving the first input sequence, CHIP0 extracts S0 to light up the 6 connected LED beads. The first input sequence after extracting S0 is reconstructed into a first output sequence (including the sequence S1, ..., SK-1, with the original identifier data retained between S1, ..., SK-1) that meets the aforementioned first requirement. This output sequence is then output to the next-level driver chip CHIP1, ..., and so on, until CHIPK-1 receives the last set of basic data SK-1. It can be understood that this application uses a single-wire serial cascade method for data transmission and configuration instructions, sending the data from CHIP0 first, ..., and finally the data from CHIPK-1. Furthermore, it eliminates the need for a separate data line to transmit the clock signal, saving lines and costs.

[0148] In some optional implementations, when the previous-level constant current driver chip has no first output sequence to send to the next-level constant current driver chip, the previous-level constant current driver chip outputs a second output sequence until the previous-level constant current driver chip starts sending the first output sequence; or, before the previous-level constant current driver chip needs to send the first output sequence to the next-level constant current driver chip, the previous-level constant current driver chip first outputs a second output sequence to the next-level constant current driver chip and then sends the first output sequence; any consecutive M bits of data in the second output sequence are different from the frame header sequence.

[0149] As mentioned earlier, this ensures that the decoding circuit of the subsequent constant current drive chip is in a stable working state before receiving display data, thus guaranteeing the reliability and accuracy of display data reception.

[0150] In some alternative implementations, the constant current drive chip determines its own position based on the received first input sequence, and determines the time to use the corresponding set of basic data for display based on its own position.

[0151] The first input sequence includes an identifier data group and a basic data group, both of which are related to each cascaded chip. For example, the basic data group corresponds one-to-one with each cascaded chip, while the identifier data group is also related to the number of cascaded chips (the number of identifier data groups can be equal to the number of chips, or one less or one more). Each constant current driver chip can calculate the number of chips cascaded after it based on its own position, thereby calculating the time when all chips receive their respective display data. When all chips receive their corresponding display data, each chip can determine when to output a constant current based on the received display data, thereby driving the LED to light up. In this way, synchronous display can be achieved without a separate data line to transmit the clock signal.

[0152] In some optional implementations, after the constant current driving chip identifies the frame header sequence, it starts counting the number of basic data groups in the first input sequence to obtain a first count value; after identifying the frame tail sequence, the constant current driving chip determines the time for displaying the basic data corresponding to the constant current driving chip based on the first count value.

[0153] refer to Figures 7-8Taking CHIP0 as an example, after receiving the first input sequence, CHIP0 first receives the frame header sequence (e.g., 112 bits all 1s). When the decoding circuit recognizes the frame header sequence, it begins data reading. Following the frame header sequence are register data (three registers, each 16 bits), which is the aforementioned Q-bit configuration sequence. Next, it recognizes the first group of basic data following the frame header sequence (each group of display data has the same number of bits, e.g., 96 bits; the first group of basic data is the display data of CHIP0), then recognizes the second group of basic data (i.e., the display data of CHIP1), and so on, and then recognizes the Kth group of basic data (i.e., the display data of CHIPK-1). When the frame end sequence (e.g., 144 bits all 1s) is detected, CHIP0 considers the data reading to be complete. During the aforementioned data reading process, the total number of basic data sets in the first input sequence can be counted. This allows determining CHIP0's position within the cascaded constant current driver chips and the number of subsequent constant current driver chips. Consequently, the time when the last constant current driver chip receives the last set of basic data (i.e., the time when all driver chips receive their respective display data) can be estimated. In this way, each constant current driver chip can know the time when the last constant current driver chip receives the last set of basic data, and based on this, control the display time of each constant current driver chip based on its corresponding set of basic data, i.e., control the lighting of the LEDs electrically connected to it, thus achieving synchronization of the cascaded LED driver chips. Therefore, the frame end sequence function, in addition to indicating the end of the standard data sequence, also has a delay synchronization function.

[0154] In summary, the data transmission circuit, constant current drive chip, and display system provided in this application can ensure the reliability and accuracy of data transmission and reception. At the same time, the constant current drive chip and display system can guarantee the display effect of the LED display screen, and can also use a single-wire transmission method, which can save data cables and consumables, while ensuring synchronous display.

[0155] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0156] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A data transmission circuit, characterized in that, include: The receiving end is used to receive the first input sequence; The sending end is used to output the first output sequence; The first input sequence and the first output sequence have a unified data structure, and both the first input sequence and the first output sequence satisfy the following: they sequentially include a frame header sequence and a data sequence. When the length of the data sequence is greater than M, any M consecutive data bits in the data sequence are different from the frame header sequence, wherein the length of the frame header sequence is M; The data sequence includes: a basic data group; each basic data group can be selected as any X-bit sequence excluding one or more X-bit special sequences; wherein, the one or more X-bit special sequences are related to the frame header sequence.

2. The data transmission circuit according to claim 1, characterized in that, M>=X.

3. The data transmission circuit according to claim 1, characterized in that, The values ​​that need to be discarded in the basic data are deduced from the frame header sequence.

4. The data transmission circuit according to claim 1, characterized in that, The values ​​of the frame header sequence are calculated by setting the values ​​to be discarded from the basic data.

5. The data transmission circuit according to any one of claims 1-4, characterized in that, The first input sequence and / or the first output sequence further includes: a P-bit frame tail sequence located at the end of the data sequence; The first input sequence and / or the first output sequence satisfy the following condition: when the length of the data sequence is greater than P, any consecutive P bits of data in the data sequence are not the same as the frame tail sequence.

6. The data transmission circuit according to claim 5, characterized in that, The data sequence of the first input sequence and / or the data sequence of the first output sequence further include: A configuration sequence, which serves as functional configuration data and / or instruction data.

7. The data transmission circuit according to claim 5, characterized in that, When the transmitting end has no first output sequence to send, the transmitting end outputs a second output sequence until the transmitting end starts sending the first output sequence. Any consecutive M bits of data in the second output sequence are different from the frame header sequence. Alternatively, when the transmitting end needs to send the first output sequence, the transmitting end outputs the second output sequence and then sends the first output sequence; any consecutive M bits of data in the second output sequence are different from the frame header sequence.

8. The data transmission circuit according to claim 5, characterized in that, The data transmission circuit uses return-to-zero code to transmit data, and distinguishes each bit of data in the first input sequence and / or the first output sequence according to the duty cycle.

9. A constant current driving chip, characterized in that, The constant current drive chip includes the data transmission circuit as described in any one of claims 1-8; The constant current driver chip obtains a set of basic data corresponding to the constant current driver chip based on the first input sequence received by the data transmission circuit. The constant current drive chip outputs a constant current based on the corresponding set of basic data.

10. The constant current driving chip according to claim 9, characterized in that, The constant current driver chip extracts the first input sequence to obtain a set of basic data corresponding to the constant current driver chip; When the first input sequence after truncation still contains basic data groups, the data transmission circuit outputs the remaining basic data groups through the transmitting end.

11. A display system, characterized in that, It includes K constant current driving chips as described in any one of claims 9-10; the K constant current driving chips are cascaded; the upper-level constant current driving chip outputs a first output sequence to the lower-level constant current driving chip, and the first output sequence serves as the first input sequence of the lower-level constant current driving chip.

12. The display system according to claim 11, characterized in that, The constant current drive chip determines its own position based on the received first input sequence, and then determines the time to use the corresponding set of basic data for display based on its own position.

13. The display system according to claim 12, characterized in that, After the constant current driver chip recognizes the frame header sequence, it starts counting the number of basic data groups in the first input sequence to obtain a first count value; after recognizing the frame tail sequence, the constant current driver chip determines the time to use the basic data corresponding to the constant current driver chip for display based on the first count value.

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