Display panel, display device, and method of manufacturing display panel

Abstract

The display panel, the display device and the manufacturing method of the display panel are provided. The display panel comprises a substrate substrate; a pixel circuit arranged on the substrate substrate, the pixel circuit comprising a transistor, the transistor comprising an active layer, a gate, a first electrode and a second electrode; and a fingerprint identification circuit, the fingerprint identification circuit comprising a photosensitive circuit, a storage circuit and an output circuit, the storage circuit comprising a first capacitor, the first capacitor comprising a first capacitor electrode and a second capacitor electrode; the first capacitor electrode is arranged in the same layer as at least one of the gate, the active layer, the first electrode or the second electrode, and / or the second capacitor electrode is arranged in the same layer as at least one of the gate, the active layer, the first electrode or the second electrode; the first capacitor electrode and the second capacitor electrode are arranged in different layers, and the orthographic projection of the first capacitor electrode and the second capacitor electrode on the substrate substrate at least partially overlaps.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel, a display device, and a method for manufacturing the display panel. Background Technology

[0002] Organic Light Emitting Diode (OLED) display technology is gradually being widely adopted, becoming the most promising replacement for Liquid Crystal Display (LCD). Compared to LCD, OLED offers a superior user experience in terms of image quality, response speed, and thinness. OLED also boasts higher screen transmittance, enabling under-display and in-screen fingerprint recognition.

[0003] One of the key challenges of in-display fingerprint recognition technology is its resistance to strong light. Under strong light, the sensor cannot distinguish the signal differences corresponding to the valleys and ridges of the finger, causing the sensor to malfunction. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a display panel, a display device, and a method for manufacturing a display panel to meet the requirements for in-screen fingerprint recognition under strong light.

[0005] On one hand, embodiments of this disclosure provide a display panel, including: a substrate; a pixel circuit disposed on the substrate, the pixel circuit including transistors, the transistors of the pixel circuit including an active layer, a gate, a first electrode, and a second electrode; and a fingerprint recognition circuit, the fingerprint recognition circuit including a photosensitive circuit, a storage circuit, and an output circuit, the storage circuit including a first capacitor, the first capacitor including a first capacitor electrode and a second capacitor electrode; wherein, the photosensitive circuit is configured to convert a received optical signal into an electrical signal, the storage circuit is configured to store the electrical signal, and the output circuit includes a control switch, the control switch being configured to control the photosensitive circuit to charge the storage circuit in an open state, and to output at least the stored electrical signal in a closed state, so as to perform fingerprint recognition based on the output electrical signal; wherein, the first capacitor electrode is disposed in the same layer as at least one of the gate, the active layer, the first electrode, or the second electrode, and / or, the second capacitor electrode is disposed in the same layer as at least one of the gate, the active layer, the first electrode, or the second electrode; the first capacitor electrode and the second capacitor electrode are disposed in different layers, and the orthogonal projections of the first capacitor electrode and the second capacitor electrode on the substrate at least partially overlap.

[0006] In some embodiments, the gate includes a first gate line and a second gate line, the first gate line and the second gate line being in different layers; and a first capacitor electrode is disposed in the same layer as the first gate line or the second gate line, and a second capacitor electrode is disposed in the same layer as the first gate line or the second gate line.

[0007] In some embodiments, the display panel further includes: a first gate dielectric layer disposed between the active layer and the first gate line; a second gate dielectric layer disposed between the first gate line and the second gate line; and an interlayer dielectric layer disposed on the side of the second gate dielectric layer away from the substrate.

[0008] In some embodiments, the first capacitor electrode is connected to the first electrode through a first via, the first via being disposed in the second gate dielectric layer and the interlayer dielectric layer; or the second capacitor electrode is connected to the first electrode through a second via, the second via being disposed in the interlayer dielectric layer, the second via exposing the second capacitor electrode.

[0009] In some embodiments, the gate includes a first gate line and a second gate line, the first gate line and the second gate line are in different layers; and the first capacitor electrode is disposed in the same layer as the first gate line or the second gate line, and the second capacitor electrode is disposed in the same layer as the active layer.

[0010] In some embodiments, the first capacitor electrode is disposed in the same layer as at least one of the gate, active layer, or first electrode, and the second capacitor electrode is disposed in the first metal layer, wherein the first metal layer is located in a different layer from the gate, active layer, and first electrode; or the second capacitor electrode is disposed in the same layer as at least one of the gate, active layer, or first electrode, and the first capacitor electrode is disposed in the second metal layer, wherein the second metal layer is located in a different layer from the gate, active layer, and first electrode.

[0011] In some embodiments, the first capacitor electrode is disposed on the same layer as the first electrode, and the second capacitor electrode is disposed on the side of the photosensitive circuit away from the substrate. There is a distance between the second capacitor electrode and the orthographic projection of the photosensitive circuit on the substrate.

[0012] In some embodiments, the display panel further includes: an interlayer dielectric layer disposed on the side of the gate away from the substrate; an insulating layer having a first thickness greater than a second thickness of the interlayer dielectric layer; a first electrode including: a first sub-electrode disposed on the side of the interlayer dielectric layer away from the substrate; a second sub-electrode disposed on the side of the first sub-electrode away from the substrate, the insulating layer being disposed between the first sub-electrode and the second sub-electrode; and a photosensitive circuit disposed on the side of the second sub-electrode away from the substrate.

[0013] In some embodiments, the storage circuit further includes at least one second capacitor connected in parallel with the first capacitor, each of the at least one second capacitor including a third electrode and a fourth electrode.

[0014] In some embodiments, the third electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode, and the fourth electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode; the third electrode and the fourth electrode are disposed in different layers, and the orthogonal projections of the third electrode and the fourth electrode on the substrate at least partially overlap.

[0015] In some embodiments, the third electrode is disposed in the same layer as at least one of the gate, active layer, or first electrode, and the fourth electrode is disposed in the third metal layer, which is located in a different layer from the gate, active layer, and first electrode; or the fourth electrode is disposed in the same layer as at least one of the gate, active layer, or first electrode, and the fourth electrode is disposed in the fourth metal layer, which is located in a different layer from the gate, active layer, and first electrode.

[0016] In some embodiments, the gate includes a first gate line and a second gate line, which are located on different layers; the third electrode is disposed on the same layer as the first gate line or the second gate line, and the fourth electrode is disposed on the same layer as the first gate line or the second gate line, which are located on different layers.

[0017] In some embodiments, the display panel further includes: a plurality of pixel units disposed on a substrate, the plurality of pixel units being arranged in an array on the substrate, and the orthographic projections of the pixel units and the photosensitive circuit on the substrate overlapping.

[0018] In some embodiments, the pixel unit includes at least one sub-pixel, each sub-pixel includes a light-emitting element, the light-emitting element includes an anode; and the pixel circuit includes a sub-pixel driving circuit, the first electrode of the transistor of the sub-pixel driving circuit being connected to the anode.

[0019] In some embodiments, the output circuit includes a first transistor, and the sub-pixel driving circuit includes at least one second transistor; wherein the first electrode of the first transistor and the first electrode of the second transistor are disposed on the same layer; and / or the gate of the first transistor and the gate of the second transistor are disposed on the same layer; and / or the active layer of the first transistor and the active layer of the second transistor are disposed on the same layer.

[0020] In some embodiments, the photosensitive circuitry includes a PIN photodiode.

[0021] In some embodiments, the display panel further includes a transparent conductive layer disposed on the side of the PIN photodiode away from the substrate, the transparent conductive layer being connected to a bias-introduced electrode.

[0022] On the other hand, embodiments of this disclosure provide a display device. The display device includes a display panel as described in any of the above embodiments.

[0023] On the other hand, embodiments of this disclosure provide a method for manufacturing a display panel, comprising: providing a substrate; disposing a pixel circuit on the substrate, the pixel circuit including a gate, an active layer, a first electrode, and a second electrode; disposing a fingerprint recognition circuit; the fingerprint recognition circuit including a photosensitive circuit, a storage circuit, and an output circuit, the storage circuit including a first capacitor, the first capacitor including a first capacitor electrode and a second capacitor electrode; the transistor of the output circuit being disposed on the same layer as the transistor of the pixel circuit; wherein, the photosensitive circuit is configured to convert a received optical signal into an electrical signal, the storage circuit is configured to store the electrical signal, and the output circuit includes a control switch, the control switch being configured to control the photosensitive circuit to charge the storage circuit in an open state, and to output at least the stored electrical signal in a closed state, so as to perform fingerprint recognition based on the output electrical signal; wherein, the first capacitor electrode is disposed on the same layer as at least one of the gate, the active layer, the first electrode, or the second electrode, and / or, the second capacitor electrode is disposed on the same layer as at least one of the gate, the active layer, the first electrode, or the second electrode; the first capacitor electrode and the second capacitor electrode are disposed on different layers, and the orthogonal projections of the first capacitor electrode and the second capacitor electrode on the substrate at least partially overlap.

[0024] In some embodiments, the first capacitor electrode and the second capacitor electrode are manufactured by: forming a fifth metal layer and patterning the fifth metal layer to form the first capacitor electrode and the first gate line; forming a second gate dielectric layer; forming a sixth metal layer and patterning the sixth metal layer to form the second capacitor electrode and the second gate line; a first width of the first capacitor electrode in a cross-section perpendicular to the extension direction of the first gate line being greater than a second width of the second capacitor electrode in a cross-section perpendicular to the extension direction of the second gate line; forming an interlayer dielectric layer and forming vias in areas where the projections of the first capacitor electrode and the second capacitor electrode on the substrate do not overlap to expose the first capacitor electrode; and forming a first electrode such that the first capacitor electrode and the first electrode are electrically connected.

[0025] In some embodiments, the first capacitor electrode and the second capacitor electrode are manufactured by: forming an active layer; patterning the active layer to form a patterned active layer, the patterned active layer including an electrically connected first patterned region and a second patterned region, the first patterned region corresponding to the active layer of the transistor in the output circuit, and the second patterned region corresponding to the first capacitor electrode; sequentially forming a first gate dielectric layer, a first gate line, a second gate dielectric layer, and a seventh metal layer; and patterning the seventh metal layer to form the second capacitor electrode and the second gate line.

[0026] In some embodiments, the first capacitor electrode and the second capacitor electrode are manufactured by: forming an eighth metal layer; patterning the eighth metal layer to form a patterned eighth metal layer, the patterned eighth metal layer including an electrically connected third patterned region and a fourth patterned region, the third patterned region corresponding to the first electrode of the transistor of the output circuit, and the fourth patterned region corresponding to the first capacitor electrode; sequentially forming a photosensitive circuit, a dielectric layer and a ninth metal layer; and patterning the ninth metal layer to form the second capacitor electrode.

[0027] In some embodiments, the method of manufacturing the display panel further includes: forming at least one second capacitor connected in parallel with the first capacitor, each of the at least one second capacitor including a third electrode and a fourth electrode; the third electrode and the fourth electrode are manufactured in the same way as the first capacitor electrode and the second capacitor electrode. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0029] Figure 1 This is a structural diagram of a display panel provided according to an embodiment of the present disclosure;

[0030] Figure 2 This is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0031] Figure 3 and Figure 4 This is a schematic diagram illustrating the working principle of a fingerprint sensor according to an embodiment of the present disclosure;

[0032] Figure 5 This is a schematic diagram of fingerprint recognition in a display panel according to some embodiments of the present disclosure;

[0033] Figure 6 and Figure 7 A method provided according to some embodiments of this disclosure Figure 5 A schematic diagram of the fingerprint valleys and ridges reflecting light in a fingerprint sensor;

[0034] Figure 8 A circuit diagram of a fingerprint recognition circuit provided according to an embodiment of the present disclosure;

[0035] Figure 9 A circuit diagram of a fingerprint recognition circuit provided according to another embodiment of the present disclosure;

[0036] Figure 10 This is a schematic diagram of the structure of a display panel provided according to an embodiment of the present disclosure;

[0037] Figure 11 For embodiments provided in accordance with this disclosure Figure 10 A planar design of all film layers with gate1 and gate2 as the capacitor electrodes;

[0038] Figure 12 For embodiments provided in accordance with this disclosure Figure 10 A planar design diagram of a poly Si, gate1, gate2, SD, and ILD layer with gate1 and gate2 as the capacitor electrodes;

[0039] Figure 13 This is a schematic diagram of the structure of a display panel provided according to an embodiment of the present disclosure;

[0040] Figure 14 For embodiments provided in accordance with this disclosure Figure 13 A planar design of all film layers with polySi and gate2 as the capacitor electrodes;

[0041] Figure 15 For embodiments provided in accordance with this disclosure Figure 13 A planar design diagram of a capacitor consisting of polySi, gate1, gate2, SD, and ILD layers, with polySi and gate2 as the capacitor electrodes.

[0042] Figure 16 This is a schematic diagram of the structure of a display panel provided according to an embodiment of the present disclosure;

[0043] Figure 17 For embodiments provided in accordance with this disclosure Figure 16 A planar design of all film layers with SD2 and the newly added metal as the two electrodes of the capacitor;

[0044] Figure 18 For embodiments provided in accordance with this disclosure Figure 16 A planar design diagram of a capacitor with poly Si and gate2 as the two electrodes, including SD2, metal, and anode layers;

[0045] Figure 19 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure; and

[0046] Figure 20 A block diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0047] To more clearly illustrate the purpose, technical solutions, and advantages of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the following description of the embodiments is intended to explain and illustrate the overall concept of this disclosure and should not be construed as limiting the disclosure. In the specification and drawings, the same or similar reference numerals refer to the same or similar parts or components. For clarity, the drawings are not necessarily drawn to scale, and some well-known parts and structures may be omitted from the drawings.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” “right,” “top,” or “bottom,” etc., are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described object changes. When an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0049] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0050] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0052] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0053] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0054] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0055] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0056] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0057] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0058] As used herein, “about” or “approximately” includes the value stated and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0059] As used herein, the same reference numerals can refer to both signal lines and signal terminals, as well as the signals corresponding to signal lines and signal terminals.

[0060] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0061] Embodiments of this disclosure provide a display device, which may be, for example, either an OLED display device or a QLED (Quantum Dot Light Emitting Diodes) display device.

[0062] The following section uses an OLED display device as an example to introduce the structure of the display device.

[0063] Figure 1 This is a structural diagram of a display panel provided according to an embodiment of the present disclosure.

[0064] like Figure 1 As shown, the display panel 1 includes a display area 10 and a non-display area 11 located around the display area 10. Multiple pixel units arranged in an array are disposed in the display area 10, and each pixel unit may include one or more sub-pixels P. Each sub-pixel P is provided with a pixel driving circuit 12 and a light-emitting device D coupled to the pixel driving circuit 12. A gate driving circuit 13 is disposed in the non-display area 11, and the output terminal of the gate driving circuit 13 is coupled to a gate line 1330. Pixel driving circuits 12 located in the same row are coupled to the same gate line 1330. In this display panel 1, since all the thin-film transistors in the gate driving circuit 13 are located in the non-display area 11, they occupy a large area in the non-display area 11, resulting in a large area of ​​the non-display area 11, for example, a long length and width.

[0065] Figure 2 This is a structural diagram of a display panel provided according to another embodiment of the present disclosure.

[0066] like Figure 2 As shown, the display panel 1' has a display area 10 and a non-display area 11. The non-display area 11 is, for example, arranged around the display area 10.

[0067] The display panel 1' includes: a substrate, a plurality of pixel units disposed on the substrate, and a gate driving circuit 13. Each pixel unit may include one or more sub-pixels P. The plurality of pixel units are arranged in an array on the substrate, and each pixel unit includes at least one sub-pixel P. Each sub-pixel P includes a light-emitting element D located in a light-emitting area and a pixel driving circuit 12 located in a non-light-emitting area.

[0068] The gate driving circuit 13 includes multiple cascaded shift registers and multiple gate lines. One shift register is coupled to multiple pixel driving circuits 12 in at least one row of pixel units through at least one gate line. The shift register is used to provide gate driving signals to the multiple pixel driving circuits 12 through at least one gate line.

[0069] The pixel driving circuit 12 can be a 2T1C type pixel driving circuit, a 3T1C type pixel driving circuit, or a 7T1C type pixel driving circuit, where T represents a thin-film transistor (TFT) and C represents a storage capacitor. The 2T1C type includes two TFTs and one storage capacitor in the pixel driving circuit 12, and so on.

[0070] Figure 2At least one first thin-film transistor group 131 is located in the display area 10 and distributed between adjacent sub-pixels P in the same row of sub-pixels, wherein each first thin-film transistor group 131 includes, for example, one first thin-film transistor.

[0071] exist Figure 2 In the display area 10, all the first thin-film transistor groups 131 included in the gate drive circuit 13 are located in the display area 10, and the first thin-film transistor groups 131 included in each shift register are distributed in the area between adjacent sub-pixels P in the same row of sub-pixels P.

[0072] The control signal line 132 or the connecting line 133 may be made of a metallic material, such as molybdenum (Mo), titanium (Ti), copper (Cu), silver (Ag), or aluminum (Al). The control signal line may be a multilayer metal structure, which is not limited here.

[0073] In some embodiments, the light emitted by the light-emitting device D is directed toward the side away from the substrate. The display panel 1' of this structure is a top-emitting display panel. In the top-emitting display panel, the orthographic projection of the portion of the gate driving circuit 13 located in the display area 10 onto the substrate can overlap with the orthographic projection of the light-emitting device D onto the substrate, without affecting the aperture ratio of the display panel 1'.

[0074] Regardless of whether the display panel 1' is a bottom-emitting or top-emitting display panel, the structure of the display panel 1' is as follows: Figure 10 As shown, along the thickness direction of the display panel 1', the display panel 1' may include a light-shielding layer, a buffer layer, a thin-film transistor, an anode, and a planarization layer disposed on a substrate. Among them, the thin-film transistor is the driving transistor T3 in the pixel driving circuit 12, which includes, for example, a first active layer, a first gate insulating layer, a gate, an interlayer insulating layer, an SD layer (source-drain layer), and a passivation layer.

[0075] The display panel 1' may also include a light-shielding layer, the material of which is, for example, a light-shielding material, such as a black matrix material or a metal material. Figure 10 Taking a metallic material as an example, the light-shielding layer needs to be coupled to the SD layer to form a structure similar to a dual-channel structure, thereby improving the electrical performance of the thin-film transistor. The light-shielding layer is configured to prevent light incident from the substrate from affecting the first active layer, thus impacting the performance of the thin-film transistor.

[0076] The material of the first active layer can be, for example, a metal oxide, polycrystalline silicon, or amorphous silicon; the metal oxide is, for example, indium gallium zinc oxide.

[0077] The gate material can be, for example, a metallic material, such as tungsten, molybdenum, titanium, copper, silver, or aluminum, and its structure can be, for example, a single-layer structure.

[0078] The material of the SD layer can be a metal, such as tungsten, molybdenum, titanium, copper, silver, aluminum, etc., and its structure can be a single layer or a multilayer structure.

[0079] The materials of the buffer layer, the first gate insulating layer, the interlayer insulating layer, and the passivation layer are, for example, inorganic insulating materials. For example, inorganic insulating materials include, but are not limited to, at least one of silicon oxide (SiOx) and silicon nitride (SiN).

[0080] The anode material is, for example, a conductive material, including ITO, which can be a single-layer structure or a multilayer structure.

[0081] The planarization layer is made of an organic material, such as polyimide (PI), and serves a planarization function.

[0082] Figure 3 and Figure 4 This is a schematic diagram illustrating the working principle of a fingerprint sensor according to an embodiment of the present disclosure.

[0083] like Figure 3 and Figure 4 As shown, light incident on the fingerprint 500 is reflected by the fingerprint 500, and the reflected light is converted into an electrical signal in the photosensitive unit. At this time, the lead-out electrode connected to the photosensitive unit can act as a receiving electrode to receive the electrical signal generated by the photosensitive unit. Since the fingerprint 500 includes valleys 510 and ridges 520, their light reflection capabilities are different (valleys 510 have a stronger light reflection capability), resulting in different intensities of light reflected back by the valleys 510 and ridges 520. Therefore, the intensity of the light reflected can be determined by the electrical signal received by the receiving electrode, indicating whether the light was reflected by a valley or a ridge.

[0084] Figure 5 This is a schematic diagram of a fingerprint recognition circuit in a display panel according to some embodiments of the present disclosure. Figure 5 As shown, the fingerprint recognition structure includes multiple photosensitive units 50. When a fingerprint comes into contact with the substrate, light is reflected by the fingerprint 500, and the reflected light is converted into an electrical signal by the photosensitive unit 50. At this time, the receiving electrode receives the electrical signal, thereby realizing the reception of the electrical signal generated by the photosensitive unit 50 at different positions.

[0085] Figure 6 and Figure 7 A method provided according to some embodiments of this disclosure Figure 5 A schematic diagram of the fingerprint valleys and ridges reflecting light in a fingerprint sensor.

[0086] like Figure 6 and Figure 7As shown, since the fingerprint 500 includes valleys 510 and ridges 520, their light-reflecting abilities differ (for example, valleys 510 have a stronger light-reflecting ability), resulting in different intensities of light reflected back by the valleys 510 and ridges 520. Therefore, the positional information of the valleys and ridges in the fingerprint 500 can be obtained by receiving electrical signals from receiving electrodes coupled to multiple sensitive units 10 at different locations, thereby enabling fingerprint recognition. Furthermore, at the surface 181 of the display panel that contacts the user's finger, the ridges 520 will contact the surface 181, and there is air between the valleys 510 and the surface 181, resulting in different refractive indices of the paths of light reflected from the valleys 510 and ridges 520, which also affects the intensity of light reflected back by the valleys 510 and ridges 520.

[0087] Specifically, when incident light reaches a valley 510 of the fingerprint 500, the energy or intensity of the light reflected from the valley 510 is greater. When incident light reaches a ridge 520 of the fingerprint 500, the energy or intensity of the light reflected from the ridge 520 is less. Therefore, the difference in intensity and energy of the light reflected from the valley 510 and ridge 520 of the fingerprint 500 is relatively large. Based on this difference, it is possible to determine whether the current position is a valley or a ridge, thus obtaining the positional information of the valleys and ridges in the fingerprint 500.

[0088] This disclosure relates to the field of sensing technology. Based on the pixel structure, pixel circuit, and process structure of OLED displays, it proposes a pixel circuit structure that improves the in-cell integration of fingerprint sensors in OLED displays, enhancing their resistance to strong light and improving their signal-to-noise ratio (SNR). Furthermore, this disclosure provides two process implementation methods to address the problem of fingerprint saturation under strong light in in-cell fingerprint recognition technology.

[0089] Fingerprint recognition has become a standard feature on mobile phones. Fingerprint recognition technology is divided into under-display fingerprint recognition and in-cell fingerprint recognition. Under-display fingerprint recognition achieves this by attaching the fingerprint sensor module to the underside of the screen. In-cell fingerprint recognition integrates the fingerprint sensor directly into the display screen. Therefore, in-cell fingerprint recognition allows for thinner and lighter phones. As flagship phones increasingly adopt curved and foldable screens, OLED displays have become the choice for most flagship models. Therefore, combining OLED screens with in-cell fingerprint recognition technology is an important research direction for future mobile phone unlocking.

[0090] The principle of in-display fingerprint recognition is to add a fingerprint recognition sensor and fingerprint recognition circuit inside the OLED pixel. Since the fingerprint sensor is integrated into the OLED pixel circuit, it can also be called a sensor pixel circuit, or simply a pixel circuit. It is a different concept from the pixel circuit of the OLED display (used to drive organic light-emitting diodes to emit light).

[0091] Figure 8 This is a circuit diagram of a fingerprint recognition circuit provided according to an embodiment of the present disclosure.

[0092] like Figure 8 As shown, the display panel may include a photosensitive circuit and an output circuit. The photosensitive circuit may include a photosensitive unit, which can specifically employ various photoelectric sensors. The output circuit may include a transistor. The output of the photosensitive unit can be connected to the input terminal of the output circuit.

[0093] In some embodiments, the photosensitive circuit includes a PIN photodiode, and the output circuit includes a thin-film transistor (hereinafter referred to as a switch TFT) acting as a switch. The input terminal of the PIN photodiode receives a bias signal (Vbias), and upon receiving reflected light from a fingerprint, generates an induced electrical signal and transmits this signal to the source of the switch TFT. A read circuit can read the induced electrical signal from the drain of the switch TFT. It should be noted that the gate of the switch TFT can receive a gate signal (Vg).

[0094] Zero-bias mode and reverse-bias mode are two operating modes of a photodiode. For example, in zero-bias mode, the photodiode has a smaller dark current. In reverse-bias mode, linear output can be achieved. Some embodiments of the photoelectric conversion circuit provided in this disclosure can switch between these two operating modes of the photodiode to facilitate selection according to actual needs. For example, when the photoelectric conversion circuit performs a detection function, the photodiode can be selected to operate in reverse-bias mode to obtain linear output characteristics. When the photoelectric conversion circuit performs a charging function, the photodiode can be selected to operate in zero-bias mode to have a lower dark current. However, the embodiments of this disclosure are not limited in this respect.

[0095] Specifically, in the pixel circuit of the sensor, each pixel consists of a PIN photodiode and a switching TFT. The PIN photodiode operates in a reverse-biased state. In the dark, the PIN photodiode has very low leakage current. In the light, the reverse-biased current increases, generating a large amount of photogenerated charge. The PIN photodiode and its upper and lower electrodes form a capacitor to store the photogenerated charge. When the photogenerated charge accumulates to a certain integration time, the switching TFT turns on, reading the charge stored in the PIN photodiode. Because the light intensity reflected from the valleys and ridges of a fingerprint differs from that reaching the PIN photodiode, after a certain integration time, the amount of photogenerated charge in the PIN photodiodes corresponding to the valley and ridge positions differs, thus enabling fingerprint identification.

[0096] For example, the capacitance value of the first capacitor is in the range of 10pF-100pF.

[0097] For example, when the photosensitive element is implemented as a photodiode, the size of the first capacitor C1 is more than 100 times the capacitance value of the photodiode itself (reverse bias capacitor).

[0098] refer to Figure 8 As shown, in the pixel circuit of the in-screen fingerprint sensor, under illumination, the PIN photodiode acts as both the generator of photogenerated charge and its inherent capacitance is used to store the photogenerated charge. During operation, the switch TFT first turns on, resetting the potential at position 1 to a fixed value (e.g., a preset value, such as 1.42V). After a certain integration time (e.g., 5ms, 10ms, 30ms, 50ms, 80ms, or 100ms), the switch TFT turns on again, reading the charge stored in the capacitance of the PIN photodiode.

[0099] One of the key challenges of in-display fingerprint recognition technology is its resistance to strong light. This is primarily because the in-display fingerprint sensor is located between the TFT and OLED light-emitting diode layers, resulting in extremely high transmittance, significantly higher than the light intensity received by under-display fingerprint sensors. The light received by the sensor includes light reflected from the display via the finger or the film layer, as well as light reaching the sensor through the finger from the outside environment. Especially in strong outdoor light environments, the light intensity can reach 10W 1x, and the light intensity reaching the sensor through the finger can reach tens or hundreds of 1x. Such high light intensity causes the PIN photodiode to generate a high amount of charge. According to the formula ΔQ = C × ΔU, since the capacitance C is fixed, the voltage ΔU has an upper limit. Excessive ΔU increases the number of dead pixels in the diode and reduces stability. Therefore, the PIN photodiode's charge storage capacity has an upper limit. Strong outdoor light causes the amount of photogenerated charge generated by the PIN photodiode to far exceed its stored charge limit, leading to charge saturation. Consequently, the signal difference between the PIN photodiodes corresponding to the valleys and ridges of the finger cannot be distinguished, causing sensor failure.

[0100] Figure 9 This is a circuit diagram of a fingerprint recognition circuit provided according to another embodiment of the present disclosure.

[0101] This disclosure provides an OLED structure that enhances the resistance to strong light in in-cell fingerprint sensors. For example... Figure 9 As shown, by adding one or more new capacitors to the output terminal of the PIN photodiode, with one side of the capacitor connected to the negative terminal of the PIN photodiode and the other side connected to a constant voltage signal or Vbias voltage, the high charge storage capacity of the PIN photodiode under strong light conditions is improved. This increased charge storage capacity effectively addresses the saturation problem of the PIN photodiode in the in-cell fingerprint sensor of the OLED display under strong outdoor light. Furthermore, increasing the upper limit of stored charge can further increase the upper limit of signal strength, which is beneficial for improving the signal-to-noise ratio.

[0102] refer to Figure 9 As shown, one or more new capacitors (C1, C2, etc.) are added to the output terminal of the PIN photodiode to store charge. Taking the addition of a single capacitor C1 as an example, one electrode (position 1) of the new capacitor C1 is connected to the negative terminal of the PIN photodiode, and the other electrode (position 2) of the new capacitor C1 can be connected to a constant voltage signal. This constant voltage signal can be any one of VGL, a separate constant voltage signal, or a Vbias signal. The voltage difference can be determined based on the amount of charge to be stored. Specifically, it can be determined using the formula ΔQ = C × ΔU: when the ΔU of the new capacitor C1 increases, the amount of charge that can be stored, ΔQ, can increase. Capacitor C1 and the PIN photodiode jointly store charge. Due to the sensitive light response of the PIN photodiode under strong light conditions, it generates a large amount of photogenerated charge. The voltage difference between the two electrodes (position 1 and position 2) of the newly added capacitor C1 can increase the total charge storage capacity. During operation, the switch TFT turns on first, resetting the potential of electrode position 1 to a fixed value (e.g., 1.42V or other potentials). After a certain integration time (e.g., 5ms, 10ms, 30ms, 50ms, 80ms or 100ms, etc.), the switch TFT turns on, reading out all the charge stored in the PIN and the new capacitor.

[0103] For example, during the photosensitive stage, the switching TFT is turned off, allowing the photodiode to receive the light signal and convert it into an electrical signal, which is then stored in the newly added capacitor.

[0104] For example, when the photoelectric conversion circuit does not perform light detection to achieve related functions, the photosensitive element can sense ambient light for a long time and convert it into an electrical signal. The storage circuit has a large storage capacity to store the photoelectric charge generated by photoelectric sensing, which can ensure the effective storage and accumulation of electrical signals and reduce the risk of oversaturation of the charge storage capacity of the fingerprint detection circuit under strong light.

[0105] During the read-out phase, the transistor is turned on, and the photodiode is reverse-biased. The stored electrical signal is output through the TFT switch for reading.

[0106] In order to improve the strong light saturation resistance of the PIN photodiode in the fingerprint recognition sensor of the OLED screen, this embodiment increases the capacitance to enhance the charge storage capacity of the PIN photodiode, effectively improving the strong light saturation problem of in-screen fingerprint recognition. Furthermore, increasing the upper limit of the charge stored in the PIN photodiode can further increase the upper limit of the signal quantity, promoting the improvement of the SNR (Signal-to-Noise Ratio) of the fingerprint recognition sensor (SNR = Signal Quantity / Noise).

[0107] The newly added capacitor can be implemented using various structural designs. Correspondingly, various manufacturing processes can also be employed for these different designs.

[0108] In some embodiments, the display panel may include a substrate, pixel circuitry, and fingerprint recognition circuitry.

[0109] The pixel circuit is disposed on the substrate and includes a transistor. The transistor includes an active layer, a gate, a first electrode, and a second electrode. For example, the first electrode can be a source and the second electrode can be a drain. Alternatively, the first electrode can also be a drain and the second electrode can be a source; no limitation is made here.

[0110] The fingerprint recognition circuit includes a photosensitive circuit, a storage circuit, and an output circuit. The storage circuit includes a first capacitor, which includes a first capacitor electrode and a second capacitor electrode. The transistors of the output circuit are arranged on the same layer as the transistors of the pixel circuit.

[0111] The photosensitive circuit is configured to convert the received optical signal into an electrical signal, the storage circuit is configured to store the electrical signal, and the output circuit includes a control switch configured to control the photosensitive circuit to charge the storage circuit in the open state, and to output at least the stored electrical signal in the closed state, so as to perform fingerprint recognition based on the output electrical signal.

[0112] The first capacitor electrode is disposed in the same layer as at least one of the gate, active layer, first electrode or second electrode, and / or the second capacitor electrode is disposed in the same layer as at least one of the gate, active layer, first electrode or second electrode; the first capacitor electrode and the second capacitor electrode are disposed in different layers, and the orthogonal projections of the first capacitor electrode and the second capacitor electrode on the substrate at least partially overlap.

[0113] The term "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask for a single patterning process. Depending on the specific pattern, the same patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0114] To achieve the structure of the newly added capacitor, existing metal layers in the OLED display panel can be reused as electrodes for the new capacitor. Alternatively, a new metal layer can be added as part of the electrodes for the new capacitor.

[0115] In some embodiments, where space allows, the gate (which may include a first gate line (gate1, abbreviated as g1) and a second gate line (gate2, abbreviated as g2)), heavily doped polysilicon (poly Si), and source / drain layers (a double-layer source / drain layer may include a first source / drain layer (Source / Drain 1, abbreviated as SD1) and a second source / drain layer (Source / Drain 2, abbreviated as SD2)) from the OLED display panel structure can be reused as the two electrodes of the newly added capacitor. Furthermore, a gate insulator (GI) can be used as the insulating layer between the two electrodes of the newly added capacitor. The above structure requires no additional processing steps and incurs no cost increase.

[0116] It should be noted that OLED display panels can have structures such as single-layer gate, double-layer gate, single-layer source / drain, or double-layer source / drain. One or more of these layers can be reused as at least one electrode of a newly added capacitor, or at least one electrode of multiple newly added capacitors.

[0117] For example, the first electrode of the newly added capacitor can be formed in the layer where the first gate line g1 is located, and the second electrode of the newly added capacitor can be formed in the layer where the second gate line g2 is located.

[0118] For example, the first electrode of the newly added capacitor can be formed in the layer where the first gate line g1 is located, and the second electrode of the newly added capacitor can be formed in the layer where the first source and drain SD1 is located.

[0119] For example, the first electrode of the newly added capacitor can be formed in the layer where the first gate line g1 is located, and the second electrode of the newly added capacitor can be formed in the layer where the second source and drain SD2 is located.

[0120] For example, the first electrode of the newly added capacitor can be formed in the layer where the second gate line g2 is located, and the second electrode of the newly added capacitor can be formed in the layer where the first source and drain SD1 is located.

[0121] For example, the first electrode of the newly added capacitor can be formed in the layer where the second gate line g2 is located, and the second electrode of the newly added capacitor can be formed in the layer where the second source and drain SD2 is located.

[0122] For example, the first electrode of the newly added capacitor can be formed in the layer where the first gate line g1 is located, and the second electrode of the newly added capacitor can be formed in the layer where the heavily doped polysilicon (poly Si) is located.

[0123] For example, the first electrode of the newly added capacitor can be formed in the layer where the second gate line g2 is located, and the second electrode of the newly added capacitor can be formed in the layer where the heavily doped polysilicon (poly Si) is located.

[0124] The insulating layer between the two electrodes of the newly added capacitor can reuse one or more layers of insulating material already present in the OLED display panel.

[0125] In some embodiments, the display panel may further include one or more electrical insulating layers.

[0126] For example, an interlayer dielectric layer is disposed on the side of the gate away from the substrate.

[0127] For example, an insulating layer, the first thickness of which may be greater than the second thickness of the interlayer dielectric layer. The insulating layer may include, but is not limited to, at least one of a capping layer, an interlayer dielectric layer, a protective layer, or a planarization layer.

[0128] For example, the material of the gate dielectric layer includes, but is not limited to, at least one of silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide, etc.

[0129] For example, the gate is disposed above the gate dielectric layer. The gate can be made of a conductive material. For example, the gate can be a metallic material such as tungsten, aluminum, or copper.

[0130] For example, an interlayer dielectric layer is disposed around the periphery of the active layer, the gate dielectric layer, and the gate. The materials of the interlayer insulating layer include, but are not limited to, silicon dioxide, silicon oxynitride, and organic transparent materials.

[0131] For example, the first electrode includes: a first sub-electrode and a second sub-electrode.

[0132] The first sub-electrode is disposed on the side of the interlayer dielectric layer away from the substrate. The second sub-electrode is disposed on the side of the first sub-electrode away from the substrate, and an insulating layer is disposed between the first and second sub-electrodes.

[0133] For example, the photosensitive circuit is located on the side of the second sub-electrode away from the substrate.

[0134] Figure 10 This is a schematic diagram of the structure of a display panel provided according to an embodiment of the present disclosure.

[0135] like Figure 10 As shown, the gate includes a first gate line g1 and a second gate line g2, and the first gate line g1 and the second gate line g2 are located in different layers.

[0136] The first capacitor electrode 25 is disposed on the same layer as the first gate line g2 or the second gate line g2, and the second capacitor electrode 27 is disposed on the same layer as the first gate line g1 or the second gate line g2.

[0137] In addition, the aforementioned display panel may also include multiple electrically insulating layers, and through-holes are provided in the electrically insulating layers to achieve electrical connection between electrodes of different layers.

[0138] For example, the first gate dielectric layer 24 is disposed between the active layer 22 and the first gate line g1.

[0139] For example, a second gate dielectric layer 26 is disposed between the first gate line g1 and the second gate line g2.

[0140] For example, an interlayer dielectric layer 28 is disposed on the side of the second gate dielectric layer g2 away from the substrate 20.

[0141] Figure 10 In the first capacitor electrode 25, the first capacitor electrode 25 is connected to the first electrode 25 through the first via K1. The first via K1 is disposed in the second gate dielectric layer 26 and the interlayer dielectric layer 28, and the first via K1 exposes the first capacitor electrode g1.

[0142] Furthermore, if the second capacitor electrode 27 is used as the output terminal of the newly added capacitor, it can be connected to the first electrodes 29 and 33 through the second via. The second via is disposed in the interlayer dielectric layer 28, and the second via exposes the second capacitor electrode 27.

[0143] In some embodiments, the display panel may further include a transparent conductive layer disposed on the side of the PIN photodiode away from the substrate, the transparent conductive layer being connected to the introduction electrode 45 of the bias signal (Vbias signal). This helps to reduce the contact resistance between the PIN photodiode and the introduction electrode 45, thereby reducing the overall resistance of the circuit. Furthermore, using a transparent conductive electrode reduces the absorption and / or reflection of light by the electrode. For example, the material of the transparent conductive layer includes, but is not limited to, at least one of indium tin oxide (ITO) and indium zinc tin oxide (ITZO).

[0144] refer to Figure 10 As shown, the display panel may include: a substrate 20, a buffer layer 21, an active layer 22, a first gate dielectric layer 24, a first electrode 25, a first gate line g1, a first gate dielectric layer 26, a second gate line g2, a second electrode 27, an interlayer dielectric layer (ILD) 28, a first source / drain electrode SD1, a first source / drain electrode of the transistor in the output circuit 29, a first protective layer (PVX1) 30, a first planarization layer (e.g., PLN1) 31, a first protective layer (PVX2) 32, a second source / drain electrode SD2, a second source / drain electrode of the transistor in the output circuit 33, the N-terminal of a PIN photodiode 34, the I-terminal of a PIN photodiode 35, the P-terminal of a PIN photodiode 36, an ohmic contact layer (e.g., ITO) 37, a capping layer 38, a second planarization layer (e.g., PLN2) 39, an anode 40, an organic light-emitting layer (EL) 41, a microstructure layer (e.g., a microsphere layer PS) 43, a cathode 42, and a thin film encapsulation layer. Encapsulation (TFE) 44.

[0145] The introduction electrode 45, which is in contact with the ohmic contact layer (such as ITO) 37, can be configured to introduce, for example... Figure 9 The Vbias electrical signal in the output circuit. The transistor in the output circuit can be implemented as a thin-film transistor, and its active layer is, for example, amorphous silicon, polycrystalline silicon, or metal oxide semiconductor (such as indium gallium zinc oxide (IGZO), aluminum-doped zinc oxide (AZO), indium zinc oxide (IZO), etc.).

[0146] It should be noted that the OLED display panel structure shown above is only for the purpose of understanding the technical solutions of this disclosure and should not be construed as a limitation on the technical solutions of the embodiments of this disclosure. For example, the first protective layer (PVX1) 30, the first planarization layer (such as PLN1) 31, and the first protective layer (PVX2) may use fewer or more layers. For example, the gate may use a single gate layer and a single gate dielectric layer, or the gate may use three gate layers and three or more gate dielectric layers, etc. For example, the source and drain may use a single source and drain layer, or the source and drain may use three or more source and drain layers, etc., without limitation here.

[0147] Figure 11 For embodiments provided in accordance with this disclosure Figure 10 A planar design of all film layers with gate1 and gate2 as the two electrodes of the capacitor.

[0148] like Figure 11 The diagram shown is a planar design of all the film layers of an OLED display panel, which features a newly added capacitive fingerprint recognition circuit. Figure 11 The topmost diamond and pentagonal patterns correspond to multiple anodes in the OLED display panel. Each anode serves as the anode of an organic light-emitting diode (OLED), and each anode corresponds to a sub-pixel. Each sub-pixel emits light of a specific color, such as red, blue, or green. It should be noted that various arrangement methods can be used to position each sub-pixel.

[0149] For example, refer to Figure 2 When the sub-pixels P in the central display panel 1' are arranged in the standard RGB mode, each pixel includes three sub-pixels P. The emission colors of these three sub-pixels P are the three primary colors, such as red, green, and blue in sequence. The RGB mode arrangement is the most standard arrangement method. It divides a square pixel into three equal parts, and assigns a different color to each part, which makes it easy to create sub-pixels P.

[0150] For example, when the sub-pixels P in the display panel 1' are arranged in RGB Pentile (RGB arrangement) mode, each pixel unit includes 4 sub-pixels P. The light emission colors of these four sub-pixels P are, for example, red, green, blue and green in sequence, and the area of ​​the sub-pixels with the light emission colors of red and blue is larger than the area of ​​the sub-pixels P with the light emission color of green.

[0151] Pentile arrangement primarily reduces the number of sub-pixels P by having adjacent pixels share sub-pixels P, thereby achieving the effect of simulating high resolution with low resolution. The biggest advantage of pentile arrangement is increased transparency, requiring less power consumption for the same brightness, thus improving the battery life of display panel 1' and significantly reducing the cost of display panel 1'.

[0152] Within the same row of sub-pixels P, the order of the emitted colors of each sub-pixel P in each pixel unit is the same. For example, in each pixel unit in the first row, the first sub-pixel P emits red light, the second emits green light, the third emits blue light, and the fourth also emits green light. That is, in this pixel unit, the order of the emitted colors of each sub-pixel P is red, green, blue, and green. The emitted colors of the sub-pixels P in pixel units located in different rows are not the same. For example, in the second row of sub-pixels P, the order of the emitted colors of each sub-pixel P in each pixel unit is blue, green, red, and green.

[0153] Each pixel unit includes three sub-pixels P: the first sub-pixel P emits red light, the second emits green light, and the third emits blue light. The order of the light emission colors of the sub-pixels P in pixel units located in different rows is the same: red, green, and blue. In this structure, one pixel unit constitutes one pixel.

[0154] When multiple sub-pixels P are divided into multiple pixel units, the gate driving circuit 13 can be disposed between two adjacent pixel units. For example, at least one first thin-film transistor group 131 is located between two adjacent pixel units.

[0155] When multiple sub-pixels P are divided into multiple pixel units, and the first thin-film transistor group 131 is disposed between two adjacent pixels P, the spacing between two adjacent sub-pixels P in each pixel unit is small. On the one hand, when a pixel unit can be considered as a pixel, adjacent pixels can be displayed relatively independently, which helps to ensure the display effect of the display panel 1'. On the other hand, since the number of pixel units is less than the number of sub-pixels P, utilizing the empty area between two adjacent pixel units to place the first thin-film transistor group 131 helps to increase the pixel density (PPI) of the display panel 1'.

[0156] Figure 12 For embodiments provided in accordance with this disclosure Figure 10 A planar design diagram of a poly Si, gate1, gate2, SD, and ILD layer with gate1 and gate2 as the capacitor terminals.

[0157] refer to Figure 12 As shown, for ease of viewing the layout of the newly added capacitors, only the polySi, gate1, gate2, SD, and ILD layers are shown. The shape of the first electrode 25 in the layer containing the first gate line gate1 is as follows... Figure 12 The dashed box marked "gate1" indicates the second electrode 27. The shape of the second electrode 27 in the layer containing the second gate line "gate2" is as follows... Figure 12 The shape indicated by the marker gate2, however, the second electrode 27 and the orthographic projection of the first electrode 25 on the substrate 20 at least partially overlap.

[0158] In some embodiments, the gate includes a first gate line and a second gate line, which are located in different layers.

[0159] Accordingly, the first capacitor electrode is disposed on the same layer as the first gate line or the second gate line, and the second capacitor electrode is disposed on the same layer as the active layer.

[0160] Figure 13 This is a schematic diagram of the structure of a display panel provided according to an embodiment of the present disclosure.

[0161] like Figure 13 As shown, with Figure 10 The difference is that the OLED display panel does not have a first electrode 25 on the layer where the first gate line g1 is located, but instead has a first electrode 25 on the layer where the active layer is located. The electrode on the active layer is used as the first electrode 25 of the newly added capacitor, and the second electrode 27 is used on the layer where the second gate line g2 is located.

[0162] Alternatively, a first electrode 25 can be provided on the layer containing the active layer, and a second electrode 27 can be provided on the layer containing the first gate line g1, which will not be described in detail here.

[0163] Figure 13 The display panel may include: a substrate 20, a buffer layer 21, an active layer 22, a first gate dielectric layer 24, a first electrode 25, a first gate line g1, a first gate dielectric layer 26, a second gate line g2, a second electrode 27, an interlayer dielectric layer (ILD) 28, a first source / drain electrode SD1, a first source / drain electrode of the transistor in the output circuit 29, a first protective layer (PVX1) 30, a first planarization layer (e.g., PLN1) 31, a first protective layer (PVX2) 32, a second source / drain electrode SD2, a second source / drain electrode of the transistor in the output circuit 33, the N-terminal of the PIN photodiode 34, the I-terminal of the PIN photodiode 35, the P-terminal of the PIN photodiode 36, an ohmic contact layer (e.g., ITO, to reduce contact resistance) 37, a capping layer 38, a second planarization layer (e.g., PLN2) 39, an anode 40, an organic light-emitting layer (EL) 41, a microstructure layer (e.g., PS) 43, a cathode 42, and a thin-film encapsulation layer (TFE) 44.

[0164] Figure 14 For embodiments provided in accordance with this disclosure Figure 13 A planar design of all film layers with polySi and gate2 as the capacitor electrodes.

[0165] like Figure 14 As shown, you can refer to the information about Figure 13 The difference lies in the fact that the active layer also has a first electrode, but the other layouts can be the same, so they will not be described in detail here.

[0166] Figure 15 For embodiments provided in accordance with this disclosure Figure 13 A planar design diagram of a capacitor consisting of polySi, gate1, gate2, SD, and ILD layers, with polySi and gate2 as the capacitor electrodes.

[0167] like Figure 15 As shown, the dashed dumbbell-shaped frame marked poly Si is the first electrode formed in the layer where the active layer is located. The first electrode and the second electrode (located in the layer where the second gate line gate2 is located) overlap in their orthogonal projections on the substrate to form the aforementioned newly added capacitors C1, C2, etc.

[0168] In some embodiments, the first electrode or the second electrode may be disposed in the newly added metal layer.

[0169] For example, when space is limited, an additional metal layer and an insulating layer can be added. The cover layer is not masked separately but is lithographically applied together with the newly added insulating layer. Therefore, only one mask is needed, with the lower electrode of the PIN photodiode and the added metal layer serving as the two poles of the new capacitor.

[0170] In some embodiments, the first capacitor electrode is disposed in the same layer as at least one of the gate, active layer, or first electrode, and the second capacitor electrode is disposed in the first metal layer, which is located in a different layer from the gate, active layer, and first electrode. Alternatively, the second capacitor electrode is disposed in the same layer as at least one of the gate, active layer, or first electrode, and the first capacitor electrode is disposed in the second metal layer, which is located in a different layer from the gate, active layer, and first electrode.

[0171] Figure 16 This is a schematic diagram of the structure of a display panel provided according to an embodiment of the present disclosure.

[0172] like Figure 16 As shown, with Figure 10 The difference is that the OLED display panel does not have a first electrode 25 on the layer where the first gate line g1 is located, nor does it have a second electrode 27 on the layer where the second gate line g2 is located. Figure 16 A first electrode 25 is disposed in the layer containing the second source / drain electrode 33. A second electrode 27 is disposed in the newly added metal layer. The first electrode 25 is disposed at a position corresponding to the second electrode 27 in the layer containing the second source / drain electrode 33.

[0173] Alternatively, the first electrode 25 or the second electrode 27 can be disposed on the layer containing the first source / drain electrode SD1. The first electrode 25 or the second electrode 27 can also be disposed on the layer containing the first gate line g1. The first electrode 25 or the second electrode 27 can also be disposed on the layer containing the second gate line g2. The first electrode 25 or the second electrode 27 can also be disposed on the layer containing the active layer (heavily doped Poly-Si), which will not be detailed here.

[0174] Figure 16The display panel may include: a substrate 20, a buffer layer 21, an active layer 22, a first gate dielectric layer 24, a first gate line g1, a first gate dielectric layer 26, a second gate line g2, an interlayer dielectric layer (ILD) 28, a first source / drain electrode SD1, a first source / drain electrode of the transistor in the output circuit 29, a first protective layer (PVX1) 30, a first planarization layer (e.g., PLN1) 31, a first protective layer (PVX2) 32, a second source / drain electrode SD2, a second source / drain electrode of the transistor in the output circuit 33, a first electrode 25, the N-terminal of a PIN photodiode 34, the I-terminal of a PIN photodiode 35, the P-terminal of a PIN photodiode 36, an ohmic contact layer (e.g., ITO, to reduce contact resistance) 37, a capping layer 38, a second electrode 27, a second planarization layer (e.g., PLN2) 39, an anode 40, an organic light-emitting layer (EL) 41, a microstructure layer (e.g., PS) 43, a cathode 42, and a thin-film encapsulation layer (TFE) 44.

[0175] It should be noted that a new insulating layer can also be provided for the first electrode 25, such as a new insulating layer between the first electrode 25 and the second electrode 27.

[0176] In some embodiments, the first capacitor electrode is disposed on the same layer as the first electrode, and the second capacitor electrode is disposed on the side of the photosensitive circuit away from the substrate. A distance exists between the second capacitor electrode and the orthographic projection of the photosensitive circuit onto the substrate. (See reference...) Figure 16 As shown, there is a certain gap between the second electrode 27 and the PIN photodiode (including N-pole 34, I-pole 35 and P-pole 36) on the substrate 20.

[0177] Figure 17 For embodiments provided in accordance with this disclosure Figure 16 A planar design of all film layers with SD2 and the newly added metal as the two electrodes of the capacitor.

[0178] like Figure 17 As shown, you can refer to the information about Figure 13 The difference lies in the addition of a metal layer, within which a second electrode 27 is disposed. Furthermore, a first electrode 25 is disposed on the layer containing the second source / drain electrodes SD2. Other layouts remain the same and will not be elaborated further.

[0179] Figure 18 For embodiments provided in accordance with this disclosure Figure 16 A planar design diagram of a capacitor consisting of SD2, metal, and anode layers, with poly Si and gate2 as the capacitor electrodes.

[0180] like Figure 18As shown, the box with grooves marked "metal" is the second electrode formed in the newly added metal layer. The second electrode and the first electrode (located in the layer where the second source and drain SD2 are located) overlap in their orthogonal projections on the substrate to form the newly added capacitors C1, C2, etc.

[0181] The above methods can effectively improve the saturation problem of PIN photodiodes in OLED in-cell fingerprint recognition under strong outdoor light without making too many changes to the display panel of in-screen fingerprint recognition or increasing costs, and effectively improve its anti-strong light performance and signal-to-noise ratio.

[0182] The following provides an example of a scenario where at least two new capacitors are added.

[0183] In some embodiments, reference Figure 9 As shown, the storage circuit also includes at least one second capacitor connected in parallel with the first capacitor, and each of the at least one second capacitor includes a third electrode and a fourth electrode.

[0184] In some embodiments, the third electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode, and the fourth electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode; the third electrode and the fourth electrode are disposed in different layers, and the orthogonal projections of the third electrode and the fourth electrode on the substrate at least partially overlap.

[0185] For example, the first electrode and the third electrode can be disposed in the same layer or in different layers. For example, the second electrode and the fourth electrode can be disposed in the same layer or in different layers. For example, the first electrode and the fourth electrode can be disposed in the same layer or in different layers. For example, the second electrode and the third electrode can be disposed in the same layer or in different layers.

[0186] In some embodiments, the third electrode is disposed on the same layer as at least one of the gate, active layer, or first electrode, and the fourth electrode is disposed on the third metal layer, which is located on a different layer from the gate, active layer, and first electrode.

[0187] For example, refer to Figure 10 and Figure 13 The first electrode can be placed in the layer where the first gate line g1 is located, the second electrode can be placed in the layer where the second gate line g2 is located, the third electrode can be placed in the layer where the second gate line g2 is located, and the fourth electrode can be placed in the layer where the active layer is located.

[0188] For example, the first electrode can be disposed in the layer containing the first gate line g1. For example, the second electrode can be disposed in the layer containing the second gate line g2. For example, the third electrode can be disposed in the layer containing the first source / drain electrode SD1. For example, the fourth electrode can be disposed in the layer containing the second source / drain electrode SD2.

[0189] In some embodiments, the fourth electrode is disposed on the same layer as at least one of the gate, the active layer, or the first electrode, and the fourth electrode is disposed on a fourth metal layer, which is located on a different layer from the gate, the active layer, and the first electrode.

[0190] In some embodiments, the gate includes a first gate line and a second gate line, which are located on different layers. A third electrode is disposed on the same layer as either the first or second gate line, and a fourth electrode is disposed on the same layer as either the first or second gate line, but the third and fourth electrodes are located on different layers.

[0191] For example, refer to Figure 10 and Figure 16 As shown, the first electrode can be placed in the layer where the first gate line g1 is located, the second electrode can be placed in the layer where the second gate line g2 is located, the third electrode can be placed in the layer where the second source / drain electrode 33 is located, and the fourth electrode can be placed in the newly added metal layer. Figure 16 (The floor where number 27 is located, or other floors).

[0192] For example, refer to Figure 10 and Figure 16 As shown, the first electrode can be placed in the layer where the first gate line g1 is located, the second electrode can be placed in the layer where the second gate line g2 is located, the third electrode can be placed in the layer where the second source / drain electrode 33 is located, and the fourth electrode can be placed in the newly added metal layer. Figure 16 (The floor where number 27 is located, or other floors).

[0193] For example, the first electrode can be placed in the layer where the second gate line g2 is located, the second electrode can be placed in the layer where the active layer is located, the third electrode can be placed in the layer where the second source / drain electrode 33 is located, and the fourth electrode can be placed in the newly added metal layer. Figure 16 (The floor where number 27 is located, or other floors).

[0194] In some embodiments, a PIN photodiode can occupy the position of a sub-pixel in the pixel unit of the OLED display panel, which facilitates the formation of half-screen fingerprint recognition (the fingerprint recognition area occupies approximately half of the entire screen area) or full-screen fingerprint recognition (the fingerprint recognition area occupies approximately the entire screen area).

[0195] Specifically, the display panel may include multiple pixel units. These pixel units are disposed on a substrate, and an array of pixel units is arranged on the substrate. The orthographic projections of the pixel units and the photosensitive circuitry onto the substrate overlap.

[0196] Among them, reference Figure 10 As shown, a pixel unit includes at least one sub-pixel, and each sub-pixel includes a light-emitting element, which includes an anode.

[0197] The pixel circuit includes a sub-pixel driving circuit, in which the first electrode of the transistor is connected to the anode. For example, the drain of the transistor in the sub-pixel driving circuit may be connected to the anode, facilitating the application of voltage to the organic light-emitting diode (OLED). The drain and anode of the transistor in the sub-pixel driving circuit can be connected via a via.

[0198] For example, a pixel unit may include four sub-pixels: a red sub-pixel, a blue sub-pixel, a green sub-pixel, and a fingerprint detection sub-pixel.

[0199] refer to Figure 1 and Figure 10 As shown, a pixel unit located in the fingerprint recognition area may include three sub-pixels: RGB, each sub-pixel including a light-emitting element that emits red, green, and blue light, respectively. In addition, this pixel unit also includes a sub-pixel for housing a PIN photodiode, a switching TFT, and an additional capacitor. This disclosure does not limit the arrangement of the PIN photodiode, the switching TFT, and the additional capacitor with the relevant components in the light-emitting sub-pixel.

[0200] In some embodiments, the output circuit includes a first transistor, and the sub-pixel driving circuit includes at least one second transistor.

[0201] For example, the first electrode of the first transistor and the first electrode of the second transistor are disposed on the same layer. For example, the second electrode of the first transistor and the second electrode of the second transistor are disposed on the same layer.

[0202] For example, the gate of the first transistor is disposed on the same layer as the gate of the second transistor.

[0203] For example, the active layer of the first transistor and the active layer of the second transistor are disposed on the same layer.

[0204] In some embodiments, to further improve the signal-to-noise ratio of the fingerprint recognition circuit output signal, the output circuit may further include an operational amplifier (AMP). For example, the operational amplifier includes an input terminal and an output terminal, the input terminal being connected to the output terminal of an additional capacitor to receive photoelectric signals, and the output terminal outputting an amplified photoelectric signal.

[0205] This disclosure provides a pixel circuit structure for an OLED in-cell fingerprint sensor that improves its resistance to strong light and signal-to-noise ratio by adding one or more capacitors to a PIN photodiode.

[0206] This disclosure provides a process structure for an OLED in-cell fingerprint sensor that improves its resistance to strong light and signal-to-noise ratio by adding one or more capacitors to a PIN photodiode.

[0207] This disclosure also provides a process structure that can reuse heavily doped poly Si as one electrode of the newly added capacitor.

[0208] Another aspect of this disclosure provides a method for manufacturing a display panel.

[0209] Figure 19 This is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0210] like Figure 19 As shown, the manufacturing method 190 of the display panel may include operations S191 to S193.

[0211] In operation S191, a substrate is provided.

[0212] In operation S192, a pixel circuit is formed on the substrate. The pixel circuit includes a gate, an active layer, a first electrode, and a second electrode.

[0213] In operation S193, a fingerprint recognition circuit is set up; the fingerprint recognition circuit includes a photosensitive circuit, a storage circuit, and an output circuit. The storage circuit includes a first capacitor, which includes a first capacitor electrode and a second capacitor electrode; the transistors of the output circuit are arranged on the same layer as the transistors of the pixel circuit.

[0214] The photosensitive circuit is configured to convert the received optical signal into an electrical signal, the storage circuit is configured to store the electrical signal, and the output circuit includes a control switch configured to control the photosensitive circuit to charge the storage circuit in the open state, and to output at least the stored electrical signal in the closed state, so as to perform fingerprint recognition based on the output electrical signal.

[0215] The first capacitor electrode is disposed in the same layer as at least one of the gate, active layer, first electrode or second electrode, and / or the second capacitor electrode is disposed in the same layer as at least one of the gate, active layer, first electrode or second electrode; the first capacitor electrode and the second capacitor electrode are disposed in different layers, and the orthogonal projections of the first capacitor electrode and the second capacitor electrode on the substrate at least partially overlap.

[0216] In some embodiments, the first capacitor electrode and the second capacitor electrode are manufactured in the following manner.

[0217] First, a fifth metal layer is formed and patterned to form a first capacitor electrode and a first gate line.

[0218] Then, a second gate dielectric layer is formed.

[0219] Next, a sixth metal layer is formed and patterned to form a second capacitor electrode and a second gate line; the first width of the cross section of the first capacitor electrode perpendicular to the extension direction of the first gate line is greater than the second width of the cross section of the second capacitor electrode perpendicular to the extension direction of the second gate line.

[0220] Then, an interlayer dielectric layer is formed, and vias are formed in areas where the projections of the first capacitor electrode and the second capacitor electrode on the substrate do not overlap to expose the first capacitor electrode.

[0221] Next, a first electrode is formed so that the first capacitor electrode and the first electrode are electrically connected.

[0222] In one specific embodiment, the existing first gate line (gate1), second gate line (gate2), heavily doped poly Si, first source / drain electrode (SD1), and second source / drain electrode (SD2) of the OLED structure are reused as the electrodes of the newly added capacitor, and the first gate dielectric layer (GI1) serves as the insulating layer of the newly added capacitor. The following explanation uses the existing first gate line (gate1) and second gate line (gate2) metals of the OLED structure as the electrodes of the newly added capacitor. Gate1 is connected to SD1 on the lower electrode side of the PIN photodiode via a via. Gate2 can be connected to a normal voltage signal independently, or it can be connected to the anode layer via a via to connect to the Vbias signal. The second gate dielectric layer (GI2) serves as the insulating layer of the capacitor. (See the planar design diagram for reference.) Figure 11 and Figure 12 As shown.

[0223] In some embodiments, the first capacitor electrode and the second capacitor electrode can be manufactured in the following manner.

[0224] First, an active layer is formed.

[0225] Then, the active layer is patterned to form a patterned active layer. The patterned active layer includes a first patterned region and a second patterned region that are electrically connected. The first patterned region corresponds to the active layer of the transistor in the output circuit, and the second patterned region corresponds to the first capacitor electrode.

[0226] Next, the first gate dielectric layer, the first gate line, the second gate dielectric layer, and the seventh metal layer are formed in sequence.

[0227] Then, the seventh metal layer is patterned to form the second capacitor electrode and the second gate line.

[0228] In one specific embodiment, the example of using the existing heavily doped polySi layer (conductive) and the second gate line (gate2) of the OLED structure as the electrodes of the newly added capacitor is described. The heavily doped polySi layer connected to the lower electrode side of the PIN photodiode is conductive and can serve as one electrode of the newly added capacitor. The second gate line (gate2) can be connected to a normal voltage signal alone, or it can be connected to the anode layer via a via to connect to the Vbias signal. The first gate dielectric layer GI1 and the second gate dielectric layer GI2 are used as the insulating layers of the newly added capacitor. The planar design is shown in the figure. Figure 14 and Figure 15 As shown.

[0229] The two embodiments described above are suitable for use where design space allows. Any two masks, such as heavily doped poly Si layers, gate1, gate2, SD1, and SD2 layers, can be reused to form multilayer capacitors connected in parallel without adding any process, increasing thickness, or increasing cost.

[0230] The process flow of the two embodiments described above can be as follows: First, a buffer insulating layer is deposited. Next, polysilicon is deposited, crystallized, and photolithographically patterned to form a polysilicon pattern. Then, a GI1 insulating layer is deposited, followed by gate1 layer deposition and photolithography to form a pattern. Next, polysilicon is doped to form a channel. Then, a GI2 insulating layer is deposited, followed by gate2 layer deposition and photolithography, and an ILD insulating layer deposition and photolithography. GI1, GI2, and ILD are etched together to form vias connecting to the polysilicon or gate1 or gate2. Next, an SD1 layer is deposited and photolithographically patterned to form a TFT structure. Then, PVX1 is deposited, PLN1 is coated with resist, exposed, and developed. Then, PVX2 is deposited and photolithographically patterned. PVX1 and PVX2 are etched together. Next, SD2 is deposited and photolithographically patterned to form the lower electrode of the PIN. Then, N-Si, I-Si, P-Si of the PIN and the upper electrode ITO are deposited, coated with resist, exposed, developed, ITO etched, and the PIN etched. Finally, a cover layer is deposited. Then comes PLN2 coating, exposure, and development. Next is anolyte deposition and photolithography. Then comes EL evaporation, PDL coating, exposure, and development. Finally, PS photolithography, cathode deposition, and encapsulation layer deposition.

[0231] This embodiment offers the following advantages: For example, it provides more feasible methods for capacitor formation, particularly by utilizing heavily doped polySi as one electrode of the capacitor. For instance, one side of the capacitor is connected to the negative electrode of the PIN, while the other side can be connected to a constant voltage signal. The voltage difference across the capacitor can be adjusted based on the PIN charge generation, thereby increasing the charge storage capacity and meeting the requirements for fingerprint recognition under strong PIN light. For example, the increased upper limit of capacitor storage capacity allows for increased backlight brightness during backlight testing without causing PIN saturation, further enhancing signal strength and improving the signal-to-noise ratio. For instance, the number of capacitors per sensing pixel can be one, or multiple capacitors connected in parallel across multiple metal layers, mitigating the problem of insufficient capacitance due to insufficient usable area in a certain pixel circuit layer.

[0232] In some embodiments, the first capacitor electrode and the second capacitor electrode are manufactured in the following manner.

[0233] First, the eighth metal layer is formed.

[0234] Then, the eighth metal layer is patterned to form a patterned eighth metal layer, which includes a third patterned region and a fourth patterned region that are electrically connected. The third patterned region corresponds to the first electrode of the transistor in the output circuit, and the fourth patterned region corresponds to the first capacitor electrode.

[0235] Next, the photosensitive circuit, dielectric layer, and ninth metal layer are formed sequentially. The photosensitive circuit can be formed through thin film processing, photolithography, and etching processes. For example, the P / I / N electrode stack of the PIN photodiode is first formed, and then the PIN photodiode is formed through photolithography and etching processes.

[0236] Then, the ninth metal layer is patterned to form the second capacitor electrode.

[0237] A new metal layer and insulating layer are added above the cover insulating layer on the PIN photodiode. The second source / drain, SD2, serves as the lower electrode of the newly added capacitor, the cover insulating layer serves as the insulating layer for the new capacitor, and the new metal layer serves as the upper electrode of the capacitor. The upper electrode can be connected to a constant voltage signal independently. Alternatively, the upper electrode can be connected to the anode layer via a via to receive the Vbias signal. (Reference) Figures 16-18 As shown, this technical solution is suitable for implementation under conditions of limited design space. The advantage of this approach is that the newly added capacitor film layer is located far from the sensing and display TFT circuits, resulting in lower noise impact from crosstalk between the display and sensing capacitors. It should be noted that the material of the newly added metal layer can be Mo, Ti / Al / Ti, Mo / Al / Mo, ITO, etc., and the metal thickness can vary from [missing information - likely a range from 0 to 1]. Change to Both are acceptable. It should be noted that implementations that do not require an additional metal layer and implementations that include an additional metal layer are compatible with each other and can be used simultaneously.

[0238] Specifically, the process flow requiring the addition of a metal layer adds one metal layer and one insulating layer PVX3 compared to the process without adding a metal layer. However, the number of exposures only increases by one. Specifically, a buffer insulating layer can be deposited first. Next, polysilicon is deposited, crystallized, and photolithographically patterned. Then, the first gate dielectric layer GI1 is deposited. Then, the first gate line (gate1) layer is deposited and photolithographically patterned. Next, polysilicon is doped to form a channel. Then, the second gate dielectric layer GI2 is deposited, the second gate line (gate2) layer is deposited and photolithographically patterned, and the ILD insulating layer is deposited and photolithographically patterned. GI1, GL2, and ILD are etched together to form vias connecting to the polysilicon or gate1 or gate2. Next, the SD1 layer is deposited and photolithographically patterned to form the TFT structure. Then, PVX1 is deposited, PLN1 is coated, exposed, and developed. Then, PVX2 is deposited and photolithographically patterned. PVX1 and PVX2 are etched together, and then SD2 is deposited and photolithographically patterned to form the lower electrode of the PIN. Then, the N-Si, I-Si, P-Si layers of the PIN photodiode and the indium tin oxide (TTO) top electrode are deposited, followed by resist coating, exposure and development, ITO etching, and PIN etching. Next, a cover layer is deposited, followed by a metal layer deposition and photolithography to form the pattern, serving as the top electrode of the newly added capacitor. Then, an insulating layer (PVX3) is deposited, photolithographically etched, and the cover and PVX3 are etched together. Next, resist coating, exposure, and development are performed on the PLN2 layer. Then, the anode is deposited and photolithographically etched. Next, EL deposition is performed, followed by resist coating, exposure, and development on the PDL layer. Finally, photolithography of the PS layer, cathode deposition, and encapsulation layer deposition are performed.

[0239] This embodiment offers advantages over embodiments that do not require an additional metal layer, for example, the electrodes of the newly added capacitor are further away from the TFTs and signal traces of the display and sensor below, separated by two layers of PVX and a thicker resin layer. Therefore, crosstalk to the display and sensor signal traces below is significantly reduced. This implementation reduces the sensor's impact on the display and also reduces noise generated by the display. For example, adding a metal layer allows for a larger design area, enabling the formation of a larger capacitor, greatly improving resistance to strong light, and also allowing for increased backlight brightness during testing, significantly improving the sensor's signal-to-noise ratio. For example, one electrode of the newly added capacitor is connected to the negative terminal of a PIN photodiode, while the other electrode can be connected to a constant voltage signal. Adjusting the voltage difference across the capacitor by controlling the charge generation of the PIN photodiode increases the charge storage capacity, meeting the requirements for fingerprint recognition detection under strong PIN light. For example, the increased upper limit of the capacitor's storage capacity allows for increased backlight brightness during backlight testing without saturating the PIN photodiode's storage capacity, further increasing the signal strength and improving the signal-to-noise ratio.

[0240] In some embodiments, the above-described method for manufacturing the display panel may further include the following operations: forming at least one second capacitor connected in parallel with the first capacitor, each of the at least one second capacitor including a third electrode and a fourth electrode; the third electrode and the fourth electrode are manufactured in the same manner as the first capacitor electrode and the second capacitor electrode.

[0241] This disclosure provides an OLED structure that enhances the strong light resistance of in-cell fingerprint sensors. By adding one or more additional capacitors to the PIN location, with one electrode connected to the negative terminal of the PIN photodiode and the other electrode connected to a constant voltage signal or a Vbias signal, the high charge storage capacity of the PIN photodiode in strong light environments is improved, effectively addressing the saturation problem of the PIN photodiode under strong outdoor light in OLED in-cell fingerprint recognition. Furthermore, the increased upper limit of stored charge leads to a further increase in the upper limit of signal quantity, which is beneficial for improving the signal-to-noise ratio.

[0242] This disclosure provides a structural design method for an OLED display panel. For example, where design space allows, existing OLED structure layers such as gate1, gate2, heavily doped poly Si, SD1, and SD2 are reused as the electrodes of a new capacitor, with GI serving as the insulating layer. No additional processing steps or cost increases are required. Conversely, when design space is insufficient, a metal layer and an insulating layer need to be added. The cover layer is not photolithographically ...

[0243] Another aspect of this disclosure provides a display device, including the display panel shown above.

[0244] Figure 20 A block diagram of an electronic device provided in an embodiment of this disclosure.

[0245] like Figure 20 As shown, the electronic device 2000 includes one or more display panels 1, 1' as shown above.

[0246] In some embodiments, reference Figure 1 and Figure 2 As shown, the display panel 1' further includes: a light-emitting element disposed in the light-emitting area, the light-emitting element including: an anode; the anode is coupled to the drain of the thin-film transistor of the pixel driving circuit.

[0247] The light emitted by the light-emitting element D passes through the substrate; the orthographic projection of the portion of the gate driving circuit 13 located in the display area 10 onto the substrate does not overlap with the orthographic projections of the light-emitting element D and the pixel driving circuit 12 onto the substrate.

[0248] When the light emitted by the light-emitting element D passes through the substrate, the display panel 1 is a bottom-emitting type display panel. When the orthographic projection of the part of the gate driving circuit 13 located in the display area 10 on the substrate does not overlap with the orthographic projection of the light-emitting element D and the pixel driving circuit 12 on the substrate, the gate driving circuit 13 will not affect the aperture ratio of the display panel 1'. The area where the gate driving circuit 13 is located is a non-light-emitting area, and the area where the light-emitting element D is located is a light-emitting area.

[0249] In some embodiments, the orthographic projection of the non-light-emitting area where the pixel driving circuit 12 is located on the substrate and the orthographic projection of the light-emitting area where the light-emitting element D is located on the substrate do not overlap.

[0250] In some embodiments, the orthographic projection of the area where the pixel driving circuit 12 is located on the substrate partially overlaps with the orthographic projection of the light-emitting area where the light-emitting element D is located on the substrate. Specifically, the two plates of the storage capacitor in the pixel driving circuit 12 are made of, for example, a transparent conductive material. One plate is made of the same material as the first active layer, i.e., indium gallium zinc oxide (IGaZN). In this case, the plate can be fabricated simultaneously with the first active layer, thereby reducing the number of masking operations. The other plate is made of, for example, indium tin oxide (ITO). In this case, the orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the light-emitting element D on the substrate. In this structure, since both plates of the storage capacitor are transparent, the storage capacitor can be located in the light-emitting area, while the area of ​​the pixel driving circuit 12 other than the storage capacitor is a non-light-emitting area. When the storage capacitor is located in the light-emitting area, the aperture ratio of the display panel 1' can be increased.

[0251] For example, each pixel unit includes four sub-pixels P, and the arrangement of the light-emitting colors of these four sub-pixels P is, for example, red, green, blue, and any combination of colors, such as green, blue, or white (White, W). When combined with white, this arrangement of sub-pixels P can increase the brightness of the pixel unit, thereby improving the display effect of the display panel 1'.

[0252] In some embodiments, the light emitted by the light-emitting element D is directed toward the side away from the substrate. This type of display panel 1' is a top-emitting display panel. In a top-emitting display panel, the orthographic projection of the portion of the gate driving circuit 13 located in the display area 10 onto the substrate can overlap with the orthographic projection of the light-emitting element D onto the substrate, without affecting the aperture ratio of the display panel 1'.

[0253] Regardless of whether the display panel 1' is a bottom-emitting or top-emitting display panel, the structure of the display panel 1' is as follows: Figure 11 As shown, along the thickness direction of the display panel 1', the display panel 1' includes a light-shielding layer, a buffer layer, a thin-film transistor, an anode, and a planarization layer disposed on a substrate. The thin-film transistor is the driving transistor T3 in the pixel driving circuit 12. The thin-film transistor includes, for example, a first active layer, a first gate insulating layer, a gate, an interlayer insulating layer, a source / drain layer (SD layer), and a passivation layer.

[0254] The material of the light-shielding layer is, for example, a light-shielding material, such as a black matrix material or a metallic material. Figure 11Taking a metallic material as an example, the light-shielding layer needs to be coupled to the SD layer to form a structure similar to a dual-channel structure, thereby improving the electrical performance of the thin-film transistor. The light-shielding layer is configured to prevent light incident from the substrate from affecting the first active layer, thus impacting the performance of the thin-film transistor.

[0255] The material of the first active layer is, for example, a metal oxide or polycrystalline silicon or amorphous silicon; the metal oxide is, for example, indium gallium zinc oxide.

[0256] The gate material is, for example, a metallic material, such as molybdenum, titanium, copper, silver, or aluminum, and its structure is, for example, a single-layer structure.

[0257] In some embodiments, the cathode is made of a transparent conductive material, and the anode is made of a metallic material. The metallic material can be one with high conductivity and high reflectivity, which allows light emitted from the light-emitting layer 141 towards the substrate to be reflected by the anode to the top of the pixel unit for emission, thus improving light extraction efficiency and reducing energy consumption.

[0258] The material of the SD layer can be a metal, such as molybdenum, titanium, copper, silver, or aluminum. Its structure can be a single layer or a multilayer structure. For example, the conductive layer of the source / drain electrode can be Ti / Al / Ti.

[0259] Specifically, the gate material may include metallic materials, such as metals like Mo, Al, and Cu, and their alloys. The source and drain materials may also include metallic materials, such as metals like Mo, Al, and Cu, and their alloys. The semiconductor materials constituting the active layer may include, for example, amorphous silicon, polycrystalline silicon, and oxide semiconductors. Oxide semiconductor materials may include, for example, IGZO (indium gallium zinc oxide) and ZnO (zinc oxide).

[0260] The materials of the buffer layer, the first gate insulating layer, the interlayer insulating layer and the passivation layer are, for example, inorganic insulating materials, such as at least one of silicon oxide (SiOx) and silicon nitride (SiN).

[0261] The anode material is, for example, a conductive material, including ITO, which can be a single-layer structure or a multilayer structure.

[0262] The planarization layer is made of an organic material, such as polyimide (PI), and serves a planarization function.

[0263] The gate can be routed in two layers in the GIA region (such as the first gate line g1 and the second gate line g2), which can reduce the resistance (RC) of the first conductive layer.

[0264] In addition, the display device 2000 may include one or more processors 2010 and computer-readable storage media 2020.

[0265] Specifically, processor 2010 may include, for example, a general-purpose microprocessor, an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. Processor 2010 may also include onboard memory for caching purposes.

[0266] Computer-readable storage media 2020 may be, for example, non-volatile computer-readable storage media, including but not limited to: magnetic storage devices such as magnetic tape or hard disk (HDD); optical storage devices such as optical disc (CD-ROM); memory such as random access memory (RAM) or flash memory, etc.

[0267] The computer-readable storage medium 2020 may include a program 2021, which may include code / computer-executable instructions that, when executed by the processor 2010, cause the processor 2010 to perform image display data processing. For example, in an exemplary embodiment, the code in the program 2021 may include one or more program modules, such as program module 2021A, program module 2021B, ...

[0268] The aforementioned display device can include any device or product with display functionality. For example, the aforementioned display device can be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (such as head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0269] Although this disclosure has been described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to be illustrative of embodiments of this disclosure and should not be construed as limiting the disclosure. The dimensions in the drawings are merely schematic and should not be construed as limiting the disclosure.

[0270] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: Substrate; A pixel circuit disposed on the substrate, the pixel circuit including a transistor, the transistor of the pixel circuit including an active layer, a gate, a first electrode and a second electrode; as well as A fingerprint recognition circuit includes a photosensitive circuit, a storage circuit, and an output circuit. The storage circuit includes a first capacitor, which includes a first capacitor electrode and a second capacitor electrode. The photosensitive circuit includes a photodiode. The photosensitive circuit is configured to convert the received optical signal into an electrical signal, the storage circuit is configured to store the electrical signal, and the output circuit includes a control switch configured to control the photosensitive circuit to charge the storage circuit in an open state, and to output at least the stored electrical signal in a closed state, so as to perform fingerprint recognition based on the output electrical signal. Wherein, the first capacitor electrode is disposed in the same layer as at least one of the gate, the active layer, the first electrode, or the second electrode, and / or, the second capacitor electrode is disposed in the same layer as at least one of the gate, the active layer, the first electrode, or the second electrode; the first capacitor electrode and the second capacitor electrode are disposed in different layers, and the orthogonal projections of the first capacitor electrode and the second capacitor electrode on the substrate at least partially overlap.

2. The display panel according to claim 1, wherein, The gate includes a first gate line and a second gate line, wherein the first gate line and the second gate line are located in different layers; and The first capacitor electrode is disposed on the same layer as the first gate line or the second gate line, and the second capacitor electrode is disposed on the same layer as the first gate line or the second gate line.

3. The display panel according to claim 2, further comprising: A first gate dielectric layer is disposed between the active layer and the first gate line; A second gate dielectric layer is disposed between the first gate line and the second gate line; as well as An interlayer dielectric layer is disposed on the side of the second gate dielectric layer away from the substrate.

4. The display panel according to claim 3, wherein: The first capacitor electrode is connected to the first electrode through a first via, and the first via is disposed in the second gate dielectric layer and the interlayer dielectric layer; or The second capacitor electrode is connected to the first electrode through a second via. The second via is disposed in the interlayer dielectric layer and exposes the second capacitor electrode.

5. The display panel according to claim 1, wherein, The gate includes a first gate line and a second gate line, wherein the first gate line and the second gate line are located in different layers; and The first capacitor electrode is disposed on the same layer as the first gate line or the second gate line, and the second capacitor electrode is disposed on the same layer as the active layer.

6. The display panel according to claim 1, wherein: The first capacitor electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode, and the second capacitor electrode is disposed in the first metal layer, wherein the first metal layer is located in a different layer from the gate, the active layer, and the first electrode. or The second capacitor electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode, and the first capacitor electrode is disposed in the second metal layer. The second metal layer is located in a different layer from the gate, the active layer, and the first electrode.

7. The display panel according to claim 6, wherein, The first capacitor electrode is disposed in the same layer as the first electrode, and the second capacitor electrode is disposed on the side of the photosensitive circuit away from the substrate. There is a distance between the second capacitor electrode and the orthographic projection of the photosensitive circuit on the substrate.

8. The display panel according to claim 7, further comprising: An interlayer dielectric layer is disposed on the side of the gate away from the substrate. An insulating layer, wherein the first thickness of the insulating layer is greater than the second thickness of the interlayer dielectric layer; The first electrode includes: The first sub-electrode is disposed on the side of the interlayer dielectric layer away from the substrate. A second sub-electrode is disposed on the side of the first sub-electrode away from the substrate, and the insulating layer is disposed between the first sub-electrode and the second sub-electrode; and The photosensitive circuit is disposed on the side of the second sub-electrode away from the substrate.

9. The display panel according to claim 1, wherein, The storage circuit further includes at least one second capacitor connected in parallel with the first capacitor, each of the at least one second capacitor including a third electrode and a fourth electrode.

10. The display panel according to claim 9, wherein: The third electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode, and the fourth electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode; The third electrode and the fourth electrode are disposed on different layers, and the orthogonal projections of the third electrode and the fourth electrode on the substrate at least partially overlap.

11. The display panel according to claim 9, wherein: The third electrode is disposed in the same layer as at least one of the gate, the active layer, or the first electrode, and the fourth electrode is disposed in the third metal layer, wherein the third metal layer is located in a different layer from the gate, the active layer, and the first electrode. or The fourth electrode is disposed on the same layer as at least one of the gate, the active layer, or the first electrode, and the fourth electrode is disposed on a fourth metal layer, which is located on a different layer from the gate, the active layer, and the first electrode.

12. The display panel according to claim 9, wherein, The gate includes a first gate line and a second gate line, which are located on different layers; the third electrode is disposed on the same layer as the first gate line or the second gate line, and the fourth electrode is disposed on the same layer as the first gate line or the second gate line, which are located on different layers.

13. The display panel according to any one of claims 1 to 12, further comprising: Multiple pixel units are disposed on the substrate, and the multiple pixel units are arranged in an array on the substrate. The orthographic projections of the pixel units and the photosensitive circuit on the substrate overlap.

14. The display panel according to claim 13, wherein, The pixel unit includes at least one sub-pixel, each sub-pixel including a light-emitting element, the light-emitting element including an anode; and The pixel circuit includes a sub-pixel driving circuit, wherein the first electrode of the transistor in the sub-pixel driving circuit is connected to the anode.

15. The display panel according to claim 14, wherein, The output circuit includes a first transistor, and the sub-pixel driving circuit includes at least one second transistor; wherein... The first electrode of the first transistor and the first electrode of the second transistor are disposed on the same layer; and / or The gate of the first transistor is disposed on the same layer as the gate of the second transistor; and / or The active layer of the first transistor and the active layer of the second transistor are disposed on the same layer.

16. The display panel according to any one of claims 1 to 12, wherein, The photosensitive circuit includes a PIN photodiode.

17. The display panel according to claim 16, further comprising: A transparent conductive layer is disposed on the side of the PIN photodiode away from the substrate, and the transparent conductive layer is connected to the bias-introduced electrode.

18. A display device comprising the display panel as described in any one of claims 1 to 17.

19. A method for manufacturing a display panel, comprising: Provide substrates; A pixel circuit is disposed on the substrate, the pixel circuit including a gate, an active layer, a first electrode and a second electrode; A fingerprint recognition circuit is provided; the fingerprint recognition circuit includes a photosensitive circuit, a storage circuit, and an output circuit; the storage circuit includes a first capacitor, the first capacitor including a first capacitor electrode and a second capacitor electrode; the transistor of the output circuit is disposed on the same layer as the transistor of the pixel circuit; the photosensitive circuit includes a photodiode; The photosensitive circuit is configured to convert the received optical signal into an electrical signal, the storage circuit is configured to store the electrical signal, and the output circuit includes a control switch configured to control the photosensitive circuit to charge the storage circuit in an open state, and to output at least the stored electrical signal in a closed state, so as to perform fingerprint recognition based on the output electrical signal. Wherein, the first capacitor electrode is disposed in the same layer as at least one of the gate, the active layer, the first electrode, or the second electrode, and / or, the second capacitor electrode is disposed in the same layer as at least one of the gate, the active layer, the first electrode, or the second electrode; the first capacitor electrode and the second capacitor electrode are disposed in different layers, and the orthogonal projections of the first capacitor electrode and the second capacitor electrode on the substrate at least partially overlap.

20. The method for manufacturing a display panel according to claim 19, wherein, The first capacitor electrode and the second capacitor electrode are manufactured in the following manner: A fifth metal layer is formed, and the fifth metal layer is patterned to form a first capacitor electrode and a first gate line; Forming a second gate dielectric layer; A sixth metal layer is formed and the sixth metal layer is patterned to form a second capacitor electrode and a second gate line; the first width of the first capacitor electrode in a cross section perpendicular to the extension direction of the first gate line is greater than the second width of the second capacitor electrode in a cross section perpendicular to the extension direction of the second gate line. An interlayer dielectric layer is formed, and vias are formed in areas where the projections of the first capacitor electrode and the second capacitor electrode on the substrate do not overlap to expose the first capacitor electrode; as well as A first electrode is formed such that the first capacitor electrode and the first electrode are electrically connected.

21. The method for manufacturing a display panel according to claim 19, wherein, The first capacitor electrode and the second capacitor electrode are manufactured in the following manner: Formation of an active layer; The active layer is patterned to form a patterned active layer, the patterned active layer including a first patterned region and a second patterned region that are electrically connected, the first patterned region corresponding to the active layer of the transistor of the output circuit, and the second patterned region corresponding to the first capacitor electrode. The first gate dielectric layer, the first gate line, the second gate dielectric layer, and the seventh metal layer are formed sequentially. as well as The seventh metal layer is patterned to form a second capacitor electrode and a second gate line.

22. The method for manufacturing a display panel according to claim 19, wherein, The first capacitor electrode and the second capacitor electrode are manufactured in the following manner: Formation of the eighth metal layer; The eighth metal layer is patterned to form a patterned eighth metal layer, the patterned eighth metal layer including an electrically connected third patterned region and a fourth patterned region, the third patterned region corresponding to the first electrode of the transistor of the output circuit, and the fourth patterned region corresponding to the first capacitor electrode; The photosensitive circuit, the dielectric layer, and the ninth metal layer are formed sequentially. as well as The ninth metal layer is patterned to form the second capacitor electrode.

23. The method for manufacturing a display panel according to any one of claims 19 to 22, further comprising: At least one second capacitor is formed in parallel with the first capacitor, and each of the at least one second capacitor includes a third electrode and a fourth electrode; The third electrode and the fourth electrode are manufactured in the same way as the first capacitor electrode and the second capacitor electrode.

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