Quantum controller fast path interface

Abstract

Techniques are provided for routing qubit data. For example, one or more embodiments described herein can include a computer-implemented method for training a quantum controller fast path interface that can control the routing of the qubit data. The computer-implemented method can include training, by a system operably coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and a conditional engine by adjusting a delay value such that an equalized clock domain is characterized by a direct register-to-register transfer mode.

Description

Background Technology

[0001] This disclosure relates to a fast path interface for a quantum controller, and more specifically, to routing qubit information between one or more quantum controllers and a conditional engine via a fast path interface for a quantum controller characterized by a direct register-to-register transfer mode.

[0002] In quantum computing systems, it has been considered advantageous to develop hardware paths for routing qubit information, preferably as quickly as possible, to controllers of other qubits within a given qubit network. This transfer of qubit data to other qubit controllers would allow for the application of efficient conditional operations to these qubits. This has various potential applications in the world of quantum computing, including but not limited to topics such as forcing qubits to a known state and qubit teleportation. However, typical implementations of qubit data routing interfaces employ asynchronous boundaries and additional header information to constrain qubit data, which can be detrimental to system operation because these qubits continuously degrade as data transfer occurs. Summary of the Invention

[0003] The following overview is presented to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, nor is it intended to define any scope of any particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, computer-implemented methods, apparatuses, and / or computer program products for routing qubit data are described.

[0004] According to one embodiment, a computer-implemented method is provided. The computer-implemented method may include: training a quantum controller fast path interface, operatively coupled to a processor, by adjusting latency values ​​for routing qubit data bits between a quantum controller and a conditional engine, such that the uniformly paced clock domain is characterized by a direct register-to-register transfer mode. An advantage of this computer-implemented method is its ability to train the interface to reduce data transfer latency.

[0005] In some instances, the computer-implemented method may further include: the system selecting a delay value capable of stabilizing the uniform clock domain by shifting a delay device in the fast path interface of the quantum controller. An advantage of such a computer-implemented method is that embedded software can be used to train the interface rather than relying on hardware components.

[0006] According to one embodiment, a computer program product is provided for routing qubit data bits between a quantum controller and a conditional engine. The computer program product may include a computer-readable storage medium containing program instructions. The program instructions are executable by a processor to cause the processor to: train a quantum controller fast path interface by adjusting latency values ​​such that the uniform clock domain of the quantum controller fast path interface is characterized by a direct register-to-register transfer mode.

[0007] In some examples, the computer program product can also cause the processor to evaluate the stability of the uniformly paced clock domain at the delay value for the target line of the fast path interface of the quantum controller. An advantage of this computer program product is that quantum data bits can be centered from the domain edge so as to be outside the setup and hold time window.

[0008] According to an embodiment, a system is provided. The system may include: a quantum controller fast path interface that routes qubit data packets between the quantum controller and a conditional engine via a packet transport protocol, in which sender information is inferred from the data position within the qubit data packets. The advantage of such a system is that it can route qubit data traffic with low latency to account for qubit degradation.

[0009] In some examples of the system, the qubit data packets include an effective pairing of the data location with the qubit. An advantage of this system is that it allows for data packets of qubit data to be defined without requiring overhead information. Attached Figure Description

[0010] Figure 1 A block diagram of an example non-limiting quantum controller fast path interface, according to one or more embodiments described herein, is shown, capable of routing qubit information between one or more qubit controllers and / or conditional engines.

[0011] Figure 2 A block diagram of an example non-limiting training component capable of training a fast path interface for a quantum controller according to one or more embodiments described herein is shown;

[0012] Figure 3 A block diagram of an example non-limiting training component, according to one or more embodiments described herein, is shown, capable of evaluating clock domain stability associated with a given delay routine of a quantum controller fast path interface.

[0013] Figure 4A block diagram of an example non-limiting training component capable of tracking clock domain stability associated with a delay routine of a quantum controller fast path interface, according to one or more embodiments described herein, is shown.

[0014] Figure 5 A block diagram of an example non-limiting training component, according to one or more embodiments described herein, is shown, capable of controlling one or more latency values ​​associated with a latency routine of a quantum controller fast path interface.

[0015] Figure 6 A block diagram of an example non-limiting training component, according to one or more embodiments described herein, is shown, capable of evaluating clock domain stability associated with a given delay routine of a quantum controller fast path interface.

[0016] Figure 7 A flowchart is shown of an example non-limiting computer implementation of a method that can be used to train a fast path interface for a quantum controller according to one or more embodiments described herein;

[0017] Figure 8 A block diagram of an example non-limiting paternoster hardware protocol capable of being adopted by a quantum controller fast path interface according to one or more embodiments described herein is shown.

[0018] Figure 9 A flowchart is shown of an example non-limiting computer implementation of a method for training a fast path interface for a quantum controller, according to one or more embodiments described herein.

[0019] Figure 10 A block diagram is shown illustrating an example non-limiting operating environment that can facilitate one or more embodiments described herein. Detailed Implementation

[0020] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being limited by any explicit or implicit information presented in the prior art or invention description or detailed description sections.

[0021] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances.

[0022] Considering these problems with other implementations of qubit information routing, this disclosure can be implemented to generate solutions to one or more of these problems via a trainable quantum controller fast path interface that can employ one or more consecutive data packet transmission protocols. Advantageously, one or more embodiments described herein can relate to a quantum controller fast path interface that can be trained to exhibit data transfer characteristics similar to direct register-to-register transfers. Furthermore, this interface can be implemented using one or more consecutive packet transmission methods. Thus, qubit data can be routed between registries without the overhead bits traditionally used to identify the start and end of data packets. Furthermore, this interface can identify data sender information based on bit positions within data packets without traditional overhead bits.

[0023] Various embodiments of the present invention may relate to computer processing systems, computer-implemented methods, apparatuses, and / or computer program products that facilitate efficient, effective, and autonomous (e.g., without direct human guidance) routing of qubit information. For example, one or more embodiments described herein may relate to a quantum controller fast path interface capable of routing qubit information between one or more quantum controllers (e.g., the lowest-level quantum controller) and a conditional engine. One or more quantum controllers may excite one or more qubits, and the conditional engine may perform one or more Boolean operations on those qubits and route the results back to the endpoint. In various embodiments, the interface may be implemented using a continuous packet transmission method, wherein data packets containing only qubit data locations and qubit valids can be continuously transmitted between the controller and the conditional engine. Furthermore, the boundaries of the data packets may be established via one or more training algorithms embedded within the interface.

[0024] This computer processing system, computer-implemented method, apparatus, and / or computer program product employs hardware and / or conditional software to solve inherently highly technical (e.g., qubit information routing), non-abstract, and incapable of being performed by humans as a set of mental actions. Furthermore, one or more embodiments described herein can constitute a technical improvement over conventional qubit information routing via a quantum controller fast path interface employing an embedded training algorithm to define data packet boundaries. Additionally, the various embodiments described herein can demonstrate a technical improvement over conventional qubit information routing via a quantum controller fast path interface that uses a continuous packet transmission protocol to transfer data between registry entries without including overhead bits to define qubit data.

[0025] Furthermore, one or more embodiments described herein are practically applicable by establishing an interface between the quantum controller and the conditional engine that can be characterized by register-to-register transfer patterns. For example, the embodiments described herein can employ embedded training algorithms to define data packet boundaries for implementation in a continuous packet transmission protocol that identifies data sender information based on bit positions within data packets. One or more embodiments described herein can control one or more delay routines within one or more receiver chips based on the stability of the uniform clock domain. Thus, one or more embodiments can center data bits from the edge of a stable clock domain to place data bits outside the setup and hold window of the receive clock. For example, the embodiments described herein can control the delay routines of this interface to cross-line aligned data patterns and / or maximize timing margins to minimize the risk of data slippage that can be caused by device variations and / or temperature variations.

[0026] Figure 1 A block diagram of an example non-limiting interface 100 for routing qubit information between one or more quantum controller architecture blocks 102 and conditional engine architecture blocks 104 is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Aspects of systems (e.g., interface 100, etc.), apparatus, or processes in various embodiments of the invention may constitute one or more machine-executable components embodied within one or more machines (e.g., embodied within one or more computer-readable media associated with one or more machines). Such components, when executed by one or more machines (e.g., computers, computing devices, virtual machines, etc.), enable the machines to perform the described operations.

[0027] One or more quantum controller architecture blocks 102 may include one or more quantum controllers 106 operatively coupled to one or more transmitter chips 108 and receiver chips 110. In various embodiments, one or more quantum controllers 106 may be operatively coupled to one or more qubits. Exemplary qubit technologies may include, but are not limited to, trapped ion qubits and / or superconducting qubits. For example, in the case where the qubit is a trapped ion qubit, multiple ions may act as qubits, along with one or more traps for holding these ions in specific locations. Furthermore, a laser or microwave source may be directed to one or more of these ions to influence the quantum state of the ions, the laser may cool and / or enable the measurement of the ions, and / or one or more photon detectors may measure the state of the ions. In another instance, a superconducting qubit (e.g., a superconducting quantum interference device "SQUID") may be a photolithographically defined electronic circuit that may be cooled to milliKelvin temperatures to exhibit quantized energy levels (e.g., quantized states due to charge or magnetic flux). Superconducting qubits may be based on Josephson junctions, such as transmon qubits and / or the like. Furthermore, superconducting qubits are compatible with microwave-controlled electronics and can be used with gate-based technologies or integrated cryogenic control. Additional exemplary qubit technologies may include, but are not limited to: photonic qubits, quantum dot qubits, gate-based neutral atom qubits, semiconductor qubits (e.g., optically or electrically gated), topological qubits, combinations thereof, etc. As described herein, the term "superconducting" can characterize a material exhibiting superconducting properties at or below its superconducting critical temperature, such as aluminum (e.g., a superconducting critical temperature of 1.2 Kelvin) or niobium (e.g., a superconducting critical temperature of 9.3 Kelvin). Furthermore, those skilled in the art will recognize that other superconducting materials (e.g., hydride superconductors, such as lithium hydride / magnesium alloys) can be used in the various embodiments described herein.

[0028] One or more quantum controllers 106 can excite one or more qubits and / or output the results from such excitation. In various embodiments, one or more quantum controllers 106 can transmit qubit data generated by exciting one or more qubits to a conditional engine architecture block 104. For example, one or more quantum controllers 106 can transmit qubit data via one or more transmitter chips 108. One or more transmitter chips 108 of one or more quantum controller architecture blocks 102 are operatively coupled to one or more receiver chips 110 of the conditional engine architecture block 104. For example, one or more transmitter chips 108 of one or more quantum controller architecture blocks 102 are operatively coupled to one or more receiver chips 110 of the conditional engine architecture block 104 via one or more transmission line buses 112. Furthermore, one or more transmitter chips 108 may include a fast path transmit logic layer 113 for guiding one or more consecutive packet transmission protocols for guiding qubit data from one or more quantum controllers 106 to the conditional engine architecture block 104.

[0029] Furthermore, one or more quantum controllers 106 can stimulate one or more qubits based on one or more commands received via one or more receiver chips 110. In various embodiments, the one or more commands can be generated by the conditional engine architecture block 104. Figure 1 As shown, one or more receiver chips 110 of one or more quantum controller architecture blocks 102 can be operatively coupled to one or more transmitter chips 108 of conditional engine architecture blocks 104. For example, one or more receiver chips 110 of one or more quantum controller architecture blocks 102 can be operatively coupled to one or more transmitter chips 108 of conditional engine architecture blocks 104 via one or more transmission line buses 112.

[0030] The conditional engine architecture block 104 may include one or more conditional engines 116 operatively coupled to one or more transmitter chips 108 and / or receiver chips 110. For example... Figure 1 As shown, the conditional engine architecture block 104 can be operatively coupled to multiple quantum controller architecture blocks 102 via interface 100. Although in Figure 1Two quantum controller architecture blocks 102 are shown, but the architecture of interface 100 is not limited to this, and embodiments including more than two quantum controller architecture blocks 102 are also conceivable. In various embodiments, conditional engine 116 can generate one or more commands to guide the operation of one or more quantum controllers 106 based on received qubit data. For example, one or more conditional engines 116 can perform one or more Boolean operations and / or transformations based on qubit data transmitted by one or more quantum controller architecture blocks 102 and received via one or more receiver chips 110 of conditional engine architecture block 104. For example, one or more conditional engines 116 can control one or more conditional operations between quantum controllers 106 to perform various applications, such as forcing qubits to a known state and / or qubit instantaneous shifting.

[0031] In addition, interface 100 may include a common clock source generated from oscillator reference 118. For example... Figure 1 As shown, a common oscillator reference 118 can be operatively coupled to both one or more quantum controller architecture blocks 102 and conditional engine architecture blocks 104. For example, the transmit and receive clocks of the transmitter chip 108 and receiver chip 110 of interface 100 can be derived from the common clock of oscillator reference 118. In various embodiments, the common clock can be passed through a phase-locked loop network 120 to generate multiple clocks selectable via a glitch-free clock multiplexer 122. The glitch-free clock multiplexer 122 can derive clock signals for one or more conditional engines 116, transmitter chip 108, and / or receiver chip 110 of conditional engine architecture block 104.

[0032] The conditional engine architecture block 104 may also include one or more embedded processors 124, which may employ one or more training components 126 to execute one or more algorithms for training the interface 100. The one or more embedded processors 124 and / or training components 126 are operatively coupled to one or more programmable registers 128 included in the receiver chip 110 of the conditional engine architecture block 104. The one or more programmable registers 128 may control one or more delay elements 130 placed along one or more data paths established by the interface 100. Example delay elements 130 may include, but are not limited to: variable digital delay elements, serial chains of digital buffers (e.g., stages of a serial chain coupled to a multiplexer), analog circuitry, combinations thereof, and / or the like. Furthermore, the one or more receiver chips 110 of the conditional engine architecture block 104 may include one or more receiver logic layers 132 that can send qubit data values ​​to a programmable crossbar multiplexer 134.

[0033] In various embodiments, qubit data can be broadcast from one or more quantum controllers 106 and transmitted to the fast path transmit logic layer 113 of the transmit chip 108 of the quantum controller architecture block 102. As further described herein, the transmit logic layer 113 may include one or more free-running data pointers 114 and / or mask fields 115. In various embodiments, the one or more free-running data pointers 114 can select which qubit data and qubit valid pairs to transmit on one or more transmission line buses 112 each clock cycle. Furthermore, in various embodiments, one or more mask fields 115 can set and / or clear valid bits in data packets, wherein these bits can be set when received on the corresponding channel of the quantum controller 106 and cleared when a routing scheme rotation activates a routing scheme that allocates one or more lines to a given qubit data. The qubit data can also be multiplexed on a configurable number of lines in the transmission line bus 112. The transmission line bus 112 may include a line bundled with a packet start pulse for coordination with the receiver logic layer 132 of the corresponding receiver chip 110, and a parity check signal line to protect the qubit data signal, the qubit valid signal, and / or the packet start signal.

[0034] The receive logic layer 132 of the receive chip 110 of the conditional engine architecture block 104 can send qubit data to the programmable cross-multiplexer 134, where the data can be mapped to the receive buffer of the conditional engine 116. In various embodiments, the receive logic layer 132 may also include one or more free-running data pointers 114. The corresponding receive chip 110 may be paired with the corresponding transmitter chip 108 such that one or more free-running data pointers 114 of the receive logic layer 132 can be synchronized to the free-running data pointers 114 of the paired transmitter logic layer 113. Synchronization may be achieved via one or more training algorithms and / or computer-implemented methods executed by the training component 126 and further described herein. The receive logic layer 132 may have the same understanding of the number of lines in the transmission line bus 112 and the number of qubits coupled to the quantum controller 106 on the paired transmitter chip 108.

[0035] In various embodiments, the routing of data signals can be matched externally to the field-programmable gate array (“FPGA”) device to produce minimal skew. The transmitter chip 108 and / or receiver chip 110, which directly drive and / or receive the transmission line bus 112, can also be constrained to special I / O buffer registers to minimize internal data skew on interface 100. Timing constraints can be employed to attempt to minimize clock skew on these same registers.

[0036] like Figure 1 As shown, the transmit and receive clocks of both the transmitter chip 108 and the receiver chip 110 can be derived from a common oscillator reference 118 and passed through a PLL network 120 to generate multiple clocks selectable via a glitch-free clock multiplexer 122. The selected clocks on the transmitter chip 108 and the receiver chip 110 can be frequency-matched, provided that the same frequency is selected via register select bits. Because the clocks can be frequency-matched but not transmitted with the qubit data, the interface 100 can be a synchronized clock interface between the transmitter chip 108 and the receiver chip 110 on the drive and receive transmission line bus 112.

[0037] Although the skew of the transmission line bus 112 can be matched at all stages, including the drive and receive registers, the delay element 130 can be introduced into the data path along with the programmable register 128; this allows the training component 126 to train the data path so that the qubit data bits are centered from the edge of the synchronous clock domain and outside the setup and hold window of the receive clock. Furthermore, the training component 126 can ensure that the data pattern of the qubit data bits is aligned with the other lines of the transmission line bus 112. In various embodiments, the training component 126 can select the delay value of the delay element 130 to maximize timing margin and minimize the risk of future bit slippage that may result from variations due to component changes or temperature variations.

[0038] Figure 2-6 A block diagram of an example non-limiting training component 126 according to various embodiments described herein is shown. Training component 126 can execute one or more training algorithms to present the data transfer pattern of the interface as a direct register-to-register transfer. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, training component 126 can train interface 100 prior to one or more qubit data transfers between one or more quantum controllers 106 and conditional engine 116. For example, training component 126 can interact with programmable register 128 to observe line data and / or shift one or more delay elements 130.

[0039] like Figure 2As shown, training component 126 may include line selection component 202. In various embodiments, line selection component 202 may select an initial line of transmission line bus 112 as a training target. The data path associated with the selected line may be controlled by training component 126 via manipulating one or more delay elements 130. For example, training component 126 may identify a delay value to be executed by programmable register 128 controlling delay elements 130. Training component 126 may analyze each of the various delay routines available for the selected line (e.g., each delay routine may be associated with a relevant delay value) by changing the delay value associated with delay element 130. In various embodiments, line selection component 202 may also designate a line of each transmission line bus 112 as a reference line. For example, when training the target transmission line bus 112, the first line of transmission line bus 112 selected by line selection component 202 may be considered a reference line.

[0040] like Figure 3 As shown, training component 126 may also include domain stability component 302. In various embodiments, domain stability component 302 can evaluate the step-clock domain stability of the selected line at the current delay routine for the data path. In one or more embodiments, domain stability component 302 can determine whether the transmission pattern associated with the current delay routine exhibits a stable single register-to-register level between the corresponding transmitter chip 108 and receiver chip 110. For example, domain stability component 302 can analyze the qubit data bit string transmitted by transmitter chip 108 to identify one or more patterns. Furthermore, the string pattern characterizing a stable single register-to-register level can be predefined by domain stability component 302. If the qubit data bit string received by receiver chip 110 matches a predefined pattern, domain stability component 302 can determine that the step-clock domain stability associated with the current delay value for delay element 130 is a stable single register transfer level (“RTL”) level. For example, programmable register 128 can be a shift registry, the predefined pattern can be a predefined level of the shift registry, and domain stability component 302 can determine whether the received qubit data string is in the predefined shift registry level. If the current delay routine is not characterized by a stable single register-to-register level transfer pattern, training component 126 can continue to analyze other delay routines and / or lines of transmission line bus 112.

[0041] In various embodiments, the domain stability component 302 can analyze the observed data transmission pattern of the line multiple times to determine whether the uniform clock domain stability is characterized by a stable single register to register-level pattern. For example, the domain stability component 302 can analyze the pattern hundreds of times by enabling and disabling the data transmission pattern from the transmitter side. By repeatedly analyzing the data transmission pattern of the current delay routine, the domain stability component 302 can enhance the confidence in the pattern determination.

[0042] like Figure 4 As shown, training component 126 may further include domain region component 402. In various embodiments, domain region component 402 may track a stable domain region of the synchronizing clock. If domain stability component 302 determines that the delay routine currently being evaluated is a stable single register-to-register level, domain region component 402 may then determine whether the selected line is a reference line or aligned with a reference line. For example, if the selected line is not a reference line, domain region component 402 may cross-reference the qubit data of the selected line with the qubit data of the reference line to ensure that the selected line is aligned with the reference line. If the selected line is neither a reference line nor aligned with a reference line, training component 126 may continue analyzing other delay routines and / or lines of transmission line bus 112.

[0043] When the selected line is a reference line, or when the selected line is aligned with a reference line, the domain region component 402 can further determine whether the delay routine has reached a known stable region of the step-time clock domain. If the selected line and the delay routine are in a known stable region, the domain region component 402 can increase the size of the corresponding region. For example, the domain region component 402 can increase the size of the region by a defined value (e.g., increase the size of the region by 1). If the selected line and the delay routine are not in a known stable region, the domain region component 402 can track a new region of the step-time clock domain. In various embodiments, the domain region component 402 can thereby track the domain stability associated with each delay routine (e.g., with each delay value) for the selected line. For example, the domain region component 402 can generate a table of stable delay regions for the selected line, where the boundaries of the stable regions can be determined by the presence of one or more unstable delay values.

[0044] like Figure 5As shown, training component 126 may additionally include delay value component 502. In various embodiments, delay value component 502 may determine whether there are any other delay routines that can be evaluated for the selected line. For example, delay value component 502 may determine whether there are any delay values ​​for delay element 130 that have not yet been evaluated during the training of the selected line. If there are available delay routines that have not yet been evaluated for the selected line, delay value component 502 may increase the current delay value to establish an alternative delay routine, which, according to the above features, can be further evaluated by domain stability component 302 and / or domain region component 402.

[0045] like Figure 6 As shown, training component 126 may also include centering component 602. In various embodiments, centering component 602 may select a delay value and thereby select a delay routine that places the selected line within the maximum stable region of the uniform clock domain. For example, once all available delay routines for the selected line have been evaluated, centering component 602 may select a delay value that reaches the maximum stable region. Furthermore, centering component 602 may center the selected line within the active clock edge of the region so that the qubit data bits are outside a restrictive time window. For example, centering component 602 may center the selected line starting from the edge of the maximum stable clock region so that the qubit data bits are outside the setup-hold time window. Furthermore, training component 126 may repeat the above features and / or operations with each line of the target transmission line bus 112.

[0046] Figure 7 A flowchart illustrating an example non-limiting training algorithm 700 executable by training component 126 according to one or more embodiments described herein is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. The various steps of training algorithm 700 can be performed by training component 126 and associated components of training component 126 according to the features and / or operations described herein.

[0047] At 702, training algorithm 700 may include selecting (e.g., via line selection component 202) a line of transmission line bus 702 as a training target. At 704, training algorithm 700 may include evaluating the uniform domain stability at the delay value currently being evaluated. For example, training component 126 may observe qubit data transmitted on the selected line with the current delay value. The delay value may be relative to one or more delay elements 130 arranged along the data path and may be implemented in the direction of training component 126 by programmable register 128.

[0048] At 706, training algorithm 700 may include determining whether the transmission pattern of the selected line with the current delay value exhibits a stable single register-to-register level between chips (e.g., between the transmitter chip 108 of quantum controller architecture block 102 and the receiver chip 110 of conditional engine architecture block 104). As described herein, in various embodiments, domain stability component 302 may determine whether the observed qubit data bit string is characterized by a defined pattern associated with a single RTL level. If the observed pattern exhibits a stable single register-to-register level, training algorithm 700 may proceed to step 708. If the observed pattern does not exhibit a stable single register-to-register level, training algorithm 700 may proceed to step 710.

[0049] At 708, training algorithm 700 may include determining whether the selected line is a reference line. In various embodiments, domain stability component 302 may designate a line from target transmission line bus 112 as a reference line. For example, a first line of target transmission line bus 112 selected for training may be designated as a reference line. If the selected line is a reference line, training algorithm 700 may proceed to step 712. If the selected line is not a reference line, training algorithm 700 may proceed to step 714.

[0050] At 714, training algorithm 700 may include determining whether the selected line is aligned with a reference line. For example, observed qubit data of the selected line may be cross-referenced with a snapshot of qubit data transmitted along the reference line (e.g., via domain region component 402) to determine whether the selected line and the reference line are aligned. If the selected line and the reference line are aligned, training algorithm 700 may proceed to step 712. If the selected line and the reference line are not aligned, training algorithm 700 may proceed to step 710.

[0051] At 712, training algorithm 700 may include determining whether a delay routine is already in a stable region. For example, domain region component 402 may track stable regions associated with the selected line via one or more region tracking tables for stable delay regions, wherein the boundaries of the stable regions may be determined by the presence of one or more unstable delay values. If it is determined that the delay routine is within a known stable region, training algorithm 700 may proceed to step 716. If the delay routine is not within a known stable region, training algorithm 700 may proceed to step 718.

[0052] At 716, training algorithm 700 may include increasing the current region size. For example, domain region component 402 may increase the size of a known stable region by a defined value (e.g., by 1). At 718, training algorithm 700 may include tracking new stable regions. For example, domain region component 402 may update the region tracking table associated with the selected line to reflect the increased region size and / or the presence of new stable regions. Training algorithm 700 may proceed from step 716 or step 718 to step 710.

[0053] At 710, training algorithm 700 may include determining whether there are additional delay values ​​to evaluate for the selected line. For example, delay value component 502 may determine whether all available delay values ​​for delay element 130 have already been evaluated for the selected line by training component 126. For example, delay value component 502 may refer to a table constructed by domain region component 402 to determine previously evaluated delay values ​​and compare these delay values ​​with a list of delay values ​​for delay element 130 that can be used by programmable register 128. If additional delay values ​​to evaluate exist, training algorithm 700 may proceed to step 720. If no additional delay values ​​are available for evaluation, training algorithm 700 may proceed to step 722.

[0054] At 720, the training algorithm 700 may include increasing the latency value. For example, the latency value component 502 may increase the latency value by a defined value to a latency value that has not yet been evaluated by the training component 126 for the selected line. Figure 7 As shown, once the delay value increases to a new delay value, the training algorithm 700 can repeat steps 706-718 to evaluate the transmission pattern and / or domain stability associated with the new delay value. At 722, the training algorithm 700 may include selecting a delay value associated with the maximum stable region. For example, the centering component 602 may query a region tracking table constructed by the domain region component 402 to identify the maximum region associated with the evaluated delay value. In various embodiments, the training algorithm 700 may also include centering the qubit data bits of the selected line and delay routine within the receive clock domain, starting from the active clock edge, at 722. For example, the qubit data bits may be centered starting from the rising and falling edges of the maximum region. Thus, the qubit data bits can be placed outside the setup and hold time window for each edge. For example, if the maximum region has a size of 300 and a boundary defined by a minimum delay value of 100 and a maximum delay value of 400, the centering component 602 may select a delay value of 250 for the selected line.

[0055] In one or more embodiments, algorithm 700 may be trained repeatedly for each line of the target transmission line bus 112 and / or for each transmission line bus 112 of the interface 100. For example, embedded training component 126 may perform steps 702-722 for each line of one or more transmission line buses 112 to train interface 100.

[0056] Figure 8 A diagram is shown illustrating an example non-limiting continuous packet transport protocol 800 that may be employed by interface 100 according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, interface 100 may employ the example continuous packet transport protocol 800 after training performed by embedded training component 126. Figure 8 As shown, according to the continuous packet transmission protocol 800, data packets containing only qubit data positions and qubit valids can be continuously transmitted between one or more transmitter chips 108 of the quantum controller architecture block 102 and the receiver chip 110 of the conditional engine architecture block 104. The boundaries of the data packets can be established during training performed by the training component 126 (e.g., during training performed according to the training algorithm 700). As qubit data becomes available, the continuous packet transmission protocol 800 can hold that data until the next data packet arrives, inserting new bits of the qubit data (e.g., new qubit measurements) and qubit validations, and then sending the packet to the receiver chip 110. Thus, no overhead bits are needed to identify the start and end of the data packets, and sender information can be inferred from the bit positions within the data packets. Advantageously, the continuous packet transmission protocol 800 enables data transmission during the runtime of the interface 100 to be performed with low latency to overcome qubit degradation that occurs during transmission.

[0057] In one or more embodiments, the continuous packet transmission protocol can be implemented by combining the transmit logic layer 113 of the transmitter chip 108 of the quantum controller architecture block 102 with the receive logic layer 132 of the receiver chip 110 of the conditional engine architecture block 104. Furthermore, the inter-chip transmission line bus 112 may include "k" lines (e.g., such as...). Figure 8As shown, lines 0, 1, 2 to "k" are represented, where the total number of lines is a positive even integer. The transmit logic layer 113 can traverse multiple routing schemes that guide line allocation by masking the number of qubits emitted via a free-running pointer in the current cycle. Additionally, the transmit logic layer 113 can set the valid vector of transmitted qubits based on reception from the associated quantum controller 106 acquisition channel. Furthermore, the valid vector of transmitted qubits can be cleared upon transmission to the conditional engine architecture block 104. The receive logic layer 132 can have the same understanding of the routing scheme rotation as the transmit logic layer 113. Furthermore, the receive logic layer 132 can process the currently incoming qubit data and valid pairs on the transmission line bus 112 for each cycle and forward these pairs to the conditional engine 116 according to the conditional allocation mapping.

[0058] like Figure 8 As shown, the continuous packet transmission protocol 800 may include multiple cycles (e.g., "x" cycles up to and including cycle "n"). Within each cycle, the continuous packet transmission protocol 800 may employ different routing schemes to allocate lines for transmitting qubit data and valid pairs. The number of cycles can be configured based on the number of qubit data and valid pairs broadcast from the quantum controller 106. As long as the transmit logic layer 113 and receive logic layer 132 are configured with the same routing scheme for rotation and cycle counting, qubit constraint information can be inferred based on the lines used for data transmission, the current cycle count, and / or the qubit data bit positions within the data packet.

[0059] When the number of qubits controlled by the quantum controller 106 is "q" and the number of lines "i" of the transmission line bus 112 is greater than or equal to twice the number of qubits "q" (e.g., where 2×q≤i), qubit data from the corresponding qubit can be routed to the same line (e.g., line 0) in each cycle (e.g., at least because there are enough lines for each qubit data and qubit valid from the quantum controller 106). However, when the number of lines "i" is less than twice the number of qubits "q" (e.g., where 2×q>i), the transmit logic layer 113 and the receive logic layer 132 can traverse multiple routing schemes to alternate line allocation in each cycle, and thereby transmit all available qubit data and valid pairs without limiting overhead information and / or without strictly dedicated lines.

[0060] For example, an array “a” containing grouped data can be defined according to the following Equation 1:

[0061]

[0062] For example: a[0] can contain qubit 0 data, a[1] can contain qubit 0 valid, a[2] = qubit 1 data, and so on. Furthermore, assigning a given line "w" with index "k" to the data packet array "a" during a given clock period "x" can be characterized by the following Equation 2:

[0063] w k =a[(i*x+k)%(2*q)] (2)

[0064] Figure 8 An exemplary routing scheme rotation is illustrated, where line allocation changes every clock cycle. For example, during cycle 0 of a continuous packet transmission protocol 800, qubit data from qubit 0 can be routed to line 0, valid qubits from qubit 0 can be routed to line 1, qubit data from qubit 1 can be routed to line 2, and so on. For example, cycle 0 can follow a routing scheme such that valid qubits routed to line "k" are from qubit ((k+1) / 2)-1 (e.g., with respect to line 1, "k" equals 1 and therefore valid qubits from qubit 0 are routed to line 1, as shown), and qubit data from the same qubit is routed to the previous line in the index (e.g., qubit data from qubit 0 is routed to line 0).

[0065] In the next cycle, the continuous packet transmission protocol 800 can rotate to a new routing scheme so that the lines have different qubit allocations. For example, during cycle 1 of the continuous packet transmission protocol 800, qubit data from qubit 1 can be routed to line 0, qubit valid data from qubit 1 can be routed to line 1, qubit data from qubit 3 can be routed to line 2, qubit valid data from qubit 3 can be routed to line 3, and so on. For example, cycle 1 can follow a routing scheme such that qubit valid data routed to line "k" is from qubit ((k+1) / 2)*2-1 (e.g., with respect to line 3, "k" equals 3 and therefore qubit valid data from qubit 3 is routed to line 3), and qubit data from the same qubit is routed to the previous line (e.g., qubit data from qubit 3 is routed to line 2).

[0066] During example period 0, data packets for qubits 0 and 2 are available because the qubit data and valid pairs for both qubits are assigned to lines (e.g., lines 0-1 and 4-5). However, during example period 1, data packets for qubits 0 and 2 are unavailable because the routing scheme employed during period 1 does not assign lines to the qubit data and valid pairs for these qubits. Therefore, when qubit data and valid pairs become available starting from qubits 0 and 2, the qubit data and valid pairings can be forced to wait for one period by the transmission logic circuitry layer 113, which employs a routing scheme with available data packets for qubit data and valid pairings for qubits 0 and / or 2. For example, available qubit data and valid pairings from qubits 0 and / or 2 can be forced to wait until example period 0 or another period with available data packets is active in the rotation of the routing scheme.

[0067] When the Continuous Packet Transport Protocol 800 traverses the routing scheme, the round-robin protocol can eventually loop back to the initial routing scheme, and the Continuous Packet Transport Protocol 800 can traverse the routing scheme again. For example, Figure 8 The example shows that the routing scheme for period "n" is the same as the initial rotation scheme for period 0, for example; thus, it shows that in period "n", the continuous packet transmission protocol 800 can begin to repeat the rotation protocol. For example, the routing scheme for period "n+1" can be the same as the routing scheme for period 1, for example.

[0068] Figure 9 A flowchart of an example non-limiting computer implementation of a method 900 that can be used for training interface 100 according to one or more embodiments described herein is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, training component 126 may employ the computer-implemented method 900 via executing training algorithm 700.

[0069] At 902, the computer-implemented method 900 may include evaluating (e.g., via domain stability component 302) the stability of a uniformly paced clock domain at one or more delay values ​​for a target line (e.g., included within transmission line bus 112) of a quantum controller fast path interface (e.g., interface 100) by a system (e.g., interface 100) operatively coupled to a processor (e.g., embedded processor 124). At 904, the computer-implemented method 900 may include determining (e.g., via domain stability component 302) whether the uniformly paced clock domain is characterized by a stable direct register-to-register transfer pattern at one or more delay values.

[0070] At 906, the computer-implemented method 900 may include determining, by the system (e.g., interface 100), (e.g., via domain area component 402), whether a target line is a reference line or whether it is aligned with a reference line. For example, domain area component 402 may designate one or more lines of transmission line bus 112 as reference lines. Furthermore, if the target line is not a reference line, domain area component 402 may determine whether the target line is aligned with a reference line. At 908, the computer-implemented method 900 may include identifying, by the system (e.g., interface 100), (e.g., via domain area component 402 and / or delay value component 502), the boundaries of multiple stable regions of a uniform clock domain. For example, domain area component 402 may track various stable and unstable regions associated with the evaluated delay value via a region tracking table according to the various embodiments described herein. At 910, the computer-implemented method 900 may include selecting, by the system (e.g., interface 100), (e.g., via centering component 602), a delay value centered starting from the active clock edge of the largest stable region.

[0071] This invention can be a system, method, and / or computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combinations of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

[0072] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0073] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone conditional packet, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing the status information of the computer-readable program instructions.

[0074] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0075] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0076] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0077] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a non-consecutive order as shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0078] To provide additional context for the various embodiments described herein, Figure 10 The following discussion is intended to provide a general description of a suitable computing environment 1000 in which the various embodiments described herein may be implemented. Although the embodiments have been described above in the general context of computer-executable instructions that can run on one or more computers, those skilled in the art will recognize that the embodiments may also be implemented in combination with other program modules and / or as a combination of hardware and software.

[0079] Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the methods of this invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (“IoT”) devices, distributed computing systems, and personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, each of which can be operatively coupled to one or more associated devices.

[0080] The embodiments illustrated herein can also be implemented in a distributed computing environment, where specific tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules can reside in both local and remote memory storage devices. For example, in one or more embodiments, a computer-executable component can be executed from memory, which may include or consist of one or more distributed memory units. As used herein, the terms "memory" and "storage unit" are interchangeable. Furthermore, one or more embodiments described herein enable the execution of code from a computer-executable component in a distributed manner, for example, by multiple processors working together or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" can encompass a single memory or storage unit at one location or multiple memories or storage units at one or more locations.

[0081] Computing devices typically include a variety of media, which may include computer-readable storage media, machine-readable storage media, and / or communication media, these two terms being used differently from each other herein. A computer-readable storage medium or a machine-readable storage medium can be any available storage medium accessible by a computer, and includes volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, a computer-readable storage medium or a machine-readable storage medium can be implemented in combination with any method or technique used for storing information such as computer-readable or machine-readable instructions, program modules, structured data, or unstructured data.

[0082] Computer-readable storage media may include, but are not limited to: random access memory (“RAM”), read-only memory (“ROM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory or other memory technologies, compact disc read-only memory (“CDROM”), digital universal disc (“DVD”), Blu-ray disc (“BD”) or other optical disc storage, magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, solid-state drives or other solid-state storage devices, or other tangible and / or non-transitory media that can be used to store desired information. In this regard, the terms “tangible” or “non-transitory” as used herein with respect to storage devices, memories, or computer-readable media shall be understood to exclude only the propagation of transient signals themselves as a modifier, and shall not waive the rights to all standard storage devices, memories, or computer-readable media that do not only propagate transient signals themselves.

[0083] Computer-readable storage media can be accessed by one or more local or remote computing devices, for example via access requests, queries or other data retrieval protocols, for various operations concerning the information stored in the media.

[0084] Communication media typically embody computer-readable instructions, data structures, program modules, or other structured or unstructured data in data signals such as modulated data signals (e.g., carrier waves or other transmission mechanisms), and include any information delivery or transmission medium. The term "modulated data signal" refers to a signal whose one or more characteristics are set or altered in a manner that encodes information in one or more signals. By way of example and not limitation, communication media include wired media, such as wired networks or direct-line connections, and wireless media, such as acoustic, RF, infrared, and other wireless media.

[0085] Refer again Figure 10 An example environment 1000 for implementing various embodiments of the aspects described herein includes a computer 1002, which includes a processing unit 1004, system memory 1006, and a system bus 1008. The system bus 1008 couples system components, including but not limited to system memory 1006, to the processing unit 1004. The processing unit 1004 may be any of a variety of commercially available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1004.

[0086] System bus 1008 can be any of several types of bus structures that can be further interconnected to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. System memory 1006 includes ROM 1010 and RAM 1012. The basic input / output system (“BIOS”) can be stored in non-volatile memory such as ROM, erasable programmable read-only memory (“EPROM”), EEPROM, etc. The BIOS contains basic routines such as those that help transfer information between components within computer 1002 during startup. RAM 1012 may also include high-speed RAM, such as static RAM for caching data.

[0087] Computer 1002 also includes an internal hard disk drive (“HDD”) 1014 (e.g., EIDE, SATA), one or more external storage devices 1016 (e.g., floppy disk drive (“FDD”) 1016, memory stick or flash drive reader, memory card reader, etc.), and an optical disc drive 1020 (e.g., capable of reading from or writing to CD-ROMs, DVDs, BDs, etc.). While the internal HDD 1014 is shown as residing within computer 1002, it can also be configured for external use within a suitable chassis (not shown). Furthermore, although not shown in environment 1000, a solid-state drive (“SSD”) can be used as a supplement to or replacement for HDD 1014. HDD 1014, external storage devices 1016, and optical disc drive 1020 can be connected to system bus 1008 via HDD interface 1024, external storage interface 1026, and optical disc drive interface 1028, respectively. The interface 1024 for the external driver implementation may include at least one or both of Universal Serial Bus (“USB”) and Institute of Electrical and Electronics Engineers (“IEEE”) 1394 interface technologies. Other external driver connectivity technologies are within the scope of the embodiments described herein.

[0088] The drive and its associated computer-readable storage medium provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 1002, the drive and storage medium are suitable for storing any data in a suitable digital format. Although the above description of computer-readable storage media refers to a corresponding type of storage device, those skilled in the art will understand that other types of computer-readable storage media (whether currently existing or developed in the future) may also be used in the example operating environment, and further, any such storage medium may contain computer-executable instructions for performing the methods described herein.

[0089] Multiple program modules may be stored in the drive and RAM 1012, including an operating system 1030, one or more application programs 1032, other program modules 1034, and program data 1036. All or part of the operating system, applications, modules, and / or data may also be cached in RAM 1012. The systems and methods described herein can be implemented using various commercially available operating systems or combinations of operating systems.

[0090] Computer 1002 may optionally include emulation technology. For example, a system hypervisor (not shown) or other intermediary may emulate the hardware environment of operating system 1030, and the emulation hardware may optionally be integrated with... Figure 10 The hardware shown is different. In this embodiment, the operating system 1030 may include one of a plurality of virtual machines (“VMs”) hosted at the computer 1002. Furthermore, the operating system 1030 may provide a runtime environment for the application 1032, such as the Java Runtime Environment or the .NET Framework. A runtime environment is a consistent execution environment that allows the application 1032 to run on any operating system that includes a runtime environment. Similarly, the operating system 1030 may support containers, and the application 1032 may take the form of a container, which is a lightweight, standalone, executable package of software, including, for example, code, runtime, system tools, system libraries, and application settings.

[0091] Furthermore, computer 1002 may enable security modules, such as a Trusted Processing Module (“TPM”). For example, with TPM, the boot component hashes the next boot component in time and waits for the result to match a security value before loading the next boot component. This process can occur at any layer of the computer 1002’s code execution stack, for example, at the application execution level or at the operating system (“OS”) kernel level, thereby achieving security at any code execution level.

[0092] Users can input commands and information into computer 1002 through one or more wired / wireless input devices (e.g., keyboard 1038, touchscreen 1040, and pointing devices such as mouse 1042). Other input devices (not shown) may include microphones, infrared (“IR”) remote controls, radio frequency (“RF”) remote controls, or other remote controls, joysticks, virtual reality controllers and / or virtual reality headsets, game controllers, styluses, image input devices (e.g., cameras), gesture sensor input devices, visual motion sensor input devices, emotion or face detection devices, biometric input devices (e.g., fingerprint or iris scanners), etc. These and other input devices are often connected to processing unit 1004 via input device interface 1044, which is coupled to system bus 1008, but can be connected via other interfaces such as parallel ports, IEEE 1394 serial ports, game ports, USB ports, IR interfaces, etc. Interfaces, etc.

[0093] Monitor 1046 or other types of display devices can also be connected to system bus 1008 via an interface such as video adapter 1048. In addition to monitor 1046, computers typically include other peripheral output devices (not shown), such as speakers, printers, etc.

[0094] Computer 1002 can operate in a networked environment via logical connections to one or more remote computers (such as remote computer 1050) via wired and / or wireless communications. Remote computer 1050 may be a workstation, server computer, router, personal computer, laptop computer, microprocessor-based entertainment device, peer-to-peer device, or other public network node, and typically includes many or all of the elements described relative to computer 1002; however, for brevity, only memory / storage device 1052 is shown. The depicted logical connections include wired / wireless connections to a local area network (“LAN”) 1054 and / or a larger network (e.g., a wide area network (“WAN”) 1056). Such LAN and WAN networking environments are common in offices and companies and facilitate enterprise-wide computer networks (such as intranets), all of which can connect to global communication networks such as the Internet.

[0095] When used in a LAN networking environment, computer 1002 can connect to local network 1054 via a wired and / or wireless communication network interface or adapter 1058. Adapter 1058 can facilitate wired or wireless communication to LAN 1054, which may also include a wireless access point (“AP”) disposed thereon for communicating with adapter 1058 in wireless mode.

[0096] When used in a WAN networking environment, computer 1002 may include modem 1060 or may be connected to a communication server on WAN 1056 via other means (such as via the Internet) for establishing communication on WAN 1056. Modem 1060 (which may be internal or external and wired or wireless) may be connected to system bus 1008 via input device interface 1044. In a networking environment, program modules depicted relative to computer 1002 or parts thereof may be stored in remote memory / storage device 1052. It should be understood that the network connection shown is an example, and other means of establishing communication links between computers may be used.

[0097] When used in a LAN or WAN networking environment, computer 1002 can access cloud storage systems or other network-based storage systems as a supplement to or replacement of external storage device 1016 as described above. Typically, the connection between computer 1002 and the cloud storage system can be established, for example, on LAN 1054 or WAN 1056 via adapter 1058 or modem 1060, respectively. When computer 1002 is connected to an associated cloud storage system, external storage interface 1026 can manage the storage provided by the cloud storage system via adapter 1058 and / or modem 1060, just like other types of external storage. For example, external storage interface 1026 can be configured to provide access to cloud storage sources as if those sources were physically connected to computer 1002.

[0098] Computer 1002 is operable to communicate with any wireless device or entity operably arranged in wireless communication (e.g., printer, scanner, desktop and / or laptop computer, portable data assistant, communications satellite, any device or location associated with a wirelessly detectable tag (e.g., self-service terminal, newsstand, store shelf, etc.) and telephone). This may include Wireless Fidelity (“Wi-Fi”) and Wireless technology. Therefore, communication can be a predefined structure like a traditional network, or simply self-organizing communication between at least two devices.

[0099] The above description includes only examples of systems, computer program products, and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components, products, and / or computer-implemented methods; however, those skilled in the art will recognize that many other combinations and substitutions of this disclosure are possible. Furthermore, with regard to the use of the terms "comprising," "having," "possessing," etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a manner similar to that interpreted when the term "comprising" is used as a transitional term in the claims. Various embodiments have been described for illustrative purposes, but these descriptions are not exhaustive or intended to limit one to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer-implemented method, comprising: The system, operatively coupled to the processor, trains a quantum controller fast path interface for routing qubit data bits between the quantum controller and the conditional engine by adjusting latency values ​​such that the uniform clock domain of the quantum controller fast path interface is characterized by a direct register-to-register transfer mode.

2. The computer-implemented method according to claim 1 further includes: The system selects the delay value of the stable uniform clock domain by shifting the delay device of the fast path interface of the quantum controller.

3. The computer-implemented method according to claim 2, wherein, The training begins at the edge of the active clock and centers the qubit data bits within the received clock domain.

4. The computer-implemented method according to claim 3, wherein, The training maximizes the time margin of the received clock domain.

5. The computer-implemented method according to any one of claims 1-4, further comprising: The system identifies the boundaries of multiple stable regions of the uniform clock domain by tracking the stability of the uniform clock domain at multiple delay values ​​achievable at the fast path interface of the quantum controller for the target line.

6. The computer-implemented method according to claim 5, wherein, The training further includes: The system selects a preferred delay value from the plurality of delay values ​​that is associated with the largest stable region among the plurality of stable regions; and The system uses the preferred delay value together with the target line to route the qubit data bits.

7. The computer-implemented method according to any one of claims 1-4, further comprising: The system evaluates the stability of the uniformly paced clock domain at the delay value for the target line of the quantum controller's fast path interface.

8. The computer-implemented method according to claim 7, wherein, The assessment includes: The evaluation, characterized by the stability of the system based on the uniform clock domain and the direct register-to-register transfer mode, determines whether the target line is the reference line for the fast path interface of the quantum controller; and The system determines whether the target line is aligned with the reference line by an evaluation based on the stability of the uniform clock domain characterized by the direct register-to-register transfer mode.

9. The computer-implemented method according to claim 8, wherein, The assessment further includes: The system determines whether the qubit data bit is in a stable region of the uniform clock domain based on the determination that the target line is the reference line or aligned with the reference line.

10. A computer program product comprising program instructions executable by a processor to cause the processor to: The quantum controller fast path interface for routing qubit data bits between the quantum controller and the conditional engine is trained by adjusting the delay value so that the uniform clock domain of the quantum controller fast path interface is characterized by a direct register-to-register transfer mode.

11. The computer program product according to claim 10, wherein, The program instructions also cause the processor to: The processor selects the receive clock domain that stabilizes the uniform clock domain by shifting the delay device of the fast path interface of the quantum controller.

12. The computer program product according to any one of claims 10 to 11, wherein, The program instructions also cause the processor to: The processor evaluates the stability of the uniform clock domain at the delay value for the target line of the quantum controller's fast path interface.

13. The computer program product according to claim 12, wherein, The program instructions also cause the processor to: The processor determines whether the target line is a reference line for the fast path interface of the quantum controller by evaluating the stability of the uniform clock domain based on the direct register-to-register transfer mode. as well as The processor determines whether the target line is aligned with the reference line by an evaluation based on the stability of the uniform clock domain characterized by the direct register-to-register transfer mode.

14. The computer program product according to claim 13, wherein, The program instructions also cause the processor to: The processor determines whether the qubit data bit is in a stable region of the uniform clock domain based on the determination that the target line is the reference line or aligned with the reference line; as well as The processor increases the size of the stable region based on the determination of the qubit data bits in the stable region.

15. The computer program product according to claim 14, wherein, The latency values ​​are derived from a plurality of latency values ​​to be evaluated by the processor, wherein the evaluation provides a plurality of stable regions associated with the plurality of latency values ​​for the target line, and wherein the program instructions further cause the processor to: The processor selects a preferred delay value from the plurality of delay values ​​that is associated with the largest stable region among the plurality of stable regions; and The processor uses the preferred delay value together with the target line to route the qubit data bits.

16. A computer system, comprising: A fast path interface for the quantum controller routes qubit data packets between the quantum controller and the conditional engine via a packet transport protocol in which sender information is inferred from the data position within the qubit data packets. The system trains the quantum controller's fast path interface by adjusting the delay value, so that the uniform clock domain of the quantum controller's fast path interface is characterized by a direct register-to-register transfer mode.

17. The system according to claim 16, wherein, The quantum controller broadcasts qubit data to the transmit logic circuit of the quantum controller fast path interface, the transmit logic circuit being synchronized with the receive logic circuit operatively coupled to the conditional engine, and wherein the system selects the delay value of the stable uniform clock domain by shifting the delay device of the quantum controller fast path interface.

18. The system according to claim 17, wherein, The transmit logic circuit traverses multiple routing schemes, which distribute the qubit data packets to multiple transmission lines, and wherein the training starts from the edge of the active clock and centers the qubit data bits in the receive clock domain.

19. The system according to claim 18, wherein, While traversing the multiple routing schemes, the packet transmission protocol continuously transmits qubit data between the transmit logic circuit and the receive logic circuit, wherein the training maximizes the time margin of the receive clock domain.

20. The system according to any one of claims 16-19, wherein, The qubit data grouping includes the effective pairing of the data position with the qubit.

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