Display substrate and display device

Abstract

A display substrate and a display device are disclosed. The display substrate includes: a substrate including a first display area and a second display area, wherein the light transmittance of the first display area is greater than that of the second display area; a plurality of first sub-pixels located in the first display area, at least one of the plurality of first sub-pixels including: a first pixel circuit and a first light-emitting device; the first pixel circuit including: a storage capacitor and a driving transistor, and further including: a data writing sub-circuit configured to write a data voltage signal to the gate of the driving transistor in response to a first scan signal and a second scan signal; a reset sub-circuit configured to provide an initial voltage signal to a first electrode of the first light-emitting device in response to a second scan signal; and a light emission control sub-circuit configured to transmit a driving current to the first light-emitting device in response to a light emission control signal; the orthographic projection of the first electrode on the substrate covers at least a portion of the orthographic projection of the first pixel circuit on the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display substrate and a display device. Background Technology

[0002] With the increasing demand from users for diverse uses of display devices and the emergence of design requirements for high screen-to-body ratios, sensors that were originally placed outside the display area are now required to be placed within the display area in more and more display products. That is, the sensors are placed below the display screen. In this case, the area of ​​the display screen corresponding to the sensor is required to have high transmittance while still being able to display. Summary of the Invention

[0003] This disclosure provides a display substrate and a display device.

[0004] In a first aspect, this disclosure provides a display substrate, comprising:

[0005] The substrate includes a first display area and a second display area located at least one side of the first display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area;

[0006] A plurality of first sub-pixels are disposed on the substrate and located in the first display area. At least one of the plurality of first sub-pixels includes: a first pixel circuit and a first light-emitting device. The first pixel circuit includes: a storage capacitor and a driving transistor. The first electrode of the driving transistor is connected to a first voltage line. The two plates of the storage capacitor are respectively connected to the gate and the first electrode of the driving transistor. The first pixel circuit further includes:

[0007] The data writing sub-circuit is configured to write a data voltage signal into the gate of the driving transistor in response to a first scan signal and a second scan signal;

[0008] A reset sub-circuit is configured to provide an initial voltage signal to the first electrode of the first light-emitting device in response to the second scan signal;

[0009] The light emission control sub-circuit is configured to transmit the drive current output by the drive transistor to the first light emission device in response to the light emission control signal;

[0010] Wherein, the orthogonal projection of the first electrode of the first light-emitting device on the substrate covers at least a portion of the orthogonal projection of the first pixel circuit on the substrate.

[0011] In some embodiments, the data writing sub-circuit includes:

[0012] A first write transistor, the gate of which is connected to a first scan line for providing the first scan signal, and the second terminal of which is connected to the gate of the driving transistor, wherein the first write transistor is an oxide transistor;

[0013] The second write transistor has its gate connected to a second scan line for providing the second scan signal, its first terminal connected to a data line for providing the data voltage signal, and its second terminal connected to the first terminal of the first write transistor. The second write transistor is a polysilicon transistor.

[0014] In some embodiments, the first and second terminals of the second write transistor are arranged along a first direction, the orthographic projection of the second write transistor on the substrate is located on one side of the storage capacitor along a second direction, the first write transistor is located on one side of the second write transistor along the first direction, and the first and second directions intersect.

[0015] In some embodiments, the data line includes: a data line body portion and a bent portion, the data line body portion extending along a first direction, the orthographic projection of the bent portion on the substrate being located on one side of the orthographic projection of the storage capacitor on the substrate along a second direction, and bending toward the orthographic projection of the storage capacitor on the substrate, the orthographic projection of the bent portion on the substrate at least partially overlapping the orthographic projection of the gate of the second write transistor on the substrate.

[0016] The first direction and the second direction intersect.

[0017] In some embodiments, the orthographic projection of the curved portion on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate.

[0018] In some embodiments, the gate of the first write transistor includes an electrically connected first gate and a second gate, wherein the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the second gate on the substrate.

[0019] The first pixel circuit also includes:

[0020] The first adapter electrode has one end connected to the first gate of the first write transistor through a via, and the other end connected to the second gate of the first write transistor through a via.

[0021] The second adapter electrode is connected to the first adapter electrode via a via, and the first scan line is connected to the second adapter electrode via a via.

[0022] In some embodiments, the first pixel circuit further includes:

[0023] The third transfer electrode is connected to the gate of the second write transistor through a via;

[0024] The fourth adapter electrode is connected to the third adapter electrode via a via, and the second scan line is connected to the fourth adapter electrode via a via.

[0025] In some embodiments, the first pixel circuit further includes a fifth adapter electrode, the data line is connected to the fifth adapter electrode through a via, and the fifth adapter electrode is connected to the first electrode of the second write transistor through a via.

[0026] In some embodiments, the first pixel circuit further includes: a sixth adapter electrode, one end of which is connected to the first electrode of the first write transistor through a via, and the other end of which is connected to the second electrode of the second write transistor through a via.

[0027] In some embodiments, the orthographic projection of the sixth transition electrode on the substrate overlaps at least partially with the orthographic projection of the first electrode of the first light-emitting device on the substrate.

[0028] In some embodiments, the orthographic projection of the active layer of the first write transistor on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate, and the orthographic projection of the active layer of the second write transistor on the substrate is located within the orthographic projection range of the first electrode of the first light-emitting device on the substrate.

[0029] In some embodiments, the first pixel circuit further includes:

[0030] The seventh adapter electrode is connected to the second electrode of the first write transistor through a via, and the other end of the seventh adapter electrode is connected to the gate of the drive transistor through a via.

[0031] In some embodiments, the orthographic projection of the seventh adapter electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate.

[0032] In some embodiments, the first pixel circuit further includes an eighth adapter electrode and a ninth adapter electrode, wherein the first voltage line is connected to the ninth adapter electrode through a via, the ninth adapter electrode is connected to the eighth adapter electrode through a via, and the eighth adapter electrode is connected to the first electrode of the driving transistor through a via.

[0033] In some embodiments, the two plates of the storage capacitor include a first plate and a second plate, the gate of the driving transistor is integrally formed with the first plate, and the eighth transfer electrode is also connected to the second plate through a via.

[0034] In some embodiments, the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate.

[0035] In some embodiments, the light emission control sub-circuit includes: a light emission control transistor, the gate of which is connected to a light emission control line for providing the light emission control signal, a first electrode of which is connected to a second electrode of the driving transistor, and a second electrode of which is connected to a first electrode of the first light-emitting device.

[0036] In some embodiments, the first pixel circuit further includes a tenth transition electrode and an eleventh transition electrode, wherein the light emission control line is connected to the eleventh transition electrode through a via, the eleventh transition electrode is connected to the tenth transition electrode through a via, and the tenth transition electrode is connected to the gate of the light emission control transistor through a via.

[0037] In some embodiments, the first and second electrodes of the light-emitting control transistor are arranged along a second direction, and the orthographic projection of the storage capacitor on the substrate is located on one side of the orthographic projection of the first electrode of the light-emitting control transistor on the substrate along a first direction, the first direction intersecting the second direction.

[0038] In some embodiments, the reset sub-circuit includes: a reset transistor, the gate of which is connected to a second scan line for providing the second scan signal, the first electrode of which is connected to an initialization voltage line for providing the initial voltage signal, and the second electrode of which is connected to a first electrode of the first light-emitting device.

[0039] In some embodiments, the first pixel circuit further includes a twelfth transition electrode and a thirteenth transition electrode, wherein the initialization voltage line is connected to the thirteenth transition electrode through a via, the thirteenth transition electrode is connected to the twelfth transition electrode through a via, and the twelfth transition electrode is connected to the first terminal of the reset transistor through a via.

[0040] In some embodiments, the first pixel circuit further includes a fourteenth transition electrode, a fifteenth transition electrode, and a sixteenth transition electrode, wherein the first electrode of the light-emitting device is connected to the sixteenth transition electrode through a via, the sixteenth transition electrode is connected to the fifteenth transition electrode through a via, the fifteenth transition electrode is connected to the fourteenth transition electrode through a via, and the fourteenth transition electrode is connected to the second electrode of the reset transistor through a via.

[0041] In some embodiments, the first and second terminals of the reset transistor are arranged along a first direction, and the orthogonal projection of the reset transistor on the substrate is located on one side of the orthogonal projection of the storage capacitor on the substrate along a second direction.

[0042] In some embodiments, the data writing sub-circuit includes a first write transistor and a second write transistor.

[0043] The gate of the second write transistor and the gate of the reset transistor are formed as an integral structure, and the integral structure extends along the second direction.

[0044] In some embodiments, the display substrate includes, in a direction away from the substrate, the following layers sequentially disposed: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a transparent lead layer, and a first electrode layer, wherein the first pixel circuit includes at least one polysilicon transistor and at least one oxide transistor.

[0045] The first semiconductor layer includes: an active layer, a first electrode, and a second electrode of each polysilicon transistor in the first pixel circuit; the first gate metal layer includes: the gate of each polysilicon transistor in the first pixel circuit; the second gate metal layer includes: the first gate of each oxide transistor in the first pixel circuit and the first electrode of the storage capacitor; the second semiconductor layer includes: an active layer, a first electrode, and a second electrode of each oxide transistor in the first pixel circuit; the third gate metal layer includes: the second electrode of the storage capacitor; the transparent lead layer includes the first voltage line; the first electrode layer includes the first electrode of the first light-emitting device.

[0046] In some embodiments, the data writing sub-circuit includes a first write transistor, the gate of which includes a first gate and a second gate.

[0047] The transparent lead layer further includes a first scan line, and the display substrate further includes a first source / drain metal layer and a second source / drain metal layer located between the third gate metal layer and the transparent lead layer, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate.

[0048] The first source / drain metal layer includes a first transition electrode, and the second source / drain metal layer includes a second transition electrode. The first scan line is connected to the second transition electrode through a via, and the second transition electrode is connected to the first transition electrode through a via. The two ends of the first transition electrode are respectively connected to the first gate and the second gate of the first write transistor through vias.

[0049] In some embodiments, the data writing sub-circuit further includes a second writing transistor, the transparent lead layer further includes a second scan line, the first source-drain metal layer further includes a third transition electrode, the second source-drain metal layer further includes a fourth transition electrode, the second scan line is connected to the fourth transition electrode through a via, the fourth transition electrode is connected to the third transition electrode through a via, and the third transition electrode is connected to the gate of the second writing transistor through a via.

[0050] In some embodiments, the transparent lead layer further includes a data line, the first source / drain metal layer further includes a fifth transition electrode, the data line is connected to the fifth transition electrode through a via, and the fifth transition electrode is connected to the first electrode of the second write transistor through a via.

[0051] In some embodiments, the first source / drain metal layer further includes a sixth transition electrode, one end of which is connected to the first electrode of the first write transistor via a via, and the other end of which is connected to the second electrode of the second write transistor via a via.

[0052] In some embodiments, the first source / drain metal layer further includes a seventh transition electrode, the seventh transition electrode being connected to the second terminal of the first write transistor via a via, and the other end of the seventh transition electrode being connected to the gate of the drive transistor via a via.

[0053] In some embodiments, the display substrate further includes a first source / drain metal layer and a second source / drain metal layer located between the third gate metal layer and the transparent lead layer, the second source / drain metal layer being located on the side of the first source / drain metal layer away from the substrate; the first source / drain metal layer includes an eighth transition electrode, and the second source / drain metal layer includes a ninth transition electrode; the first voltage line is connected to the ninth transition electrode through a via, the ninth transition electrode is connected to the eighth transition electrode through a via, the eighth transition electrode is connected to the first electrode of the driving transistor through a via, and the eighth transition electrode is also connected to the second electrode of the storage capacitor through a via.

[0054] In some embodiments, the light emission control sub-circuit includes a light emission control transistor, and the display substrate further includes a first source / drain metal layer and a second source / drain metal layer located between the third gate metal layer and the transparent lead layer, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate.

[0055] The first source / drain metal layer includes a tenth transition electrode, and the second source / drain metal layer includes an eleventh transition electrode.

[0056] The transparent lead layer further includes: a light-emitting control line, which is connected to the eleventh adapter electrode through a via, and the eleventh adapter electrode is connected to the tenth adapter electrode through a via.

[0057] In some embodiments, the reset sub-circuit includes a reset transistor; the display substrate further includes a first source / drain metal layer and a second source / drain metal layer located between the third gate metal layer and the transparent lead layer, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate.

[0058] The first source / drain metal layer includes a twelfth and a fourteenth transition electrode; the second source / drain metal layer includes a thirteenth and a fifteenth transition electrode; the transparent lead layer includes an initialization voltage line, which is connected to the thirteenth transition electrode via a via, and the thirteenth transition electrode is connected to the twelfth transition electrode via a via; the first electrode of the light-emitting device is connected to the fifteenth transition electrode via a via, the fifteenth transition electrode is connected to the fourteenth transition electrode via a via, and the fourteenth transition electrode is connected to the second electrode of the reset transistor via a via.

[0059] In some embodiments, a plurality of first sub-pixels in the first display area are arranged in multiple rows and columns, a plurality of first sub-pixels in the same column are arranged along a first direction, a plurality of first sub-pixels in the same row are arranged along a second direction, and each pair of adjacent rows of first sub-pixels forms a repeating group, wherein the two rows of first sub-pixels in the repeating group are arranged alternately.

[0060] The display substrate further includes:

[0061] Multiple light emission control lines are used to provide the light emission control signal. Each light emission control line corresponds to a repeating group. Different light emission control lines correspond to different repeating groups. Each light emission control line is connected to the first pixel circuit of each first sub-pixel in the corresponding repeating group.

[0062] Multiple first scan lines are used to provide the first scan signal. Each first scan line corresponds to one repeating group. Different first scan lines correspond to different repeating groups. Each first scan line is connected to the first pixel circuit of each first sub-pixel in the corresponding repeating group.

[0063] Multiple second scan lines are used to provide the second scan signal. Each second scan line corresponds to one of the repeating groups. Different second scan lines correspond to different repeating groups. Each second scan line is connected to the first pixel circuit of each first sub-pixel in the corresponding repeating group.

[0064] Multiple initialization voltage lines are used to provide the initial voltage signal. Each initialization voltage line corresponds to a repeating group. Different initialization voltage lines correspond to different repeating groups. Each initialization voltage line is connected to the first pixel circuit of each first sub-pixel in the corresponding repeating group.

[0065] Multiple data lines are used to provide the data voltage signal. Each data line corresponds to a column of the repeating group. Different data lines correspond to the first sub-pixel of different columns. Each data line is connected to the first pixel circuit of each first sub-pixel in the corresponding column.

[0066] In some embodiments, within the same repeating group, one row of first sub-pixels consists of first-color sub-pixels, and another row of sub-pixels comprises alternating second-color and third-color sub-pixels.

[0067] The light-emitting control line includes: a control line body and a control line lead-out portion, wherein the control line body extends along a second direction and the control line lead-out portion extends along a first direction;

[0068] In the same repeating group, the first pixel circuit in the first sub-pixel of one row is connected to the main body of the control line, and the first pixel circuit in the first sub-pixel of another row is connected to the lead-out portion of the control line.

[0069] In some embodiments, the first scan line includes: a scan line body portion and a scan line lead-out portion, the scan line body portion including: a plurality of scan line segments arranged sequentially in the second direction, the plurality of scan line segments being connected sequentially to form a curved structure in the scan line body portion; the scan line lead-out portion extends along the first direction;

[0070] In the same repeating group, the first pixel circuit in the first sub-pixel of one row is connected to the main body of the scan line, and the first pixel circuit in the first sub-pixel of another row is connected to the extension of the scan line.

[0071] In some embodiments, the display substrate further includes:

[0072] A plurality of second sub-pixels are disposed on the substrate and located in the second display area, at least one of the plurality of second sub-pixels including: a second pixel circuit and a second light-emitting device, the second pixel circuit being configured to provide a driving current to the second light-emitting device.

[0073] Secondly, embodiments of this disclosure also provide a display device, including the display substrate described above.

[0074] In some embodiments, the display device further includes at least one image sensor, the image sensor's orthographic projection onto the substrate being located in the first display area. Attached Figure Description

[0075] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0076] Figure 1 This is a plan view of a display device provided in some embodiments of the present disclosure.

[0077] Figure 2 The display device provided in some embodiments of this disclosure is along Figure 1 A cross-sectional view of line A-A' in the middle.

[0078] Figure 3 This is an equivalent circuit diagram of the second pixel circuit provided in some embodiments of this disclosure.

[0079] Figure 4 for Figure 3 The timing diagram of the second pixel circuit is shown.

[0080] Figure 5A This is a circuit diagram of a first pixel circuit provided in some embodiments of this disclosure.

[0081] Figure 5B This is a circuit schematic diagram of the first pixel circuit provided in some other embodiments of this disclosure.

[0082] Figure 6A for Figure 5B A timing diagram of the first pixel circuit in the image.

[0083] Figure 6B for Figure 5B Another timing diagram of the first pixel circuit in the diagram.

[0084] Figure 7 This is a plan view of the first semiconductor layer provided in some embodiments of this disclosure.

[0085] Figure 8 This is a plan view of the first gate metal layer provided in some embodiments of this disclosure.

[0086] Figure 9 This is a schematic diagram of a second gate metal layer provided in some embodiments of this disclosure.

[0087] Figure 10 This is a schematic diagram of a second semiconductor layer provided in some embodiments of the present disclosure.

[0088] Figure 11 This is a schematic diagram of a third gate metal layer provided in some embodiments of this disclosure.

[0089] Figure 12 This is a schematic diagram of the first source / drain metal layer provided in some embodiments of this disclosure.

[0090] Figure 13 This is a schematic diagram of the second source / drain metal layer provided in some embodiments of this disclosure.

[0091] Figure 14 This is a planar view of the first semiconductor layer, first gate metal layer, second gate metal layer, second semiconductor layer, third gate metal layer, first source / drain metal layer, and second source / drain metal layer stacked together, as provided in some embodiments of this disclosure.

[0092] Figure 15 This is a superimposed planar view of the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the vias on the second planarization layer provided in some embodiments of this disclosure.

[0093] Figure 16 For along Figure 15 A cross-sectional view of line B-B' in the middle.

[0094] Figure 17 For along Figure 15 A cross-sectional view of line C-C' in the middle.

[0095] Figure 18 For along Figure 15 A cross-sectional view of line D-D' in the middle.

[0096] Figure 19 This is a plan view of the transparent lead layer and the first electrode layer provided in some embodiments of this disclosure.

[0097] Figure 20 This is a plan view of the first electrode layer and a plurality of first pixel circuits provided in some embodiments of this disclosure.

[0098] Figure 21This is a schematic diagram showing the arrangement of multiple sub-pixels in a first display area provided in some embodiments of this disclosure. Detailed Implementation

[0099] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0100] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0101] When an element is described as being "on" another element, "connected to" another element, or "bonded to" another element, the element may be directly on, directly connected to, or directly bonded to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bonded to" another element, there are no intermediate elements. Furthermore, the term "connection" can refer to a physical connection or an electrical connection.

[0102] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0103] It should be noted that in this paper, "same layer" or "same layer configuration" refers to a layer structure formed by first forming a film layer and then patterning that film layer using the same photomask through a single patterning process. The specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed through the same patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness, but the distances from the multiple elements, components, structures, and / or portions in the "same layer" to the substrate are not necessarily the same.

[0104] Those skilled in the art will understand that, unless otherwise stated herein, the expressions “continuous extension,” “monolithic structure,” “integral structure,” or similar expressions mean that multiple elements, components, structures, and / or portions are located on the same layer and are typically formed during manufacturing by the same patterning process, and that these elements, components, structures, and / or portions are continuous extensions without gaps or breaks between them.

[0105] Figure 1 This is a planar schematic diagram of a display device provided in some embodiments of the present disclosure, which schematically illustrates the planar structure of the display substrate included in the display device. Figure 2 The display device provided in some embodiments of this disclosure is along Figure 1 A cross-sectional view along line A-A'. The display substrate can be an electroluminescent display substrate, such as an OLED display substrate. Figure 1 As shown, the display substrate 100 includes a display area, which may include a first display area AA1 and a second display area AA2. For example, the first display area AA1 and the second display area AA2. For example, the second display area AA2 at least partially surrounds (e.g., completely surrounds) the first display area AA1.

[0106] like Figure 2 As shown, the display substrate 100 may include a substrate 1. The image sensor 2 may be disposed on the back side of the substrate 1 located in the first display area AA1 (in...). Figure 2 (As shown in the lower part, for example, the side with the opposite light emission direction when displayed), the first display area AA1 can meet the imaging requirements of the image sensor 2 for light transmittance.

[0107] For example, the transmittance of the first display area AA1 is greater than the transmittance of the second display area AA2. The image sensor 2 is configured to receive light from the display side of the display substrate 100. Figure 2The upper side of the display area (for example, the light direction, or the direction in which the human eye is located when the display is displayed) allows for operations such as image capture, distance perception, and light intensity perception. These light rays, for example, pass through the first display area AA1 and then illuminate the image sensor, thereby being sensed by the image sensor.

[0108] It should be noted that in the exemplary embodiment illustrated, the second display area AA2 completely surrounds the first display area AA1; however, the embodiments disclosed herein are not limited to this. For example, in other embodiments, the first display area AA1 may be located at the upper edge of the display substrate. For instance, the first display area AA1 may be surrounded on three sides by the second display area AA2, and its upper side may be flush with the upper side of the display substrate.

[0109] For example, the shape of the first display area AA1 can be circular, elliptical, polygonal, or rectangular, and the shape of the second display area AA2 can be circular, annular, elliptical, or rectangular, but the embodiments disclosed herein are not limited thereto. As another example, the shapes of both the first display area AA1 and the second display area AA2 can be rectangular, rounded rectangles, or other suitable shapes.

[0110] exist Figures 1 to 2 The display substrate shown can utilize OLED display technology. Due to its advantages such as wide viewing angle, high contrast, fast response, low power consumption, foldability, and flexibility, OLED display substrates are increasingly widely used in display products. With the development and widespread application of OLED display technology, the demand for high screen-to-body ratio displays is becoming increasingly strong. Figures 1 to 2 The display substrate shown employs an under-display camera solution. This avoids the need for a hole in the display screen, increases the screen-to-body ratio, and provides a better visual experience.

[0111] For example, a display substrate may include a substrate 1 and various film layers disposed on the substrate 1. For example, the display substrate may further include a driving circuit layer, a light-emitting device layer, and an encapsulation layer disposed on the substrate 1. Figure 2 The diagram schematically illustrates a driving circuit layer 3 and a light-emitting device layer 4. The driving circuit layer 3 includes a driving circuit structure, and the light-emitting device layer 4 includes light-emitting devices such as those used in OLEDs. The driving circuit structure controls the light emission of each sub-pixel's light-emitting device to achieve a display function. This driving circuit structure includes thin-film transistors, storage capacitors, and various signal lines. These signal lines include gate lines, data lines, power lines, etc., to provide control signals, data signals, power supply voltages, and other signals to the pixel driving circuit in each sub-pixel.

[0112] For example, the first display area AA1 can correspond to an under-display camera, that is, the first display area AA1 can be an under-display camera area. For example, the display substrate 100 includes the first display area AA1, which can be circular, approximately circular, elliptical, polygonal, or other shapes.

[0113] For example, in conjunction with reference Figure 1 and Figure 2 In the illustrated embodiment, one image sensor 2 can be provided to correspond to the first display area AA1. However, the embodiments of this disclosure are not limited to this; in other embodiments, more first display areas AA1 and image sensors 2 can be provided. Furthermore, the shape of the sub-display areas can be determined according to the shape of the hardware structure to be installed. For example, the orthographic projection of each first display area AA1 onto the substrate can have one or more of the following shapes: circular, elliptical, rectangular, rounded rectangle, square, rhombus, trapezoid, polygon, etc., and various combinations thereof.

[0114] By setting a display area with higher light transmittance than the normal display area in the display substrate, and installing hardware structures such as cameras under the display substrate, functions such as under-display cameras can be realized, thereby increasing the screen-to-body ratio and achieving a full-screen effect.

[0115] In related technologies, the portion of the second display area closest to the first display area is formed as a transition zone. In some embodiments of these technologies, the pixel circuit connected to the anode of the first light-emitting device in the first display area is located in the transition zone. This arrangement effectively reduces the resolution of the transition zone. Furthermore, when the pixel circuit connected to the first light-emitting device is located in the transition zone, the first light-emitting device is connected to the corresponding pixel circuit via transparent leads. However, the lengths of the transparent leads between different first light-emitting devices and their corresponding pixel circuits are not necessarily equal, resulting in inconsistent luminous brightness of the first light-emitting devices.

[0116] This disclosure provides a display substrate, such as... Figure 1 and Figure 2 As shown, the display substrate 100 includes: a substrate 1 and a plurality of first sub-pixels P1. The substrate includes a first display area AA1 and a second display area AA2 located on at least one side of the first display area AA1. The light transmittance of the first display area AA1 is greater than that of the second display area AA2.

[0117] A plurality of first sub-pixels P1 are disposed on a substrate 1 and located in a first display area AA1. At least one first sub-pixel P1 includes a first pixel circuit and a first light-emitting device. Optionally, a plurality of second sub-pixels P2 are also disposed on the substrate 1 and located in a second display area AA2. The second sub-pixels P2 include a second pixel circuit and a second light-emitting device.

[0118] Figure 3 Here is an equivalent circuit diagram of the second pixel circuit provided in some embodiments of this disclosure, such as... Figure 3 As shown, the second pixel circuit may include: a first reset transistor T1', a threshold compensation transistor T2', a driving transistor T3', a data writing transistor T4', a first light-emitting control transistor T5', a second light-emitting control transistor T6', a second reset transistor T7', and a storage capacitor Cst'.

[0119] In this configuration, the gate of the first reset transistor T1' is connected to the first reset line Re1. The first terminal of the first reset transistor T1', the gate of the driving transistor T3', and the first terminal of the threshold compensation transistor T2' are connected to the first node N1'. The second terminal of the first reset transistor T1' is connected to the first initialization voltage line Vinit1'. The gate of the threshold compensation transistor T2' is connected to the first scan line N-Gate'. The second terminal of the threshold compensation transistor T2', the second terminal of the driving transistor T3', and the first terminal of the second light-emitting control transistor T6' are connected to the third node N3'. The gate of the data writing transistor T4' is connected to the second scan line P-Gate'. The first terminal of the data writing transistor T4' is connected to the data line Data'. The second terminal of the data writing transistor T4', the first terminal of the driving transistor T3', and the second terminal of the first light-emitting control transistor T5' are connected to the second node N2'. The first terminal of the first light-emitting control transistor T5' is connected to the first voltage line VDD'. The gate of the second reset transistor T7' is connected to the second reset line Re2. The first electrode of the second reset transistor T7' and the second electrode of the second light-emitting control transistor T6' are connected to the fourth node N4'. The second electrode of the second reset transistor T7' is connected to the second initialization voltage line Vinit2'. The first electrode of the second light-emitting device 20 is connected to the fourth node N4', and the second electrode of the second light-emitting device 20 is connected to the second voltage line VSS'. The first electrode of the second light-emitting device 20 is the anode, and the second electrode is the cathode. The first initialization voltage line Vinit1' and the second initialization voltage line Vinit2' can be the same signal line or different signal lines.

[0120] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0121] In one example, the first reset transistor T1' and the compensation transistor T2' can be oxide transistors, specifically N-type transistors. The remaining transistors T3' to T7' are all polysilicon transistors, specifically P-type transistors. In this embodiment, the polysilicon transistors are, for example, low-temperature polysilicon transistors. When the first reset transistor T1' is an oxide transistor, its leakage current during the light-emitting phase of the second light-emitting device 20 is relatively small. Therefore, when the display substrate performs low-frequency display, the brightness of the second light-emitting device can be better maintained during the display period of each frame.

[0122] Figure 4 for Figure 3 The timing diagram of the second pixel circuit shown is as follows: Figure 4As shown, in some examples, the operation of the second pixel circuit may include: an initialization phase t0, a data writing phase t1', and a light-emitting phase t2'. In the initialization phase t0, the first reset line Re1 provides a high-level signal, and the second reset line Re2 provides a low-level signal. At this time, the first reset transistor T1' and the second reset transistor T7' are turned on, and the initial voltage on the first initialization voltage line Vinit1' is transmitted to the first node N1', thereby resetting the gate voltage of the driving transistor T3'. The initial voltage on the second initialization voltage line Vinit2' is transmitted to the second node N2', thereby resetting the voltage of the first electrode of the second light-emitting device 20. In the data writing phase t1', the second scan line P-Gate' provides a low-level signal, and the first scan line N-Gate' provides a high-level signal. When the first scan line N-Gate' provides a high-level signal, the compensation transistor T2' turns on, and the gate and first terminal of the driving transistor T3' are shorted, making the driving transistor T3' equivalent to a diode. When the second scan line P-Gate' provides a low-level signal, the data writing transistor T4' turns on, writing the data voltage signal written on the data line Data' to the gate of the driving transistor T3' until the driving transistor T3' turns off. The gate voltage of the driving transistor T3' is Vdata' + Vth' (Vth < 0, where Vth is the threshold voltage of the driving transistor T3' and Vdata' is the data voltage provided by the data line Data'), and it is stored in the storage capacitor Cst'. The voltages across the storage capacitor Cst' are Vdata' + Vth' and Vdd', respectively, where Vdd' is the voltage on the first voltage line VDD'. During this stage, because the writing time of the writing transistor T4 is relatively long, the data voltage on the data line Data' can be fully written to the gate of the driving transistor T3'. During the light-emitting stage, the light-emitting control line EM' provides a low-level signal, and both the first light-emitting control transistor T5' and the second light-emitting control transistor T6' are turned on. The first terminal of the driving transistor T3' is connected to the first voltage line VDD', and the voltage of the first terminal of the driving transistor T3' changes instantaneously from Vdata' in the previous stage to Vdd'. The second light-emitting device 20 emits light under the drive of the driving transistor T3'. At this time, the driving transistor T3' operates in the saturation region, the gate voltage of the driving transistor T3' is Vdata'+Vth', and the voltage of the first terminal of the driving transistor T3' is Vdd'. Therefore, the voltage between the gate and the first terminal of the driving transistor T3' is: Vgs'=(Vdata'+Vth')-Vdd'.

[0123] The drive current of the driving transistor T3' is as follows:

[0124]

[0125]

[0126]

[0127] in, These are constants related to the characteristics of the driving transistor T3'. , Electron mobility driving transistor T3' It is the insulating capacitance per unit area. The aspect ratio of the driving transistor T3'.

[0128] It should be noted that the period during which the second reset line Re2 provides a low-level signal does not necessarily have to be within the initialization phase t0, as long as the period during which the second reset line Re2 provides a low-level signal is before the light-emitting phase t2'. For example, the second reset line Re2 can also provide a low-level signal during the data writing phase t1'. During the data writing phase t1', the period during which the second scan line P-Gate' provides a low-level signal can be the same as the period during which the first scan line N-Gate' provides a high-level signal, or it can be within the period during which the first scan line N-Gate' provides a high-level signal.

[0129] It should be noted that the 7T1C structure used in the second pixel circuit described above is only an example. Of course, other structures, such as 9T1C, can also be used in the second pixel circuit.

[0130] Figure 5A Here are circuit schematics of the first pixel circuit provided in some embodiments of this disclosure, such as... Figure 5AAs shown, the first pixel circuit includes a storage capacitor Cst and a driving transistor T3. The first electrode of the driving transistor T3 is connected to the first voltage line VDD, and the two plates of the storage capacitor Cst are respectively connected to the gate and the first electrode of the driving transistor T3. The first pixel circuit also includes a data writing sub-circuit 11, a reset sub-circuit 13, and a light emission control sub-circuit 12. The data writing sub-circuit 11 is connected to the first scan line N-Gate and the second scan line P-Gate. The first scan line N-Gate provides a first scan signal, and the second scan line P-Gate provides a second scan signal. The data writing sub-circuit 11 is configured to write a data voltage signal to the gate of the driving transistor T3 in response to the first and second scan signals. The reset sub-circuit 13 is connected to the second scan line P-Gate and is configured to provide an initial voltage signal to the first electrode of the first light-emitting device 21 in response to the second scan signal. The light emission control sub-circuit 12 is connected to the light emission control line EM and is configured to transmit the driving current output by the driving transistor to the first light-emitting device 21 in response to the light emission control signal. The orthographic projection of the first electrode of the first light-emitting device 21 onto the substrate 1 covers at least a portion of the orthographic projection of the first pixel circuit onto the substrate 1.

[0131] In this embodiment, the operation of the first pixel circuit includes a writing and reset stage and a light-emitting stage. The first scan line N-Gate provides a first scan signal, the second scan line P-Gate provides a second scan signal, and the data line provides a data voltage signal. At this time, the initial voltage signal on the initialization voltage line is written to the first electrode of the first light-emitting device 21, and the data writing sub-circuit 11 writes the data voltage signal to the gate of the driving transistor. At this time, the voltage stored in the storage capacitor is Vdata - Vdd. In the light-emitting stage, the light-emitting control line provides a light-emitting control signal, and the first light-emitting device 21 emits light under the drive of the driving transistor T3. At this time, the driving transistor T3' operates in the saturation region, and the voltage between the gate and the first electrode of the driving transistor T3 is: Vgs = Vdata - Vdd. The driving current of the driving transistor T3 is as follows:

[0132]

[0133] Where Vdd is the voltage on the first voltage line VDD, Vdata is the voltage of the data voltage signal provided by the data line Data, Vth is the threshold voltage of the driving transistor T3, and β is a constant related to the characteristics of the driving transistor T3.

[0134] In this embodiment, the orthographic projection of the first electrode of the first light-emitting device 21 onto the substrate 1 covers at least a portion of the orthographic projection of the first pixel circuit onto the substrate 1. That is, the first pixel circuit connected to the first light-emitting device 21 is disposed in the first display area without occupying space in the second display area, thus not affecting the resolution of the first display area. Furthermore, since the orthographic projection of the first electrode of the first light-emitting device 21 onto the substrate 1 covers the orthographic projection of the first pixel circuit onto the substrate 1, the distances between different first light-emitting devices 21 and their respective connected first pixel circuits can be substantially the same, thereby improving the uniformity of the display in the first display area. Additionally, in the first pixel circuit, the data voltage signal is directly written to the gate of the driving transistor T3 by the data writing sub-circuit 11, eliminating the need for a reset sub-circuit 13 to reset the gate of the driving transistor T3. This simplifies the structure of the first pixel circuit, minimizing its impact on the transmittance of the first display area.

[0135] Figure 5B This is a circuit schematic diagram of the first pixel circuit provided in some other embodiments of this disclosure. Figure 5B The first pixel circuit shown is Figure 5A This is a specific implementation of the first pixel circuit in [the image / process]. For example... Figure 5B As shown, the first pixel circuit includes the aforementioned storage capacitor Cst, driving transistor T3, data writing sub-circuit 11, reset sub-circuit 13, and light emission control sub-circuit 12. The data writing sub-circuit 11 includes a first writing transistor T1 and a second writing transistor T2. The gate of the first writing transistor T1 is connected to the first scan line N-Gate for providing the first scan signal, and the second terminal of the first writing transistor T1 is connected to the gate of the driving transistor T3. The gate of the second writing transistor T2 is connected to the second scan line P-Gate for providing the second scan signal, and the second terminal of the second writing transistor T2 is connected to the first terminal of the first writing transistor T1. The first terminal of the second writing transistor T2 is connected to the data line Data for providing the data voltage signal.

[0136] The light-emitting control sub-circuit 12 includes a light-emitting control transistor T4. The gate of the light-emitting control transistor T4 is connected to a light-emitting control line EM for providing a light-emitting control signal. The first electrode of the light-emitting control transistor T4 is connected to the second electrode of the driving transistor T3. The second electrode of the light-emitting control transistor T4 is connected to the first electrode of the first light-emitting device 21.

[0137] The reset sub-circuit 13 includes a reset transistor T5. The gate of the reset transistor T5 is connected to the second scan line P-Gate for providing the second scan signal. The first electrode of the reset transistor T5 is connected to the initialization voltage line for providing the initial voltage signal. The second electrode of the reset transistor T5 is connected to the first electrode of the first light-emitting device 21.

[0138] In some examples, the reset transistor T5, the second write transistor T2, the drive transistor T3, and the light-emitting control transistor T4 can all be low-temperature polysilicon transistors, and are P-type transistors. The first write transistor T1 is an oxide transistor, and is an N-type transistor.

[0139] Figure 6A for Figure 5B A timing diagram of the first pixel circuit in the image. Figure 6B for Figure 5B Another timing diagram of the first pixel circuit in the display. When the display substrate is used for high-frequency display (e.g., display frequency greater than or equal to 60Hz), Figure 5B The timing diagram of the first pixel circuit in the diagram is as follows: Figure 6A As shown, the operation of the first pixel circuit includes a write and reset phase t1 and an emission phase t2. In the write and reset phase t1, the first scan line N-Gate provides a high-level first scan signal, the second scan line P-Gate provides a low-level second scan signal, the data line Data provides a data voltage signal, and the emission control line EM provides a high-level signal. At this time, the initial voltage signal on the initialization voltage line Vinit is written to the first electrode of the first light-emitting device 21, and the data writing sub-circuit 11 writes the data voltage signal to the gate of the driving transistor T3. The voltage stored in the storage capacitor Cst is Vdata - Vdd. In the emission phase t2, the emission control line EM provides a low-level emission control signal, and the first light-emitting device 21 emits light under the drive of the driving transistor T3. At this time, the driving transistor T3 operates in the saturation region, and the voltage between the gate and the first electrode of the driving transistor T3 is Vgs = Vdata - Vdd. The driving current of the driving transistor T3 is... The time period during which the second scan line P-Gate provides a low-level signal can be the same as the time period during which the first scan line N-Gate provides a high-level signal, or it can be within the time period during which the first scan line N-Gate provides a high-level signal. The time period during which the first scan line N-Gate provides a high-level signal and the time period during which the second scan line P-Gate provides a low-level signal both fall within the time period during which the light-emitting control line EM provides a high-level signal.

[0140] When the display substrate is used for low-frequency displays (e.g., display frequency less than 60Hz), Figure 5B The timing diagram of the first pixel circuit in the diagram is as follows: Figure 6B As shown, the operation of the first pixel circuit includes not only the write and reset phase t1 and the light emission phase t2, but also an anode reset phase t3. In the anode reset phase t3, the light emission control line EM provides a high-level signal, the first scan line N-Gate provides a low-level signal, and the second scan line P-Gate provides a low-level signal, thereby resetting the voltage of the first electrode of the first light-emitting device 21 by the reset transistor T5. The reason for including the anode reset phase t3 in the operation of the first pixel circuit is that the first light-emitting device 21 does not emit light during the write and reset phase t1. If the number of times the first light-emitting device 21 does not emit light per second is small, the human eye can easily perceive screen flickering. Adding the anode reset phase t3 increases the number of times the first light-emitting device 21 does not emit light, preventing the human eye from perceiving a flickering screen.

[0141] exist Figure 5A and Figure 5B In the first pixel circuit shown, a threshold compensation transistor is no longer used. During data voltage writing, the data voltage signal is directly written to the gate of the driving transistor T3 without the need for a threshold compensation transistor. Therefore, the data voltage signal writing speed is extremely fast, making it suitable for high-frequency display products. Furthermore, the first write transistor T1 is an oxide transistor, which has lower leakage current during the light-emitting stage, resulting in more stable brightness of the first light-emitting device 21 during the light-emitting stage. Therefore, the first pixel circuit can also be used in low-frequency display products.

[0142] In some embodiments of this disclosure, the display substrate includes the following layers sequentially disposed along a direction away from the substrate 1: a first semiconductor layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer dielectric layer, a second semiconductor layer, a third gate insulating layer, a third gate metal layer, a second interlayer dielectric layer, a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a transparent lead layer, and a third planarization layer.

[0143] Figure 7 This is a plan view of the first semiconductor layer provided in some embodiments of this disclosure. Figure 8 This is a plan view of the first gate metal layer provided in some embodiments of this disclosure. Figure 9 This is a schematic diagram of the second gate metal layer provided in some embodiments of this disclosure. Figure 10 This is a schematic diagram of the second semiconductor layer provided in some embodiments of the present disclosure. Figure 11 This is a schematic diagram of the third gate metal layer provided in some embodiments of this disclosure. Figure 12 This is a schematic diagram of the first source / drain metal layer provided in some embodiments of this disclosure. Figure 13 This is a schematic diagram of the second source / drain metal layer provided in some embodiments of this disclosure. Figure 14 This is a planar view of the stacked first semiconductor layer, first gate metal layer, second gate metal layer, second semiconductor layer, third gate metal layer, first source / drain metal layer, and second source / drain metal layer provided in some embodiments of this disclosure. Figure 15 This is a superimposed planar view of the first semiconductor layer, first gate metal layer, second gate metal layer, second semiconductor layer, third gate metal layer, first source / drain metal layer, second source / drain metal layer, and vias on the second planarization layer provided in some embodiments of this disclosure. Figure 16 For along Figure 15 A sectional view of line B-B' in the middle. Figure 17 For along Figure 15 A sectional view of line C-C' in the middle. Figure 18 For along Figure 15 A cross-sectional view of line D-D' in the middle. Figure 19 This is a plan view of the transparent lead layer and the first electrode layer provided in some embodiments of this disclosure. Figure 20 This is a plan view of the first electrode layer and a plurality of first pixel circuits provided in some embodiments of this disclosure.

[0144] Combination Figures 7 to 18 As shown, the first semiconductor layer Act1 can be formed by patterning semiconductor material. The first semiconductor layer Act1 can include the active layer and doped region patterns of each P-type transistor (i.e., the second write transistor T2, the drive transistor T3, the reset transistor T5, and the light-emitting control transistor T4) in the first pixel circuit. The active layer and doped region patterns of each transistor in the same first pixel circuit are integrally formed. For the same P-type transistor, doped region patterns are provided on both sides of the active layer of the P-type transistor. The doped region patterns on both sides of the active layer can serve as the first electrode and the second electrode of the P-type transistor, respectively. Figure 7 The active layers T2_a, T3_a~T5_a of each P-type transistor are marked. It should be noted that in the embodiments of this disclosure, the position of the active layer of each transistor represents the position of the corresponding transistor.

[0145] In some embodiments, the orthogonal projection of the active layer T2_a of the second write transistor T2 onto the substrate 1 is located within the orthogonal projection range of the first electrode 211 of the first light-emitting device onto the substrate 1.

[0146] like Figure 7As shown, the first electrode T5_1 and the second electrode T5_2 of the reset transistor T5 are arranged along a first direction. The orthographic projection of the reset transistor T5 on the substrate 1 is located on one side of the orthographic projection of the storage capacitor Cst on the substrate 1 along a second direction, and the orthographic projection of the reset transistor T5 on the substrate 1 is located between the orthographic projection of the storage capacitor Cst on the substrate 1 and the orthographic projection of the second write transistor T2 on the substrate 1. The first direction intersects the second direction; for example, the first direction is perpendicular to the second direction. The active layer T2_a of the second write transistor T2 is spaced apart from the active layer T5_a of the reset transistor T5. The active layer T5_a of the reset transistor T5, the active layer T3_a of the driving transistor T3, and the active layer T4_a of the light-emitting control transistor T4 are formed as a continuous pattern. The first electrode T4_1 and the second electrode T4_2 of the light-emitting control transistor T4 are arranged along the second direction. The second electrode T4_2 of the light-emitting control transistor T4 and the second electrode T5_2 of the reset transistor T5 are formed into a single structure. The first electrode T4_1 of the light-emitting control transistor T4 and the second electrode T3_2 of the driving transistor T3 are formed into a single structure.

[0147] like Figure 8 As shown, the first gate metal layer Gate1 includes: the gate T2_g of the second write transistor T2, the gate T5_g of the reset transistor T5, the gate T3_g of the drive transistor T3, the gate T4_g of the light-emitting control transistor T4, and the first plate Cst1 of the storage capacitor Cst. The gate T2_g of the second write transistor T2 and the gate T5_g of the reset transistor T5 are formed as a single structure, extending along a second direction. The gate T3_g of the drive transistor T3 and the first plate Cst1 of the storage capacitor Cst are also formed as a single structure.

[0148] In some embodiments, the first write transistor T1 is a dual-gate transistor, and the gate of the first write transistor T1 includes a first gate T1_g1 and a second gate T1_g2. (Combined with...) Figures 9 to 11 As shown, the second plate Cst2 of the storage capacitor Cst and the first gate T1_g1 of the first write transistor T1 are located in the second gate metal layer Gate2. The first plate Cst1 and the second plate Cst2 of the storage capacitor Cst are arranged opposite to each other. The second gate T1_g2 of the first write transistor T1 is located in the third gate metal layer Gate3. The first gate T1_g1 and the second gate T1_g2 are arranged opposite to each other.

[0149] like Figure 9As shown, the second electrode Cst2 of the storage capacitor Cst includes: an electrode body portion Cst21 and an electrode connecting portion Cst22. The electrode body portion Cst21 is approximately rectangular, with chamfered corners at the corners. The electrode connecting portion Cst22 is used to connect to the first voltage line VDD. The orthographic projection of the storage capacitor Cst onto the substrate 1 is located on one side of the orthographic projection of the first electrode T4_1 of the light-emitting control transistor T4 onto the substrate 1 along a first direction.

[0150] In some embodiments, the orthographic projection of the second electrode plate Cst2 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 211 of the first light-emitting device on the substrate 1.

[0151] like Figure 9 As shown, the first gate T1_g1 of the first write transistor T1 is formed as a bent structure. For example, the first gate T1_g1 of the first write transistor T1 includes a gate body portion T1_g11 and a gate connection portion T1_g12, with the gate connection portion T1_g12 located on one side of the gate body portion T1_g11 along the second direction.

[0152] like Figure 10 As shown, the second semiconductor layer Act2 includes the active layer T1_a of the first write transistor T1. The second semiconductor layer Act2 is made of an oxide semiconductor material, such as IGZO. In the same first pixel circuit, doped region patterns are provided on both sides of the active layer T1_a of the first write transistor T1. The doped region patterns on both sides of the active layer T1_a can serve as the first electrode T1_1 and the second electrode T1_2 of the first write transistor T1, respectively. The first electrode T1_1 and the second electrode T1_2 of the first write transistor T1 can be arranged along a first direction. The dimensions of the first electrode T1_1 and the second electrode T1_2 of the first write transistor T1 in the first direction are both larger than the dimensions of the active layer T1_a in the first direction, so that the structure in the first source / drain metal layer SD1 can be connected to the first electrode T1_1 and the second electrode T1_2 of the first write transistor T1 through vias.

[0153] In some embodiments, the orthographic projection of the active layer T1_a of the first write transistor T1 onto the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 211 of the first light-emitting device onto the substrate 1.

[0154] In this embodiment of the present disclosure, the first write transistor T1 is a dual-gate transistor, and the first gate T1_g1 and the second gate T1_g2 are located on both sides of the active layer T1_a along its thickness direction, which can prevent the first write transistor T1 from experiencing characteristic drift due to the active layer T1_a being exposed to light.

[0155] Figure 14The positions of the first write transistor T1 and the second write transistor T2 are marked by two dashed boxes. Figures 7 to 11 , Figure 14 As shown, the orthogonal projection of the second write transistor T2 onto the substrate 1 is located on one side of the storage capacitor Cst along the second direction. Additionally, the first write transistor T1 is located on one side of the second write transistor T2 along the first direction. The first and second directions intersect; for example, the first direction is perpendicular to the second direction.

[0156] like Figure 12 As shown, the first source / drain metal layer SD1 includes: a first transition electrode E1, a third transition electrode E3, a fifth transition electrode E5, a sixth transition electrode E6, a seventh transition electrode E7, an eighth transition electrode E8, a tenth transition electrode E10, a twelfth transition electrode E12, and a fourteenth transition electrode E14.

[0157] Specifically, the orthographic projection of the first transition electrode E1 on the substrate 1 overlaps with the orthographic projection of the first gate T1_g1 of the first write transistor T1 on the substrate 1. The orthographic projection of the fourteenth transition electrode E14 on the substrate 1 overlaps with the orthographic projection of the second electrode T4_2 of the light-emitting control transistor T4 on the substrate 1. The orthographic projection of the third transition electrode E3 on the substrate 1 overlaps with the orthographic projection of the gate T2_g of the second write transistor T2 on the substrate 1. The orthographic projection of the fifth transition electrode E5 on the substrate 1 overlaps with the orthographic projection of the first electrode T2_1 of the second write transistor T2 on the substrate 1.

[0158] The sixth transition electrode E6 includes a first portion E61, a second portion E62, and an intermediate portion E60 connecting the two. The orthographic projection of the second portion E62 of the sixth transition electrode E6 on the substrate 1 overlaps with the orthographic projection of the second electrode T2_2 of the second write transistor T2 on the substrate 1. The orthographic projection of the first portion E61 of the sixth transition electrode E6 on the substrate 1 overlaps with the orthographic projection of the first electrode T1_1 of the first write transistor T1 on the substrate 1. The intermediate portion E60 of the sixth transition electrode E6 can be bent. Figure 12 , Figures 14 to 18 As shown, one end of the sixth transition electrode E6 is connected to the first electrode T1_1 of the first write transistor T1 through the tenth via V10, and the other end is connected to the second electrode T2_2 of the second write transistor T2 through the eleventh via V11. The tenth via V10 penetrates the third gate insulating layer GI3 and the second interlayer dielectric layer ILD2, while the eleventh via V11 penetrates the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2.

[0159] In some embodiments, the orthographic projection of the sixth transition electrode E6 on the substrate 1 overlaps at least partially with the orthographic projection of the first electrode 211 of the first light-emitting device on the substrate 1.

[0160] The orthographic projection of the seventh transition electrode E7 on the substrate 1 overlaps with the orthographic projection of the second electrode T1_2 of the first write transistor T1 and the orthographic projection of the gate T3_g of the driving transistor T3 on the substrate 1. One end of the seventh transition electrode E7 is connected to the first electrode T1_2 of the first write transistor T1 through the twelfth via V12, and the other end of the seventh transition electrode E7 is connected to the gate T3_g of the driving transistor T3 through the thirteenth via V13. The twelfth via penetrates the third gate insulating layer GI3 and the second interlayer dielectric layer ILD2, and the thirteenth via penetrates the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2.

[0161] In some embodiments, the orthographic projection of the seventh transition electrode E7 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 211 of the first light-emitting device on the substrate 1.

[0162] The orthographic projection of the eighth transition electrode E8 on the substrate 1 overlaps with the orthographic projection of the second plate Cst2 of the storage capacitor Cst and the orthographic projection of the first electrode T3_1 of the driving transistor T3 on the substrate 1. The orthographic projection of the tenth transition electrode E10 on the substrate 1 overlaps with the orthographic projection of the gate T4_g of the light-emitting control transistor T4 on the substrate 1. The orthographic projection of the twelfth transition electrode E12 on the substrate 1 overlaps with the orthographic projection of the reset transistor T5_1 on the substrate 1. The orthographic projection of the fourteenth transition electrode on the substrate 1 overlaps with the orthographic projection of the second electrode T5_2 of the reset transistor T5 on the substrate 1.

[0163] like Figure 13 As shown, the second source / drain metal layer SD2 includes: a data line Data, a second transition electrode E2, a fourth transition electrode E4, a ninth transition electrode E9, an eleventh transition electrode E11, a thirteenth transition electrode E13, and a fifteenth transition electrode E15. Figure 13As shown, the data line Data includes a main body Data1 and a bent portion Data2, which are integrally formed. The main body Data1 extends along a first direction. The orthographic projection of the bent portion Data2 on the substrate 1 is located on one side of the orthographic projection of the storage capacitor Cst on the substrate 1 along a second direction, and bends towards the orthographic projection of the storage capacitor Cst on the substrate 1. The orthographic projection of the bent portion Data2 on the substrate 1 at least partially overlaps with the orthographic projection of the gate T2_g of the second write transistor T2 on the substrate 1. In some embodiments, the orthographic projection of the bent portion Data2 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 211 of the first light-emitting device on the substrate 1.

[0164] In some embodiments, combined with Figures 7 to 18 As shown, the data line Data is connected to the fifth transition electrode E5 through the ninth via V9 that passes through the first planarization layer PLN1. The fifth transition electrode E5 is connected to the first electrode T2_1 of the second write transistor T2 through the eighth via V8. The eighth via V8 passes through the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2.

[0165] The fourth transfer electrode E4 is located on the side of the bent portion Data2 away from the storage capacitor Cst. The orthographic projection of the fourth transfer electrode E4 on the substrate 1 at least partially overlaps with the orthographic projection of the third transfer electrode E3 on the substrate 1. When the second scan line P-Gate is connected to the gate T2_g of the second write transistor T2, it can be connected to the gate T2_g of the second write transistor T2 through the third transfer electrode E3 and the fourth transfer electrode E4.

[0166] The thirteenth transfer electrode E13 is located on the side of the bent portion Data2 near the storage capacitor Cst. The orthographic projection of the thirteenth transfer electrode E13 on the substrate 1 at least partially overlaps with the orthographic projection of the twelfth transfer electrode E12 on the substrate 1. The initialization voltage line Vinit can be connected to the first terminal T5_1 of the reset transistor T5 through the thirteenth transfer electrode E13 and the twelfth transfer electrode E12. The second transfer electrode E2 is located on one side of the fifteenth transfer electrode E15 along the first direction. The orthographic projection of the second transfer electrode E2 on the substrate 1 at least partially overlaps with the orthographic projection of the first transfer electrode E1 on the substrate 1. The first scan line N-Gate can be connected to the first gate T1_g1 and the second gate T1_g2 of the first write transistor T1 through the second transfer electrode E2 and the first transfer electrode E1. The ninth transfer electrode E9 is located on one side of the eleventh transfer electrode E11 along the first direction. The orthographic projection of the ninth transfer electrode E9 on the substrate 1 at least partially overlaps with the orthographic projection of the eighth transfer electrode E8 on the substrate 1. The orthographic projection of the eleventh transition electrode E11 on the substrate 1 at least partially overlaps with the orthographic projection of the tenth transition electrode E10 on the substrate 1. The orthographic projection of the fifteenth transition electrode E15 on the substrate 1 at least partially overlaps with the orthographic projection of the fourteenth transition electrode E14 on the substrate 1.

[0167] like Figure 19 As shown, the transparent lead layer includes: a first scan line N-Gate, a second scan line P-Gate, a light emission control line EM, a first voltage line VDD, an initialization voltage line Vinit, and a sixteenth transition electrode E16. Each signal line in the transparent lead layer can be made of a transparent conductive material, such as indium tin oxide (ITO).

[0168] Combination Figures 7 to 19 As shown, the first scan line N-Gate is connected to the gate T1_g of the first write transistor T1 through the first transition electrode E1 and the second transition electrode E2. Specifically, one end of the first transition electrode E1 is connected to the first gate T1_g1 of the first write transistor T1 through the first via V1, and the other end of the first transition electrode E1 is connected to the second gate T1_g2 of the first write transistor T1 through the second via V2. The first via V1 penetrates the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2, and the second via V2 penetrates the second interlayer dielectric layer ILD2. One end of the second transition electrode E2 is connected to the first transition electrode E1 through the third via V3 penetrating the first planarization layer PLN1, and the first scan line N-Gate is connected to the other end of the second transition electrode E2 through the fourth via V4 penetrating the second planarization layer PLN2.

[0169] The second scan line P-Gate is connected to the gate T2_g of the second write transistor T2 via the third transition electrode E3 and the fourth transition electrode E4. Specifically, the third transition electrode E3 is connected to the gate T2_g of the second write transistor T2 via the fifth via V5, which simultaneously penetrates the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2. The fourth transition electrode E4 is connected to the third transition electrode E3 via the sixth via V6 penetrating the first planarization layer PLN1, and the second scan line P-Gate is connected to the fourth transition electrode E4 via the seventh via V7 penetrating the second planarization layer PLN2.

[0170] The first voltage line VDD is connected to the first terminal T3_1 of the driving transistor T3 through the eighth transition electrode E8 and the ninth transition electrode E9. Specifically, the eighth transition electrode E8 is connected to the first terminal T3_1 of the driving transistor T3 through the fourteenth via V14, which penetrates the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2. The ninth transition electrode E9 is connected to the eighth transition electrode E8 through the fifteenth via V15, which penetrates the first planarization layer PLN1. The first voltage line VDD is connected to the ninth transition electrode E9 through the sixteenth via, which penetrates the second planarization layer PLN2.

[0171] In addition, the eighth transition electrode E8 is also connected to the second plate Cst2 of the storage capacitor Cst through the seventeenth via V17, thereby realizing the electrical connection between the second plate Cst2 of the storage capacitor Cst and the first voltage line. The seventeenth via penetrates the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2.

[0172] The light-emitting control line EM is connected to the gate T4_g of the light-emitting control transistor T4 through the tenth transition electrode E10 and the eleventh transition electrode E11. Specifically, the tenth transition electrode E10 is connected to the gate T4_g of the light-emitting control transistor T4 through the eighteenth via V18, which penetrates the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2; the eleventh transition electrode E11 is connected to the tenth transition electrode E10 through the nineteenth via penetrating the first planarization layer PLN1; and the light-emitting control line EM is connected to the eleventh transition electrode E11 through the twentieth via V20 penetrating the second planarization layer PLN2.

[0173] The initialization voltage line Vinit is connected to the first terminal T5_1 of the reset transistor T5 through the twelfth transition electrode E12 and the thirteenth transition electrode E13. Specifically, the twelfth transition electrode E12 is connected to the first terminal T5_1 of the reset transistor T5 through the twenty-first via V21, which penetrates the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2. The thirteenth transition electrode E13 is connected to the twelfth transition electrode E12 through the twenty-second via V22, which penetrates the first planarization layer PLN1 between the first source / drain metal layers SD1 and the second source / drain metal layers SD2. The initialization voltage line Vinit is connected to the thirteenth transition electrode E13 through the twenty-third via V23, which penetrates the second planarization layer PLN2 between the transparent lead layer and the second source / drain conductive layer.

[0174] Combination Figures 14-15 , Figures 19-20 As shown, the first electrode 211 of the first light-emitting device includes an electrode body portion 2111 and an electrode connection portion 2112 connected to the electrode body portion 2111. Optionally, the electrode body portion 2111 is generally circular. The electrode connection portion 2112 is connected to the second electrode T5_2 of the reset transistor T5 through a fourteenth transition electrode E14 and a fifteenth transition electrode E15. Specifically, the fourteenth transition electrode E14 is connected to the second electrode T5_2 of the reset transistor T5 through a twenty-fourth via V24, the fifteenth transition electrode E15 is connected to the fourteenth transition electrode E14 through a twenty-fifth via V25, the sixteenth transition electrode E16 is connected to the fifteenth transition electrode E15 through a twenty-sixth via V26 penetrating the second planarization layer PLN2, and the electrode connection portion 2112 is connected to the sixteenth transition electrode E16 through a twenty-seventh via V27 penetrating the third planarization layer. The twenty-fourth via V24 penetrates the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate insulating layer GI3, and the second interlayer dielectric layer ILD2; the twenty-fifth via V25 penetrates the first planarization layer PLN1 between the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0175] Figure 21 This is a schematic diagram illustrating the arrangement of multiple sub-pixels in a first display area provided in some embodiments of this disclosure. Each sub-pixel in the first display area includes a first pixel circuit and a first light-emitting device. The multiple sub-pixels are arranged in multiple rows and columns. Multiple sub-pixels in the same column are arranged along a first direction, and multiple sub-pixels in the same row are arranged along a second direction. Each pair of adjacent rows of sub-pixels forms a repeating group 30, and the two rows of sub-pixels in the repeating group 30 are arranged alternately. Figure 21The rectangle 30a in the diagram represents the area where the first pixel circuit is located. In one example, within the same repeating group 30, one row of sub-pixels consists of first-color sub-pixels, and the other row includes alternating second-color and third-color sub-pixels. The color of each sub-pixel is specifically the color emitted by the first light-emitting device within that sub-pixel. The first electrode of the first light-emitting device in the first-color sub-pixel is denoted as 211r, the first electrode of the first light-emitting device in the second-color sub-pixel is denoted as 211b, and the first electrode of the first light-emitting device in the third-color sub-pixel is denoted as 211g. The area of ​​the first electrode 211g is smaller than the area of ​​the first electrode 211r, and the area of ​​the first electrode 211r is smaller than the area of ​​the first electrode 211b. For example, the first-color sub-pixel might be green, the second-color sub-pixel red, and the third-color sub-pixel blue.

[0176] In some embodiments, the orthogonal projection of the first electrode 211r on the substrate 1 covers the orthogonal projections of the second write transistor T2, at least a portion of the first write transistor T1, the reset transistor T5, and at least a portion of the light-emitting control transistor T4 on the substrate 1, and also covers at least a portion of the driving transistor T3 and at least a portion of the storage capacitor Cst on the substrate 1. Similarly, the orthogonal projection of the first electrode 211b on the substrate 1 covers the orthogonal projections of the second write transistor T2, most of the first write transistor T1, the reset transistor T5, and most of the light-emitting control transistor T4 on the substrate 1, and also covers most of the driving transistor T3 and most of the storage capacitor Cst on the substrate 1. The orthographic projection of the first electrode 211g on the substrate 1 covers the orthographic projection of the second write transistor T2 on the substrate 1, the orthographic projection of at least a portion of the first write transistor T1 on the substrate 1, the orthographic projection of the reset transistor T5 on the substrate 1, the orthographic projection of at least a portion of the light-emitting control transistor T4 on the substrate 1, and also covers the orthographic projection of at least a portion of the driving transistor T3 on the substrate 1, and the orthographic projection of at least a portion of the storage capacitor Cst on the substrate 1.

[0177] Combination Figure 19 and Figure 21As shown, each light-emitting control line EM corresponds to a repeating group 30, and different light-emitting control lines EM correspond to different repeating groups 30. Each light-emitting control line EM is connected to the first pixel circuit of each sub-pixel in the corresponding repeating group 30. In some embodiments, the light-emitting control line EM includes: a control line body portion EM1 and a control line lead portion EM2. The control line body portion EM1 extends generally along a second direction, and the control line lead portion EM2 extends along a first direction. In the same repeating group 30, the first pixel circuit in one row of sub-pixels is connected to the control line body portion EM1, and the first pixel circuit in another row of sub-pixels is connected to the control line lead portion EM2.

[0178] Each first scan line N-Gate corresponds to a repeating group 30, and different first scan lines N-Gates correspond to different repeating groups 30. Each first scan line N-Gate is connected to the first pixel circuit of each sub-pixel in the corresponding repeating group 30. In some embodiments, the first scan line N-Gate includes a scan line body portion N-Gate1 and a scan line lead-out portion N-Gate2. The scan line body portion N-Gate1 includes a plurality of scan line segments arranged sequentially in a second direction. The plurality of scan line segments are connected sequentially to form a curved structure in the scan line body portion N-Gate1. The scan line lead-out portion N-Gate2 extends along a first direction. In the same repeating group 30, the first pixel circuit in one row of sub-pixels is connected to the scan line body portion N-Gate1, and the first pixel circuit in another row of sub-pixels is connected to the scan line lead-out portion N-Gate2.

[0179] Each second scan line P-Gate corresponds to a repeating group 30. Different second scan lines P-Gates correspond to different repeating groups 30. Each second scan line P-Gate is curved and connected to the first pixel circuit of each sub-pixel in the corresponding repeating group 30.

[0180] Each initialization voltage line Vinit corresponds to a repeating group 30. Different initialization voltage lines Vinit correspond to different repeating groups 30. Each initialization voltage line Vinit is curved and connected to the first pixel circuit of each sub-pixel in the corresponding repeating group 30.

[0181] Each data line Data corresponds to a repeating group 30. Different data lines Data correspond to different columns of sub-pixels. Each data line Data is connected to the first pixel circuit in each sub-pixel of the corresponding column.

[0182] As described above, a second pixel circuit is provided in the second display area of ​​the display substrate. The second pixel circuit is connected to a first initialization voltage line Vinit1', a second initialization voltage line Vinit2', a first voltage line VDD', a first scan line N-Gate', a second scan line P-Gate', and a light emission control line EM'. In this case, each initialization voltage line Vinit in the first display area can be connected to one first initialization voltage line Vinit1' in the second display area, each first scan line N-Gate in the first display area AA1 can be connected to one first scan line N-Gate' in the second display area AA2, each second scan line P-Gate in the first display area AA1 can be connected to one second scan line P-Gate' in the second display area AA2, and each light emission control line EM in the first display area AA1 can be connected to one light emission control line EM' in the second display area AA2.

[0183] In this case, the same driver chip can be used to drive the first pixel circuit and the second pixel circuit to work simultaneously. When the display substrate is used for high-frequency display, the operating timing of the first pixel circuit in the first display area AA1 is as follows: Figure 6A As shown, the operating timing of the first pixel circuit in the second display area AA2 is as follows: Figure 4 As shown in the diagram, when the second pixel circuit is in the data writing stage t1', the first pixel circuit is in the writing and reset stage t1; when the second pixel circuit is in the light-emitting stage t2', the first pixel circuit is in the light-emitting stage t2. When the display substrate is used for low-frequency display, the operating timing of the first pixel circuit in the first display area AA1 is as follows: Figure 6B As shown, the operating timing of the second pixel circuit in the second display area AA2 is compared to Figure 4 In this case, an anode reset stage t3' is added. During the anode reset stage t3' of the second pixel circuit, the light emission control line EM' connected to the second pixel circuit provides the same signal as the light emission control line EM connected to the first pixel circuit. The first scan line N-Gate' connected to the second pixel circuit provides the same signal as the first scan line N-Gate connected to the first pixel circuit. The second scan line P-Gate' connected to the second pixel circuit provides the same signal as the second scan line P-Gate connected to the first pixel circuit. The first reset line Re1 and the second reset line Re2 connected to the second pixel circuit both provide low-level signals.

[0184] In addition, in this embodiment of the present disclosure, the low-temperature polysilicon transistor in the first display area AA1 can be fabricated simultaneously with the low-temperature polysilicon transistor in the second display area AA2, and the oxide transistor in the first display area AA1 can be fabricated simultaneously with the oxide transistor in the second display area AA2.

[0185] This disclosure also provides a display device. The display device may include the display substrate described above. The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0186] like Figure 1 and Figure 2 As shown, the display device further includes an image sensor 2, which is located on one side of the display substrate 100. The orthographic projection of the image sensor onto the display substrate 100 falls within the first display area AA1.

[0187] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising: The substrate includes a first display area and a second display area located at least one side of the first display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area; A plurality of first sub-pixels are disposed on the substrate and located in the first display area. At least one of the plurality of first sub-pixels includes: a first pixel circuit and a first light-emitting device. The first pixel circuit includes: a storage capacitor and a driving transistor. The first electrode of the driving transistor is connected to a first voltage line. The two plates of the storage capacitor are respectively connected to the gate and the first electrode of the driving transistor. The first pixel circuit further includes: The data writing sub-circuit is configured to write a data voltage signal into the gate of the driving transistor in response to a first scan signal and a second scan signal; A reset sub-circuit is configured to provide an initial voltage signal to the first electrode of the first light-emitting device in response to the second scan signal; The light emission control sub-circuit is configured to transmit the drive current output by the drive transistor to the first light emission device in response to the light emission control signal; Wherein, the orthogonal projection of the first electrode of the first light-emitting device on the substrate covers at least a portion of the orthogonal projection of the first pixel circuit on the substrate; The data line of the data voltage signal includes: a data line body and a bent portion. The data line body extends along a first direction. The orthographic projection of the bent portion on the substrate is located on one side of the orthographic projection of the storage capacitor on the substrate along a second direction, and bends toward the orthographic projection of the storage capacitor on the substrate. The first direction and the second direction intersect. Wherein, the orthographic projection of the curved portion on the substrate overlaps at least partially with the orthographic projection of the first electrode of the first light-emitting device on the substrate. 2.The display substrate of claim 1, wherein, The data writing sub-circuit includes: A first write transistor, the gate of which is connected to a first scan line for providing the first scan signal, and the second terminal of which is connected to the gate of the driving transistor, wherein the first write transistor is an oxide transistor; The second write transistor has its gate connected to a second scan line for providing the second scan signal, its first terminal connected to a data line for providing the data voltage signal, and its second terminal connected to the first terminal of the first write transistor. The second write transistor is a polysilicon transistor. 3.The display substrate of claim 2, wherein, The first and second terminals of the second write transistor are arranged along a first direction, and the orthographic projection of the second write transistor on the substrate is located on one side of the storage capacitor along a second direction. The first write transistor is located on the side of the second write transistor along the first direction, and the first and second directions intersect.

4. The display substrate according to claim 2, wherein the orthographic projection of the curved portion on the substrate at least partially overlaps with the orthographic projection of the gate of the second write transistor on the substrate. 5.The display substrate of claim 2, wherein, The gate of the first write transistor includes an electrically connected first gate and a second gate, wherein the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the second gate on the substrate. The first pixel circuit also includes: The first adapter electrode has one end connected to the first gate of the first write transistor through a via, and the other end connected to the second gate of the first write transistor through a via. The second adapter electrode is connected to the first adapter electrode via a via, and the first scan line is connected to the second adapter electrode via a via. 6.The display substrate of claim 2, wherein, The first pixel circuit also includes: The third transfer electrode is connected to the gate of the second write transistor through a via; The fourth adapter electrode is connected to the third adapter electrode via a via, and the second scan line is connected to the fourth adapter electrode via a via. 7.The display substrate of claim 2, wherein, The first pixel circuit further includes a fifth adapter electrode, the data line is connected to the fifth adapter electrode through a via, and the fifth adapter electrode is connected to the first electrode of the second write transistor through a via. 8.The display substrate of claim 2, wherein, The first pixel circuit further includes: a sixth adapter electrode, one end of which is connected to the first electrode of the first write transistor through a via, and the other end of which is connected to the second electrode of the second write transistor through a via. The orthographic projection of the sixth adapter electrode on the substrate overlaps at least partially with the orthographic projection of the first electrode of the first light-emitting device on the substrate. 9.The display substrate of claim 2, wherein, The orthographic projection of the active layer of the first write transistor on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate, and the orthographic projection of the active layer of the second write transistor on the substrate is located within the orthographic projection range of the first electrode of the first light-emitting device on the substrate. 10.The display substrate of claim 2, wherein, The first pixel circuit also includes: The seventh adapter electrode is connected to the second electrode of the first write transistor through a via, and the other end of the seventh adapter electrode is connected to the gate of the drive transistor through a via; the orthographic projection of the seventh adapter electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate.

11. The display substrate according to claim 2, wherein, The first pixel circuit further includes an eighth adapter electrode and a ninth adapter electrode. The first voltage line is connected to the ninth adapter electrode through a via, the ninth adapter electrode is connected to the eighth adapter electrode through a via, and the eighth adapter electrode is connected to the first electrode of the driving transistor through a via.

12. The display substrate according to claim 11, wherein, The storage capacitor has two plates: a first plate and a second plate. The gate of the driving transistor is integrally formed with the first plate. The eighth transfer electrode is also connected to the second plate through a via. The orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate.

13. The display substrate according to any one of claims 1 to 12, wherein, The light-emitting control sub-circuit includes: a light-emitting control transistor, the gate of which is connected to a light-emitting control line for providing the light-emitting control signal, the first electrode of which is connected to the second electrode of the driving transistor, and the second electrode of which is connected to the first electrode of the first light-emitting device.

14. The display substrate according to claim 13, wherein, The first pixel circuit further includes a tenth transition electrode and an eleventh transition electrode. The light emission control line is connected to the eleventh transition electrode through a via. The eleventh transition electrode is connected to the tenth transition electrode through a via. The tenth transition electrode is connected to the gate of the light emission control transistor through a via.

15. The display substrate according to claim 13, wherein, The first and second electrodes of the light-emitting control transistor are arranged along a second direction, and the orthographic projection of the storage capacitor on the substrate is located on one side of the orthographic projection of the first electrode of the light-emitting control transistor on the substrate along a first direction, the first direction intersecting the second direction.

16. The display substrate according to any one of claims 1 to 12, wherein, The reset sub-circuit includes: a reset transistor, the gate of which is connected to a second scan line for providing the second scan signal, the first electrode of which is connected to an initialization voltage line for providing the initial voltage signal, and the second electrode of which is connected to the first electrode of the first light-emitting device.

17. The display substrate according to claim 16, wherein, The first pixel circuit further includes a twelfth transition electrode and a thirteenth transition electrode. The initialization voltage line is connected to the thirteenth transition electrode through a via. The thirteenth transition electrode is connected to the twelfth transition electrode through a via. The twelfth transition electrode is connected to the first terminal of the reset transistor through a via.

18. The display substrate according to claim 16, wherein, The first pixel circuit further includes a fourteenth transition electrode, a fifteenth transition electrode, and a sixteenth transition electrode. The first electrode of the light-emitting device is connected to the sixteenth transition electrode through a via. The sixteenth transition electrode is connected to the fifteenth transition electrode through a via. The fifteenth transition electrode is connected to the fourteenth transition electrode through a via. The fourteenth transition electrode is connected to the second electrode of the reset transistor through a via.

19. The display substrate according to claim 16, wherein, The first and second terminals of the reset transistor are arranged along a first direction, and the orthographic projection of the reset transistor on the substrate is located on one side of the orthographic projection of the storage capacitor on the substrate along a second direction.

20. The display substrate according to claim 16, wherein, The data writing sub-circuit includes a first write transistor and a second write transistor. The gate of the second write transistor and the gate of the reset transistor are formed as an integral structure, and the integral structure extends along the second direction.

21. The display substrate according to any one of claims 1 to 12, wherein, The display substrate includes, in a direction away from the substrate, the following layers sequentially disposed: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a transparent lead layer, and a first electrode layer. The first pixel circuit includes at least one polysilicon transistor and at least one oxide transistor. The first semiconductor layer includes: an active layer, a first electrode, and a second electrode of each polysilicon transistor in the first pixel circuit; the first gate metal layer includes: the gate of each polysilicon transistor in the first pixel circuit; the second gate metal layer includes: the first gate of each oxide transistor in the first pixel circuit and the first electrode of the storage capacitor; the second semiconductor layer includes: an active layer, a first electrode, and a second electrode of each oxide transistor in the first pixel circuit; the third gate metal layer includes: the second electrode of the storage capacitor; the transparent lead layer includes the first voltage line; the first electrode layer includes the first electrode of the first light-emitting device.

22. The display substrate according to claim 21, wherein, The data writing sub-circuit includes a first writing transistor, and the gate of the first writing transistor includes a first gate and a second gate. The transparent lead layer further includes a first scan line, and the display substrate further includes a first source / drain metal layer and a second source / drain metal layer located between the third gate metal layer and the transparent lead layer, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate. The first source / drain metal layer includes a first transition electrode, and the second source / drain metal layer includes a second transition electrode. The first scan line is connected to the second transition electrode through a via, and the second transition electrode is connected to the first transition electrode through a via. The two ends of the first transition electrode are respectively connected to the first gate and the second gate of the first write transistor through vias.

23. The display substrate according to claim 22, wherein, The data writing sub-circuit further includes a second writing transistor, the transparent lead layer further includes a second scan line, the first source-drain metal layer further includes a third transition electrode, the second source-drain metal layer further includes a fourth transition electrode, the second scan line is connected to the fourth transition electrode through a via, the fourth transition electrode is connected to the third transition electrode through a via, and the third transition electrode is connected to the gate of the second writing transistor through a via.

24. The display substrate according to claim 23, wherein, The transparent lead layer also includes a data line, and the first source / drain metal layer also includes a fifth transition electrode. The data line is connected to the fifth transition electrode through a via, and the fifth transition electrode is connected to the first electrode of the second write transistor through a via.

25. The display substrate according to claim 23, wherein, The first source / drain metal layer further includes a sixth transition electrode, one end of which is connected to the first electrode of the first write transistor through a via, and the other end of which is connected to the second electrode of the second write transistor through a via.

26. The display substrate according to claim 22, wherein, The first source / drain metal layer further includes a seventh transition electrode, which is connected to the second electrode of the first write transistor through a via, and the other end of the seventh transition electrode is connected to the gate of the drive transistor through a via.

27. The display substrate according to claim 21, wherein, The display substrate further includes a first source / drain metal layer and a second source / drain metal layer located between the third gate metal layer and the transparent lead layer, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate; the first source / drain metal layer includes an eighth transition electrode, and the second source / drain metal layer includes a ninth transition electrode. The first voltage line is connected to the ninth adapter electrode through a via, the ninth adapter electrode is connected to the eighth adapter electrode through a via, the eighth adapter electrode is connected to the first electrode of the driving transistor through a via, and the eighth adapter electrode is also connected to the second electrode of the storage capacitor through a via.

28. The display substrate according to claim 21, wherein, The light emission control sub-circuit includes a light emission control transistor. The display substrate further includes a first source / drain metal layer and a second source / drain metal layer located between the third gate metal layer and the transparent lead layer. The second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate. The first source / drain metal layer includes a tenth transition electrode, and the second source / drain metal layer includes an eleventh transition electrode. The transparent lead layer further includes: a light-emitting control line, which is connected to the eleventh adapter electrode through a via, and the eleventh adapter electrode is connected to the tenth adapter electrode through a via.

29. The display substrate according to claim 21, wherein, The reset sub-circuit includes a reset transistor; the display substrate further includes a first source / drain metal layer and a second source / drain metal layer located between the third gate metal layer and the transparent lead layer, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate. The transparent lead layer includes a sixteenth transition electrode; the first source / drain metal layer includes a twelfth and a fourteenth transition electrode; the second source / drain metal layer includes a thirteenth and a fifteenth transition electrode; the transparent lead layer includes an initialization voltage line; the initialization voltage line is connected to the thirteenth transition electrode via a via; the thirteenth transition electrode is connected to the twelfth transition electrode via a via; the first electrode of the light-emitting device is connected to the sixteenth transition electrode via a via; the sixteenth transition electrode is connected to the fifteenth transition electrode via a via; the fifteenth transition electrode is connected to the fourteenth transition electrode via a via; and the fourteenth transition electrode is connected to the second electrode of the reset transistor via a via.

30. The display substrate according to any one of claims 1 to 12, wherein, The first display area has multiple first sub-pixels arranged in multiple rows and columns. Multiple first sub-pixels in the same column are arranged along a first direction, and multiple first sub-pixels in the same row are arranged along a second direction. Each pair of adjacent rows of first sub-pixels forms a repeating group, and the two rows of first sub-pixels in the repeating group are arranged alternately. The display substrate further includes: Multiple light emission control lines are used to provide the light emission control signal. Each light emission control line corresponds to a repeating group. Different light emission control lines correspond to different repeating groups. Each light emission control line is connected to the first pixel circuit of each first sub-pixel in the corresponding repeating group. Multiple first scan lines are used to provide the first scan signal. Each first scan line corresponds to one repeating group. Different first scan lines correspond to different repeating groups. Each first scan line is connected to the first pixel circuit of each first sub-pixel in the corresponding repeating group. Multiple second scan lines are used to provide the second scan signal. Each second scan line corresponds to one of the repeating groups. Different second scan lines correspond to different repeating groups. Each second scan line is connected to the first pixel circuit of each first sub-pixel in the corresponding repeating group. Multiple initialization voltage lines are used to provide the initial voltage signal. Each initialization voltage line corresponds to a repeating group. Different initialization voltage lines correspond to different repeating groups. Each initialization voltage line is connected to the first pixel circuit of each first sub-pixel in the corresponding repeating group. Multiple data lines are used to provide the data voltage signal. Each data line corresponds to a column of the repeating group. Different data lines correspond to the first sub-pixel of different columns. Each data line is connected to the first pixel circuit of each first sub-pixel in the corresponding column.

31. The display substrate according to claim 30, wherein, In the same repeating group, one row of sub-pixels consists of a first color sub-pixel, and another row of sub-pixels includes alternating second and third color sub-pixels. The light-emitting control line includes: a control line body and a control line lead-out portion, wherein the control line body extends along a second direction and the control line lead-out portion extends along a first direction; In the same repeating group, the first pixel circuit in the first sub-pixel of one row is connected to the main body of the control line, and the first pixel circuit in the first sub-pixel of another row is connected to the lead-out portion of the control line.

32. The display substrate according to claim 30, wherein, The first scan line includes a scan line body and a scan line lead-out portion. The scan line body includes a plurality of scan line segments arranged sequentially in the second direction. The plurality of scan line segments are connected sequentially to form a curved structure in the scan line body. The scan line lead-out portion extends along the first direction. In the same repeating group, the first pixel circuit in the first sub-pixel of one row is connected to the main body of the scan line, and the first pixel circuit in the first sub-pixel of another row is connected to the extension of the scan line.

33. The display substrate according to any one of claims 1 to 12, wherein, The display substrate further includes: A plurality of second sub-pixels are disposed on the substrate and located in the second display area, at least one of the plurality of second sub-pixels including: a second pixel circuit and a second light-emitting device, the second pixel circuit being configured to provide a driving current to the second light-emitting device.

34. A display device comprising the display substrate as described in any one of claims 1 to 33.

35. The display device according to claim 34, wherein, The display device further includes at least one image sensor, the orthographic projection of which is located on the substrate in the first display area.

Images