Zynq-based near-sensing radar echo data and state information acquisition system

Abstract

The application discloses a near-sensing radar echo data and state information acquisition system based on Zynq, which comprises a data acquisition module, a DDR read-write controller module, a parameter analysis module, a data transmission module and a sensor interface module on the PL end of the Zynq chip, and a serial port module and a network port module on the PS end; the system combines multiple integrated circuits with specific functions on a single chip, has the characteristics of IP multiplexing and software and hardware collaborative design, and carries the hardware design of a sensor group and a CX8142 chip, so that the acquisition of radar echo data and state information is realized. The application has certain universality and generality, can realize real-time monitoring of system temperature, voltage and attitude information for a radar system using a Zynq-7000 series chip, can also collect and store echo signals, and finally can transmit the collected echo signals and state signals to an upper computer through a network port and a serial port for analysis and verification.

Description

Technical Field

[0001] This invention relates to a data acquisition system, specifically a Zynq-based system for acquiring near-sensing radar echo data and status information. Background Technology

[0002] With the continuous development of radar technology and integrated circuit processes, the size of radar is constantly decreasing, while its data processing capabilities are continuously improving. Therefore, the requirements for the real-time performance, stability, and transmission rate of data acquisition are also constantly increasing. In practical applications, in order to accurately extract information such as distance, speed, and angle from radar signals, a high-speed acquisition system is needed to precisely acquire the echo signals from the radio frequency front-end, ensuring that the signal processing system can resolve the target information.

[0003] Traditional radar hardware design schemes use an FPGA + processor architecture. Although this architecture can meet the requirements of sampling rate and transmission rate, the PCB design has relatively more interconnections, a relatively larger area, and is relatively complex and expensive. Summary of the Invention

[0004] The purpose of this invention is to provide a Zynq-based system for acquiring near-sensing radar echo data and status information.

[0005] The technical solution to achieve the purpose of this invention is: a near-sensing radar echo data and status information acquisition system based on Zynq, including a data acquisition module, a DDR read / write control module, a data transmission module, a parameter parsing module, and a sensor interface module on the PL end of the Zynq chip, as well as a serial port module and a network port module on the PS end of the software.

[0006] The data acquisition module is used for configuring the RF direct acquisition transceiver chip CX8142, converting high-speed interface data from serial to parallel, and buffering, splicing, and cross-clock domain processing of echo signals.

[0007] The DDR read / write control module is used to receive the data output by the data acquisition module, write it into the PL terminal DDR for storage, and finally send the stored data to the data transmission module according to the AXI4_Stream protocol.

[0008] The data transmission module is used for data interaction between the PL end and the PS end, realizing the transmission of data stored in the DDR of the PL end to the DDR of the PS end, as well as the reception of commands issued by the PS end.

[0009] The parameter parsing module is used to receive and parse commands sent from the PS terminal, control the working mode of the RF direct acquisition transceiver chip, and control the data storage capacity of the DDR read / write control module.

[0010] The sensor interface module is used to read and write control of each sensor in the sensor group, configure its working mode and receive status information.

[0011] The serial port module is used to interact with the host computer, including uploading data collected by the sensor and receiving commands issued by the host computer.

[0012] The network port module is used to interact with the host computer and upload the echo signal collected by the CX8142 chip.

[0013] Furthermore, the data acquisition module includes:

[0014] The intermediate frequency parameter configuration module is used to configure the working mode, sampling rate and intermediate frequency of the CX8142 RF direct acquisition transceiver chip. Its working mode is controlled by the parameter parsing module.

[0015] The JESD204B module is used for receiving DDC channel data under high-speed SERDES technology, as well as for serial-to-parallel conversion of echo data.

[0016] The asynchronous FIFO module is used for converting the echo data bit width and processing data across clock domains.

[0017] Furthermore, the DDR read / write control module includes:

[0018] The read control module is used to receive data output by the MIG core and return it to the downstream module, as well as to interact with the status signals of the arbitration module, and finally give the DDR read command and read address.

[0019] The write control module is used to receive data, starting address, and data size from the upstream module, and is responsible for interacting with the status signals of the arbitration module. Finally, it provides the DDR write command, write address, and data.

[0020] The read / write arbitration module is used to avoid conflicts caused by simultaneous read and write operations. The arbitration priority is write first, then read.

[0021] The MIG module is used to connect directly to the DDR chip and perform read and write operations on the DDR chip.

[0022] Furthermore, the data transmission module includes:

[0023] AXI_FIFO module: used for receiving and storing the output data of the DDR read / write control module, solving the cross-clock domain processing of data from the PL end to the PS end;

[0024] AXI_DMA module: Used for DMA data transfer between PL and PS terminals, with the PS terminal controlling the direction, size, and storage space of the data transfer.

[0025] Furthermore, the parameter parsing module is used to receive and parse commands sent from the PS side, control the working mode of the CX8142 chip, and determine the amount of data stored by the DDR read / write control module.

[0026] Furthermore, the sensor interface module instantiates different IP cores based on different sensor interfaces to control the reading and writing of sensors, configure the working mode of the sensor chip, and receive status information.

[0027] Furthermore, the network port module is used to upload echo and reference data to the host computer for data analysis and verification.

[0028] Compared with the prior art, the significant advantages of this invention are: (1) This invention designs a radar echo data and status information acquisition system based on a Zynq chip with an all-programmable multi-processor SoC architecture as the main control chip. This system utilizes Zynq's unique high-speed internal bus architecture to reduce the PCB interconnections between chips and realize PL (Programmable Logic) and PS (Processor) (1) High-speed communication between the System) realizes the collaborative work of software and hardware to meet the real-time requirements of the acquisition system and at the same time, real-time monitoring and early warning of the system operating environment, ensuring the efficient and stable operation of the system; (2) This invention utilizes the characteristics of the collaborative work of software and hardware of the Zynq chip SoC architecture to realize the system is configurable and reconfigurable, that is, it communicates with the host computer through the network port and serial port of the PS, so that different parameters can be sent on the host computer, and then the various modules of the PL end can be configured to control the system operation, etc.; (3) This invention utilizes the IP reuse characteristics of the Zynq chip to realize multiple different low-speed interfaces such as SPI, UART, I2C interface, and then adapts to various interface sensor chips to realize real-time monitoring and early warning of the radar system operating environment; (4) This invention uses the domestic RF direct acquisition transceiver chip CX8142, which integrates two DUC and two DDC channels to realize signal transmission and reception. Attached Figure Description

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0030] Figure 1 This is a structural diagram of the Zynq-based near-sensing radar echo data and status information acquisition system of the present invention.

[0031] Figure 2 yes Figure 1 The diagram shows the structural block diagram of the data acquisition module in the system shown.

[0032] Figure 3 yes Figure 1The diagram shows the block diagram of DDR read / write control in the system shown.

[0033] Figure 4 yes Figure 1 The diagram shows the structural block diagram of the data transmission module in the system.

[0034] Figure 5 yes Figure 1 The diagram shows the structural block diagram of the sensor group module in the system. Detailed Implementation

[0035] This invention proposes a Zynq-based near-sensing radar echo data and status information acquisition system. It leverages the advantages of Xilinx's first-generation fully programmable SoC architecture, the Zynq-7000 series chips—a system or product formed by combining multiple integrated circuits with specific functions on a single chip. This includes a complete hardware system and its embedded software, featuring IP reuse and hardware-software co-design characteristics. The system incorporates a sensor array and the CX8142 chip to acquire radar echo data and status information. The system includes a data acquisition module, a DDR read / write controller module, a parameter parsing module, a data transmission module, and a sensor interface module on the Zynq chip's PL side; and serial port and Ethernet modules on the PS side. This invention has a certain degree of versatility and universality, enabling real-time monitoring of system temperature, voltage, and attitude status information of radar systems using the Zynq-7000 series chips. It can also acquire and store echo signals, and finally transmit the acquired echo and status signals to a host computer for analysis and verification via Ethernet and serial ports.

[0036] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0037] Combination Figure 1 This embodiment of a ZYNQ-based near-sensing radar echo data and status information acquisition system includes a hardware PL terminal data acquisition module, a DDR read / write control module, a parameter parsing module, a data transmission module, and a sensor interface module; and a software PS terminal serial port module and a network port module.

[0038] The data acquisition module is used for configuring the CX8142 RF direct acquisition transceiver chip, converting high-speed interface data from serial to parallel, and splicing, buffering, and cross-clock domain processing of echo and reference signals.

[0039] The DDR read / write control module is used to receive data from the data acquisition module, write the data into the PL's DDR3 for storage, and convert the data transmission format to AXI4_STREAM format.

[0040] The parameter parsing module is used to receive commands from the PS terminal, control the working mode of the RF direct acquisition transceiver chip, and determine the data capacity of the DDR storage.

[0041] The data transmission module is used for data interaction between the PL and PS ends, realizing the transmission of data from the DDR of the PL end to the DDR of the PS end for storage, and receiving commands from the PS end;

[0042] The sensor interface module is used to read and write the sensor chip, configure its working mode, and read sensor data.

[0043] The serial port module is used to communicate with the host computer, upload data collected by the sensor, and receive commands issued by the host computer.

[0044] The network port module is used to upload echo and reference data to the host computer for data analysis and verification;

[0045] Combination Figure 2 The data acquisition module includes:

[0046] The intermediate frequency parameter configuration module is used to configure the CX8142's operating mode, sampling rate, and intermediate frequency. Its operating mode is controlled by the parameter parsing module.

[0047] The JESD204B module is used for receiving DDC channel data under high-speed SERDES technology, as well as for serial-to-parallel conversion of echo data.

[0048] The asynchronous FIFO module is used for the conversion of echo and reference data bit width, as well as cross-clock domain processing between the data acquisition clock and the DDR user clock;

[0049] The data acquisition module implements the following specific functions:

[0050] First, the intermediate frequency parameter configuration module parses the WORK_MODE parameter to select the operating mode of the CX8142 RF direct acquisition transceiver chip, and then writes the configuration information via the SPI protocol. Next, the JBSD204B module performs serial-to-parallel conversion on the serial data output from the CX8142, resulting in two 16-bit parallel echo data channels (I and Q). The JBSD204B module is implemented by instantiating the Xilinx JBSD204B IP core and operating in mode 0. Finally, the asynchronous FIFO module concatenates the echo I / Q data into a 32-bit data reception. When the data write depth is 1024, 128 256-bit data segments are read and output simultaneously using the DDR user clock, addressing the DDR read / write bit width issue and cross-clock domain issues.

[0051] Combination Figure 3 The DDR read / write control module includes:

[0052] The read control module is used to receive data output by the MIG core and return it to the downstream module, as well as to interact with the status signals of the arbitration module, and finally give the DDR read command and read address.

[0053] The write control module is used to receive data, starting address, and data size from the upstream module, and is responsible for interacting with the status signals of the arbitration module. Finally, it provides the DDR write command, write address, and data.

[0054] The read-write arbitration module is used to avoid conflicts caused by simultaneous read and write operations. The arbitration priority is write first, then read.

[0055] The MIG module is used to directly connect to the DDR chip for read and write operations. The specific functions of the DDR read / write control module are as follows:

[0056] The write control module receives output data from the data acquisition module, first initiating a write request to the read-write arbitration module. Upon receiving an acknowledgment signal, it outputs the write address, write command, and write data to the MIG core. When the amount of data written equals the DATA_SIZE parameter, the write operation stops and the read operation begins. Until the downstream data transmission module TREADY goes high, the read control module initiates a read request to the read-write arbitration module. Upon receiving a read acknowledgment signal, it outputs the read address and read command to the MIG core. Finally, the MIG core outputs the stored echo signal and sends it to the downstream module according to the AXI4_Stream protocol format. The MIG core is implemented by instantiating the memory interface generator IP core provided by Xilinx.

[0057] Combination Figure 4 The data transmission module includes:

[0058] AXI_FIFO module: used for receiving and storing the output data of the DDR read / write control module, solving the cross-clock domain processing of data from the PL end to the PS end;

[0059] AXI_DMA module: used for data transfer between the PL and PS ends, controlling the direction, size, and storage space of data transmission through the PS end;

[0060] The specific functions of the data transmission module are as follows:

[0061] The AXI_FIFO module caches upstream module output data by instantiating the AXI_STRAM DATA FIFO IP core. When the data volume reaches 1024 256-bit wide bytes, the DMA module initiates a DMA transfer, reading data from the AXI_FIFO module and transferring it to the PS-side DDR. The data size and storage space are controlled by the PS-side via the AXI_GP interface. The AXI_DMA module is also used to transfer PS data to the PL. When the host computer sends parameters to the PS-side via the serial port module, the PS-side will initiate a DMA transfer to transmit the data to the PL's parameter parsing module.

[0062] Combination Figure 5 Sensor interface module: used to read and write sensor chips, configure their working modes, and read sensor data;

[0063] The specific functions of the sensor interface module are as follows:

[0064] Different low-speed interface IP cores can be instantiated based on the sensor chip connected to the Zynq chip. The PS end controls the low-speed interface IP cores through the AXI_GP interface, thereby configuring the working mode of the sensor chip and reading data.

Claims

1. A Zynq-based near-sensing radar echo data and status information acquisition system, characterized in that, It includes the data acquisition module, DDR read / write control module, data transmission module, parameter parsing module, and sensor interface module on the Zynq chip PL side, as well as the serial port module and network port module on the software PS side; The data acquisition module is used for configuring the RF direct acquisition transceiver chip CX8142, converting high-speed interface data from serial to parallel, and buffering, splicing, and cross-clock domain processing of echo signals. The DDR read / write control module is used to receive the data output by the data acquisition module, write it into the PL terminal DDR for storage, and finally send the stored data to the data transmission module according to the AXI4_Stream protocol. The data transmission module is used for data interaction between the PL end and the PS end, realizing the transmission of data stored in the DDR of the PL end to the DDR of the PS end, as well as the reception of commands issued by the PS end. The parameter parsing module is used to receive and parse commands sent from the PS terminal, control the working mode of the RF direct acquisition transceiver chip, and control the data storage capacity of the DDR read / write control module. The sensor interface module is used to read and write control of each sensor in the sensor group, configure its working mode and receive status information. The serial port module is used to interact with the host computer, including uploading data collected by the sensor and receiving commands issued by the host computer. The network port module is used to interact with the host computer and upload the echo signal collected by the CX8142 chip.

2. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 1, characterized in that, The data acquisition module includes: The intermediate frequency parameter configuration module is used to configure the CX8142's operating mode, sampling rate, and intermediate frequency. Its operating mode is controlled by the parameter parsing module. The JESD204B module is used for receiving DAC channel data under high-speed SERDES technology, as well as for serial-to-parallel conversion of echo data. The asynchronous FIFO module is used for converting the echo data bit width and processing data across clock domains.

3. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 2, characterized in that, The intermediate frequency parameter configuration module parses the WORK_MODE parameter to select the working mode of the CX8142 RF direct acquisition transceiver chip and writes the configuration information via the SPI protocol; the JBSD204B module performs serial-to-parallel conversion on the serial data output by the CX8142 to obtain two 16-bit parallel echo data channels (I and Q); the asynchronous FIFO module concatenates the echo I / Q data into 32-bit data for reception, and when the data write depth is 1024, it reads 128 256-bit data at once and outputs them through the DDR user clock.

4. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 1, characterized in that, The DDR read / write control module includes: The read control module is used to receive data output by the MIG core and return it to the downstream module, as well as to interact with the status signals of the arbitration module, and finally give the DDR read command and read address. The write control module is used to receive data, starting address, and data size from the upstream module, and is responsible for interacting with the status signals of the arbitration module. Finally, it provides the DDR write command, write address, and data. The read-write arbitration module is used to avoid conflicts caused by simultaneous read and write operations. The arbitration priority is write first, then read. The MIG module is used to connect directly to the DDR chip and perform read and write operations on the DDR chip.

5. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 4, characterized in that, The write control module receives output data from the data acquisition module, first initiates a write request to the read-write arbitration module, and after receiving the response signal, starts outputting the write address, write command and write data to the MIG core; when the amount of data written is equal to the size of the DATA_SIZE parameter, the write operation stops and the read operation begins. When the downstream data transmission module TREADY goes high, the read control module initiates a read request to the read-write arbitration module. After receiving the read response signal, it starts to output the read address and read command to the MIG core. Finally, the MIG core outputs the stored echo signal and sends it to the downstream module in accordance with the AXI4_Stream protocol format.

6. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 1, characterized in that, The data transmission module includes: AXI_FIFO module: used for receiving and storing the output data of the DDR read / write control module, solving the cross-clock domain processing of data from the PL end to the PS end; AXI_DMA module: Used for DMA data transfer between PL and PS terminals, with the PS terminal controlling the direction, size, and storage space of data transfer.

7. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 6, characterized in that, The AXI_FIFO module caches upstream module output data by instantiating the AXI_STRAM DATA FIFO IP core. When the data volume reaches 1024 256-bit wide data points, the DMA module initiates a DMA transfer to read and transfer data from the AXI_FIFO module to the PS-side DDR. The data size and storage space are controlled by the PS-side through the AXI_GP interface. The AXI_DMA module is used to transfer PS data to the PL. When the host computer sends parameters to the PS-side through the serial port module, the PS-side will initiate a DMA transfer to transmit the data to the PL's parameter parsing module.

8. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 1, characterized in that, The parameter parsing module is used to receive and parse commands sent from the PS terminal, control the working mode of the CX8142 chip, and determine the amount of data stored by the DDR read / write control module.

9. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 1, characterized in that, The sensor interface module instantiates different IP cores according to different sensor interfaces to control the reading and writing of sensors, configure the working mode of sensor chips, and receive status information.

10. The Zynq-based near-sensing radar echo data and status information acquisition system according to claim 1, characterized in that, The network port module is used to upload echo and reference data to the host computer for data analysis and verification.

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