Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a display area, a binding area connected with the display area, the display area comprising a plurality of data signal lines extending along a second direction, a plurality of first transfer connection electrodes extending along a first direction, a plurality of third transfer connection electrodes extending along the second direction, and a plurality of sub-pixels arranged in an array; at least a part of the first transfer connection electrodes are connected with the plurality of data signal lines respectively, and are connected with at least a part of the third transfer connection electrodes respectively, one end of the third transfer connection electrode connected with the first transfer connection electrode is connected with the binding area; the plurality of data signal lines have different lengths along the second direction; the plurality of sub-pixels form a plurality of pixels arranged in an array, one pixel comprises at least three adjacent sub-pixels, and the arrangement modes of the plurality of first transfer connection electrodes and the plurality of third transfer connection electrodes in two pixels are consistent. The present disclosure can improve the phenomenon of uneven light emission caused by inconsistent anode end differences.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] With the rapid development of display technology, irregularly shaped display devices have gradually gained market share. The emergence of irregularly shaped display devices has broken through the limitations of the single rectangular structure of display devices, making their applications increasingly widespread. For example, irregularly shaped display devices are currently widely used in fields such as smart wearables and smart vehicles. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate, including a display area and a bonding area connected to the display area. The display area includes multiple data signal lines extending along a second direction, multiple first transition connection electrodes extending along a first direction, multiple third transition connection electrodes extending along the second direction, and multiple sub-pixels arranged in an array. The multiple data signal lines are respectively connected to multiple columns of sub-pixels, and the data signal lines, the first transition connection electrodes, and the third transition connection electrodes are respectively disposed on three conductive layers.

[0005] At least a portion of the first adapter connection electrodes are electrically connected to the plurality of data signal lines respectively, and are also electrically connected to at least a portion of the third adapter connection electrodes respectively. One end of the third adapter connection electrode connected to the at least a portion of the first adapter connection electrodes is electrically connected to the bonding area. In the display area, the lengths of the plurality of data signal lines along the second direction are not exactly the same.

[0006] The plurality of sub-pixels form a plurality of pixels arranged in an array, and each pixel includes at least three adjacent sub-pixels. The arrangement of the plurality of first transition connection electrodes and the plurality of third transition connection electrodes located in two pixels is consistent.

[0007] In an exemplary embodiment, the display area includes a first display area and a second display area. A plurality of first transition connection electrodes located in the second display area penetrate the second display area along a first direction, and at least a portion of the first transition connection electrodes located in the second display area are electrically connected to the plurality of data signal lines respectively. A plurality of first transition connection electrodes located in the first display area do not penetrate the first display area of ​​the display substrate along the first direction. At least a portion of third transition connection electrodes are electrically connected to a plurality of first transition connection electrodes located in the second display area.

[0008] The arrangement of the first adapter electrode, the third adapter electrode, and the data signal line in the pixels located in the first display area and the second display area is the same.

[0009] In an exemplary embodiment, the display substrate further includes a plurality of second initial signal lines extending along a second direction, a plurality of second transition connection electrodes extending along a first direction, and a plurality of fourth transition connection electrodes extending along a second direction. The second initial signal lines are disposed on the same layer as the plurality of data signal lines, the plurality of second transition connection electrodes are disposed on the same layer as the plurality of first transition connection electrodes, and the plurality of fourth transition connection electrodes are disposed on the same layer as the plurality of third transition connection electrodes.

[0010] The plurality of second transition connection electrodes located in the second display area penetrate the second display area of ​​the display substrate along the first direction and are electrically connected to the plurality of second initial signal lines respectively. The plurality of second transition connection electrodes located in the first display area do not penetrate the first display area of ​​the display substrate along the first direction. At least a portion of the fourth transition connection electrodes are electrically connected to the plurality of second transition connection electrodes located in the second display area respectively.

[0011] In an exemplary embodiment, a pixel includes three sub-pixels. Three columns of sub-pixels and three data signal lines are arranged in the same pixel space. The three columns of sub-pixels are respectively connected to the three data signal lines. Adjacent columns of pixels share a second initial signal line, which is located between adjacent columns of pixels. Twenty third transition connection electrodes and one fourth transition connection electrode are arranged in the two columns of pixels sharing the second initial signal line. Each column of pixels has ten first transition connection electrodes, and one second transition connection electrode is located between the two columns of pixels.

[0012] Within the same row of pixel space, there are 6 second transition connection electrodes and 1 second transition connection electrode.

[0013] In an exemplary embodiment, a pixel includes three sub-pixels. In the same column pixel space, there are three columns of sub-pixels, three data signal lines, and nine third transition connection electrodes. The three columns of sub-pixels are respectively connected to the three data signal lines. In the same row pixel space, there are six first transition connection electrodes.

[0014] In an exemplary embodiment, a pixel includes three sub-pixels. In the same column pixel space, there are three columns of sub-pixels, three data signal lines, and three third transition connection electrodes. The three columns of sub-pixels are respectively connected to the three data signal lines. In the same row pixel space, there are two first transition connection electrodes.

[0015] In an exemplary embodiment, the sub-pixel includes a first transistor to a fifth transistor and a storage capacitor. On a plane parallel to the display substrate, the second transistor, the first transistor, the third transistor, the fourth transistor, and the fifth transistor are arranged along a second direction. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the third transistor on the substrate.

[0016] Within the same pixel, two adjacent sub-pixels are symmetrically arranged with respect to a first center line, which is the center line extending from the two adjacent sub-pixels along a second direction.

[0017] In an exemplary embodiment, the same column of sub-pixels includes multiple sub-pixel groups, each sub-pixel group includes two adjacent sub-pixels, and the two sub-pixels in the same sub-pixel group share a fifth transistor.

[0018] In an exemplary embodiment, at least one sub-pixel includes a pixel driving circuit, which includes a plurality of oxide transistors and a storage capacitor; in a plane perpendicular to the display substrate, the display substrate includes a substrate and a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate;

[0019] The semiconductor layer includes: the active layer of the plurality of oxide transistors;

[0020] The first conductive layer includes: the control electrode of the plurality of oxide transistors and the first electrode of the storage capacitor;

[0021] The second conductive layer includes: the second electrode of the storage capacitor;

[0022] The third conductive layer includes: the plurality of data signal lines and the first and second electrodes of the plurality of oxide transistors;

[0023] The fourth conductive layer includes: the plurality of first transition connection electrodes;

[0024] The fifth conductive layer includes the plurality of third transition connection electrodes.

[0025] In an exemplary embodiment, the third conductive layer further includes: a plurality of second initial signal lines extending along a second direction; two adjacent columns of pixels share a second initial signal line, and a plurality of data signal lines in the two columns of pixels sharing a second initial signal line are symmetrical with respect to the second initial signal line;

[0026] The fourth conductive layer further includes: a plurality of second transition connection electrodes extending along a first direction, wherein the plurality of second transition connection electrodes located in the second display area are respectively electrically connected to the plurality of second initial signal lines;

[0027] The fifth conductive layer further includes: a plurality of fourth transition connection electrodes extending along the second direction; the plurality of fourth transition connection electrodes are respectively electrically connected to the plurality of second transition connection electrodes located in the second display area.

[0028] In an exemplary embodiment, the first conductive layer further includes: a plurality of first power connection lines extending along a first direction; in the same column of sub-pixels, there are a plurality of sub-pixel groups, each sub-pixel group includes two adjacent sub-pixels, in the same sub-pixel group, the two sub-pixels share a first power connection line, and the two sub-pixels in the same sub-pixel group are symmetrical with respect to the first power connection line;

[0029] The third conductive layer further includes: a first power line extending along the second direction; the first power line is electrically connected to the first power connection line through a via.

[0030] In an exemplary embodiment, the display substrate is heart-shaped, the bonding area is located on one side of the display area, and the first display area, the second display area, and the bonding area are arranged sequentially along a second direction.

[0031] In an exemplary embodiment, at least a portion of the first adapter connection electrodes are electrically connected to the plurality of data signal lines through a plurality of first adapter vias, and at least a portion of the third adapter connection electrodes are electrically connected to the at least a portion of the first adapter connection electrodes through a plurality of third adapter vias. The arrangement direction of the plurality of first adapter vias forms a first angle with the centerline of the display substrate extending along the second direction, and the arrangement direction of the plurality of third adapter vias forms a second angle with the centerline of the display substrate extending along the second direction.

[0032] In an exemplary embodiment, the first included angle is 30 to 60 degrees, and the second included angle is 15 to 45 degrees.

[0033] In an exemplary embodiment, the arrangement direction of the plurality of first transition vias is symmetrical with respect to the centerline extending along the second direction of the display substrate, and the arrangement direction of the plurality of third transition vias is symmetrical with respect to the centerline extending along the second direction of the display substrate.

[0034] In an exemplary embodiment, in the display area located on one side of the centerline extending along the second direction of the display substrate, a plurality of first transition vias are arranged in at least two directions, and the at least two arrangement directions are parallel to each other, and the connecting lines of the plurality of first transition vias in the at least two arrangement directions are arranged along the second direction; a plurality of third transition vias are arranged in at least two directions, and the at least two arrangement directions are parallel to each other, and the connecting lines of the plurality of third transition vias in the at least two arrangement directions are arranged along the second direction.

[0035] In an exemplary embodiment, the fourth conductive layer further includes anode connection electrodes that are electrically connected to a plurality of sub-pixels respectively, wherein the orthographic projections of the first and third transfer connection electrodes on the substrate do not overlap with the orthographic projections of the plurality of anode connection electrodes on the substrate.

[0036] In an exemplary embodiment, the display substrate further includes an anode conductive layer, which includes a plurality of anodes, and the plurality of anodes are respectively connected to the plurality of anode connection electrodes; the orthographic projection of the plurality of anodes in the same pixel on the substrate and the orthographic projection of the plurality of first transition connection electrodes and the plurality of third transition connection electrodes on the substrate have a first overlapping region, and the plurality of pixels correspond to a plurality of first overlapping regions, and the areas of the plurality of first overlapping regions are the same.

[0037] In an exemplary embodiment, the dimension of the bonding area along the first direction is smaller than the dimension of the display area along the first direction, and the plurality of third adapter connection electrodes include two parts: one extending to the bonding area and the other not extending to the bonding area. The plurality of third adapter connection electrodes extending to the bonding area are electrically connected to the plurality of first adapter connection electrodes located in the second display area.

[0038] This disclosure also provides a display device, including the display substrate described in any of the foregoing embodiments.

[0039] The display substrate and display device provided in this disclosure include a display area in the display substrate comprising multiple data signal lines, multiple first transition connection electrodes, multiple third transition connection electrodes, and multiple sub-pixels arranged in an array. At least a portion of the first transition connection electrodes are electrically connected to the multiple data signal lines and to at least a portion of the third transition connection electrodes. One end of the third transition connection electrode connected to the at least a portion of the first transition connection electrodes is electrically connected to a bonding area. In the display area, the lengths of the multiple data signal lines along a second direction are not entirely the same. The multiple sub-pixels form multiple pixels arranged in an array, and each pixel includes at least three adjacent sub-pixels. The arrangement of the multiple first transition connection electrodes and the multiple third transition connection electrodes in two pixels is consistent. The display substrate provided in this disclosure, with the consistent arrangement of the multiple first transition connection electrodes and the multiple third transition connection electrodes in two pixels, ensures consistent anode step differences in the multiple pixels, effectively avoiding uneven light emission. The display substrate provided in this embodiment has multiple data signal lines in the display area with different lengths along the second direction. This can be applied to irregularly shaped display substrates and can avoid the phenomenon of uneven light emission caused by inconsistent anode polarity in irregularly shaped display substrates.

[0040] Of course, implementing any product or method of this disclosure does not necessarily require achieving all the advantages described above simultaneously. Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description and embodiments, or may be learned by practicing this disclosure. The objects and other advantages of embodiments of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings.

[0041] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0042] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0043] Figure 1 The diagram shown is a structural schematic of a display device;

[0044] Figure 2 The diagram shown is a schematic representation of a planar structure of a display substrate.

[0045] Figure 3 The diagram shown is a cross-sectional view of a display substrate.

[0046] Figure 4 The diagram shown is an equivalent circuit diagram of a pixel driving circuit.

[0047] Figure 5 The figure shown is a schematic diagram of a planar structure of a display substrate provided in an embodiment of this disclosure;

[0048] Figure 6a The diagram shown is a planar structure schematic of a display substrate provided in an exemplary embodiment of this disclosure;

[0049] Figure 6b The diagram shown is a planar structure schematic of a display substrate provided in an exemplary embodiment of this disclosure;

[0050] Figure 6c The diagram shown is a planar structure schematic of a display substrate provided in an exemplary embodiment of this disclosure;

[0051] Figure 7 The diagram shown is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0052] Figure 8a The diagram shown is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0053] Figure 8b The diagram shown is a schematic diagram of the first conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0054] Figure 9a The diagram shown is a schematic diagram of a display substrate after the second conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0055] Figure 9b The diagram shown is a schematic diagram of the second conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0056] Figure 10 The diagram shown is a schematic diagram of a display substrate after the fourth insulating layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0057] Figure 11a The diagram shown is a schematic diagram of a display substrate after the formation of the third conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0058] Figure 11b The diagram shown is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0059] Figure 12a The diagram shown is a schematic diagram of a display substrate after the formation of a fifth insulating layer and a first planarization layer pattern, according to an exemplary embodiment of the present disclosure.

[0060] Figure 12bThe diagram shown is a schematic diagram of a display substrate after the formation of a fifth insulating layer and a first planarization layer pattern, according to an exemplary embodiment of the present disclosure.

[0061] Figure 13a The diagram shown is a schematic diagram of a display substrate after the fourth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0062] Figure 13b The diagram shown is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0063] Figure 13c The diagram shown is a schematic diagram of the fourth conductive layer pattern in a display substrate provided in an exemplary embodiment of this disclosure.

[0064] Figure 14 The diagram shown is a schematic diagram of a display substrate after the formation of a sixth insulating layer and a second planarization layer pattern, according to an exemplary embodiment of the present disclosure.

[0065] Figure 15a The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0066] Figure 15b The diagram shown is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0067] Figure 15c The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0068] Figure 15d The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0069] Figure 16 The diagram shown is a schematic diagram of a display substrate after a third planarization layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0070] Figure 17a The diagram shown is a schematic diagram of a display substrate after an anode conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0071] Figure 17b The diagram shown is a schematic diagram of the anode conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0072] Figure 18 The diagram shown is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0073] Figure 19The figure shown is a planar schematic diagram of a display substrate provided in an exemplary embodiment of this disclosure;

[0074] Figure 20 The diagram shown is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0075] Figure 21 The figure shown is a planar schematic diagram of a display substrate provided in an exemplary embodiment of this disclosure;

[0076] Figure 22 The diagram shown is a schematic representation of the border area of ​​a display substrate provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0077] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0078] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0079] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0080] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0081] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0082] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0083] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0084] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0085] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0086] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0087] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0088] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0089] Figure 1The diagram illustrates the structure of a display device. The display substrate may include a timing controller, a data signal driver, a scan signal driver, a light-emitting signal driver, and a pixel array. The timing controller is connected to the data signal driver, scan signal driver, and light-emitting signal driver. The data signal driver is connected to multiple data signal lines (D1 to Dn), the scan signal driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting signal driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, clock signals, scan start signals, etc., of specifications suitable for the scan signal driver to the scan signal driver, and clock signals, transmit stop signals, etc., of specifications suitable for the light-emitting signal driver to the light-emitting signal driver. The data signal driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. The light emission signal driver can generate transmit signals to be provided to light emission signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0090] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0091] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0092] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels in an OLED display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0093] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the driving force of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first and third encapsulation layers 401 and 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first and third encapsulation layers 401 and 403, ensuring that external moisture cannot enter the light-emitting structure layer 103.

[0094] In an exemplary embodiment, the organic light-emitting layer 303 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole block layers of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0095] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 4 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 4As shown, the pixel driving circuit may include 5 transistors (first transistor T1 to fifth transistor T5) and 1 storage capacitor C. The pixel driving circuit may be connected to 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, first initial signal line INIT1, second initial signal line INIT2, first power line VDD and second power line VSS).

[0096] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second terminal of the first transistor T1, the second terminal of the second transistor T2, the control terminal of the third transistor T3, and the first plate of the storage capacitor C. The second node N2 is connected to the first terminal of the third transistor T3 and the second terminal of the fifth transistor T5. The third node N3 is connected to the second terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second plate of the storage capacitor C.

[0097] In an exemplary embodiment, the first plate of the storage capacitor C is connected to the first node N1, and the second plate of the storage capacitor C is connected to the third node N3, that is, the first plate of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0098] The control electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the data signal line D, and the second electrode of the first transistor is connected to the first node N1. When a conduction-level scan signal is applied to the first scan signal line S1, the first transistor T1 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0099] The control electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is connected to the first node N1. When a conduction-level scan signal is applied to the second scan signal line S2, the second transistor T2 transmits the initial voltage of the second initial signal line INIT2 to the control electrode of the third transistor T3, thereby initializing the charge of the control electrode of the third transistor T3.

[0100] The control electrode of the third transistor T3 is connected to the first node N1, meaning the control electrode of the third transistor T3 is connected to the first plate of the storage capacitor C. The first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode. The control electrode of the fourth transistor T4 is connected to the third scan signal line S3. The first electrode of the fourth transistor T4 is connected to the first initial signal line INIT1, and the second electrode of the fourth transistor T4 is connected to the third node N3. When the on-level scan signal is applied to the third scan signal line S3, the fourth transistor T4 transmits the initial voltage of the first initial signal line INIT1 to the first electrode of the light-emitting device, thereby initializing or releasing the accumulated charge in the first electrode of the light-emitting device.

[0101] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The fifth transistor T5 can be called a light-emitting transistor. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 emits light by forming a drive current path between the first power supply line VDD and the second power supply line VSS.

[0102] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

[0103] In an exemplary embodiment, the first transistor T1 to the fifth transistor T5 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the fifth transistor T5 may include both P-type and N-type transistors.

[0104] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the first initial signal line INIT1 can extend in the horizontal direction, while the second power line VSS, the first power line VDD, the second initial signal line INIT2, and the data signal line D can extend in the vertical direction.

[0105] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0106] Due to the diverse shapes of customized display substrates and the need for minimal bezels to meet the demands of high-end customers, some pixel data signal lines or other vertical signal lines must cross the display area (Fanoutin AA, or FIAA for short). This technique of data signal lines and other vertical signal lines passing through the display area is called FIA technology. For top-emitting devices, many FIA traces need to pass under the anode of the device. Due to the limited planarization capability of the planarization layer, this trace will cause a certain step difference in the anode layer, resulting in uneven light emission.

[0107] This disclosure provides a display substrate, which may include a display area and a bonding area connected to the display area. The display area includes multiple data signal lines extending along a second direction, multiple first transition connection electrodes extending along a first direction, multiple third transition connection electrodes extending along a second direction, and multiple sub-pixels arranged in an array. The multiple data signal lines are respectively connected to multiple columns of sub-pixels, and the data signal lines, the first transition connection electrodes, and the third transition connection electrodes are respectively disposed on three conductive layers.

[0108] At least a portion of the first adapter connection electrodes are electrically connected to multiple data signal lines respectively, and are also electrically connected to at least a portion of the third adapter connection electrodes respectively. One end of the third adapter connection electrode connected to at least a portion of the first adapter connection electrodes is electrically connected to the bonding area. In the display area, the lengths of the multiple data signal lines along the second direction are not exactly the same.

[0109] Multiple sub-pixels form an array of pixels, each pixel including at least three adjacent sub-pixels, and the arrangement of multiple first transition connection electrodes and multiple third transition connection electrodes located in two pixels is consistent.

[0110] The display substrate provided in this embodiment includes a display area comprising multiple data signal lines, multiple first transition connection electrodes, multiple third transition connection electrodes, and multiple sub-pixels arranged in an array. At least a portion of the first transition connection electrodes are electrically connected to the multiple data signal lines and to at least a portion of the third transition connection electrodes. One end of the third transition connection electrode connected to the at least a portion of the first transition connection electrodes is electrically connected to a bonding area. In the display area, the lengths of the multiple data signal lines along a second direction are not entirely the same. The multiple sub-pixels form multiple pixels arranged in an array, and each pixel includes at least three adjacent sub-pixels. The arrangement of the multiple first transition connection electrodes and the multiple third transition connection electrodes in two pixels is consistent. The consistent arrangement of the multiple first transition connection electrodes and the multiple third transition connection electrodes in two pixels in the display substrate provided in this embodiment ensures consistent anode step differences in the multiple pixels, effectively preventing uneven light emission. The display substrate provided in this embodiment has multiple data signal lines in the display area with different lengths along the second direction. This can be applied to irregularly shaped display substrates and can avoid the phenomenon of uneven light emission caused by inconsistent anode polarity in irregularly shaped display substrates.

[0111] In an exemplary implementation, such as Figures 5 to 6c As shown, the display substrate may include a display area AA and a bonding area 10 connected to the display area AA. The display area AA includes multiple data signal lines 48 extending along the second direction Y, multiple first transition connection electrodes 51 extending along the first direction X, multiple third transition connection electrodes 61 extending along the second direction Y, and multiple sub-pixels arranged in an array. The multiple data signal lines 48 are respectively connected to multiple columns of sub-pixels. The data signal lines 48, the first transition connection electrodes 51, and the third transition connection electrodes 61 are respectively disposed on three conductive layers; at least a portion of the first transition connection electrodes 51 are... Each of the data signal lines 48 is electrically connected to at least a portion of the third transition connection electrodes 61, and one end of the third transition connection electrode 61, which is electrically connected to at least a portion of the first transition connection electrodes 51, is electrically connected to the bonding area 10AA. In the display area AA, the lengths of the multiple data signal lines 48 along the second direction Y are not exactly the same. Multiple sub-pixels form multiple pixels P arranged in an array. Each pixel P includes at least three adjacent sub-pixels. The arrangement of the multiple first transition connection electrodes 51 and the multiple third transition connection electrodes 61 located in two pixels P is consistent.

[0112] In an exemplary embodiment, the arrangement of the plurality of first transition connection electrodes 51, the plurality of third transition connection electrodes 61, and the plurality of data signal lines 48 located in two pixels P is consistent to improve the consistency of the wiring under the anodes of the plurality of pixels and avoid uneven light emission caused by inconsistent anode polarity among the plurality of pixels. For example, at least a portion of the number, line width, area, extension direction, and arrangement direction of the plurality of first transition connection electrodes 51, the plurality of third transition connection electrodes 61, and the plurality of data signal lines 48 located in two pixels P are consistent.

[0113] In an exemplary implementation, such as Figure 5 As shown, the display area AA may include a first display area AA1 and a second display area AA2. A plurality of first transition connection electrodes 51 located in the second display area AA2 penetrate the second display area AA2 along a first direction X, and at least a portion of the first transition connection electrodes 51 located in the second display area AA2 are electrically connected to a plurality of data signal lines 48 respectively. A plurality of first transition connection electrodes 51 located in the first display area AA1 do not penetrate the first display area AA1 along the first direction X. At least a portion of the third transition connection electrodes 61 are electrically connected to a plurality of first transition connection electrodes 51 located in the second display area AA2 respectively. The arrangement of the first transition connection electrodes 51, the third transition connection electrodes 61 and the data signal lines 48 in the pixels located in the first display area AA1 and the second display area AA2 is consistent.

[0114] In an exemplary embodiment, at least a portion of the number, line width, area, and extension direction of the first transition connection electrode 51, the second transition connection electrode 61, and the data signal line 48 in the pixels located in the first display area AA1 and the second display area AA2 are consistent. This improves the consistency of the traces under the anodes of multiple pixels in the first display area AA1 and the second display area AA2, avoiding uneven light emission due to inconsistent anode polarity among multiple pixels, thereby improving the uniformity of light emission in the display area AA. For example, the number, line width, area, and extension direction of the first transition connection electrode 51, the second transition connection electrode 61, and the data signal line 48 in the pixels located in the first display area AA1 and the second display area AA2 are all the same.

[0115] In an exemplary implementation, such as Figure 5As shown, the plurality of first transition connection electrodes 51 located in the second display area AA2 penetrate the second display area AA2 along the first direction X, that is, the plurality of first transition connection electrodes 51 located in the second display area AA2 are not disconnected in the first direction X, and are connected in the second display area AA2; the plurality of first transition connection electrodes 51 located in the first display area AA1 do not penetrate the first display area AA1 along the first direction X, that is, the plurality of first transition connection electrodes 51 located in the first display area AA1 are not disconnected in the first direction X, and are not connected in the first display area AA1.

[0116] The display substrate provided in this embodiment has the same arrangement of the first transition connection electrode 51, the second transition connection electrode 61, and the data signal line 48 in the pixels located in the first display area and the second display area. This ensures that the anode step difference is consistent across multiple pixels, effectively preventing uneven light emission. The display substrate provided in this embodiment can be applied to irregularly shaped display substrates, avoiding uneven light emission caused by inconsistent anode step differences in irregularly shaped display substrates.

[0117] In the embodiments disclosed herein, such as Figure 5 As shown, the multiple first transition connection electrodes 51 located in the first display area AA1 may not participate in signal transmission, but can improve the consistency of the traces under the anodes of multiple pixels and avoid uneven light emission due to inconsistent anode diameters.

[0118] In an exemplary embodiment, at least a portion of the first adapter connection 51 electrodes located in the second display area AA2 are electrically connected to multiple data signal lines 48, which may include two cases: one case is that the number of all the first adapter connection electrodes 51 located in the second display area AA2 is the same as the number of data signal lines 48, and all the first adapter connection electrodes 51 located in the second display area AA2 are electrically connected to multiple data signal lines 48; the other case is that the number of all the first adapter connection electrodes 51 located in the second display area AA2 is greater than the number of data signal lines 48, a portion of the first adapter connection electrodes 51 located in the second display area AA2 are electrically connected to multiple data signal lines 48, and another portion of the first adapter connection electrodes 51 located in the second display area AA2 can be used as a parallel structure of the first power line VDD or the second power line VSS to reduce the voltage drop of the first power line VDD or the second power line VSS.

[0119] In an exemplary implementation, such as Figure 13b and 15bAs shown, the display substrate may further include a plurality of second initial signal lines 49 extending along the second direction Y, a plurality of second transition connection electrodes 52 extending along the first direction X, and a plurality of fourth transition connection electrodes 62 extending along the second direction Y. The second initial signal lines 49 are disposed on the same layer as a plurality of data signal lines 48, the plurality of second transition connection electrodes 52 are disposed on the same layer as a plurality of first transition connection electrodes 51, and the plurality of fourth transition connection electrodes 62 are disposed on the same layer as a plurality of third transition connection electrodes 61.

[0120] Multiple second transition connection electrodes 52 located in the second display area AA2 penetrate the second display area AA2 of the display substrate along the first direction X, and are electrically connected to multiple second initial signal lines 49 respectively. Multiple second transition connection electrodes 52 located in the first display area AA1 do not penetrate the first display area AA1 of the display substrate along the first direction X. At least a portion of the fourth transition connection electrodes 62 are electrically connected to multiple second transition connection electrodes 52 located in the second display area AA2 respectively.

[0121] In an exemplary embodiment, a plurality of second transition connection electrodes 52 located in the second display area AA2 penetrate the second display area AA2 of the display substrate along the first direction X, that is, the plurality of second transition connection electrodes 52 located in the second display area AA2 are not disconnected and are connected in the first direction X; a plurality of second transition connection electrodes 52 located in the first display area AA1 do not penetrate the first display area AA1 of the display substrate along the first direction X, that is, the plurality of second transition connection electrodes 52 located in the first display area AA1 are disconnected and are not connected in the first direction X. In an exemplary embodiment, on a plane parallel to the display substrate, a plurality of data signal lines 48 and a plurality of second initial signal lines 49 extend along the second direction Y and are arranged along the first direction X; a plurality of first transition connection electrodes 51 and a plurality of second transition connection electrodes 52 extend along the first direction X and are arranged along the second direction Y; a plurality of third transition connection electrodes 61 and a plurality of fourth transition connection electrodes 62 extend along the second direction Y and are arranged along the first direction X; the first direction X and the second direction Y intersect.

[0122] In an exemplary implementation, such as Figures 6a to 6cAs shown, a pixel P can include three sub-pixels P1, P2, and P3. In the same column of pixel space, there can be three columns of sub-pixels and three data signal lines 48. The three columns of sub-pixels are connected to the three data signal lines 48 respectively. Two adjacent columns of pixels share a second initial signal line 49, which is located between the two adjacent columns of pixels. In the two columns of pixels sharing the second initial signal line 49, there are 20 third transition connection electrodes 61 and 1 fourth transition connection electrode 62. Each column of pixel space has 10 third transition connection electrodes 61 and 1 fourth transition connection electrode 62 located between the two columns of pixels. In the same row of pixel space, there are 6 first transition connection electrodes 51 and 1 second transition connection electrode 52.

[0123] In an exemplary implementation, such as Figure 15d As shown, a pixel may include three sub-pixels. In the same column pixel space, there are three columns of sub-pixels, three data signal lines 48 and nine third transition connection electrodes 61. The three columns of sub-pixels are respectively connected to the three data signal lines 48. In the same row pixel space, there are six first transition connection electrodes 51.

[0124] In an exemplary implementation, such as Figure 20 As shown, a pixel may include three sub-pixels. In the same column pixel space, there are three columns of sub-pixels, three data signal lines 48 and three third transition connection electrodes 61. The three columns of sub-pixels are respectively connected to the three data signal lines 48. In the same row pixel space, there are two first transition connection electrodes 51.

[0125] In an exemplary implementation, such as Figure 13a As shown, a sub-pixel may include a first transistor T1 to a fifth transistor T5 and a storage capacitor. On a plane parallel to the display substrate, a second transistor T2, a first transistor T1, a third transistor T3, a fourth transistor T4, and a fifth transistor T5 are arranged along the second direction Y. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the third transistor T3 on the substrate. In the same pixel, two adjacent sub-pixels are symmetrically arranged with respect to a first center line, which is the center line extending from the two adjacent sub-pixels along the second direction Y.

[0126] In an exemplary implementation, such as Figure 13aAs shown, within the same column of subpixels, multiple subpixel groups Z can be included. Each subpixel group can include two adjacent subpixels. Two subpixels in the same subpixel group Z share a single fifth transistor T5, which reduces the number of transistors and saves space on the display substrate. In this embodiment, within the same pixel column, four subpixels in two adjacent subpixel groups can be located in four rows of subpixels. Within the same pixel column, two adjacent subpixels in two adjacent subpixel groups Z do not share the fifth transistor T5, but two subpixels in the same subpixel group Z can share the fifth transistor T5.

[0127] In an exemplary embodiment, at least one sub-pixel may include a pixel driving circuit, which may include a plurality of oxide transistors and a storage capacitor; in a plane perpendicular to the display substrate, the display substrate includes a substrate and a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate;

[0128] The semiconductor layer includes: an active layer of multiple oxide transistors;

[0129] The first conductive layer includes: the control electrode of a plurality of oxide transistors and the first electrode of a storage capacitor;

[0130] The second conductive layer includes: the second electrode of the storage capacitor;

[0131] The third conductive layer includes: multiple data signal lines 48 and multiple first and second electrodes of oxide transistors, with the data signal lines 48 extending along the second direction Y;

[0132] The fourth conductive layer includes: a plurality of first transition connection electrodes 51, the first transition connection electrodes 51 extending along a first direction X;

[0133] The fifth conductive layer includes a plurality of third transition connection electrodes 61, which extend along the second direction Y and intersect the first direction X and the second direction Y on a plane parallel to the display substrate.

[0134] In an exemplary implementation, such as Figure 11b As shown, the third conductive layer may further include: a plurality of second initial signal lines 49 extending along the second direction Y; two adjacent columns of pixels share a second initial signal line 49, and a plurality of data signal lines 48 in the two columns of pixels sharing a second initial signal line 49 are symmetrical with respect to the second initial signal line 49;

[0135] like Figure 13b As shown, the fourth conductive layer may further include: a plurality of second transition connection electrodes 52 extending along the first direction X, wherein the plurality of second transition connection electrodes 52 located in the second display area AA2 are electrically connected to a plurality of second initial signal lines 49 respectively.

[0136] like Figure 15b As shown, the fifth conductive layer may further include: a plurality of fourth transfer connection electrodes 62 extending along the second direction Y; the plurality of fourth transfer connection electrodes 62 are electrically connected to a plurality of second transfer connection electrodes 52 located in the second display area AA2 respectively.

[0137] In an exemplary implementation, such as Figure 8b As shown, the first conductive layer may further include: a plurality of first power connection lines 26 extending along the first direction X; as Figure 13a As shown, in the same column of sub-pixels, there may be multiple sub-pixel groups Z. Each sub-pixel group Z may include two adjacent sub-pixels. In the same sub-pixel group Z, the two sub-pixels share a first power connection line 26. The two sub-pixels in the same sub-pixel group Z may be symmetrical with respect to the first power connection line 26.

[0138] like Figure 11b As shown, the third conductive layer may further include: a first power line 47 extending along the second direction Y; the first power line 47 may be electrically connected to the first power connection line 26 through a via.

[0139] In an exemplary implementation, such as Figure 5 As shown, the display substrate can be heart-shaped, the display area AA can include a first display area AA1 and a second display area AA2, the bonding area 10 can be located on one side of the display area AA, and the first display area AA1, the second display area AA2 and the bonding area 10 can be arranged sequentially along the second direction Y.

[0140] In an exemplary implementation, such as Figure 12b , Figure 13c , Figure 14 , Figure 15c , Figure 21 As shown, at least a portion of the first adapter connection electrodes 51 can be electrically connected to multiple data signal lines 48 through multiple first adapter vias Vm1, and at least a portion of the third adapter connection electrodes 61 can be electrically connected to at least a portion of the first adapter connection electrodes 51 through multiple third adapter vias Vm3. The arrangement direction of the multiple first adapter vias Vm1 forms a first angle F1 with the center line Q1-Q1 extending along the second direction Y of the display substrate, and the arrangement direction of the multiple third adapter vias Vm3 forms a second angle F2 with the center line Q1-Q1 extending along the second direction Y of the display substrate.

[0141] In an exemplary embodiment, the first included angle F1 is 30 degrees to 60 degrees, and the second included angle F2 is 15 degrees to 45 degrees. For example, the first included angle F1 can be 45 degrees and the second included angle F2 can be 30 degrees.

[0142] In an exemplary implementation, such as Figure 21 As shown, the arrangement direction of the plurality of first transition vias Vm1 can be symmetrically arranged relative to the center line Q1-Q1 extending along the second direction Y of the display substrate, and the arrangement direction of the plurality of third transition vias Vm3 can be symmetrically arranged relative to the center line Q1-Q1 extending along the second direction Y of the display substrate.

[0143] In an exemplary implementation, such as Figure 21 As shown, in the display area AA located on one side of the centerline extending along the second direction Y of the display substrate, a plurality of first transition vias Vm1 are arranged along at least two directions, and the at least two arrangement directions are parallel to each other. The connecting lines C1 and C2 of the plurality of first transition vias Vm1 located in the at least two arrangement directions are arranged along the second direction Y. A plurality of third transition vias Vm3 are arranged along at least two directions, and the at least two arrangement directions are parallel to each other. The connecting lines D1 and D2 of the plurality of third transition vias Vm3 located in the at least two arrangement directions are arranged along the second direction Y.

[0144] In an exemplary implementation, such as Figures 13a to 15d As shown, the fourth conductive layer may also include anode connection electrodes 53 that are electrically connected to multiple sub-pixels respectively. The orthographic projections of the first transition connection electrode 51 and the third transition connection electrode 61 on the substrate do not overlap with the orthographic projections of the multiple anode connection electrodes 53 on the substrate, so as to avoid shading the anodes formed subsequently.

[0145] In an exemplary implementation, such as Figure 6a , Figure 17a and Figure 17b As shown, the display substrate may further include an anode conductive layer, which may include multiple anodes 71, each of which is connected to multiple anode connecting electrodes 53. The orthographic projections of the multiple anodes 71 in the same pixel onto the substrate and the orthographic projections of the multiple first connecting electrodes 51 and the multiple third connecting electrodes 61 onto the substrate have a first overlapping region. Multiple pixels correspond to multiple first overlapping regions, and the areas of these multiple first overlapping regions are consistent, which ensures that the end differences of the multiple anodes 71 are consistent, avoiding the problem of uneven light emission caused by inconsistent anode end differences. For example, the areas of the multiple first overlapping regions can be the same. In an exemplary embodiment, such as... Figure 5 As shown, the display substrate may include a border BB located around the display area AA. The border BB may include a first border BB1 and a second border BB2. The bonding area 10 may be located in the first border BB1 (i.e., the lower border).

[0146] In an exemplary implementation, such as Figure 5As shown, the size of the bonding area 10 along the first direction X can be smaller than the size of the display area AA along the first direction X. The plurality of third transition connection electrodes 61 can include two parts: those extending into the bonding area 10 and those not extending into the bonding area 10. The plurality of third transition connection electrodes 61 extending into the bonding area 10 are electrically connected to the plurality of first transition connection electrodes 51 located in the second display area AA2. In an exemplary embodiment, the plurality of third transition connection electrodes 61 not extending into the bonding area 10 may not be electrically connected to the plurality of first transition connection electrodes 51 located in the second display area AA2. In an exemplary embodiment, the plurality of third transition connection electrodes 61 extending into the bonding area 10 are electrically connected to the bonding area, while the plurality of third transition connection electrodes 61 not extending into the bonding area 10 may not be electrically connected to the bonding area 10. The plurality of third transition connection electrodes 61 not extending into the bonding area 10 and the plurality of first transition connection electrodes 51 located in the first display area AA1 may not participate in signal transmission, but can improve the consistency of the traces under the anodes of multiple pixels, avoiding uneven light emission due to inconsistent anode diameters.

[0147] In other embodiments, the size of the bonding area 10 along the first direction X may not be smaller than the size of the display area AA along the first direction X, and the arrangement of the bonding area 10 may be determined according to the shape of the display substrate.

[0148] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0149] In an exemplary embodiment, taking 12 sub-pixels (2 sub-pixel rows and 6 sub-pixel columns) in the display area (AA) as an example, the fabrication process of the display substrate may include the following operations.

[0150] (101) A substrate is prepared on a glass substrate. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers, and the material of the adhesive layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible material (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible material (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0151] (102) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, and patterning the semiconductor film using a patterning process to form a semiconductor layer pattern disposed on the first insulating layer, such as... Figure 7 As shown, Figure 7 This is a planar schematic diagram of the semiconductor layer in the twelve sub-pixels.

[0152] In an exemplary embodiment, the semiconductor layer pattern of each sub-pixel may include the active layer 11 of the first transistor T1 to the active layer 15 of the fifth transistor T5.

[0153] In an exemplary embodiment, in the second direction Y, within the same sub-pixel, the active layer 12 of the second transistor T2, the active layer 11 of the first transistor T1, the active layer 13 of the third transistor T3, the active layer 14 of the fourth transistor T4, and the active layer of the fifth transistor T5 are arranged sequentially.

[0154] In an exemplary embodiment, the active layer 13 of the third transistor T3 can be Ω-shaped, the active layer 11 of the first transistor T1 and the active layer 25 of the fifth transistor T5 can be n-shaped, and an active layer 12 facing away from the second transistor T2 is provided. The active layer 12 of the second transistor T2 and the active layer 14 of the fourth transistor T4 can be L-shaped.

[0155] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first regions 11-1 of the active layers 12 of multiple second transistors T2 located in the same sub-pixel row can be interconnected, making the active layers 12 of the multiple second transistors T2 located in the same sub-pixel row a single-piece structure. In an exemplary embodiment, since the first region of the active layer of the second transistor T2 in each sub-pixel is connected to the subsequently formed second initial signal line, by forming an interconnected single-piece structure of the first regions of the active layers of the second transistors T2 in the same sub-pixel row, it can be ensured that the first electrodes of the second transistors T2 in adjacent sub-pixels have the same potential. This is beneficial for improving the uniformity of the panel display, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0156] In an exemplary embodiment, adjacent sub-pixels within the same sub-pixel column can share a single fifth transistor T5. For example, sub-pixels in the Mth row of the Nth column and the (M+1)th row can share a single fifth transistor T5, and sub-pixels in the Mth row of the Nth column and the (M+1)th row can share the active layer 15 of the single fifth transistor T5, thus saving layout space. In another exemplary embodiment, a single sub-pixel column can include multiple sub-pixel groups. Each sub-pixel group can include one sub-pixel in an odd-numbered row and one sub-pixel in an even-numbered row, with four sub-pixels in two adjacent sub-pixel groups located in four sub-pixel rows.

[0157] In an exemplary embodiment, the semiconductor layers in the Nth and N+1th columns can be mirror-symmetrical with respect to a first center line, the semiconductor layers in the N+1th and N+2th columns can be mirror-symmetrical with respect to a second center line, the semiconductor layers in the N+3th and N+4th columns can be mirror-symmetrical with respect to a third center line, and the semiconductor layers in the N+4th and N+5th columns can be mirror-symmetrical with respect to a fourth center line. The first center line is the center line extending along the second direction Y for the semiconductor layers in the Nth and N+1th columns; the second center line is the center line extending along the second direction Y for the semiconductor layers in the N+1th and N+2th columns; the third center line is the center line extending along the second direction Y for the semiconductor layers in the N+3th and N+4th columns; and the fourth center line is the center line extending along the second direction Y for the semiconductor layers in the N+4th and N+5th columns.

[0158] In an exemplary embodiment, the semiconductor layer may be an oxide, i.e., the first transistor T1 to the fifth transistor T5 are oxide thin-film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfide oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film may be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0159] (103) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 8a and Figure 8b As shown, Figure 8b for Figure 8a A planar schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0160] In an exemplary embodiment, the first conductive layer pattern may include at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emission control line 24, a first electrode plate 25 of a storage capacitor, and a first power connection line 26. The main body portions of the second scan signal line 22, the first scan signal line 21, the third scan signal line 23, the light emission control line 24, and the first power connection line 26 may extend along a first direction X. In the same sub-pixel, the second scan signal line 22, the first scan signal line 21, the first electrode plate 25 of the storage capacitor, and the third scan signal line 23 are arranged along a second direction Y, and the light emission control line 24 and the first power connection line 26 are arranged along the second direction Y.

[0161] In an exemplary embodiment, two adjacent rows of sub-pixels can share a light-emitting control line 24 and a first power connection line 26. The light-emitting control line 24 and the first power connection line 26 can be located between the third scan signal lines 23 of the two adjacent sub-pixel rows. In an exemplary embodiment, within the same sub-pixel column, two adjacent sub-pixels can share a fifth transistor T5. For example, sub-pixels in the Mth row and the (M+1)th row of the Nth column can share a fifth transistor T5, and sub-pixels in the Mth row and the (M+1)th row can share a light-emitting control line 24 and a first power connection line 26 to save layout space.

[0162] Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the first scan signal line 21 can be located on the side of the first plate 25 of the storage capacitor away from the M+1th row sub-pixel, the second scan signal line 22 can be located on the side of the first scan signal line 21 away from the first plate 25 of the storage capacitor, the third scan signal line 23 can be located on the side of the first plate 25 of the storage capacitor away from the first scan signal line 21, the light emission control line 24 can be located on the side of the third scan signal line 23 away from the first plate 25 of the storage capacitor, and the first power supply connection line 26 can be located on the side of the light emission control line 24 away from the third scan signal line 23.

[0163] In an exemplary embodiment, the first electrode 25 may be located between the third scan signal line 23 and the first scan signal line 21. The first electrode 25 may be rectangular, and its orthographic projection on the substrate overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode 25 may simultaneously serve as one electrode of a storage capacitor and the control electrode of the third transistor T3. In an exemplary embodiment, the first electrode 25 may have an opening 27, which may be located at the edge of the first electrode 25. The opening 27 may be rectangular, forming an n-shaped structure. The orthographic projection of the opening 27 on the substrate overlaps with the orthographic projection of the second region 13-2 of the active layer 13 of the third transistor T3 on the substrate. In an exemplary embodiment, the opening 27 is configured to accommodate a subsequently formed fifth via. The fifth via is located within the opening 27 and exposes the second region 13-2 of the active layer 13 of the third transistor T3, connecting the second electrode of the subsequently formed third transistor T3 to the second region 13-2 of the active layer 13 of the third transistor T3.

[0164] In an exemplary embodiment, the region where the light-emitting control line 24 overlaps with the active layer of the fifth transistor T5 serves as the control electrode of the fifth transistor T5, the region where the first scan signal line 21 overlaps with the active layer of the first transistor T1 serves as the control electrode of the first transistor T1, the region where the second scan signal line 22 overlaps with the active layer of the second transistor T2 serves as the control electrode of the second transistor T2, and the region where the third scan signal line 23 overlaps with the active layer of the fourth transistor T4 serves as the control electrode of the fourth transistor T4. In an exemplary embodiment, the first scan signal line 21 has a first protrusion 21-1 and a second protrusion 21-2, which are arranged along a first direction X. Both the first protrusion 21-1 and the second protrusion 21-2 overlap with the active layer of the first transistor T1, forming a dual-gate structure for the first transistor T1. In an exemplary embodiment, the second scan signal line 22 has a first protrusion structure 22-1 and a second protrusion structure 22-2, which are arranged along a first direction X. Both the first protrusion structure 22-1 and the second protrusion structure 22-2 overlap with the active layer of the second transistor T2, forming a dual-gate structure for the second transistor T2. In the embodiments of this disclosure, the first transistor T1 and the second transistor T2 are dual-channel transistors.

[0165] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light emission control line 24, and the first power connection line 26 can be designed with equal width or with non-equal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0166] (104) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figures 9a to 9b As shown, Figure 9a This is a planar structure diagram of twelve sub-pixels. Figure 9b for Figure 9a A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0167] In an exemplary embodiment, the second conductive layer pattern includes at least: a first initial signal line 31 and a second electrode 32 of a storage capacitor, wherein the main body of the first initial signal line 31 may extend along a first direction X. The second electrode 43 of the storage capacitor serves as the other electrode of the storage capacitor.

[0168] In an exemplary embodiment, within the same sub-pixel group, along the second direction Y, in one sub-pixel, the second electrode 32 and the first initial signal line 31 of the storage capacitor are arranged sequentially along the second direction Y, while in another sub-pixel, the second electrode 32 and the first initial signal line 31 of the storage capacitor are arranged sequentially in the opposite direction of the second direction Y. For example, in the sub-pixel of the Mth row and Nth column, the second electrode 32 and the first initial signal line 31 of the storage capacitor are arranged sequentially along the second direction Y; in the sub-pixel of the M+1th row and Nth column, the second electrode 32 and the first initial signal line 31 of the storage capacitor are arranged sequentially in the opposite direction of the second direction Y.

[0169] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the orthographic projection of the second electrode plate 32 on the substrate overlaps with the orthographic projection of the first electrode plate 25 on the substrate. The first electrode plate 25 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0170] (105) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein the fourth insulating layer has a plurality of vias, such as... Figure 10 As shown, Figure 10 This is a planar structure diagram of twelve sub-pixels.

[0171] In an exemplary embodiment, the plurality of vias in each sub-pixel include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, and a sixteenth via V16.

[0172] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer 11 of the first transistor T1 onto the substrate. The fourth, third, and second insulating layers within the first via V1 are etched away, exposing the surface of the first region 11-1 of the active layer 11 of the first transistor T1. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the active layer 11 of the first transistor T1 through the via.

[0173] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer 11 of the first transistor T1 onto the substrate. The fourth, third, and second insulating layers within the second via V2 are etched away, exposing the surface of the second region 11-2 of the active layer 11 of the first transistor T1. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the active layer 11 of the first transistor T1 through the via.

[0174] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer 12 of the second transistor T2 onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region 22-1 of the active layer 12 of the second transistor T2. The third via V3 is configured to allow a subsequently formed first initial signal line to connect to the active layer 12 of the second transistor T2 through the via.

[0175] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the substrate lies within the orthogonal projection of the active layer 12 of the second transistor T2 onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the second region 12-2 of the active layer 12 of the second transistor T2. The fourth via V4 is configured to allow the second electrode of the subsequently formed first transistor T2 to be connected to the active layer 12 of the second transistor T2 through the via.

[0176] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate lies within the orthogonal projection of the active layer 13 of the third transistor T3 onto the substrate. The fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the second region 13-2 of the active layer 13 of the third transistor T3. The fifth via V5 is configured to allow the second electrode of the subsequently formed third transistor T3 to be connected to the active layer 13 of the third transistor T3 through the via.

[0177] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the active layer 13 of the third transistor T3 onto the substrate. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region 13-1 of the active layer 13 of the third transistor T3. The sixth via V6 is configured to allow the first electrode of the subsequently formed third transistor T3 to be connected to the active layer 13 of the third transistor T3 through the via.

[0178] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the active layer 14 of the fourth transistor T4 onto the substrate. The fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the second region 14-2 of the active layer 14 of the fourth transistor T4. The seventh via V7 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the active layer 14 of the fourth transistor T4 through this via.

[0179] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the active layer 14 of the fourth transistor T4 onto the substrate. The fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region 14-1 of the active layer 14 of the fourth transistor T4. The eighth via V8 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer 14 of the fourth transistor T4 through this via.

[0180] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the orthographic projection of the active layer 15 of the fifth transistor T5 onto the substrate. The fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the first region 15-1 of the active layer 15 of the fifth transistor T5. The ninth via V9 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the active layer 15 of the fifth transistor T5 through the via.

[0181] In an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the substrate lies within the orthogonal projection of the active layer 15 of the fifth transistor T5 onto the substrate. The fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the second region 15-2 of the active layer 15 of the fifth transistor T5. The tenth via V10 is configured to allow the second electrode of the subsequently formed fifth transistor T5 to be connected to the active layer 15 of the fifth transistor T5 through this via.

[0182] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the first electrode 25 onto the substrate. The fourth and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the first electrode 25 of the storage capacitor. The eleventh via V11 is configured to allow the second electrode of the subsequently formed third transistor T3 to be connected to the first electrode 25 of the storage capacitor through the via.

[0183] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the range of the orthographic projection of the first power connection line 26 onto the substrate. The fourth and third insulating layers within the twelfth via V12 are etched away, exposing the surface of the first power connection line 26. The twelfth via V12 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the first power connection line 26 through the via.

[0184] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate lies within the range of the orthographic projection of the first power connection line 26 onto the substrate. The fourth and third insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first power connection line 26. The thirteenth via V13 is configured to allow a subsequently formed first power line to be connected to the first power connection line 26 through this via.

[0185] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the orthographic projection of the second electrode 32 of the storage capacitor onto the substrate. The fourth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the second electrode 32 of the storage capacitor. The fourteenth via V14 is configured to connect the second electrode of the subsequently formed third transistor T3 to the second electrode 32 of the storage capacitor.

[0186] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the second electrode 32 of the storage capacitor onto the substrate. The fourth insulating layer within the fifteenth via V15 is etched away, exposing the surface of the second electrode 32 of the storage capacitor. The fifteenth via V15 is configured to connect the second electrode of the subsequently formed fourth transistor T4 to the second electrode 32 of the storage capacitor.

[0187] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate lies within the range of the orthographic projection of the first initial signal line 31 onto the substrate. The fourth insulating layer within the sixteenth via V16 is etched away, exposing the surface of the first initial signal line 31. The sixteenth via V16 is configured to connect the first terminal of the subsequently formed fourth transistor T4 to the first initial signal line 31.

[0188] (106) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figures 11a to 11b As shown, Figure 11a This is a planar structure diagram of twelve sub-pixels. Figure 11b for Figure 11a A schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0189] In an exemplary embodiment, the third conductive layer includes at least: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a first power line 47, a data signal line 48, and a second initial signal line 49.

[0190] In an exemplary embodiment, the first connection electrode 41 is a zigzag shape with its main body extending along the second direction Y. Its first end is connected to the second region 11-2 of the active layer 11 of the first transistor T1 through a second via V2, and to the first electrode plate 25 of the storage capacitor through an eleventh via V11. Its second end is connected to the second region 12-2 of the second transistor T2 through a fourth via V4, so that the first electrode plate 25, the second electrode of the first transistor T1, and the second electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 41 can serve as the second electrode of the first transistor T1 and the second electrode of the second transistor T2, ensuring that the second electrodes of the first transistor T1 and the second electrode of the second transistor T2 have the same potential.

[0191] In an exemplary embodiment, the second connection electrode 42 can be a strip shape extending along the first direction X of the main body portion. The second connection electrode 42 is connected to the second region 13-2 of the active layer 13 of the third transistor T3 through a fifth via V5, and to the second electrode plate 23 of the storage capacitor through a fourteenth via V14. In an exemplary embodiment, the second connection electrode 42 can serve as the second electrode of the third transistor T13, and the second connection electrode 42 is configured to connect the second region 13-2 of the active layer 13 of the third transistor T3 to the second electrode plate 23 of the storage capacitor.

[0192] In an exemplary embodiment, one end of the third connection electrode 43 is connected to the first region 13-1 of the active layer 13 of the third transistor T3 through the sixth via V6, and the other end of the third connection electrode 43 is connected to the second region 15-2 of the active layer 15 of the fifth transistor T5 through the tenth via V10. In an exemplary embodiment, the third connection electrode 43 can simultaneously serve as the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5, so that the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5 have the same potential.

[0193] In an exemplary embodiment, the third connection electrodes 43 of two adjacent rows in the same sub-pixel can be a single-piece structure. The third connection electrodes 43 in the same sub-pixel group can be connected to the second region 15-2 of the active layer 15 of the same fifth transistor T5 through the tenth via V10.

[0194] In an exemplary embodiment, the fourth connection electrode 44 is connected to the second region 14-2 of the active layer 14 of the fourth transistor T4 through the seventh via V7, and the fourth connection electrode 44 is connected to the second electrode plate 32 of the storage capacitor through the fifteenth via V15. In an exemplary embodiment, the fourth connection electrode 44 can serve as the second electrode of the fourth transistor T4.

[0195] In an exemplary embodiment, the fifth connection electrode 45 is connected to the first region 14-2 of the active layer 14 of the fourth transistor T4 via the eighth via V8, and the fifth connection electrode 45 is connected to the first initial signal line 31 in a sub-pixel row via the sixteenth via V16. In an exemplary embodiment, the fifth connection electrode 45 can serve as the first electrode of the fourth transistor T4, and the fifth connection electrode 45 is configured to connect the first electrode of the fourth transistor T4 to the first initial signal line 31.

[0196] In an exemplary embodiment, the sixth connection electrode 46 is connected to the first region 15-1 of the active layer 15 of the fifth transistor T5 through the ninth via V9, and the sixth connection electrode 46 is connected to the first power connection line 26 in a sub-pixel row through the twelfth via V13. In an exemplary embodiment, the sixth connection electrode 46 can serve as the first electrode of the fifth transistor T5 and is configured to be connected to the first power connection line 26.

[0197] In an exemplary embodiment, the sixth connection electrodes 46 of two adjacent rows in the same sub-pixel can be connected to the first region 15-1 of the active layer 15 of the same fifth transistor T5 through the ninth via V9.

[0198] In an exemplary embodiment, the first power line 47 can be a strip extending along the second direction Y of the main body. The first power line 47 is connected to multiple first power connection lines 26 through multiple thirteenth vias V13 in a sub-pixel column, and the first power supply voltage is written into the first terminal of the fifth transistor T5 through the first power connection 26. In the exemplary embodiment, since the first power line 47 is connected to all the first power connection lines 26 in a sub-pixel column, it can be ensured that all the first power connection lines 26 (i.e., the first terminal of the fifth transistor T5) in a sub-pixel column have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0199] In an exemplary embodiment, the data signal line 48 can be a strip-shaped structure extending along the second direction Y of the main body. The data signal line 48 is connected to the first region 11-1 of the active layer 11 of the first transistor T1 through the first via V1, and can provide data signals to the first region 11-1 of the active layer 11 of the first transistor T1. In an exemplary embodiment, the data signal line 48 may include a data signal line r connected to a sub-pixel emitting red light, a data signal line g connected to a sub-pixel emitting green light, and a data signal line b connected to a sub-pixel emitting blue light.

[0200] In an exemplary embodiment, the second initial signal line 49 can be a strip-shaped structure extending along the second direction Y of the main body. The second initial signal line 49 can be connected to the first region 12-1 of the active layer 12 of the second transistor T2 in the multi-row sub-pixels through the third via V3, so as to provide the initial signal to the active layer of the second transistor T2. In an exemplary embodiment, two adjacent columns of pixels can share one second initial signal line 49 to reduce the number of traces, save layout space, and thus reduce the width of the border.

[0201] (107) Forming a fifth insulating layer and a first planarization layer pattern. In an exemplary embodiment, forming the fifth insulating layer and the first planarization layer pattern may include: first coating a first planarization film on a substrate on which the aforementioned pattern is formed, then depositing a fifth insulating film, and patterning the first planarization film and the fifth insulating film using a patterning process to form a first planarization layer covering the third conductive layer pattern and a fifth insulating layer disposed on the first planarization layer, wherein a plurality of vias are provided on the fifth insulating layer and the first planarization layer, such as... Figure 12a The diagram shown is a planar structure diagram of twelve sub-pixels.

[0202] In an exemplary embodiment, the plurality of vias in each sub-pixel includes at least: a seventeenth via V17.

[0203] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate lies within the range of the orthographic projection of the fourth connection electrode 44 onto the substrate. The first planarization layer and the fifth insulating layer within the seventeenth via V17 are etched away, exposing the surface of the fourth connection electrode 44. The seventeenth via V17 is configured to allow a subsequently formed anode connection electrode to be connected to the fourth connection electrode 44 through the via.

[0204] like Figure 12b As shown, multiple first transition vias Vm1 and second transition vias Vm2 can also be provided on the fifth insulating layer and the first planarization layer.

[0205] In an exemplary embodiment, the orthographic projection of the first adapter via Vm1 onto the substrate falls within the orthographic projection range of the data signal line 48 onto the substrate. The first planarization layer and the fifth insulating layer within the first adapter via Vm1 are etched away, exposing the surface of the data signal line 48. The first adapter via Vm1 is configured to connect the data signal line 48 to a subsequently formed first adapter connection electrode.

[0206] In an exemplary embodiment, the first planarization layer and the fifth insulating layer within the second adapter via Vm2 are etched away within the orthographic projection of the second initial signal line 49 onto the substrate, exposing the surface of the second initial signal line 49. The second adapter via Vm2 is configured to connect the second initial signal line 49 to a subsequently formed second adapter connection electrode.

[0207] (108) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming a fourth conductive layer disposed on a fifth insulating layer, such as... Figures 13a to 13b As shown, Figure 13a This is a planar structure diagram of twelve sub-pixels. Figure 13b for Figure 13a A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0208] In an exemplary embodiment, the fourth conductive layer includes at least: a first transition connection electrode 51, a second transition connection electrode 52, and an anode connection electrode 53. In an exemplary embodiment, the anode connection electrode 53 is the anode connection electrode of the light-emitting element.

[0209] In an exemplary embodiment, the first transition electrode 51 can be a strip-shaped structure extending along the first direction X, and multiple first transition electrodes 51 can be arranged along the second direction Y. For example... Figure 13cAs shown, multiple first adapter connection electrodes 51 can be electrically connected to the corresponding data signal lines 48 through the first adapter vias Vm1.

[0210] In an exemplary embodiment, the second transition connection electrode 52 can be a strip-shaped structure extending along the first direction X, such as... Figure 13c As shown, the second adapter connection electrode 52 can be electrically connected to the second initial signal line 49 through the second adapter via Vm2.

[0211] In an exemplary embodiment, the anode connection electrode 53 may be a strip structure extending along the second direction Y, and the anode connection electrode 51 may be connected to the fourth connection electrode 44 through the seventeenth through hole V17.

[0212] (109) Forming a sixth insulating layer and a second planarization layer pattern. In an exemplary embodiment, forming the sixth insulating layer and the second planarization layer pattern may include: first coating a second planarization film on a substrate on which the aforementioned pattern is formed, then depositing a sixth insulating film, and patterning the second planarization film and the sixth insulating film using a patterning process to form a second planarization layer covering the fourth conductive layer pattern and a sixth insulating layer disposed on the second planarization layer, wherein a plurality of vias are provided on the sixth insulating layer and the second planarization layer, such as... Figure 14 The diagram shown is a planar structure diagram of twelve sub-pixels.

[0213] In an exemplary embodiment, the vias on the sixth insulating layer and the second planarization layer include at least: a third transition via Vm3 and a fourth transition via Vm4.

[0214] In an exemplary embodiment, the orthographic projection of the third adapter via Vm3 on the substrate is within the range of the orthographic projection of the first adapter electrode 51 on the substrate. The third adapter via Vm3 is configured to connect the first adapter electrode 51 to the subsequently formed third adapter electrode.

[0215] In an exemplary embodiment, the orthographic projection of the fourth adapter via Vm4 on the substrate falls within the range of the orthographic projection of the second adapter electrode 52 on the substrate. The fourth adapter via Vm4 is configured to connect the second adapter electrode 52 to the subsequently formed fourth adapter electrode.

[0216] (110) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive thin film using a patterning process, and forming a fifth conductive layer disposed on a fifth insulating layer, such as... Figures 15a to 15b As shown, Figure 15a This is a planar structure diagram of twelve sub-pixels. Figure 15b for Figure 15aA planar schematic diagram of the fifth conductive layer. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD3) layer.

[0217] In an exemplary embodiment, the fifth conductive layer may include a third transition connection electrode 61 and a fourth transition connection electrode 62.

[0218] In an exemplary embodiment, the third transition electrode 61 and the fourth transition electrode 62 can be a broken line structure extending along the second direction Y, and the plurality of third transition connection points 61 and the plurality of second transition connection electrodes 62 can be arranged along the first direction.

[0219] In an exemplary implementation, such as Figure 15c As shown, multiple third adapter electrodes 61 can be connected to multiple first adapter electrodes 51 through third adapter vias Vm3, and multiple fourth adapter electrodes 62 can be connected to multiple second adapter electrodes 52 through fourth adapter vias Vm4.

[0220] In an exemplary embodiment, the orthographic projections of the third transfer electrode 61 and the fourth transfer electrode 62 on the substrate do not overlap with the orthographic projection of the anode connection electrode 53 on the substrate, so as to avoid obstructing the anode connection electrode 53 and the anode subsequently formed.

[0221] In an exemplary implementation, such as Figure 15d As shown, in order to reduce the number of traces in the fourth and fifth conductive layers, the signal in the second initial signal line 49 can be introduced through the pass line, without signal transfer through the second transfer electrode 52 in the fourth conductive layer and the fourth transfer electrode 62 in the fifth conductive layer, so as to reduce the bezel of the display substrate.

[0222] (111) Forming a third planarization layer pattern. In an exemplary embodiment, forming the third planarization layer pattern may include: coating a third planarization film on a substrate on which the aforementioned pattern is formed, patterning the third planarization film using a patterning process to form a second planarization layer covering the fourth conductive layer pattern and a sixth insulating layer disposed on the second planarization layer, wherein the sixth insulating layer and the second planarization layer are provided with a plurality of vias, such as Figure 16 The diagram shown is a planar structure diagram of twelve sub-pixels.

[0223] In an exemplary embodiment, the via in each sub-pixel includes at least: an eighteenth via V18.

[0224] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate lies within the range of the orthographic projection of the anode connection electrode 53 onto the substrate. The sixth insulating layer, the second planarization layer, and the third planarization layer within the eighteenth via V18 are etched away, exposing the surface of the anode connection electrode 53. The eighteenth via V18 is configured to connect the anode of a subsequently formed light-emitting diode to the anode connection electrode 53.

[0225] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations:

[0226] (112) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on a planarization layer, such as... Figure 17a and Figure 17b As shown, Figure 17b for Figure 17a A planar schematic diagram of the anode conductive layer.

[0227] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anodes 71.

[0228] In an exemplary embodiment, the anode 71 is connected to the anode connection electrode 53 through the eighteenth through-hole V18.

[0229] In an exemplary embodiment, the orthogonal projection of the anode 71 onto the substrate can cover the orthogonal projection of the anode connection electrode 53 onto the substrate.

[0230] (113) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: depositing a pixel definition layer film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition layer using a patterning process to form a pixel definition layer pattern disposed on the anode conductive layer, such as... Figure 18 As shown.

[0231] In an exemplary embodiment, the pixel definition layer pattern may include a plurality of pixel openings 81 that expose the anode 71. In an exemplary embodiment, the orthographic projection of the pixel openings 81 onto the substrate lies within the range of the orthographic projection of the anode 71 onto the substrate.

[0232] In an exemplary embodiment, subsequent fabrication processes may include: forming an organic light-emitting layer using vapor deposition or inkjet printing; the organic light-emitting layer being connected to an anode through pixel openings; forming a cathode on the organic light-emitting layer; and connecting the cathode to the organic light-emitting layer. An encapsulation structure layer is then formed, which may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is positioned between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0233] The display substrate provided in this disclosure can be applied to irregularly shaped display substrates, ensuring that the trace shape in each pixel is consistent. This avoids inconsistencies in the traces below the anode, preventing uneven light emission caused by inconsistent anode electrode differences. The flatness of the anode conductive layer is determined by two factors: the flatness capability of the planarization layer (PLN) and the flatness of other film layers besides the planarization layer below the anode. Generally, the flatness of the planarization layer is relatively good. It is sufficient to set the flatness of the film layers other than the planarization layer of multiple pixels to be consistent, that is, to keep the traces in multiple sub-pixels below the anode as consistent as possible. This ensures that the anode electrode differences of multiple sub-pixels are as consistent as possible, avoiding uneven light emission caused by inconsistent anode electrode differences.

[0234] For irregularly shaped display substrates, in the fourth conductive layer, each row of pixels has a signal trace extending along the first direction X (which may include at least one of the first transition connection electrode 51 and the second transition connection electrode 52 in the fourth conductive layer); in the fifth conductive layer, each column of pixels has b traces extending along the second direction Y (which may include at least one of the third transition connection electrode 61 and the fourth transition connection electrode 62 in the fifth conductive layer). A pixel comprises three sub-pixels (i.e., sub-pixels that emit red, green, and blue light). A corresponding column of pixels requires three data signal lines 48 connected to each of the three sub-pixels. For different display driver chips (driver ICs), there are three possible scenarios: First, the second initial signal line 49 can be connected to the driver IC via the second transition electrode 52 and the fourth transition electrode 62. In this case, the second transition electrode 52 needs to be set in the fifth conductive layer. Therefore, the number of signal traces extending along the second direction Y in a column of pixels is four (three first transition electrodes 51 corresponding to the three data signal lines and one fourth transition electrode 62 corresponding to the second initial signal line 49). In the second case, if the driver chip does not require the second initial signal line 49 to be connected via the second transition connection electrode 52 and the fourth transition connection electrode 62, then the space of one column of pixels needs to be configured with 3 signal traces extending along the second direction Y (3 data signal lines corresponding to the first transition connection electrode 51 and 1 second initial signal line 49 corresponding to the fourth transition connection electrode 62); in the third case, if two adjacent pixel columns share one second initial signal line 49, then the space of one column of pixels needs to be configured with 3.5 signal traces extending along the second direction Y (3 data signal lines corresponding to the first transition connection electrode 51 and 0.5 second initial signal lines 49 corresponding to the fourth transition connection electrode 62).

[0235] In an exemplary embodiment, in the fourth conductive layer, the number of traces extending along the first direction X in each row of pixel space is a, and in the fifth conductive layer, the number of traces extending along the second direction Y in each column of pixel space is b.

[0236] The resolution of the irregularly shaped display substrate is H*V. Depending on the driver IC model, the number of traces extending along the second direction Y on the irregularly shaped display substrate can be set to one of the following: 3H (no need to connect the initial signal line 49 to the IC), 3.5H (two pixel columns share one second initial signal line 49), or 4H. That is, the value of b can be one of 3, 3.5, or 4. The number of pixels near the Source In side of the irregularly shaped display substrate is H / x (x is the ratio of the maximum number of pixel columns H on the irregularly shaped display substrate to the number of pixel columns on the Source In side, generally an integer, with a minimum value of 1). Therefore, b*H / x ≥ 4*H, which can be simplified to b ≥ 4*x. For ease of explanation, the parameter p can be used to represent the number of traces along the second direction Y in a pixel column space. Thus, the inequality b*H / x ≥ 4*H can be written as b ≥ p*x. The number of traces along the second direction Y in a pixel column space is the number of transition connection electrodes extending along the second direction Y in a pixel column of the fifth conductive layer. In the exemplary embodiments of this disclosure, the number of pixel columns on the Source In side can be understood as the number of pixel columns in the display substrate where the third transition connection electrode 61 extends to the bonding area 10.

[0237] For irregularly shaped display substrates, the signal traces extending along the first direction X are mainly used to transfer the data signal line 48 and the second initial signal line 49 in the third conductive layer to the transfer connection electrode extending along the first direction X in the fourth conductive layer. The transfer connection electrode extending along the second direction Y in the fifth conductive layer is mainly used to transfer the signal traces in the fourth conductive layer to the driver IC, so that the driver chip (driver IC) can provide the corresponding drive signal to the data signal line 48 and the corresponding initial signal to the second initial signal line 49.

[0238] For an irregularly shaped display substrate with a resolution of H*V, the number of signal traces extending along the first direction X in the fourth conductive layer that penetrate the display area AA of the irregularly shaped display substrate in the first direction X is V / y, where y is the ratio of the maximum number of rows V of the irregularly shaped display substrate to the number of rows on the Source-in side. To facilitate the explanation of y, a heart-shaped display substrate is used as an example. Figure 19As shown, in the fourth conductive layer, there are V / y row pixel transition electrodes that penetrate the display area AA of the heart-shaped display substrate. Therefore, the total number of signal-transmitting (effective) transition electrodes in the fourth conductive layer is a*V / y. The total number of effective traces extending along the first direction X in the fourth conductive layer is consistent with the total number of traces extending along the second direction Y in the fifth conductive layer (the traces in the fifth conductive layer are for connecting the effective traces of the fourth conductive layer to the driver chip, so the total number of traces in these two conductive layers needs to be consistent). In actual design, the total number of effective traces extending along the first direction X in the fourth conductive layer is set to be no less than the total number of traces extending along the second direction Y in the fifth conductive layer. The total number of traces extending along the first direction X in the fourth conductive layer is a*V / y, and the total number of traces extending along the second direction Y in the fifth conductive layer is p*H. Therefore, a*V / y ≥ p*H. After simplification, we can obtain a ≥ p*y*H / V. In the exemplary embodiments of this disclosure, the number of rows on the Source in side can be understood as the number of pixel rows located in the second display area AA2 (i.e., the transfer connection electrode in the fourth conductive layer located in the second display area AA2 can eventually access the signal of the driver IC through the transfer connection electrode of the fifth conductive layer).

[0239] Considering that the quantities of a and b are both integers, and for the subsequent via connections between the fourth and third conductive layers, and between the fifth and fourth conductive layers, the value of p can be set to a common divisor of a and b. However, p might be a decimal (e.g., p = 3.5 if the second initial signal line is shared by two columns of pixels), in which case it needs to be calculated as 2p. Therefore, minimizing the value of p can reduce the values ​​of a and b. Based on the principle of minimizing a and b, and according to the above analysis, the values ​​of a and b can be obtained as follows:

[0240] a = [y*H / V]*p; b = [x]*p;

[0241] If 2p is an integer and p is a decimal, then the above formula can be written as: 2a = [y*H / V]*2p; 2b = [x]*2p. Taking a heart-shaped display substrate with a resolution of 1440*1440 as an example, setting p = 3.5, y = 1, x = 3, and substituting H = 1440 and V = 1440 into the above formula, we get 2a = 14 and 2b = 21. The corresponding schematic diagram of the display substrate planar structure can be seen as follows. Figure 15a As shown.

[0242] In this embodiment, the number of traces 'a' in the fourth conductive layer and the number of traces 'b' in the fifth conductive layer are directly related to the p value. The second initial signal line 49 can reduce the p value by using a pass line method. Therefore, setting P = 3, y = 1, and x = 3, and substituting H = 1440 and V = 1440 into the above formula, we get 2a = 12 and 2b = 18. The corresponding schematic diagram of the display substrate planar structure can be seen as follows. Figure 15d As shown, Figure 15d In the structure shown, the second initial signal line 49 does not pass through the driver IC to provide the signal, but instead passes through the signal path of the chip-on-film (COF). (The second initial signal line 49 does not pass through the IC chip to provide the signal, but the way the signal is provided through COF can be called a pass line.) This reduces the number of traces in the fourth and fifth conductive layers (reducing the number of the second transition connection electrode 52 in the fourth conductive layer and the fourth transition connection electrode 62 in the fifth conductive layer).

[0243] In an exemplary embodiment, the data signal lines 49 of three sub-pixels in a pixel can be merged according to the shape of the display substrate (this design method can be called the Triple Gate principle), which can reduce the number of traces in the fourth and fifth conductive layers (i.e., reduce the p value). In this design scheme, p=1, a=2, b=3, that is, two first transition connection electrodes extending along the first direction X are set in the fourth conductive layer in the space of each row of pixels, and three third transition connection electrodes 61 extending along the second direction Y are set in the fifth conductive layer in the space of each column of pixels. The planar structure schematic diagram of the display substrate can be shown as follows. Figure 20 As shown.

[0244] In an exemplary embodiment, for irregularly shaped display substrates, such as Figure 12b , Figure 13c , Figure 14 , Figure 15c As shown, the third conductive layer and the fourth conductive layer are electrically connected through the first transition via Vm1 and the second transition via Vm2, and the fourth conductive layer and the fifth conductive layer are electrically connected through the third transition via Vm3 and the fourth transition via Vm4. The first transition via Vm1 to the fourth transition via Vm4 are not present in every pixel; their placement is determined based on the shape of the irregularly shaped display substrate. This ensures that all data signal lines and initial signal lines are connected to the bonding area 10 of the display substrate through the traces in the fourth and fifth conductive layers. The bonding area 10 allows for the electrical connection of the traces in the fifth conductive layer to the driving device 20, which may include at least one of COF and IC chip. For a heart-shaped display substrate, the placement of the first to fourth vias can be as follows: Figure 21As shown, in the display area AA, the arrangement direction of the first transition via Vm1 and the second transition via Vm2 can form a first angle F1 with the center line Q1-Q1 extending along the second direction Y of the display substrate. The arrangement direction of the third transition via Vm3 to the fourth via Vm4 can form a second angle F2 with the center line Q1-Q1 extending along the second direction Y of the display substrate. For a heart-shaped display substrate, the value of the first angle F1 can be 45 degrees. Due to the influence of the irregular shape of the display substrate, the fourth conductive layer needs to transfer all data signal lines and the second initial signal lines in the third conductive layer to the transition connection electrode of the fourth conductive layer. Usually, the transition vias are designed according to the pitch between sub-pixels, that is, the arrangement direction of multiple transition vias is basically 45 degrees. However, due to the influence of the irregular screen, this direction cannot transfer all the data signal lines and transition connection electrodes of the third conductive layer to the fourth conductive layer. Therefore, some transition vias can be arranged in a vertical direction ( Figure 21 The material moves into the display area AA of the display substrate in the first direction X or the opposite direction of the first direction X, thus forming a shape like... Figure 21 The arrangement shown forms the upper and lower sections of the transition via.

[0245] In an exemplary embodiment, the fourth conductive layer may further include a second power line, and the display substrate may further include a bezel area 30, wherein the second power line VSS may be located in the bezel area 30, such as... Figure 22 As shown, the second power line VSS located on the fourth conductive layer can be electrically connected to the fourth conductive layer in the display area through the second power connection line 50. The second power line VSS can be composed of a double-layer structure of the third conductive layer and the fourth conductive layer. The double-layer structure can reduce the voltage drop of the second power line VSS. Since the fourth conductive layer is provided with the second power line VSS, the second power line VSS can be directly electrically connected to the fourth conductive layer located in the display area AA. Figure 22 40 is the package structure area, and 60 is the initial signal line.

[0246] This disclosure also provides a display device, including the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0247] The display substrate and display device provided in this disclosure include a display area in the display substrate comprising multiple data signal lines, multiple first transition connection electrodes, multiple third transition connection electrodes, and multiple sub-pixels arranged in an array. At least a portion of the first transition connection electrodes are electrically connected to the multiple data signal lines and to at least a portion of the third transition connection electrodes. One end of the third transition connection electrode connected to the at least a portion of the first transition connection electrodes is electrically connected to a bonding area. In the display area, the lengths of the multiple data signal lines along a second direction are not entirely the same. The multiple sub-pixels form multiple pixels arranged in an array, and each pixel includes at least three adjacent sub-pixels. The arrangement of the multiple first transition connection electrodes and the multiple third transition connection electrodes in two pixels is consistent. The display substrate provided in this disclosure, with the consistent arrangement of the multiple first transition connection electrodes and the multiple third transition connection electrodes in two pixels, ensures consistent anode step differences in the multiple pixels, effectively avoiding uneven light emission. The display substrate provided in this embodiment has multiple data signal lines in the display area with different lengths along the second direction. This can be applied to irregularly shaped display substrates and can avoid the phenomenon of uneven light emission caused by inconsistent anode polarity in irregularly shaped display substrates.

[0248] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, The device includes a display area and a bonding area connected to the display area. The display area includes multiple data signal lines extending along a second direction, multiple first transition connection electrodes extending along a first direction, multiple third transition connection electrodes extending along the second direction, and multiple sub-pixels arranged in an array. The multiple data signal lines are respectively connected to multiple columns of sub-pixels. The data signal lines, the first transition connection electrodes, and the third transition connection electrodes are respectively disposed on three conductive layers. At least a portion of the first adapter connection electrodes are electrically connected to multiple data signal lines respectively, and are also electrically connected to at least a portion of the third adapter connection electrodes respectively. One end of the third adapter connection electrode connected to the at least a portion of the first adapter connection electrodes is electrically connected to the bonding area. In the display area, the lengths of the multiple data signal lines along the second direction are not exactly the same. The multiple sub-pixels form a plurality of pixels arranged in an array, and each pixel includes at least three adjacent sub-pixels. The arrangement of the multiple first transition connection electrodes and the multiple third transition connection electrodes located in the two pixels is consistent. The display area includes a first display area and a second display area, and the arrangement of the first transition connection electrode, the third transition connection electrode, and the data signal line in the pixels located in the first display area and the second display area is the same.

2. The display substrate according to claim 1, characterized in that, A plurality of first transition connection electrodes located in the second display area penetrate the second display area along a first direction, and at least a portion of the first transition connection electrodes located in the second display area are electrically connected to a plurality of data signal lines respectively. A plurality of first transition connection electrodes located in the first display area do not penetrate the first display area of ​​the display substrate along the first direction. At least a portion of the third transition connection electrodes are electrically connected to a plurality of first transition connection electrodes located in the second display area respectively.

3. The display substrate according to claim 2, characterized in that, It also includes a plurality of second initial signal lines extending along a second direction, a plurality of second transition connection electrodes extending along a first direction, and a plurality of fourth transition connection electrodes extending along a second direction. The second initial signal lines are arranged in the same layer as the plurality of data signal lines, the plurality of second transition connection electrodes are arranged in the same layer as the plurality of first transition connection electrodes, and the plurality of fourth transition connection electrodes are arranged in the same layer as the plurality of third transition connection electrodes. A plurality of second transition connection electrodes located in the second display area penetrate the second display area of ​​the display substrate along a first direction and are electrically connected to a plurality of second initial signal lines respectively. A plurality of second transition connection electrodes located in the first display area do not penetrate the first display area of ​​the display substrate along the first direction. At least a portion of the fourth transition connection electrodes are electrically connected to a plurality of second transition connection electrodes located in the second display area respectively.

4. The display substrate according to claim 3, characterized in that, A pixel comprises three sub-pixels. In the same column of pixel space, there are three columns of sub-pixels and three data signal lines. The three columns of sub-pixels are connected to the three data signal lines respectively. Adjacent columns of pixels share a second initial signal line, which is located between the two adjacent columns of pixels. In the two columns of pixels sharing the second initial signal line, there are 20 third transition connection electrodes and 1 fourth transition connection electrode. Each column of pixel space has 10 third transition connection electrodes, and 1 fourth transition connection electrode is located between the two columns of pixels. Within the same row of pixel space, there are 6 first transition connection electrodes and 1 second transition connection electrode.

5. The display substrate according to claim 2, characterized in that, A pixel consists of three sub-pixels. In the same column of pixel space, there are three columns of sub-pixels, three data signal lines, and nine third transition connection electrodes. The three columns of sub-pixels are connected to the three data signal lines respectively. In the same row of pixel space, there are six first transition connection electrodes.

6. The display substrate according to claim 2, characterized in that, A pixel comprises three sub-pixels. In the same column of pixel space, there are three columns of sub-pixels, three data signal lines, and three third transition connection electrodes. The three columns of sub-pixels are connected to the three data signal lines respectively. In the same row of pixel space, there are two first transition connection electrodes.

7. The display substrate according to any one of claims 1 to 6, characterized in that, The display substrate includes a substrate, and the sub-pixel includes a first transistor to a fifth transistor disposed on the substrate and a storage capacitor. On a plane parallel to the display substrate, the second transistor, the first transistor, the third transistor, the fourth transistor, and the fifth transistor are arranged along a second direction. The orthographic projection of the storage capacitor on the substrate and the orthographic projection of the third transistor on the substrate have an overlapping area. Within the same pixel, two adjacent sub-pixels are symmetrically arranged with respect to a first center line, which is the center line extending from the two adjacent sub-pixels along a second direction.

8. The display substrate according to claim 7, characterized in that, Within the same column of subpixels, there are multiple subpixel groups, each subpixel group consisting of two adjacent subpixels. The two subpixels in the same subpixel group share a fifth transistor.

9. The display substrate according to claim 2, characterized in that, At least one sub-pixel includes a pixel driving circuit, which includes a plurality of oxide transistors and a storage capacitor; In a plane perpendicular to the display substrate, the display substrate includes a substrate and a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate; The semiconductor layer includes: an active layer of the plurality of oxide transistors; The first conductive layer includes: control electrodes of the plurality of oxide transistors and a first electrode of the storage capacitor; The second conductive layer includes: the second electrode of the storage capacitor; The third conductive layer includes: multiple data signal lines and multiple first and second electrodes of the oxide transistors; The fourth conductive layer includes: a plurality of the first transition connection electrodes; The fifth conductive layer includes a plurality of the third transition connection electrodes.

10. The display substrate according to claim 9, characterized in that, The third conductive layer further includes: a plurality of second initial signal lines extending along the second direction; two adjacent columns of pixels share a second initial signal line, and multiple data signal lines in the two columns of pixels sharing a second initial signal line are symmetrical with respect to the second initial signal line; The fourth conductive layer further includes: a plurality of second transition connection electrodes extending along a first direction, wherein the plurality of second transition connection electrodes located in the second display area are electrically connected to a plurality of second initial signal lines respectively; The fifth conductive layer further includes: a plurality of fourth transition connection electrodes extending along the second direction; the plurality of fourth transition connection electrodes are respectively electrically connected to a plurality of second transition connection electrodes located in the second display area.

11. The display substrate according to claim 9, characterized in that, The display substrate is heart-shaped, the bonding area is located on one side of the display area, and the first display area, the second display area, and the bonding area are arranged sequentially along the second direction.

12. The display substrate according to claim 11, characterized in that, At least a portion of the first adapter connection electrodes are electrically connected to the multiple data signal lines through multiple first adapter vias, and at least a portion of the third adapter connection electrodes are electrically connected to at least a portion of the first adapter connection electrodes through multiple third adapter vias. The arrangement direction of the multiple first adapter vias forms a first angle with the centerline of the display substrate extending along the second direction, and the arrangement direction of the multiple third adapter vias forms a second angle with the centerline of the display substrate extending along the second direction.

13. The display substrate according to claim 12, characterized in that, The first included angle is 30 to 60 degrees, and the second included angle is 15 to 45 degrees.

14. The display substrate according to claim 12, characterized in that, The arrangement of the plurality of first transition vias is symmetrical with respect to the centerline of the display substrate extending along the second direction, and the arrangement of the plurality of third transition vias is symmetrical with respect to the centerline of the display substrate extending along the second direction.

15. The display substrate according to claim 14, characterized in that, The display area located on one side of the centerline extending along the second direction of the display substrate has a plurality of first transition vias arranged in at least two directions, and the at least two arrangement directions are parallel to each other. The connecting lines of the plurality of first transition vias located in the at least two arrangement directions are arranged along the second direction. Multiple third adapter vias are arranged in at least two directions, and the at least two arrangement directions are parallel to each other. The connecting lines of the multiple third adapter vias located in the at least two arrangement directions are arranged in the second direction.

16. The display substrate according to claim 9, characterized in that, The fourth conductive layer further includes anode connection electrodes that are electrically connected to multiple sub-pixels respectively, and the orthographic projections of the first and third transfer connection electrodes on the substrate do not overlap with the orthographic projections of the multiple anode connection electrodes on the substrate.

17. The display substrate according to claim 16, characterized in that, It also includes an anode conductive layer, which includes a plurality of anodes, and the plurality of anodes are respectively connected to a plurality of anode connecting electrodes; the orthographic projection of the plurality of anodes in the same pixel on the substrate and the orthographic projection of the plurality of first connecting electrodes and the plurality of third connecting electrodes on the substrate have a first overlapping region, and the plurality of pixels correspond to a plurality of first overlapping regions, and the areas of the plurality of first overlapping regions are the same.

18. The display substrate according to any one of claims 1 to 6, 9 to 17, characterized in that, The dimension of the bonding area along the first direction is smaller than the dimension of the display area along the first direction. The plurality of third adapter connection electrodes include two parts: one extending to the bonding area and the other not extending to the bonding area. The plurality of third adapter connection electrodes extending to the bonding area are electrically connected to the plurality of first adapter connection electrodes located in the second display area.

19. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 18.

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