Power conversion device and heat pump system comprising the same

Abstract

In a case where a carrier frequency employed in generation of the drive signal (Sd) is set to fsw (kHz), a maximum input power of the power conversion section (10) is set to Pmax (kW), and a dead time of the drive signal (Sd) is set to Td (μs), a formula Td ≤ (34.00 / fsw - 0.145) (1.55 - 0.055*Pmax) holds.

Description

Technical Field

[0001] This disclosure relates to a power conversion device and a heat pump system including the power conversion device, the power conversion device comprising: a power conversion section for converting three-phase AC power output from an AC power source, and a current compensation section for causing a compensation current to flow into the AC power source. Background Technology

[0002] Patent Document 1 discloses a power conversion device comprising: a power conversion unit for converting three-phase AC power output from an AC power source, and a current compensation unit for channeling a compensation current into the AC power source. In this power conversion device, the current compensation unit includes a current compensation converter, a current compensation capacitor, a current compensation reactor, a compensation control unit, and a drive signal generation unit. The current compensation converter has multiple switching elements. The current compensation capacitor is connected between DC-side nodes of the current compensation converter. The current compensation reactor is connected between the AC-side of the current compensation converter and the AC power source. The compensation control unit calculates an output voltage command value to reduce high-order harmonic components in the power supply current from the AC power source to the power conversion device using the compensation current. The drive signal generation unit generates a drive signal based on the output voltage command value using a three-phase modulation method. The drive signal is used to drive the switching elements.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Publication No. 2015-92813 Summary of the Invention

[0006] -The technical problem the invention aims to solve-

[0007] Regarding the power conversion device including a current compensation section, as in Patent Document 1, if the proportion of the dead time in the carrier cycle of the converter for the current compensation section is increased, it may not be able to adequately compensate for the high-order harmonic components contained in the load current.

[0008] The purpose of this disclosure is to more effectively compensate for the high-order harmonic components contained in the load current in a power conversion device including a current compensation section.

[0009] - Technical solutions used to solve technical problems -

[0010] The first aspect of this disclosure is a power conversion device comprising a power conversion unit 10 for converting three-phase AC power output from an AC power source 2, and a current compensation unit 20 for allowing a compensation current Ia (uvw) to flow into the AC power source 2. The current compensation unit 20 is characterized by having a current compensation converter 21, a current compensation capacitor 22, a current compensation reactor 23, a compensation control unit 26, and a drive signal generation unit 27. The current compensation converter 21 has multiple switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The current compensation capacitor 22 is connected between DC-side nodes 21a and 21b of the current compensation converter 21. The current compensation reactor 23 is connected between the AC side of the current compensation converter 21 and the AC power source 2. The compensation control unit 26 calculates output voltage command values ​​Vid and Viq to utilize the compensation current Ia (uvw) to generate a current. a(uvw) reduces the high-order harmonic components contained in the power supply current Is(uvw) supplied from the AC power supply 2 to the power conversion device 100. The drive signal generation unit 27 generates a drive signal Sd based on the output voltage command values ​​Vid and Viq through a three-phase modulation method. The drive signal Sd is used to drive the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The current compensation unit converter 21, through the switching operation of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, causes the compensation current Ia(uvw) to flow into the AC power supply 2 via the current compensation unit reactor 23. When the carrier frequency used in the generation of the drive signal Sd is set to fsw (kHz), the maximum input power of the power conversion unit 10 is set to Pmax (kW), and the dead time of the drive signal Sd is set to Td (μs), the following equation (1) holds:

[0011] Td≤(34.00 / fsw-0.145)(1.55-0.055*Pmax)……(1).

[0012] In the first aspect, compared to the case where equation (1) does not hold, it is possible to effectively reduce the high-order harmonic components contained in the power supply current Is(uvw). Therefore, it is easy to make the power supply current Is(uvw) conform to the high-order harmonic standard IEC61000-3-2 established by the IEC (International Electrotechnical Commission).

[0013] The second aspect of this disclosure is a power conversion device comprising a power conversion unit 10 for converting three-phase AC power output from an AC power source 2, and a current compensation unit 20 for causing a compensation current Ia (uvw) to flow into the AC power source 2, characterized in that: the current compensation unit 20 includes a current compensation converter 21, a current compensation capacitor 22, a current compensation reactor 23, a compensation control unit 26, and a drive signal generation unit 27. The current compensation converter 21 has multiple switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The current compensation capacitor 22 is connected between the DC side nodes 21a and 21b of the current compensation converter 21. The current compensation reactor 23 is connected between the AC side of the current compensation converter 21 and the AC power supply 2. The compensation control unit 26 calculates the output voltage command values ​​Vid and Viq to reduce the high-order harmonic components contained in the power supply current Is(uvw) supplied from the AC power supply 2 to the power conversion device 100 using the compensation current Ia(uvw). The drive signal generation unit 27 is based on the output voltage command value Vid. d. Viq generates a drive signal Sd through a two-phase modulation method. The drive signal Sd is used to drive the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The current compensation unit converter 21, through the switching action of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, causes the compensation current Ia (uvw) to flow into the AC power supply 2 via the current compensation unit reactor 23. When the carrier frequency used in generating the drive signal Sd is set to fsw (kHz), the maximum input power of the power conversion unit 10 is set to Pmax (kW), and the dead time of the drive signal Sd is set to Td (μs), the following equation (2) holds:

[0014] Td≤(45.23 / fsw-0.135)(1.48-0.048*Pmax)……(2).

[0015] In the second aspect, compared to the case where equation (2) does not hold, it is possible to effectively reduce the high-order harmonic components contained in the power supply current Is(uvw). Therefore, it is easy to make the power supply current Is(uvw) conform to the high-order harmonic standard set by IEC, namely IEC61000-3-2.

[0016] Furthermore, because a two-phase modulation method is used when generating the drive signal Sd, the dead time can be set to be longer compared to the case of using a three-phase modulation method.

[0017] A third aspect of this disclosure is a power conversion device comprising a power conversion unit 10 for converting three-phase AC power output from an AC power source 2, and a current compensation unit 20 for allowing a compensation current Ia (uvw) to flow into the AC power source 2. The current compensation unit 20 comprises a current compensation converter 21, a current compensation capacitor 22, a current compensation reactor 23, a compensation control unit 26, and a drive signal generation unit 27. The current compensation converter 21 has multiple switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The current compensation capacitor 22 is connected between DC-side nodes 21a and 21b of the current compensation converter 21. The current compensation reactor 23 is connected between the AC side of the current compensation converter 21 and the AC power source 2. The compensation control unit 26 calculates output voltage command values ​​Vid and Viq to reduce the voltage supplied from the AC power source 2 to the power conversion device 10 using the compensation current Ia (uvw). The high-order harmonic components contained in the power supply current Is(uvw) of 0 are generated by the drive signal generation unit 27 based on the output voltage command values ​​Vid and Viq through a three-phase modulation method to generate a drive signal Sd. The drive signal Sd is used to drive the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The current compensation unit converter 21 transmits the power through the switching operation of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 via the current compensation unit reactor. 23. When the compensation current Ia (uvw) flows into the AC power supply 2, and the carrier frequency used in generating the drive signal Sd is set to fsw (kHz), the maximum input power of the power conversion unit 10 is set to Pmax (kW), the dead time of the drive signal Sd is set to Td (μs), and the inductance of the current compensation unit reactor 23 when the current flowing to the current compensation unit reactor 23 is 0A is set to Lac (mH), the following equations (3) and (4) hold:

[0018] Lac≤16 / Pmax……(3)

[0019] Td≤(34.00 / fsw-0.145)……(4).

[0020] In the third aspect, compared to the case where at least one of equations (3) and (4) is not true, it is possible to effectively reduce the high-order harmonic components contained in the power supply current Is(uvw). Therefore, it is easy to make the power supply current Is(uvw) conform to the high-order harmonic standard set by IEC, namely IEC61000-3-2.

[0021] The fourth aspect of this disclosure is a power conversion device comprising a power conversion unit 10 for converting three-phase AC power output from an AC power source 2, and a current compensation unit 20 for allowing a compensation current Ia (uvw) to flow into the AC power source 2. The current compensation unit 20 is characterized by having a current compensation converter 21, a current compensation capacitor 22, a current compensation reactor 23, a compensation control unit 26, and a drive signal generation unit 27. The current compensation converter 21 has multiple switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The current compensation capacitor 22 is connected between DC-side nodes 21a and 21b of the current compensation converter 21. The current compensation reactor 23 is connected between the AC side of the current compensation converter 21 and the AC power source 2. The compensation control unit 26 calculates output voltage command values ​​Vid and Viq to reduce the voltage supplied from the AC power source 2 to the power conversion device 100 using the compensation current Ia (uvw). The high-order harmonic components contained in the power supply current Is(uvw) are generated by the drive signal generation unit 27 based on the output voltage command values ​​Vid and Viq through a two-phase modulation method to generate a drive signal Sd. The drive signal Sd is used to drive the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The current compensation unit converter 21, through the switching operation of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, transmits the signal to the reactor (2) of the current compensation unit. 3) When the compensation current Ia (uvw) flows into the AC power supply 2, and the carrier frequency used in generating the drive signal Sd is set to fsw (kHz), the maximum input power of the power conversion unit 10 is set to Pmax (kW), the dead time of the drive signal Sd is set to Td (μs), and the inductance of the current compensation unit reactor 23 when the current flowing to the current compensation unit reactor 23 is 0A is set to Lac (mH), the following equations (5) and (6) hold:

[0022] Lac≤16 / Pmax……(5)

[0023] Td≤(45.23 / fsw-0.135)……(6).

[0024] In the fourth aspect, compared to the case where at least one of equations (5) and (6) is not true, it is possible to effectively reduce the high-order harmonic components contained in the power supply current Is(uvw). Therefore, it is easy to make the power supply current Is(uvw) conform to the high-order harmonic standard set by IEC, namely IEC61000-3-2.

[0025] Furthermore, because a two-phase modulation method is used when generating the drive signal Sd, the dead time can be set to be longer compared to the case of using a three-phase modulation method.

[0026] The fifth aspect of this disclosure is, based on the third or fourth aspect, characterized in that: the ratio of the inductance of the current compensation unit reactor 23 when the current flowing to the current compensation unit reactor 23 is a peak current to the inductance of the current compensation unit reactor 23 when the current flowing to the current compensation unit reactor 23 is 0A is set to 1 / 3 or more.

[0027] In the fifth aspect, compared with setting the ratio to less than 1 / 3, it is possible to more reliably reduce the high-order harmonic components contained in the power supply current Is(uvw) and to stably control the compensation current Ia(uvw).

[0028] The sixth aspect of this disclosure is, based on any one of the first to fifth aspects, characterized in that: a filter 24 exists between the AC power supply 2 and the current compensation reactor 23, the filter 24 having a filter reactor 24a with an inductance smaller than that of the current compensation reactor 23 and a filter capacitor 24b, and the resonant frequency of the filter 24 is set to 4 kHz or higher.

[0029] In the sixth aspect, at frequencies below 4kHz, the influence of the resonance of filter 24 on the compensation current Ia(uvw) can be reduced. Therefore, in the case of a three-phase AC frequency of 50Hz or 60Hz, the high-order harmonic components up to the 40th order contained in the power supply current Is(uvw) can be reliably reduced, and the compensation current Ia(uvw) can be stably controlled.

[0030] The seventh aspect of this disclosure is, based on the second or fourth aspect, characterized in that: the drive signal generation unit 27 generates the drive signal Sd based on the output voltage command values ​​Vid and Viq, such that the amplitude of the line-to-line voltage on the AC side of the converter 21 of the current compensation unit is at least 70% relative to the DC voltage Vdc between the DC side nodes 21a and 21b.

[0031] In the seventh aspect, compared with the case where the ratio is set to less than 70%, when switching the phase of the modulation target, the rapid change of the duty cycle of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 of the converter 21 for the current compensation section can be suppressed, and thus the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably.

[0032] The eighth aspect of this disclosure is, based on the second or fourth aspect, characterized in that: the compensation control unit 26 includes a voltage command value calculation unit 29 and a DC voltage command value calculation unit 28, wherein the voltage command value calculation unit 29 calculates the output voltage command values ​​Vid and Viq based on the DC voltage Vdc between the DC side nodes 21a and 21b of the current compensation unit converter 21 and the DC voltage command value Vdc*, and the DC voltage command value calculation unit 28 calculates the DC voltage command value Vdc* based on the output voltage command values ​​Vid and Viq, such that the DC voltage command value Vdc* is less than twice the average value of the line-to-line voltage on the AC side of the current compensation unit converter 21 or less than twice the fundamental frequency component.

[0033] In the eighth aspect, compared to the case where the DC voltage command value Vdc* is twice as high as the average value of the line-to-line voltage on the AC side of the current compensation converter 21 or twice as high as the fundamental frequency component, when switching the phase of the modulation target, the rapid change of the duty cycle of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 of the current compensation converter 21 can be suppressed, and thus the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably.

[0034] The ninth aspect of this disclosure is, based on any one of the first to eighth aspects, characterized in that: the power conversion unit 10 includes a rectifier circuit 11, a power conversion unit inverter 12, a power conversion unit capacitor 14, and a power conversion unit reactor 13; the rectifier circuit 11 rectifies the three-phase AC to DC; the power conversion unit inverter 12 converts the DC to AC; the power conversion unit capacitor 14 is connected between the DC side nodes 12a and 12b of the power conversion unit inverter 12, allowing the output voltage of the rectifier circuit 11 to vary; and the power conversion unit reactor 13 is connected between the AC power supply 2 and one end of the power conversion unit capacitor 14.

[0035] In the ninth aspect, since the filter LC1 is composed of the power conversion unit capacitor 14 and the power conversion unit reactor 13, by appropriately setting the capacitance of the power conversion unit capacitor 14, it is possible to suppress the current flowing between the power conversion unit inverter 12 and the AC power supply 2 from changing with the frequency of the carrier wave of the power conversion unit inverter 12 due to the switching operation of the power conversion unit inverter 12.

[0036] Furthermore, the capacitor 14 in the power conversion section allows the output voltage of the rectifier circuit 11 to fluctuate, thereby reducing the fluctuation of the compensation current Ia(uvw), and thus more reliably reducing the high-order harmonic components contained in the power supply current Is(uvw).

[0037] The tenth aspect of this disclosure is, based on the ninth aspect, characterized in that: the capacitance of the capacitor 22 for the current compensation section is larger than the capacitance of the capacitor 14 for the power conversion section.

[0038] In the tenth aspect, since the capacitance of the capacitor 22 for the current compensation section can be set to be large enough, the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably. This is such that the pulsation of the DC voltage Vdc between the DC side nodes 21a and 21b of the converter 21 for the current compensation section can be suppressed more effectively than the pulsation of the DC voltage between the DC side nodes 12a and 12b of the inverter 12 for the power conversion section.

[0039] The eleventh aspect of this disclosure is, based on any one of the first to tenth aspects, characterized in that: the current compensation converter 21 includes six unipolar transistors as the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, the six unipolar transistors forming three bridge arms, and the drive signal generation unit 27 generates the drive signal Sd so that the current compensation converter 21 performs synchronous rectification operation.

[0040] In the eleventh aspect, compared to using bipolar transistors as switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, the voltage generated when the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 are turned on can be reduced. Therefore, the error in the output voltage Va(uvw) output by the current compensation unit converter 21 relative to the output voltage command values ​​Vid and Viq caused by this voltage can be suppressed. Thus, the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably.

[0041] The twelfth aspect of this disclosure is, based on the eleventh aspect, characterized in that: the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 are elements made primarily of wide-bandgap semiconductors, and the on-resistance of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 is less than 100 mΩ.

[0042] In the twelfth aspect, the switching speed of switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 can be accelerated, thus easily shortening the dead time. Therefore, it is easy to reduce the high-order harmonic components contained in the power supply current Is(uvw).

[0043] The thirteenth aspect of this disclosure is, based on any one of the first to twelfth aspects, characterized in that: the carrier frequency is below 100 kHz.

[0044] In the thirteenth aspect, a longer dead time can be ensured compared to cases where the carrier frequency is higher than 100 kHz.

[0045] The fourteenth aspect of this disclosure is a heat pump system comprising the power conversion device described in any one of the first to thirteenth aspects, characterized in that: the three-phase AC is input to the power conversion unit 10 via three wires 601, 602, 603, and the 10 further comprises high-order harmonic generation sources 300, 400, which cause the current in at least one of the three wires 601, 602 to generate high-order harmonics.

[0046] In the fourteenth aspect, in the heat pump system 1, the high-order harmonic components contained in the power supply current Is(uvw) can be effectively reduced. Therefore, it is easy to make the power supply current Is(uvw) conform to the high-order harmonic standard set by IEC, namely IEC61000-3-2. Attached Figure Description

[0047] Figure 1 This is a block diagram showing the structure of an air conditioning system;

[0048] Figure 2 This is a block diagram illustrating the configuration of the power conversion device according to the first embodiment of this disclosure;

[0049] Figure 3 This is the circuit diagram of the converter used in the current compensation section;

[0050] Figure 4 It is a graph showing the relationship between the dead time of the drive signal and the ratio of the amount of higher harmonic components generated during the experiment to the maximum amount of higher harmonic components generated as specified in IEC61000-3-2 when using three-phase modulation.

[0051] Figure 5 It is a graph showing the relationship between the maximum input power of the power conversion unit and the ratio of the amount of higher harmonic components generated during the experiment to the maximum amount of higher harmonic components generated as specified in IEC61000-3-2 when using three-phase modulation and two-phase modulation.

[0052] Figure 6 This table shows the dead time when the generation of higher harmonic components in the power supply current reaches the maximum generation amount specified in IEC 61000-3-2, for various second carrier frequencies, using three-phase modulation and two-phase modulation.

[0053] Figure 7 Is with Figure 6The corresponding curve graph in the table;

[0054] Figure 8 It is a graph showing the maximum output as specified in IEC61000-3-2 when using three-phase modulation, and a graph showing the current values ​​corresponding to the orders of higher harmonic components contained in the power supply current when the second carrier frequency is set to 32kHz, the maximum input power of the power conversion unit is set to 10kW, and the dead time is set to 0.5μs and 1.0μs.

[0055] Figure 9A This is a timing diagram showing the power supply current, compensation current, and load current when the dead time of the drive signal is set to 0.5μs, the second carrier frequency is set to 16kHz, the maximum input power of the power conversion unit is set to 10kW, the inductance of the current compensation unit reactor is set to 1.0mH when the current flowing to the current compensation unit reactor is 0A.

[0056] Figure 9B This is equivalent to setting the maximum input power of the power conversion unit to 10kW, the inductance of the reactor in the current compensation unit to 2.2mH when the current flowing to the reactor in the current compensation unit is 0A. Figure 9A The image;

[0057] Figure 9C This is equivalent to setting the maximum input power of the power conversion unit to 5kW, the inductance of the reactor in the current compensation unit to 1.0mH when the current flowing to the reactor in the current compensation unit is 0A. Figure 9A The image;

[0058] Figure 9D This is equivalent to setting the maximum input power of the power conversion unit to 5kW, the inductance of the reactor in the current compensation unit to 2.2mH when the current flowing to the reactor in the current compensation unit is 0A. Figure 9A The image;

[0059] Figure 10 This is a circuit diagram showing the equivalent circuit of the current compensation unit;

[0060] Figure 11 This is a block diagram showing the current control system included in the current compensation section;

[0061] Figure 12A The graph shows the transfer functions Gp, Gc, and their combined gain.

[0062] Figure 12B The phase plots of the transfer functions Gp, Gc, and their sum are shown.

[0063] Figure 13AIt is a graph showing the DC superposition characteristics of the reactor for the current compensation section when the ratio of the inductance at peak current to the inductance at zero current is set to less than 1 / 3.

[0064] Figure 13B This is equivalent to setting the ratio of the inductance at peak current to the inductance at zero current to be more than 1 / 3. Figure 13A The image;

[0065] Figure 14A This example shows the timing diagrams of the power supply current, load current, and compensation current when the maximum input power of the power conversion unit is set to 10kW and the capacitance value of the capacitor used in the power conversion unit is set to absorb the output voltage fluctuations of the rectifier circuit.

[0066] Figure 14B This is equivalent to setting the capacitance value of the capacitor used in the power conversion section to allow for variations in the output voltage of the rectifier circuit. Figure 14A The image;

[0067] Figure 15A This is an example of a timing diagram showing the power supply current, compensation current, and DC voltage when the capacitance of the capacitor for the current compensation section is set to 195μF and the capacitance of the capacitor for the power conversion section is set to 30μF.

[0068] Figure 15B This is equivalent to setting the capacitance of the capacitor used in the current compensation section to 15μF and the capacitance of the capacitor used in the power conversion section to 30μF. Figure 15A The image;

[0069] Figure 16 It is a graph showing the relationship between the current flowing through the return diode and the forward voltage when a Si-PiN diode is set in parallel with the switching element in the opposite direction, and the relationship between the current flowing through the switching element in the opposite direction and the forward voltage when the switching element is a MOSFET.

[0070] Figure 17 When using binary phase modulation, it is equivalent to Figure 4 The image;

[0071] Figure 18 It is a graph showing the maximum output as specified in IEC61000-3-2 when using a two-phase modulation method, and a graph showing the current values ​​corresponding to the orders of the higher harmonic components contained in the power supply current when the second carrier frequency is set to 48kHz, the maximum input power of the power conversion unit is set to 10kW, and the dead time is set to 0.5μs and 1.0μs.

[0072] Figure 19AThis is a timing diagram showing the DC voltage, power supply current, load current, and compensation current when the second carrier frequency is set to 48kHz, the maximum input power of the power conversion unit is set to 10kW, and the dead time is set to 0.5μsec.

[0073] Figure 19B This is equivalent to setting the dead time to 1.0 μsec. Figure 19A The image;

[0074] Figure 20 This is a block diagram showing the configuration of the drive signal generation unit according to the second embodiment;

[0075] Figure 21A It is a graph showing the relationship between the duty cycle and phase of the three switching elements in the upper arm of the converter for the current compensation section when the modulation rate is set to 40%.

[0076] Figure 21B This is equivalent to setting the modulation rate to 70%. Figure 21A The image;

[0077] Figure 22 It is equivalent to the third embodiment. Figure 2 The image. Detailed Implementation

[0078] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the following embodiments are essentially preferred examples and are not intended to limit the scope of the invention, its application, or its uses.

[0079] (First Implementation)

[0080] Figure 1 An air conditioning system 1, which is a heat pump system, is shown. The air conditioning system 1 includes a power conversion device 100, a noise filter 200, an indoor unit 300 as a source of high-order harmonics, an outdoor fan 400 as a source of high-order harmonics, and a compressor 500, as described in the first embodiment of this disclosure.

[0081] The power conversion device 100 performs power conversion on the three-phase AC power output from the AC power source 2 and input through the noise filter 200. The AC power source 2 is a three-phase four-wire AC power source. The three-phase AC power is input to the power conversion device 100 through three wires: the first wire 601, the second wire 602, and the third wire 603.

[0082] The indoor unit 300 is driven by AC power drawn from the first conductor 601 and the neutral conductor 604. The indoor unit 300 generates high-order harmonics in the first conductor 601.

[0083] The outdoor fan 400 is driven by power drawn from the second conductor 602 and the neutral conductor 604. The outdoor fan 400 generates high-order harmonics in the second conductor 602.

[0084] Compressor 500 includes electric motor 501 (see reference) Figure 2 The motor 501 is supplied with AC power converted by the power conversion device 100.

[0085] Figure 2 As also shown, the power conversion device 100 includes a power conversion unit 10 and a current compensation unit 20.

[0086] The power conversion unit 10 performs power conversion on the three-phase AC power output from the AC power source 2 and input via the first wire 601, the second wire 602, and the third wire 603. Specifically, the power conversion unit 10 includes a rectifier circuit 11, an inverter 12 for the power conversion unit, a reactor 13 for the power conversion unit, a capacitor 14 for the power conversion unit, and a conversion control unit 15.

[0087] The rectifier circuit 11 rectifies the three-phase AC output from the AC power supply 2 into DC and outputs it to the first output node 11a and the second output node 11b. Specifically, the rectifier circuit 11 is a full-wave rectifier circuit. The rectifier circuit 11 has six diodes (not shown) with a bridge-shaped junction. The cathodes of these diodes face towards the first output node 11a, and their anodes face towards the second output node 11b.

[0088] The power conversion unit inverter 12 converts the DC output from the rectifier circuit 11 into AC and outputs it to the motor 501 of the compressor 500. Specifically, the power conversion unit inverter 12 has six switching elements (not shown) and six return diodes (not shown). The six switching elements are connected in a bridge configuration. That is, the power conversion unit inverter 12 includes three switching bridge arms connected between its first DC node 12a and second DC node 12b. Each switching bridge arm is formed by connecting two switching elements in series.

[0089] In each of the three switching arms, the midpoint between the switching element of the upper arm and the switching element of the lower arm is connected to the coils of each phase (U-phase, V-phase, W-phase coils) of the motor 501. Each switching element is connected in reverse parallel to a return diode.

[0090] One end of the power conversion unit reactor 13 is connected to the first output node 11a of the rectifier circuit 11, and the other end of the power conversion unit reactor 13 is connected to the first DC node 12a of the power conversion unit inverter 12.

[0091] The power conversion unit capacitor 14 is connected between the first DC node 12a and the second DC node 12b of the power conversion unit inverter 12. Therefore, the power conversion unit reactor 13 is connected between the AC power supply 2 and one end of the power conversion unit capacitor 14.

[0092] The capacitance value of capacitor 14 for the power conversion section is set such that it allows for fluctuations in the output voltage of rectifier circuit 11, but suppresses ripple voltage caused by the switching operation of inverter 12 for the power conversion section. Ripple voltage is voltage fluctuation corresponding to the switching frequency of the switching element. Therefore, the voltage of capacitor 14 for the power conversion section, i.e., the DC link voltage, contains a pulsating component corresponding to the frequency of the AC voltage of AC power supply 2.

[0093] In detail, the capacitance of the power conversion capacitor 14 is set such that the voltage fluctuation of the power conversion capacitor 14 during switching cycles is suppressed to less than 1 / 10 of the average voltage of the power conversion capacitor 14. Therefore, the minimum capacitance required for the power conversion capacitor 14 is determined based on the switching frequency and the motor current flowing between the motor 501 and the power conversion capacitor 14.

[0094] By setting the capacitance value C of the power conversion capacitor 14 to satisfy the following formula (I), the voltage fluctuation of the power conversion capacitor 14 during the switching cycle can be suppressed to less than 1 / 10 of the average voltage of the power conversion capacitor 14. In formula (I), the output voltage fluctuation of the rectifier circuit 11 superimposed on the DC link voltage is ignored, the average value of the DC link voltage is set as VAdc, the peak value of the motor current when the AC power is at maximum is set as Imax, and the switching cycle is set as Ts.

[0095] C≥(10·Imax·Ts) / VAdc……(I)

[0096] Here, the switching period is the period during which the switching element repeatedly turns on and off. In this first embodiment, the switching element is controlled by PWM (Pulse Width Modulation) control, therefore the switching period is the carrier period of the first carrier used for PWM control.

[0097] The capacitor 14 used in the power conversion section is, for example, a film capacitor.

[0098] The capacitance of capacitor 14 in the power conversion section is relatively small, therefore, the output voltage of rectifier circuit 11 is hardly smoothed out when capacitor 14 is used in the power conversion section. As a result, a pulsating component corresponding to the frequency of AC power supply 2 remains in the DC link voltage. Since AC power supply 2 is a three-phase power supply, the pulsating component corresponding to the frequency of AC power supply 2 is six times the frequency of AC power supply 2.

[0099] A power conversion unit filter LC1 is formed by the inductive component between the AC power supply 2 and the power conversion unit capacitor 14, and the power conversion unit capacitor 14 itself. The inductive component includes a reactor 13. The capacitance of the power conversion unit capacitor 14 is set such that the power conversion unit filter LC1 attenuates the component of the first carrier frequency contained in the current. Here, the first carrier frequency is the frequency of the first carrier used to generate the control signal for the power conversion unit inverter 12. Therefore, it is possible to suppress the variation of the current flowing between the power conversion unit inverter 12 and the AC power supply 2 with the frequency of the first carrier frequency due to the switching operation of the power conversion unit inverter 12.

[0100] The conversion control unit 15 controls the on / off state of each switching element of the inverter 12 for the power conversion unit through the control signal Smd.

[0101] The current compensation unit 20 causes a compensation current Ia(uvw) to flow into the AC power supply 2. Here, the compensation current Ia(uvw) is negative in the direction of flowing from the AC power supply 2 to the current compensation unit 20. For each phase, the power supply current Is(uvw) supplied by the AC power supply 2 is the difference between the load current Io(uvw) flowing from the AC power supply 2 to the power conversion unit 10 and the compensation current Ia(uvw).

[0102] The current compensation unit 20 includes a current compensation unit converter 21, a current compensation unit capacitor 22, a corresponding current compensation unit reactor 23, a corresponding current compensation unit filter 24, a voltage detector 25, a compensation control unit 26, and a drive signal generation unit 27.

[0103] like Figure 3 As shown, the current compensation converter 21 has six switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. The switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 are unipolar transistors, specifically MOSFETs (metal oxide semiconductor field effect transistors) using wide-bandgap semiconductors as the primary material. The on-resistance of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 is less than 100mΩ. The six switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 form three switching arms connected between their first DC-side node 21a and second DC-side node 21b. Each switching arm is formed by connecting two switching elements from each of the six switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 in series.

[0104] In each of the three switching arms, the midpoint between the switching elements Sr1, Ss1, St1 of the upper arm and the switching elements Sr2, Ss2, St2 of the lower arm is called the AC side node. Each switching element Sr1, Sr2, Ss1, Ss2, St1, St2 includes a parasitic diode RD. The parasitic diode RD acts as a return element that causes current to flow in the opposite direction.

[0105] It should be noted that IGBTs (Insulated Gate Bipolar Transistors), which are bipolar transistors, can also be used instead of unipolar transistors as switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. In this case, the return diodes are connected in reverse parallel to the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2.

[0106] As in this first embodiment, when using unipolar transistors as switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, the return diodes with forward voltages lower than the parasitic diode RD can be connected in reverse parallel one by one, just as in the case of using IGBTs.

[0107] A capacitor 22 for the current compensation section is connected between DC-side nodes 21a and 21b of the current compensation section converter 21. The voltage of the capacitor 22 for the current compensation section, which is the voltage between DC-side nodes 21a and 21b of the current compensation section converter 21, is called the DC voltage Vdc. The capacitance of the capacitor 22 for the current compensation section is larger than the capacitance of the capacitor 14 for the power conversion section.

[0108] One end of each phase's current compensation reactor (current compensation reactors for phases u, v, and w) 23 is connected to any AC side node of the current compensation converter 21. The other end of each current compensation reactor 23 is connected to the AC power supply 2 via its corresponding current compensation filter 24. In other words, the current compensation reactor 23 is connected between the AC side of the current compensation converter 21 and the AC power supply 2.

[0109] Each phase's current compensation filter 24 is located between the AC power supply 2 and the current compensation reactor 23. Each current compensation filter 24 has a filter reactor 24a with an inductance smaller than that of the current compensation reactor 23, and a filter capacitor 24b. The resonant frequency of each current compensation filter 24 is set to 4kHz or higher.

[0110] Voltage detector 25 detects the line-to-line voltage of two phases of the three-phase power supply voltage output from AC power supply 2.

[0111] According to the structure described above, the current compensation unit converter 21, through the switching operation of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, causes the compensation current Ia (uvw) to flow into the AC power supply 2 via the current compensation unit reactor 23.

[0112] The compensation control unit 26 calculates the output voltage command values ​​Vid and Viq based on the DC voltage Vdc between the DC side nodes 21a and 21b of the current compensation unit converter 21 and the load current Io(uvw) flowing from the AC power supply 2 into the power conversion unit 10, so as to reduce the high-order harmonic components contained in the power supply current Is(uvw) supplied to the power conversion device 100 by using the compensation current Ia(uvw). Specifically, the compensation control unit 26 includes a phase detection unit 26a, a first dq conversion unit 26b, a second dq conversion unit 26c, a high-pass filter 26d, a first subtraction unit 26e, a voltage control unit 26f, a first addition unit 26g, a second subtraction unit 26h, a third subtraction unit 26i, a first current control unit 26j, and a second current control unit 26k.

[0113] The phase detection unit 26a detects the phase ωt of the power supply voltage based on the line-to-line voltage detected by the voltage detector 25. It should be noted that it is also possible for the voltage detector 25 to detect the difference between the voltage of one phase of the three-phase power supply voltage output from the AC power supply 2 and the voltage of the neutral line 604, i.e., the phase voltage, and the phase detection unit 26a to detect the phase ωt of the power supply voltage based on this phase voltage.

[0114] The first dq conversion unit 26b detects the current il(rt) of at least two phases of the current il(rst) which is proportional to the load current Io(uvw), performs a three-phase / two-phase conversion, and obtains the d-axis component and q-axis component iq* of the load current Io(uvw). The d-axis and q-axis are coordinate axes of a rotating coordinate system synchronized with the phase ωt detected by the phase detection unit 26a. The d-axis component is the active component, and the q-axis component is the reactive component. Since the current il(rst) is three-phase, if the current il(rt) of two phases can be detected, the d-axis component and q-axis component iq* of the load current Io(uvw) can be obtained by calculating the remaining phase.

[0115] The second dq conversion unit 26c detects the reactor current ia(uv) of two phases of the current ia(uvw) proportional to the current flowing to the reactor 23 of the current compensation unit, performs a three-phase / two-phase conversion, and obtains the d-axis component id and q-axis component iq of the compensation current Ia(uvw). Since the current ia(uvw) is three-phase, if the current ia(uv) of two phases can be detected, the d-axis component id and q-axis component iq of the compensation current Ia(uvw) can be obtained by calculating the remaining phase.

[0116] The high-pass filter 26d outputs the high-frequency component idh of the d-axis component of the load current Io(uvw) obtained by the first dq conversion unit 26b.

[0117] The first subtraction unit 26e subtracts the DC voltage Vdc between the DC side nodes 21a and 21b of the current compensation unit converter 21 from the output voltage command value Vdc*, and outputs the subtraction result.

[0118] The voltage control unit 26f performs proportional-integral control on the subtraction result output by the first subtraction unit 26e to obtain a correction value.

[0119] The first adder 26g adds the high-frequency component idh of the d-axis component output by the high-pass filter 26d to the correction value obtained by the voltage control unit 26f, and outputs the sum as the command value id* of the d-axis component.

[0120] The second subtraction unit 26h subtracts the d-axis component id of the compensation current Ia(uvw) obtained by the second dq conversion unit 26c from the instruction value id* output by the first addition unit 26g, and outputs the subtraction result.

[0121] The third subtraction unit 26i subtracts the q-axis current iq of the compensation current Ia(uv) obtained by the second dq conversion unit 26c from the q-axis current iq* of the load current Io(uvw) obtained by the first dq conversion unit 26b, and outputs the subtraction result.

[0122] The first current control unit 26j generates an output voltage command value Vid for the d-axis component, so as to reduce the subtraction result output by the second subtraction unit 26h. The first current control unit 26j generates the output voltage command value Vid for the d-axis component, for example, through proportional-integral control.

[0123] The second current control unit 26k generates an output voltage command value Viq for the q-axis component, so that the subtraction result output by the third subtraction unit 26i is reduced. The second current control unit 26k generates the output voltage command value Viq for the q-axis component, for example, through proportional-integral control.

[0124] The drive signal generation unit 27 generates a drive signal Sd based on the output voltage command values ​​Vid and Viq using a three-phase modulation method, so that the current compensation unit converter 21 can perform synchronous rectification operation. The drive signal Sd is used to drive the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 of the current compensation unit converter 21. The frequency of the second carrier used to generate the drive signal Sd is set to 100kHz or less. When the drive signal Sd drives the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, if a dead time is set for the drive signal Sd, an error will occur between the actual output voltage Va(uvw) on the AC side of the current compensation unit converter 21 and the output voltage command values ​​Vid and Viq.

[0125] In the power conversion device 100 configured as described above, the relationship between the dead time of the drive signal Sd and the ratio of the amount of high-order harmonic components generated in the power supply current Is(uvw) during the experiment to the maximum amount of high-order harmonic components generated as specified in IEC61000-3-2 (the ratio of the experimental value to the standard value) is as follows: Figure 4 As shown, IEC61000-3-2 is a high-order harmonic standard developed by the IEC (International Electrotechnical Commission). Figure 4 The diagram illustrates various cases where the second carrier frequency is set to 16kHz, 32kHz, and 48kHz. The second carrier frequency is the frequency of the second carrier used to generate the drive signal Sd. Based on... Figure 4 The relationship shown suggests that the higher the second carrier frequency, the shorter the dead time needs to be in order for the power supply current Is(uvw) to conform to the standard.

[0126] Furthermore, in the power conversion device 100 configured as described above, the relationship between the maximum input power of the power conversion unit 10 and the generation amount of higher harmonic components contained in the power supply current Is(uvw) during the experiment, relative to the maximum generation amount of higher harmonic components specified in IEC61000-3-2 (the ratio of the experimental value to the standard value), is as follows: Figure 5 As shown. Figure 5 This indicates the cases where the second carrier frequency is set to 16kHz and the dead time is set to 3.0μs, and the driving signal Sd is generated using both three-phase modulation and two-phase modulation methods. Based on Figure 5 From the relationship shown, it can be deduced that the greater the maximum input power of the power conversion unit 10, the greater the amount of higher harmonic components generated.

[0127] Figure 6This table shows the dead time (μs) when the generation of higher harmonic components contained in the power supply current Is (uvw) reaches the maximum generation amount specified in IEC61000-3-2, for various second carrier frequencies, with the maximum input power of the power conversion unit 10 set to 10kW. Figure 7 Is with Figure 6 The corresponding curve graph in the table. Figure 6 and Figure 7 The dead time is shown when three-phase modulation is used and when two-phase modulation is used to generate the drive signal Sd.

[0128] Figure 8 The diagram shows the current values ​​corresponding to the orders of higher harmonic components contained in the power supply current Is(vw) when the second carrier frequency is set to 32kHz, the maximum input power of the power conversion unit 10 is set to 10kW, and the dead time is set to 0.5μs and 1.0μs. When the dead time is set to 1.0μs, the 35th higher harmonic component exceeds the maximum generation amount specified in IEC61000-3-2. When the dead time is set to 0.5μs, the higher harmonic components of all orders are less than the maximum generation amount specified in IEC61000-3-2.

[0129] Based on the above Figures 4-8 Based on the information shown, the inventors deduced that by setting the dead time of the drive signal Sd to make the following equation (II) true, the high-order harmonic components contained in the power supply current Is(uvw) can be effectively reduced, and the power supply current Is(uvw) can be easily made to comply with IEC61000-3-2.

[0130] In Equation (II), the second carrier frequency is set to fsw (kHz), the maximum input power of the power conversion unit 10 is set to Pmax (kW), and the dead time of the drive signal Sd is set to Td (μs).

[0131] Td≤(34.00 / fsw-0.145)(1.55-0.055*Pmax)……(II)

[0132] In this first embodiment, the drive signal generation unit 27 generates a drive signal Sd so that the above equation (II) is true.

[0133] Furthermore, in this first embodiment, the drive signal generation unit 27 generates a drive signal Sd so that, in addition to equation (II), equations (III) and (IV) below also hold true.

[0134] In equations (III) and (IV), the second carrier frequency is set to fsw (kHz), the maximum input power of the power conversion unit 10 is set to Pmax (kW), the dead time of the drive signal Sd is set to Td (μs), and the inductance of the current compensation unit reactor 23 when the current flowing to the current compensation unit reactor 23 is 0A is set to Lac (mH).

[0135] Lac≤16 / Pmax……(III)

[0136] Td≤(34.00 / fsw-0.145)……(IV)

[0137] Figure 9A The following figures illustrate the power supply current Is (uvw), compensation current Ia (uvw), and load current Io (uvw) when the dead time of the drive signal Sd is set to 0.5 μs, the second carrier frequency is set to 16 kHz, the maximum input power of the power conversion unit 10 is set to 10 kW, and the inductance of the current compensation unit reactor 23 is set to 1.0 mH when the current flowing to the current compensation unit reactor 23 is 0 A. Figure 9B This is equivalent to setting the dead time of the drive signal Sd to 0.5μs, the second carrier frequency to 16kHz, the maximum input power of the power conversion unit 10 to 10kW, and the inductance of the current compensation unit reactor 23 to 2.2mH when the current flowing to the current compensation unit reactor 23 is 0A. Figure 9A The image. Figure 9C This is equivalent to setting the dead time of the drive signal Sd to 0.5μs, the second carrier frequency to 16kHz, the maximum input power of the power conversion unit 10 to 5kW, and the inductance of the current compensation unit reactor 23 to 1.0mH when the current flowing to the current compensation unit reactor 23 is 0A. Figure 9A The image. Figure 9D This is equivalent to setting the dead time of the drive signal Sd to 0.5μs, the second carrier frequency to 16kHz, the maximum input power of the power conversion unit 10 to 5kW, and the inductance of the current compensation unit reactor 23 to 2.2mH when the current flowing to the current compensation unit reactor 23 is 0A. Figure 9A The image.

[0138] exist Figure 9B In the middle, because the inductance of the reactor 23 used in the current compensation section is higher than that of the reactor 23, the current compensation section is more efficient. Figure 9A The situation is large, so the slope of the change in the compensation current Ia(uvw) corresponding to the change in the load current Io(uvw) is greater than that of the other two. Figure 9AThe slope of the SLA is gentle, increasing the high-order harmonic components in the power supply current Is(uvw), resulting in waveform distortion. Therefore, it is difficult to make the power supply current Is(uvw) conform to IEC61000-3-2. Figure 9D In addition, due to the inductance ratio of the reactor 23 used in the current compensation section... Figure 9C The situation is large, so the slope of the change in the compensation current Ia(uvw) corresponding to the change in the load current Io(uvw) is greater than that of the other two. Figure 9C The slope of the SLC is gentle. However, because the maximum input power of the power conversion unit 10 is small, the high-order harmonic components contained in the power supply current Is(uvw) and the waveform distortion of the power supply current Is(uvw) are relatively small. Figure 9A They are roughly the same. Therefore, it is easy to make the power supply current Is(uvw) conform to IEC61000-3-2.

[0139] Furthermore, since the converter 21 for the current compensation unit is connected to the power supply system via the reactor 23 for the current compensation unit and the filter 24 for the current compensation unit, the circuit of the current compensation unit 20 can be... Figure 10 The equivalent circuit representation is shown below. Figure 10 In the above, let the power supply current Is(uvw) be i s The load current Io(uvw) is i i The power supply voltage is V s The output voltage va(uvw) of the current compensation unit converter 21 is v a The reactor current ia (uvw) flowing to the reactor 23 in the current compensation section is i a The inductance of the current compensation reactor 23 is La, the inductance of the filter reactor 24a is Lf, the capacitance of the filter capacitor 24b is Cf, and the current flowing through the filter reactor 24a is i. f The current flowing through capacitor 24b in the filter is i c The voltage across capacitor 24b in the filter is V. c i a Relative to v a The transfer function Gp is ​​represented by the following equation (V).

[0140] [Mathematical Expression 1]

[0141]

[0142] As shown in equation (V), if the inductance of the current compensation reactor 23 is larger than the inductance of the filter reactor 24a, the characteristics of the transfer function Gp will become approximately inversely proportional to the inductance of the current compensation reactor 23.

[0143] Furthermore, the compensation control unit 26 performs feedback control based on the detected reactor current ia (uvw) using the first current control unit 26j and the second current control unit 26k, so that the current values ​​id and iq calculated from the reactor current ia (uvw) are consistent with the command values ​​id* and iq* obtained by extracting higher harmonic components from the load current Io (uvw). If the transfer function of the output voltage Va (uvw) of the current compensation unit converter 21 relative to the reactor current ia (uvw) is set as Gc, the current control system included in the current compensation unit 20 can be represented as follows: Figure 11 As shown.

[0144] Figure 12A The graph shows the transfer functions Gp, Gc, and their combined gain. Figure 12B The phase diagrams of the transfer functions Gp, Gc, and their sum are shown. If the gain characteristics of the first current control unit 26j and the second current control unit 26k remain constant, then the overall gain characteristic of the current compensation unit 20 will vary with the inductance of the current compensation unit reactor 23. Figure 12A In the middle, resonance of the current compensation filter 24 occurred in the area surrounded by the dashed line.

[0145] To ensure the stability of current control, the DC superposition characteristic of the current compensation reactor 23 is preferably flat. If stability is ensured when the current flowing to the current compensation reactor 23 is a peak current, the control performance will decrease when this current is low, and the high-order harmonic components contained in the power supply current Is(uvw) will increase. By setting the ratio of the inductance at peak current to the inductance at zero current to more than 1 / 3, the stability of current control can be ensured, and the high-order harmonic current can be reduced. The peak current inductance is the inductance of the current compensation reactor 23 when the current flowing to it is a peak current, and the zero current inductance is the inductance of the current compensation reactor 23 when the current flowing to it is 0A.

[0146] In this first embodiment, the ratio of the inductance at peak current to the inductance at zero current is set to 1 / 3 or more.

[0147] exist Figure 13A In the figure, the peak current Ipeak is 12A, the inductance Lzero at zero current is 2.2mH, and the inductance Lpeak at peak current is 0.6mH. Therefore, the ratio of the inductance Lpeak at peak current to the inductance Lzero at zero current is less than 1 / 3.

[0148] exist Figure 13BIn the figure, the peak current Ipeak is 12A, the inductance Lzero at zero current is 1.3mH, and the inductance Lpeak at peak current is 0.6mH. Therefore, the ratio of the inductance Lpeak at peak current to the inductance Lzero at zero current is more than 1 / 3.

[0149] Figure 12A and Figure 12B As also shown, since the resonant frequency of the current compensation filter 24 is set to 4kHz or higher, the influence of the resonance of the current compensation filter 24 on the compensation current Ia(uvw) can be reduced at frequencies below 4kHz. Therefore, when the frequency of the three-phase AC is 50Hz or 60Hz, the high-order harmonic components up to the 40th order contained in the power supply current Is(uvw) can be reliably reduced, and the compensation current Ia(uvw) can be stably controlled.

[0150] As shown in equation (V), it is preferable to set the inductance of the filter reactor 24a to be smaller than the inductance of the current compensation reactor 23.

[0151] In this first embodiment, since the capacitance value of the power conversion capacitor 14 is set to be small enough to allow for fluctuations in the output voltage of the rectifier circuit 11, it is possible to reduce the fluctuation range of the output current of the rectifier circuit 11 and suppress the peak value of the compensation current Ia(uvw) compared to setting the capacitance value of the power conversion capacitor 14 to be large enough to absorb fluctuations in the output voltage of the rectifier circuit 11.

[0152] Figure 14A Examples are given for the power conversion unit 10 with its maximum input power set to 10kW and the capacitance value of the capacitor 14 for the power conversion unit set to absorb the output voltage fluctuation of the rectifier circuit 11, i.e., when a so-called capacitor input type is used, such as the power supply current Is (uvw), load current Io (uvw), and compensation current Ia (uvw). Figure 14B This is equivalent to setting the maximum input power of the power conversion unit 10 to 10kW and setting the capacitance value of the capacitor 14 for the power conversion unit to allow for variations in the output voltage of the rectifier circuit 11. Figure 14A The image.

[0153] exist Figure 14A In this example, the effective value of the compensation current Ia(uvw) is 6.8A, and the peak value of the compensation current Ia(uvw) is 15.3A. In contrast, in... Figure 14B In the above calculation, the effective value of the compensation current Ia(uvw) is 4.5A, and the peak value is 11.0A. This means that the effective and peak values ​​of the compensation current Ia(uvw) can be suppressed to... Figure 14A Two-thirds of the cases.

[0154] Furthermore, compared to the case where the capacitance of the capacitor 22 for the current compensation section is set to be less than or equal to the capacitance of the capacitor 14 for the power conversion section, the pulsation of the DC voltage Vdc between the DC side nodes 21a and 21b of the converter 21 for the current compensation section can be suppressed, so the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably.

[0155] Figure 15A Examples are given of the power supply current Is (uvw), compensation current Ia (uvw), and DC voltage Vdc when the capacitance of capacitor 22 for the current compensation section is set to 195μF and the capacitance of capacitor 14 for the power conversion section is set to 30μF. Figure 15B This is equivalent to setting the capacitance of capacitor 22 for the current compensation section to 15μF and the capacitance of capacitor 14 for the power conversion section to 30μF. Figure 15A The image.

[0156] exist Figure 15B In, with Figure 15A In comparison, the fluctuation range of DC voltage Vdc becomes larger, and the distortion of power supply current Is(uvw) becomes larger.

[0157] In this first embodiment, because unipolar transistors are used as the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 of the current compensation converter 21 for synchronous rectification, the turn-on voltage generated when the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 are turned on can be reduced compared to the case where bipolar transistors are used as the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2. Therefore, errors in the output voltage Va(uvw) of the current compensation converter 21 caused by this turn-on voltage can be suppressed, and the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably.

[0158] Figure 16 This is a graph showing the relationship between the current flowing through the return diode and the forward voltage when Si-PiN (Silicon p-intrinsic-n) diodes, which are arranged in reverse parallel with the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2, as return diodes; and the relationship between the current flowing through the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 in the reverse direction and the forward voltage when the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 are MOSFETs.

[0159] Here, the peak current flowing through the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 is set to 12A (in...). Figure 16 (represented by the symbol ip). Let the forward voltage of a typical diode be Vf, and the forward voltage of a MOSFET be Vsd. Thus, Vf is 1.8V. In contrast, if the on-resistance is 100mΩ, then as shown in equation (VI) below, Vsd is 1.1V.

[0160] Vsd=11A*0.1Ω=1.1V……(VI)

[0161] Therefore, according to this first embodiment, the drive signal generation unit 27 generates a drive signal Sd so that equations (II) to (IV) are satisfied, thus effectively reducing the high-order harmonic components contained in the power supply current Is(uvw). Therefore, it is easy to make the power supply current Is(uvw) conform to IEC61000-3-2.

[0162] Because the ratio of inductance Lpeak at peak current to inductance Lzero at zero current is set to more than 1 / 3, the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably compared to setting the ratio to less than 1 / 3, and the compensation current Ia(uvw) can be controlled stably.

[0163] By designing the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 as components primarily made of wide-bandgap semiconductors, and setting their on-resistance to below 100mΩ, it is easy to accelerate the switching speed of these elements and shorten the dead time. Consequently, it is easier to reduce the high-order harmonic components contained in the power supply current Is(uvw).

[0164] By setting the second carrier frequency below 100kHz, a longer dead time can be ensured compared to setting it above 100kHz.

[0165] (Second Implementation)

[0166] In this second embodiment, the drive signal generation unit 27 generates a drive signal Sd based on the output voltage command values ​​Vid and Viq using a two-phase modulation method, so that the current compensation unit can perform synchronous rectification operation using the converter 21. Other structures are the same as in the first embodiment.

[0167] When a two-phase modulation method is used in the generation of the drive signal Sd, the relationship between the dead time of the drive signal Sd and the ratio of the amount of higher harmonic components generated in the power supply current Is(uvw) during the experiment to the maximum amount of higher harmonic components generated as specified in IEC61000-3-2 (the ratio of the experimental value to the standard value) is as follows: Figure 17 As shown. Figure 17 The diagram illustrates various scenarios where the second carrier frequency is set to 16kHz, 32kHz, and 48kHz. Based on... Figure 17 The relationship shown suggests that the higher the second carrier frequency, the shorter the dead time needs to be in order for the power supply current Is(uvw) to conform to the standard.

[0168] Figure 18 The diagram shows the current values ​​of higher harmonic components in the power supply current Is(uvw) when using a binary phase modulation method, with the second carrier frequency set to 48kHz, the maximum input power of the power conversion unit 10 set to 10kW, and the dead time set to 0.5μsec and 1.0μsec. When the dead time is set to 1.0μsec, the 8th, 34th, 35th, and 40th higher harmonic components exceed the maximum generation amount specified in IEC 61000-3-2. When the dead time is set to 0.5μsec, the higher harmonic components of all orders are less than the maximum generation amount specified in IEC 61000-3-2.

[0169] Figure 19A The DC voltage Vdc, power supply current Is(uvw), load current Io(uvw), and compensation current Ia(uvw) are shown when the second carrier frequency is set to 48kHz, the maximum input power of the power conversion unit 10 is set to 10kW, and the dead time is set to 0.5μsec. Figure 19B This is equivalent to setting the second carrier frequency to 48kHz, the maximum input power of the power conversion unit 10 to 10kW, and the dead time to 1.0μsec. Figure 19A The diagram. As mentioned above, in Figure 19A In, with Figure 19B In comparison, the higher harmonic components contained in the power supply current Is(uvw) are reduced.

[0170] Based on the above Figure 6 , Figure 7 as well as Figures 17-18 Based on the information shown in 9, the inventors deduced that by setting the dead time of the drive signal Sd to make the following equation (VII) true, the high-order harmonic components contained in the power supply current Is(uvw) can be effectively reduced, and the power supply current Is(uvw) can be easily made to conform to IEC61000-3-2.

[0171] In Equation (VII), the second carrier frequency is set to fsw (kHz), the maximum input power of the power conversion unit 10 is set to Pmax (kW), and the dead time of the drive signal Sd is set to Td (μs).

[0172] Td≤(45.23 / fsw-0.135)(1.48-0.048*Pmax)……(VII)

[0173] In this second embodiment, the drive signal generation unit 27 generates a drive signal Sd so that the above equation (VII) is true.

[0174] Furthermore, in this second embodiment, the drive signal generation unit 27 generates a drive signal Sd so that, in addition to equation (VII), equations (VIII) and (IX) below also hold true.

[0175] In equations (VIII) and (IX), the second carrier frequency is set to fsw (kHz), the maximum input power of the power conversion unit 10 is set to Pmax (kW), the dead time of the drive signal is set to Td (μs), and the inductance of the current compensation unit reactor 23 when the current flowing to the current compensation unit reactor 23 is 0A is set to Lac (mH).

[0176] Lac≤16 / Pmax……(VIII)

[0177] Td≤(45.23 / fsw-0.135)……(IX)

[0178] In this second embodiment, the drive signal generation unit 27 generates a drive signal Sd based on the output voltage command values ​​Vid and Viq, so that the amplitude of the line-to-line voltage on the AC side is at least 70% relative to the DC voltage Vdc. Specifically, as... Figure 20 As shown, the drive signal generation unit 27 includes a modulation rate calculation unit 27a, a limiter 27b, and a PWM modulation unit 27c.

[0179] The modulation rate calculation unit 27a calculates the phase ψ and modulation rate ks based on the output voltage command values ​​Vid and Viq generated by the first current control unit 26j and the second current control unit 26k. The modulation rate ks refers to the ratio of the amplitude (maximum value) of the line-to-line voltage on the AC side to the DC voltage Vdc.

[0180] If the phase ψ is set to ψ and the output voltage command values ​​Vid and Viq are set to Vid and Viq respectively, then ψ can be calculated using the following formula (X).

[0181] ψ=tan －1 (Viq / Vid)……(X)

[0182] If the modulation rate ks is set to ks, then ks can be calculated based on the following equations (XI) and (XII). Here, Vi is the effective value of the line-to-line voltage on the AC side of the converter 21 for the current compensation section.

[0183] Vi = Vid / cosψ……(XI)

[0184] [Mathematical Expression 2]

[0185]

[0186] When the modulation rate ks calculated by the modulation rate calculation unit 27a is 0.7 or higher, the limiter 27b directly outputs the modulation rate ks calculated by the modulation rate calculation unit 27a. On the other hand, when the modulation rate ks is lower than 0.7, it outputs 0.7 as the modulation rate ks.

[0187] The PWM modulation unit 27c generates a drive signal Sd based on the phase ψ and modulation rate ks output by the limiter 27b. When generating the drive signal Sd by the PWM modulation unit 27c, a second carrier wave is used. The carrier frequency, also known as the second carrier frequency, is a frequency of 100Hz or less.

[0188] In this second embodiment, because the modulation rate ks is set to 70% or higher, compared to the case where the modulation rate ks is set to less than 70%, the rapid change in the duty cycle of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 of the current compensation converter 21 can be suppressed when switching the phase of the modulation target. Therefore, the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably.

[0189] Figure 21A The relationship between the duty cycle and phase of the three switching elements Sr1, Ss1, and St1 in the upper arm of the current compensation converter 21 is shown when the modulation rate ks is set to 40%. Figure 21B This is equivalent to setting the modulation rate ks to 70%. Figure 21A The figure shows that, compared to the case where the modulation rate ks is set to 40%, when the modulation rate ks is set to 70% or higher, the change in the duty cycle of the switching elements Sr1, Ss1, and St1 of the current compensation converter 21 is smaller when switching the phase of the modulation target.

[0190] Therefore, according to this second embodiment, the drive signal generation unit 27 generates a drive signal Sd so that equations (VII) to (IX) are satisfied, thus effectively reducing the high-order harmonic components contained in the power supply current Is(uvw). Therefore, it is easy to make the power supply current Is(uvw) conform to IEC61000-3-2.

[0191] (Third Implementation)

[0192] Figure 22 The power conversion device 100 according to the third embodiment of this disclosure is shown.

[0193] In this third embodiment, the drive signal generation unit 27 does not include the limiter 27b, and the PWM modulation unit 27c generates the drive signal Sd based on the modulation rate ks output by the modulation rate calculation unit 27a.

[0194] The compensation control unit 26 also includes a DC voltage command value calculation unit 28.

[0195] The DC voltage command value calculation unit 28 calculates the DC voltage command value Vdc* based on the output voltage command value Vid of the d-axis component, so that the DC voltage command value Vdc* is less than twice the average value of the line-to-line voltage on the AC side of the converter 21 for the current compensation unit. Specifically, the DC voltage command value calculation unit 28 has an average value calculation unit 28a and a multiplication unit 28b.

[0196] The average value calculation unit 28a calculates the average value of the output voltage command value Vid of the d-axis component.

[0197] Multiplication unit 28b multiplies the average value calculated by average value calculation unit 28a by a specified gain K. VI Calculate the DC voltage command value Vdc*. Specify the gain K. VI It is set to 2 or below.

[0198] The phase detection unit 26a, the first dq conversion unit 26b, the second dq conversion unit 26c, the high-pass filter 26d, the first subtraction unit 26e, the voltage control unit 26f, the first addition unit 26g, the second subtraction unit 26h, the third subtraction unit 26i, the first current control unit 26j, and the second current control unit 26k of the compensation control unit 26 constitute a voltage command value calculation unit 29 that calculates the output voltage command values ​​Vid and Viq based on the DC voltage Vdc and the DC voltage command value Vdc*.

[0199] It should be noted that, alternatively, the DC voltage command value calculation unit 28 can calculate the DC voltage command value Vdc* based on the effective value of the line-to-line voltage on the AC side of the current compensation unit converter 21, so that the DC voltage command value Vdc* is less than twice the average value of the line-to-line voltage on the AC side of the current compensation unit converter 21. The relationship between the effective value of the line-to-line voltage on the AC side of the current compensation unit converter 21 and the output voltage command value Vid of the d-axis component is shown in equation (XI).

[0200] The other structures are the same as in the second embodiment, therefore the same reference numerals are used to label the same structures and their detailed descriptions are omitted.

[0201] Therefore, according to this third embodiment, the DC voltage command value Vdc* is calculated such that it is less than twice the average value of the line-to-line voltage on the AC side of the current compensation converter 21, so that the amplitude of the AC side line-to-line voltage is more than 70% relative to the DC voltage Vdc. Therefore, compared to the case where the DC voltage command value Vdc* is more than twice the average value of the line-to-line voltage on the AC side of the current compensation converter 21, when switching the phase of the modulation target, the rapid change of the duty cycle of the switching elements Sr1, Sr2, Ss1, Ss2, St1, and St2 of the current compensation converter 21 can be suppressed, and the high-order harmonic components contained in the power supply current Is(uvw) can be reduced more reliably.

[0202] (Other variations)

[0203] In the first to third embodiments described above, the high-order harmonic generation source is connected to the first wire 601 and the second wire 602 of the first wire 601, the second wire 602 and the third wire 603. However, it may also be connected to only one of the first wire 601, the second wire 602 and the third wire 603, or it may be connected to all three wires.

[0204] In the third embodiment described above, the DC voltage command value calculation unit 28 calculates the DC voltage command value Vdc* such that the DC voltage command value Vdc* is less than twice the average value of the line-to-line voltage on the AC side of the current compensation unit converter 21. However, it is also possible to calculate so that the DC voltage command value Vdc* is less than twice the fundamental frequency component of the line-to-line voltage on the AC side of the current compensation unit converter 21. That is, it is also possible that the average value calculation unit 28a calculates the fundamental frequency component of the output voltage command value Vid of the d-axis component.

[0205] In the first embodiment described above, the drive signal generation unit 27 generates a drive signal Sd to satisfy equations (II) to (IV). However, it may also generate a drive signal Sd that satisfies only equations (III) and (IV) but not equation (II). Alternatively, it may generate a drive signal Sd that satisfies equation (II) but not both or one of equations (III) and (IV).

[0206] In the second embodiment, the drive signal generation unit 27 generates a drive signal Sd to satisfy equations (VII) to (IX), but it may also generate a drive signal Sd that only satisfies equations (VIII) and (IX) and does not satisfy equation (VII). Alternatively, it may generate a drive signal Sd that satisfies equation (VII) but does not satisfy either or both of equations (VIII) and (IX).

[0207] In the first to third embodiments described above, the power conversion device 100 is installed in the air conditioning system 1, but it can also be installed in other heat pump systems used for regulating temperature or humidity. Specifically, it can also be installed in heat pump systems such as heating and hot water supply systems, display cabinets for regulating internal temperature, refrigerators, freezers, and water heaters.

[0208] -Industry Applicability-

[0209] In summary, this disclosure is useful for power conversion devices and heat pump systems including such power conversion devices, which include: a power conversion unit for converting three-phase AC power output from an AC power source, and a current compensation unit for causing a compensation current to flow into the AC power source.

[0210] - Symbol Explanation -

[0211] 1. Air conditioning system (heat pump system)

[0212] 2 AC power supply

[0213] 10 Power Conversion Section

[0214] 11 Rectifier Circuit

[0215] 12 Inverters for power conversion section

[0216] 12a First DC Node

[0217] 12b Second DC Node

[0218] 13. Reactors for power conversion section

[0219] 14 Capacitors for power conversion section

[0220] 20 Current Compensation Unit

[0221] 21. Converter for Current Compensation Section

[0222] DC nodes 21a and 21b

[0223] 22 Capacitors for current compensation section

[0224] 23. Reactors for current compensation section

[0225] 24. Filter for current compensation section

[0226] 24A filter reactor

[0227] 24b filter capacitor

[0228] 26. Compensation and Control Department

[0229] 27 Drive Signal Generation Unit

[0230] 28 DC Voltage Command Value Calculation Unit

[0231] 29 Voltage Command Value Calculation Unit

[0232] 100 Power Conversion Device

[0233] 300 Indoor Unit (High-Order Harmonic Generation Source)

[0234] 400 Outdoor Fan (High-Order Harmonic Generation Source)

[0235] 601 First Conductor

[0236] 602 Second Conductor

[0237] 603 Third Conductor

[0238] Ia(uvw) compensation current

[0239] Io(uvw) load current

[0240] Vid, Viq output voltage command values

[0241] Vdc DC voltage

[0242] Vdc* DC voltage command value

[0243] Sr1, Sr2, Sr3, Sr4, Sr5, Sr6 switching elements

[0244] Sd drive signal

Claims

1. A power conversion device comprising a power conversion unit (10) for converting three-phase AC power output from an AC power source (2), and a current compensation unit (20) for allowing a compensation current (Ia(uvw)) to flow into the AC power source (2), characterized in that: The current compensation unit (20) includes a current compensation unit converter (21), a current compensation unit capacitor (22), a current compensation unit reactor (23), a compensation control unit (26), and a drive signal generation unit (27). The current compensation unit converter (21) has multiple switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2). The capacitor (22) of the current compensation unit is connected between the DC side nodes (21a, 21b) of the current compensation unit converter (21). The current compensation unit reactor (23) is connected between the AC side of the current compensation unit converter (21) and the AC power supply (2). The compensation control unit (26) calculates the output voltage command values ​​(Vid, Viq) so as to reduce the high-order harmonic components contained in the power supply current (Is(uvw)) supplied from the AC power source (2) to the power conversion device (100) using the compensation current (Ia(uvw)). The drive signal generation unit (27) generates a drive signal (Sd) based on the output voltage command value (Vid, Viq) using a three-phase modulation method. The drive signal (Sd) is used to drive the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2). The current compensation unit converter (21) uses the switching action of the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2) to make the compensation current (Ia(uvw)) flow into the AC power supply (2) via the current compensation unit reactor (23). When the carrier frequency used in generating the drive signal (Sd) is set to fsw (kHz), the maximum input power of the power conversion unit (10) is set to Pmax (kW), and the dead time of the drive signal (Sd) is set to Td (μs), the following equation (1) holds: Td≤(34.00 / fsw-0.145)(1.55-0.055*Pmax)……(1).

2. A power conversion device comprising a power conversion unit (10) for converting three-phase AC power output from an AC power source (2), and a current compensation unit (20) for allowing a compensation current (Ia(uvw)) to flow into the AC power source (2), characterized in that: The current compensation unit (20) includes a current compensation unit converter (21), a current compensation unit capacitor (22), a current compensation unit reactor (23), a compensation control unit (26), and a drive signal generation unit (27). The current compensation unit converter (21) has multiple switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2). The capacitor (22) of the current compensation unit is connected between the DC side nodes (21a, 21b) of the current compensation unit converter (21). The current compensation unit reactor (23) is connected between the AC side of the current compensation unit converter (21) and the AC power supply (2). The compensation control unit (26) calculates the output voltage command values ​​(Vid, Viq) so as to reduce the high-order harmonic components contained in the power supply current (Is(uvw)) supplied from the AC power source (2) to the power conversion device (100) using the compensation current (Ia(uvw)). The drive signal generation unit (27) generates a drive signal (Sd) based on the output voltage command value (Vid, Viq) through a two-phase modulation method. The drive signal (Sd) is used to drive the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2). The current compensation unit converter (21) uses the switching action of the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2) to make the compensation current (Ia(uvw)) flow into the AC power supply (2) via the current compensation unit reactor (23). When the carrier frequency used in generating the drive signal (Sd) is set to fsw (kHz), the maximum input power of the power conversion unit (10) is set to Pmax (kW), and the dead time of the drive signal (Sd) is set to Td (μs), the following equation (2) holds: Td≤(45.23 / fsw-0.135)(1.48-0.048*Pmax)......(2).

3. A power conversion device comprising a power conversion unit (10) for converting three-phase AC power output from an AC power source (2), and a current compensation unit (20) for allowing a compensation current (Ia(uvw)) to flow into the AC power source (2), characterized in that: The current compensation unit (20) includes a current compensation unit converter (21), a current compensation unit capacitor (22), a current compensation unit reactor (23), a compensation control unit (26), and a drive signal generation unit (27). The current compensation unit converter (21) has multiple switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2). The capacitor (22) of the current compensation unit is connected between the DC side nodes (21a, 21b) of the current compensation unit converter (21). The current compensation unit reactor (23) is connected between the AC side of the current compensation unit converter (21) and the AC power supply (2). The compensation control unit (26) calculates the output voltage command values ​​(Vid, Viq) so as to reduce the high-order harmonic components contained in the power supply current (Is(uvw)) supplied from the AC power source (2) to the power conversion device (100) using the compensation current (Ia(uvw)). The drive signal generation unit (27) generates a drive signal (Sd) based on the output voltage command value (Vid, Viq) using a three-phase modulation method. The drive signal (Sd) is used to drive the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2). The current compensation unit converter (21) uses the switching action of the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2) to make the compensation current (Ia(uvw)) flow into the AC power supply (2) via the current compensation unit reactor (23). When the carrier frequency used in generating the drive signal (Sd) is set to fsw (kHz), the maximum input power of the power conversion unit (10) is set to Pmax (kW), the dead time of the drive signal (Sd) is set to Td (μs), and the inductance of the current compensation unit reactor (23) when the current flowing to the current compensation unit reactor (23) is 0A is set to Lac (mH), the following equations (3) and (4) hold true: Lac≤16 / Pmax ……(3) Td≤(34.00 / fsw-0.145)……(4).

4. A power conversion device comprising a power conversion unit (10) for converting three-phase AC power output from an AC power source (2), and a current compensation unit (20) for allowing a compensation current (Ia(uvw)) to flow into the AC power source (2), characterized in that: The current compensation unit (20) includes a current compensation unit converter (21), a current compensation unit capacitor (22), a current compensation unit reactor (23), a compensation control unit (26), and a drive signal generation unit (27). The current compensation unit converter (21) has multiple switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2). The capacitor (22) of the current compensation unit is connected between the DC side nodes (21a, 21b) of the current compensation unit converter (21). The current compensation unit reactor (23) is connected between the AC side of the current compensation unit converter (21) and the AC power supply (2). The compensation control unit (26) calculates the output voltage command values ​​(Vid, Viq) so as to reduce the high-order harmonic components contained in the power supply current (Is(uvw)) supplied from the AC power source (2) to the power conversion device (100) using the compensation current (Ia(uvw)). The drive signal generation unit (27) generates a drive signal (Sd) based on the output voltage command value (Vid, Viq) through a two-phase modulation method. The drive signal (Sd) is used to drive the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2). The current compensation unit converter (21) uses the switching action of the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2) to make the compensation current (Ia(uvw)) flow into the AC power supply (2) via the current compensation unit reactor (23). When the carrier frequency used in generating the drive signal (Sd) is set to fsw (kHz), the maximum input power of the power conversion unit (10) is set to Pmax (kW), the dead time of the drive signal (Sd) is set to Td (μs), and the inductance of the current compensation unit reactor (23) when the current flowing to the current compensation unit reactor (23) is 0A is set to Lac (mH), the following equations (5) and (6) hold true: Lac≤16 / Pmax ……(5) Td≤(45.23 / fsw-0.135)……(6).

5. The power conversion device according to claim 3 or 4, characterized in that: The ratio of the inductance of the current compensation unit reactor (23) when the current flowing to the current compensation unit reactor (23) is the peak current to the inductance of the current compensation unit reactor (23) when the current flowing to the current compensation unit reactor (23) is 0A is set to 1 / 3 or more.

6. The power conversion device according to any one of claims 1 to 4, characterized in that: There is a filter (24) between the AC power supply (2) and the current compensation unit reactor (23). The filter (24) has a filter reactor (24a) with an inductance smaller than that of the current compensation unit reactor (23) and a filter capacitor (24b). The resonant frequency of the filter (24) is set to 4 kHz or higher.

7. The power conversion device according to claim 2 or 4, characterized in that: The drive signal generation unit (27) generates the drive signal (Sd) based on the output voltage command value (Vid, Viq) so that the amplitude of the line-to-line voltage on the AC side of the converter (21) of the current compensation unit is 70% or more relative to the DC voltage (Vdc) between the DC side nodes (21a, 21b).

8. The power conversion device according to claim 2 or 4, characterized in that: The compensation control unit (26) includes a voltage command value calculation unit (29) and a DC voltage command value calculation unit (28). The voltage command value calculation unit (29) calculates the output voltage command value (Vid, Viq) based on the DC voltage (Vdc) and DC voltage command value (Vdc*) between the DC side nodes (21a, 21b) of the converter (21) used by the current compensation unit. The DC voltage command value calculation unit (28) calculates the DC voltage command value (Vdc*) based on the output voltage command value (Vid, Viq) so that the DC voltage command value (Vdc*) is less than twice the average value of the line-to-line voltage on the AC side of the converter (21) of the current compensation unit or less than twice the fundamental frequency component.

9. The power conversion device according to any one of claims 1 to 4, characterized in that: The power conversion unit (10) includes a rectifier circuit (11), an inverter (12) for the power conversion unit, a capacitor (14) for the power conversion unit, and a reactor (13) for the power conversion unit. The rectifier circuit (11) rectifies the three-phase AC into DC. The power conversion unit uses an inverter (12) to convert the DC to AC. The capacitor (14) of the power conversion section is connected between the DC-side nodes (12a, 12b) of the inverter (12) of the power conversion section, allowing the output voltage of the rectifier circuit (11) to vary. The power conversion unit reactor (13) is connected between the AC power supply (2) and one end of the power conversion unit capacitor (14).

10. The power conversion device according to claim 9, characterized in that: The capacitance of the capacitor (22) used in the current compensation section is greater than the capacitance of the capacitor (14) used in the power conversion section.

11. The power conversion device according to any one of claims 1 to 4, characterized in that: The current compensation unit uses a converter (21) comprising six unipolar transistors as switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2), which form three bridge arms. The drive signal generation unit (27) generates the drive signal (Sd) so that the current compensation unit performs synchronous rectification operation using the converter (21).

12. The power conversion device according to claim 11, characterized in that: The switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2) are components made primarily of wide-bandgap semiconductors. The on-resistance of the switching elements (Sr1, Sr2, Ss1, Ss2, St1, St2) is less than 100mΩ.

13. The power conversion device according to any one of claims 1 to 4, characterized in that: The carrier frequency is below 100kHz.

14. A heat pump system comprising the power conversion device according to any one of claims 1 to 13, characterized in that: The three-phase AC power is input to the power conversion unit (10) via three wires (601, 602, 603). The heat pump system (1) further includes a high-order harmonic generation source (300, 400), which causes the current in at least one of the three wires (601, 602) to generate high-order harmonics.

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