A method for implementing self-testing, a computer storage medium, and a terminal.
By instantiating two identical acquisition function units inside the FPGA, inputting analog signals respectively and adjusting the channel input to a preset waveform, the problem of lack of self-testing in track circuit signal acquisition and processing is solved, and safe and reliable acquisition and processing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING HOLLYSYS
- Filing Date
- 2022-12-21
- Publication Date
- 2026-06-30
AI Technical Summary
In existing technologies, the analog signal acquisition and processing of track circuits implemented by FPGAs lacks self-testing functions, and there is a risk of logic gate sticking and hardening, which cannot meet the fault safety principle.
Two identical acquisition function units are instantiated inside the FPGA, and analog signals are input to them respectively. The input of one of the channels is adjusted to a preset waveform occupied by the track. The self-test result is determined by comparing the output results, thus realizing the self-test of the acquisition and processing function.
The self-test of the track circuit signal acquisition module was implemented to ensure the reliability and security of the acquisition and processing functions, and to avoid the risk of logic gate sticking and solidification.
Smart Images
Figure CN116243226B_ABST
Abstract
Description
Technical Field
[0001] This article relates to, but is not limited to, rail transit technology, and in particular to a method for implementing self-testing, computer storage media, and terminal. Background Technology
[0002] A 25 Hz phase-sensitive track circuit signal acquisition module implemented entirely electronically. Figure 1 For related technology track circuit signal acquisition modules, such as Figure 1 As shown, the track circuit signal acquisition module adopts a two-out-of-two architecture, meaning that both channels use identical hardware designs. The single channel is based on a digital signal processor (DSP) and a field-programmable logic array (FPGA). The FPGA is responsible for driving the analog-to-digital converter (ADC) chip to complete the AC acquisition of signals such as local voltage and track voltage, and performing digital filtering, RMS value, phase difference, and frequency calculations on the acquired signals. Finally, all calculation results are reported to the DSP via the local bus, which performs functions such as voting on the acquired values of the two channels, determining clearing / occupancy, and data reporting.
[0003] The ADC conditioning circuit in the track circuit signal acquisition module, such as Figure 2 As shown, for the externally input 25Hz analog signal from the track circuit, the ADC conditioning circuit converts the input analog signal into a current signal through a precision resistor. A 1:1 current transformer is used to isolate the current signal. The isolated current signal is then amplified and adjusted by an operational amplifier before being sent to the ADC chip. The FPGA reads the ADC chip's registers via the Serial Peripheral Interface (SPI) bus, thereby acquiring the analog signal from the track circuit (including two local voltage signals used as reference standards and six track voltage signals). The FPGA acts as a coprocessor for the DSP, and its acquisition function unit is implemented as follows... Figure 3 As shown, the track circuit signal acquisition module is powered on, initializes and configures the ADC chip, and then acquires analog signals. The low-pass filter inside the FPGA performs low-pass filtering on the acquired signals. Based on the filtered signals, parameters such as effective value, phase, and frequency are calculated. The local voltage and track voltage are standard 25Hz sine waves, so the effective value is calculated by multiplying the maximum value by 0.707. The phase represents the phase difference between the local voltage and the track voltage. The counter is started with the zero-crossing point of the local voltage as the starting point and stopped with the zero-crossing point of the track voltage as the ending point. The actual phase difference is calculated from the counter value. The frequency is calculated using a window method. The window size is twice the signal period, i.e., 80 milliseconds. Theoretically, the signal has two zero-crossing points within 80 milliseconds. By counting the time of the two zero-crossing points, the actual frequency of the signal can be calculated.
[0004] In related technologies, the safety functions of analog signal acquisition and processing in track circuits implemented based on FPGAs lack internal logic self-testing for safety functions. Furthermore, the numerous logic gates within an FPGA pose a risk of adjacent gates sticking together and / or becoming entrenched. Therefore, safety functions implemented by FPGAs must incorporate self-testing to comply with fail-safe principles. How to implement self-testing for analog signal acquisition and processing in track circuits using FPGAs has become a problem to be solved. Summary of the Invention
[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0006] This invention provides a method, computer storage medium, and terminal for implementing self-testing, which enables self-testing of the acquisition and processing functions of the track circuit signal acquisition module.
[0007] This invention provides a method for implementing self-testing, comprising:
[0008] The analog signals of the track circuit are input into the first acquisition function unit and the second acquisition function unit respectively.
[0009] Adjust the input of the i-th acquisition and processing channel of the first acquisition function unit to the preset waveform occupied by the track;
[0010] Based on the output results of the first acquisition function unit and the second acquisition function unit, determine the self-test result of the i-th acquisition and processing channel;
[0011] The first acquisition function unit and the second acquisition function unit are units with the same structure instantiated inside the field-programmable logic array (FPGA) in the track circuit signal acquisition module, used to acquire and process the analog signals.
[0012] On the other hand, embodiments of the present invention also provide a computer storage medium storing a computer program, which, when executed by a processor, implements the above-described method for implementing self-test processing.
[0013] Furthermore, embodiments of the present invention also provide a terminal, comprising: a memory and a processor, wherein the memory stores a computer program; wherein,
[0014] The processor is configured to execute computer programs in memory;
[0015] When the computer program is executed by the processor, it implements the self-testing method as described above.
[0016] The technical solution of this application includes: inputting analog signals from the track circuit into a first acquisition function unit and a second acquisition function unit respectively; adjusting the input of the i-th acquisition processing channel of the first acquisition function unit to a preset waveform representing track occupancy; and determining the self-test result of the i-th acquisition processing channel based on the output results of the first and second acquisition function units. The first and second acquisition function units are identical units instantiated within the Field Programmable Array (FPGA) of the track circuit signal acquisition module, used for acquiring and processing the analog signals. In this embodiment, the first and second acquisition function units are instantiated within the FPGA. After inputting analog signals into the first and second acquisition function units, the input of the i-th acquisition processing channel of the first acquisition function unit is adjusted to a preset waveform representing track occupancy. By comparing the output results, the self-test of the acquisition processing function of the track circuit signal acquisition module is achieved.
[0017] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description
[0018] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions of the present invention.
[0019] Figure 1 For related technology track circuit signal acquisition modules;
[0020] Figure 2 This is a schematic diagram of the ADC conditioning circuit in the track circuit signal acquisition module of related technologies;
[0021] Figure 3 This is a schematic diagram of the relevant technology acquisition function unit;
[0022] Figure 4 This is a flowchart illustrating the self-testing process implemented in an embodiment of the present invention;
[0023] Figure 5 This is a block diagram showing the composition of the first acquisition function unit and the second acquisition function unit in an embodiment of the present invention. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.
[0025] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.
[0026] Figure 4 This is a flowchart illustrating the self-testing process implemented in an embodiment of the present invention, as shown below. Figure 4 As shown, it includes:
[0027] Step 401: Input the analog signal of the track circuit into the first acquisition function unit and the second acquisition function unit respectively;
[0028] Step 402: Adjust the input of the i-th acquisition and processing channel of the first acquisition function unit to the preset waveform occupied by the track;
[0029] Step 403: Determine the self-test result of the i-th acquisition and processing channel based on the output results of the first acquisition function unit and the second acquisition function unit;
[0030] The first and second acquisition function units are identical in structure to the field-programmable logic array (FPGA) instantiated within the track circuit signal acquisition module, and are used to acquire and process analog signals.
[0031] In this embodiment of the invention, a first acquisition function unit and a second acquisition function unit are instantiated inside the FPGA. After inputting analog signals to the first acquisition function unit and the second acquisition function unit, the input of the i-th acquisition processing channel of the first acquisition function unit is adjusted to a preset waveform occupied by the track. By comparing the output results of the acquisition processing performed by the first acquisition function unit and the second acquisition function unit, the self-test of the acquisition processing function of the track circuit signal acquisition module is realized.
[0032] In one exemplary instance, the first acquisition function unit includes N acquisition and processing channels, where i takes a value from 1 to N, i.e., the i-th acquisition and processing channel is one of the N acquisition and processing channels in the first acquisition function unit; in one exemplary instance, the present invention performs self-tests on each acquisition and processing channel through steps 401 to 403; in one exemplary instance, N is 6; in one exemplary instance, the analog signal in the present invention includes: two local voltages and six track voltage signals of the track circuit; in one exemplary instance, the local voltage is a local voltage of 110 volts.
[0033] In one exemplary embodiment, the first and second acquisition functions are used only to distinguish between two acquisition function units. When the first acquisition function unit performs a self-test, the second acquisition function module is used to process the analog signal of the track circuit. When the second acquisition function unit performs a self-test, the first acquisition function module is used to process the analog signal of the track circuit. In one exemplary embodiment, the present invention performs self-tests on the two acquisition function units alternately. That is, after all acquisition processing channels of the first acquisition function unit have completed their self-tests, all acquisition processing channels of the second acquisition function unit are self-tested, and the two acquisition function units perform self-tests alternately. Figure 5 This is a block diagram of the composition of the first acquisition function unit and the second acquisition function unit in an embodiment of the present invention, as shown below. Figure 5 As shown, the FPGA is connected to other components in the track circuit signal acquisition module via an SPI control unit. The FPGA is equipped with registers for storing analog signals, and a self-test switch determines whether to perform the self-test process of this embodiment.
[0034] In one exemplary embodiment, this invention can access the registers of the ADC chip via a Serial Peripheral Interface (SPI) bus to read the analog signal of the aforementioned track circuit. This embodiment cuts off the input to the ADC chip's register for the i-th acquisition and processing channel and writes a preset waveform occupied by the aforementioned track.
[0035] In one exemplary instance, the output results of this embodiment of the invention include: the amplitude, phase, and frequency of the track voltage output by each acquisition and processing channel of the first acquisition function unit and the second acquisition function unit.
[0036] In one exemplary instance, the embodiment of the present invention determines the self-test result of the i-th acquisition and processing channel, including:
[0037] If the output result of the i-th acquisition and processing channel is "track cleared", then the self-test of the i-th acquisition and processing channel fails.
[0038] If the output result of the i-th acquisition and processing channel is that the track is occupied, and the output results of the m acquisition and processing channels of the first acquisition function unit and the second acquisition function unit are the same except for the i-th acquisition and processing channel, then the i-th acquisition and processing channel passes the self-test.
[0039] The output result of the i-th acquisition and processing channel is that the track is occupied. However, if the output results of the m acquisition and processing channels of the first acquisition function unit and the second acquisition function unit are different, the self-test result of the i-th acquisition and processing channel is determined according to whether the local power supply of the track circuit is abnormal.
[0040] Among them, m acquisition and processing channels are the other acquisition and processing channels besides the i-th acquisition and processing channel.
[0041] In one exemplary instance, this embodiment of the invention determines the self-test result of the i-th acquisition and processing channel based on whether the local power supply of the track circuit is abnormal, including:
[0042] When a local power supply abnormality occurs in the track circuit, the self-test result of the i-th acquisition and processing channel is determined based on the amplitude of the output of the n acquisition and processing channels.
[0043] When the local power supply of the track circuit is normal, the self-test result of the i-th acquisition and processing channel is determined based on the amplitude of the output of the n acquisition and processing channels with different output results.
[0044] Among them, n acquisition and processing channels are acquisition and processing channels with different output results among m acquisition and processing channels.
[0045] In one exemplary embodiment, whether the local power supply is abnormal can be determined by referring to relevant technologies based on the voltage and frequency of the local power supply; in another exemplary embodiment, whether the local power supply is abnormal can be implemented by a DSP referring to relevant technologies.
[0046] In one exemplary instance, the amplitude of the output from the n-channel acquisition and processing channels of this embodiment determines the self-test result of the i-th acquisition and processing channel, including:
[0047] When the amplitudes of the outputs from the n acquisition and processing channels are equal, the self-test of the i-th acquisition and processing channel is determined to be passed.
[0048] If the amplitude values output by the n acquisition and processing channels are inconsistent, the self-test of the i-th acquisition and processing channel is determined to have failed. Here, if the amplitude values output by the n acquisition and processing channels have more than two possible values, it is considered that the amplitude values output by the n acquisition and processing channels are inconsistent.
[0049] In one exemplary instance, this embodiment of the invention determines the self-test result of the i-th acquisition and processing channel based on the amplitude values output by the n acquisition and processing channels with different output results, including:
[0050] If the amplitude of the output of the n acquisition and processing channels with different output results is less than the preset value and the amplitude of the output of the n acquisition and processing channels is the same, it is determined that the self-test of the i-th acquisition and processing channel has passed.
[0051] If the amplitude of the output from the n acquisition and processing channels with different output results is greater than or equal to a preset value, the self-test of the i-th acquisition and processing channel is determined to have failed.
[0052] In one exemplary instance, the preset value in the embodiment of the present invention can be determined by those skilled in the art; in one exemplary instance, the preset value in the embodiment of the present invention is equal to 1.
[0053] In one exemplary instance, the preset waveform of this embodiment of the invention includes: an all-zero waveform;
[0054] When the preset waveform is a full zero waveform, the output result of the i-th acquisition and processing channel is that when the track is occupied, the amplitude, frequency and phase of the track voltage output by the i-th acquisition and processing channel are all 0.
[0055] For safety reasons, the waveform occupied by the input track is used; among them, the all-zero waveform is the easiest to achieve.
[0056] In one exemplary instance, embodiments of the present invention can perform the above self-test via a DSP.
[0057] In one exemplary instance, when it is determined that the self-test of the i-th acquisition and processing channel has failed, the method of this embodiment of the invention further includes:
[0058] Perform a self-test on the i-th acquisition and processing channel;
[0059] If the number of self-test failures of the i-th acquisition and processing channel is greater than or equal to the preset self-test number threshold, a self-test failure is determined to have occurred.
[0060] In one exemplary instance, the self-test results in this embodiment of the invention can be fed back through a pre-defined interactive interface; in another exemplary instance, the self-test results in this embodiment of the invention include, but are not limited to, one or any combination of the following: self-test passed, self-test failed, number of self-test failures, and self-test malfunction.
[0061] This invention also provides a computer storage medium storing a computer program, which, when executed by a processor, implements the above-described method for implementing self-testing.
[0062] This invention also provides a terminal, comprising: a memory and a processor, wherein the memory stores a computer program; wherein,
[0063] The processor is configured to execute computer programs in memory;
[0064] When a computer program is executed by a processor, it implements a self-testing process as described above.
[0065] This invention also provides a track circuit signal acquisition module, which includes a DSP. The DSP is used to execute a method for implementing self-testing.
[0066] The analog signals of the track circuit are input into the first acquisition function unit and the second acquisition function unit respectively.
[0067] Adjust the input of the i-th acquisition and processing channel of the first acquisition function unit to the preset waveform occupied by the track;
[0068] Based on the output results of the first acquisition function unit and the second acquisition function unit, determine the self-test result of the i-th acquisition and processing channel;
[0069] The first and second acquisition function units are identical in structure to the field-programmable logic array (FPGA) instantiated within the track circuit signal acquisition module, and are used to acquire and process analog signals.
[0070] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
Claims
1. A method for implementing self-testing, comprising: The analog signals of the track circuit are input into the first acquisition function unit and the second acquisition function unit respectively. Adjust the input of the i-th acquisition and processing channel of the first acquisition function unit to the preset waveform occupied by the track; Based on the output results of the first acquisition function unit and the second acquisition function unit, determine the self-test result of the i-th acquisition and processing channel; The first acquisition function unit and the second acquisition function unit are units with the same structure instantiated inside the field-programmable logic array (FPGA) in the track circuit signal acquisition module, used to acquire and process the analog signals.
2. The method of claim 1, wherein, The determination of the self-test result of the i-th acquisition and processing channel includes: If the output result of the i-th acquisition and processing channel is "track cleared", then the self-test of the i-th acquisition and processing channel fails. If the output result of the i-th acquisition and processing channel is that the track is occupied, and the output results of the m acquisition and processing channels of the first acquisition function unit and the second acquisition function unit are the same except for the i-th acquisition and processing channel, then the i-th acquisition and processing channel passes the self-test. The output result of the i-th acquisition and processing channel is that the track is occupied. However, if the output results of the m acquisition and processing channels of the first acquisition function unit and the second acquisition function unit are different, the self-test result of the i-th acquisition and processing channel is determined according to whether the local power supply of the track circuit is abnormal. The m acquisition and processing channels include: other acquisition and processing channels besides the i-th acquisition and processing channel.
3. The method of claim 2, wherein, The m-channel acquisition and processing system includes n channels with different output results. Determining the self-test result of the i-th acquisition and processing channel based on whether the local power supply of the track circuit is abnormal includes: When the local power supply of the track circuit is abnormal, if the amplitudes of the outputs of the n acquisition and processing channels are equal, it is determined that the self-test of the i-th acquisition and processing channel has passed; if the amplitudes of the outputs of the n acquisition and processing channels are inconsistent, it is determined that the self-test of the i-th acquisition and processing channel has failed. When the local power supply of the track circuit is normal, if the amplitude of the output of the n acquisition and processing channels is less than the preset value and the amplitude of the output of the n acquisition and processing channels is the same, it is determined that the self-test of the i-th acquisition and processing channel has passed; if the amplitude of the output of the n acquisition and processing channels is greater than or equal to the preset value, it is determined that the self-test of the i-th acquisition and processing channel of the first acquisition function unit has failed.
4. The method of claim 3, wherein, The preset value is equal to 1.
5. The method according to any one of claims 1-4, characterized in that, The preset waveform includes: all-zero waveform.
6. The method according to any one of claims 1-4, characterized in that, When it is determined that the self-test of the i-th acquisition and processing channel has failed, the method further includes: Perform a self-test on the i-th acquisition and processing channel again; If the number of self-test failures of the i-th acquisition and processing channel is greater than or equal to a preset self-test number threshold, a self-test failure is determined to have occurred.
7. A computer storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the method for implementing self-test processing as described in any one of claims 1 to 6.
8. A terminal, comprising: A memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute computer programs in memory; When the computer program is executed by the processor, it implements the method for implementing self-test processing as described in any one of claims 1 to 6.