Semiconductor device, battery protection circuit, and power management circuit

Abstract

A chip size package type semiconductor device (1) capable of being mounted face down, comprising a semiconductor layer (40) and N (N is an integer of 3 or more) vertical MOS transistors formed in the semiconductor layer (40); the N vertical MOS transistors each have a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor on an upper surface of the semiconductor layer (40); the semiconductor layer (40) has a semiconductor substrate (32); the semiconductor substrate (32) functions as a common drain region of the N vertical MOS transistors; the area of each of the N vertical MOS transistors in a plan view of the semiconductor layer (40) corresponds to a maximum rated current of each of the N vertical MOS transistors, and the greater the maximum rated current, the greater the area.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, battery protection circuits, and power management circuits, represented by vertical transistors. Furthermore, vertical transistors refer to vertically oriented MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), BJTs (Bipolar Junction Transistors), etc. Background Technology

[0002] Previously, semiconductor devices having multiple vertical MOS transistors that allow the drain regions to be common are known (see, for example, Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 1-179456 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] In a semiconductor device having multiple vertical MOS transistors that allow the drain regions to be common, it is desirable to suppress localized heat generation.

[0008] Therefore, the purpose of this disclosure is to provide a semiconductor device or the like that can suppress localized heating.

[0009] Methods used to solve problems

[0010] The semiconductor device disclosed herein is a chip-scale packaged semiconductor device capable of being mounted face-down, comprising: a semiconductor layer; and N vertical MOS transistors formed within the semiconductor layer, where N is an integer of 3 or more; each of the N vertical MOS transistors has a gate pad electrically connected to the gate electrode of the vertical MOS transistor and one or more source pads electrically connected to the source electrode of the vertical MOS transistor on the upper surface of the semiconductor layer; the semiconductor layer has a semiconductor substrate; the semiconductor substrate functions as a common drain region of the N vertical MOS transistors; corresponding to the maximum rated current of each of the N vertical MOS transistors, the larger the maximum rated current, the larger the area of ​​each of the N vertical MOS transistors in the plan view of the semiconductor layer.

[0011] A battery protection circuit according to the present disclosure includes: the aforementioned semiconductor device; a first terminal connected to one or more source pads of one of the N vertical MOS transistors in the semiconductor device; and N-1 battery cells, wherein the first electrode of either the positive or negative electrode is connected to one or more source pads of the N-1 vertical MOS transistors in the semiconductor device, excluding the terminal connected to the vertical MOS transistor; and the first electrode of the N-1 battery cells has the same polarity.

[0012] A battery protection circuit disclosed herein comprises: a first semiconductor device; a second semiconductor device having three vertical MOS transistors; N-1 battery cells connected in series; a first terminal connected to one or more source pads of one of the N vertical MOS transistors in the first semiconductor device, and a second terminal connected to one or more source pads of one of the three vertical MOS transistors in the second semiconductor device; a second terminal connected to the negative terminal of the N-1 battery cells; and a third terminal connected to the positive terminal of the battery cell located at the positive terminal end of the series connection among the N-1 battery cells; the N-1 battery cells... Each positive terminal of the cell is connected to one or more source pads of one or more of the N-1 vertical MOS transistors (excluding the vertical MOS transistor connected to the first terminal) in the first semiconductor device. The positive terminal of the first cell located at the negative terminal end in the series connection and the negative terminal of the second cell located next to the first cell in the series connection are respectively connected to one or more source pads of one or more of the three vertical MOS transistors (excluding the vertical MOS transistor connected to the second terminal) in the second semiconductor device. The first cell and the second cell are connected in series via the second semiconductor device.

[0013] A battery protection circuit disclosed herein comprises: a first semiconductor device; a second semiconductor device having three vertical MOS transistors; N battery cells connected in series; a first terminal connected to one or more source pads of one of the N vertical MOS transistors in the first semiconductor device, and a second terminal connected to one or more source pads of one of the three vertical MOS transistors in the second semiconductor device; a second terminal connected to the negative terminal of the N battery cells; and a third terminal connected to the positive terminal of the battery cell located at the positive terminal end of the series connection among the N battery cells; the first terminal of the battery cell located at the negative terminal end of the series connection among the N battery cells is connected to the first terminal of the N vertical MOS transistors in the first semiconductor device, and the second terminal of the battery cell located at the positive terminal end of the series connection among the N battery cells is connected to the first terminal of the N vertical MOS transistors in the first semiconductor device, and the third ... first terminal of the N vertical MOS transistors in the first semiconductor device, and the third terminal of The positive terminals of each of the N-1 battery cells other than the pool cell are connected to one or more source pads of the N-1 vertical MOS transistors (excluding the vertical MOS transistor connected to the first terminal) of the first semiconductor device. The positive terminal of the first battery cell located at the negative terminal end of the series connection and the negative terminal of the second battery cell located next to the first battery cell in the series connection are respectively connected to one or more source pads of the two vertical MOS transistors (excluding the vertical MOS transistor connected to the second terminal) of the three vertical MOS transistors of the second semiconductor device. The first battery cell and the second battery cell are connected in series via the second semiconductor device.

[0014] A battery protection circuit according to the present disclosure includes: a first semiconductor device having three vertical MOS transistors and one specific vertical MOS transistor; a second semiconductor device having three vertical MOS transistors and one specific vertical MOS transistor; a first terminal connected to one source pad of the specific vertical MOS transistor in the first semiconductor device; a second terminal and a third terminal connected to one or more source pads of two of the three vertical MOS transistors in the first semiconductor device, excluding the specific vertical MOS transistor; and a fourth terminal connected to the specific vertical MOS transistor in the second semiconductor device. The S-transistor is connected to one source pad; and terminals 5 and 6 are connected to the source pads of one or more of the three vertical MOS transistors (excluding the one specific vertical MOS transistor) in the second semiconductor device; terminal 3 is a terminal for connecting to the positive terminal of one or more battery cells; terminal 6 is a terminal for connecting to the negative terminal of one or more battery cells; terminals 1, 2, 4, and 5 are terminals for connecting to a power management circuit; the power management circuit, via terminals 2 and 5, directs charging current to one or more battery cells during charging and receives discharging current from one or more battery cells during discharging.

[0015] A battery protection circuit disclosed herein comprises: a semiconductor device having three vertical MOS transistors and one specific vertical MOS transistor; a first terminal connected to one source pad of the specific vertical MOS transistor and one or more source pads of one of the three vertical MOS transistors (excluding the specific vertical MOS transistor); and a second terminal connected to one of the source pads of one of the three vertical MOS transistors (excluding the specific vertical MOS transistor). The first terminal is used to connect to the positive terminal of one or more battery cells; the third terminal is used to connect to the negative terminal of one or more battery cells; the second terminal and the fourth terminal are used to connect to a power management circuit; the power management circuit, via the second terminal and the fourth terminal, allows charging current to flow to one or more battery cells during charging, and receives discharging current from one or more battery cells during discharging.

[0016] A battery protection circuit disclosed herein comprises: a first semiconductor device having X+Y vertical MOS transistors, where X is an integer of 1 or more and Y is an integer of 2 or more; a second semiconductor device having 1+Y vertical MOS transistors; X first terminals connected to one or more source pads of each of the X+Y vertical MOS transistors in the first semiconductor device; Y second terminals connected to one or more source pads of each of the Y vertical MOS transistors (excluding the X vertical MOS transistors) in the first semiconductor device; and a third terminal connected to one or more source pads of one of the 1+Y vertical MOS transistors in the second semiconductor device. The source pads are connected; and Y fourth terminals are connected to the source pads of one or more of the Y vertical MOS transistors (excluding the one vertical MOS transistor) in the 1+Y of the second semiconductor device; the X first terminals are terminals for connecting to the positive terminals of the X battery cells; the third terminal is a terminal for connecting to the negative terminals of the X battery cells; the Y second terminals and the Y fourth terminals are terminals for connecting to the Y power management circuits; the Y power management circuits, respectively, via one of the Y second terminals and one of the Y fourth terminals, allow charging current to flow to at least one of the X battery cells during charging, and receive discharging current from the at least one battery cell during discharging.

[0017] A power management circuit disclosed herein comprises: a semiconductor device having X+Y vertical MOS transistors, where X is an integer of 1 or more and Y is an integer of 2 or more; X terminals connected to one or more source pads of each of the X+Y vertical MOS transistors in the semiconductor device; and Y circuits connected to one or more source pads of each of the Y vertical MOS transistors (excluding the X vertical MOS transistors) in the semiconductor device; the X terminals being terminals for connecting to X external circuits respectively; and the Y circuits being power-separated from each other.

[0018] The semiconductor device disclosed herein is a chip-scale packaged semiconductor device capable of being mounted face-down, comprising: a semiconductor layer; and N vertical transistors formed within the semiconductor layer, where N is an integer of 3 or more; each of the N vertical transistors has a control pad electrically connected to a control electrode for controlling the conduction of the vertical transistor, and one or more external connection pads electrically connected to an external connection electrode for receiving or releasing current from the external source of the vertical transistor on the upper surface of the semiconductor layer; the semiconductor layer has a semiconductor substrate; on the main surface side of the semiconductor substrate opposite to the main surface on which the N vertical transistors are formed, a common electrode common to the N vertical transistors is provided; corresponding to the maximum specification current of each of the N vertical transistors, the larger the maximum specification current, the larger the area of ​​each of the N vertical transistors in the plan view of the semiconductor layer.

[0019] Invention Effects

[0020] According to a technical solution disclosed herein, a semiconductor device or the like can be provided that can suppress localized heat generation. Attached Figure Description

[0021] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0022] Figure 2 This is a plan view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0023] Figure 3 This is a circuit diagram illustrating an example of the circuit structure of the semiconductor device according to Embodiment 1.

[0024] Figure 4A This is a plan view of the semiconductor device according to Embodiment 1.

[0025] Figure 4BThis is a plan view of the semiconductor device according to Embodiment 1.

[0026] Figure 5 This is a plan view of the semiconductor device according to Embodiment 1.

[0027] Figure 6 This is a plan view of the semiconductor device according to Embodiment 1.

[0028] Figure 7A This is a plan view of the semiconductor device according to Embodiment 1.

[0029] Figure 7B This is a plan view of the semiconductor device according to Embodiment 1.

[0030] Figure 8 This is a plan view of the semiconductor device according to Embodiment 1.

[0031] Figure 9 This is a plan view of the semiconductor device according to Embodiment 1.

[0032] Figure 10A This is a plan view of the semiconductor device according to Embodiment 1.

[0033] Figure 10B This is a plan view of the semiconductor device according to Embodiment 1.

[0034] Figure 10C This is a plan view of the semiconductor device according to Embodiment 1.

[0035] Figure 10D This is a plan view of the semiconductor device according to Embodiment 1.

[0036] Figure 11A This is a plan view of the semiconductor device according to Embodiment 1.

[0037] Figure 11B This is a plan view of the semiconductor device according to Embodiment 1.

[0038] Figure 11C This is a plan view of the semiconductor device according to Embodiment 1.

[0039] Figure 11D This is a plan view of the semiconductor device according to Embodiment 1.

[0040] Figure 11E This is a plan view of the semiconductor device according to Embodiment 1.

[0041] Figure 11F This is a plan view of the semiconductor device according to Embodiment 1.

[0042] Figure 11G This is a plan view of the semiconductor device according to Embodiment 1.

[0043] Figure 11H This is a plan view of the semiconductor device according to Embodiment 1.

[0044] Figure 11I This is a plan view of the semiconductor device according to Embodiment 1.

[0045] Figure 11J This is a plan view of the semiconductor device according to Embodiment 1.

[0046] Figure 12 This is a plan view of the semiconductor device according to Embodiment 1.

[0047] Figure 13A This is a plan view of the semiconductor device according to Embodiment 1.

[0048] Figure 13B This is a plan view of the semiconductor device according to Embodiment 1.

[0049] Figure 14A This is a plan view of the semiconductor device according to Embodiment 1.

[0050] Figure 14B This is a plan view of the semiconductor device according to Embodiment 1.

[0051] Figure 15 This is a plan view of the semiconductor device according to Embodiment 1.

[0052] Figure 16 This is a plan view of the semiconductor device according to Embodiment 1.

[0053] Figure 17 This is a plan view of the semiconductor device according to Embodiment 1.

[0054] Figure 18 This is a plan view of the semiconductor device according to Embodiment 1.

[0055] Figure 19 This is a plan view of the semiconductor device according to Embodiment 1.

[0056] Figure 20 This is a plan view of the semiconductor device according to Embodiment 1.

[0057] Figure 21A This is a plan view of the semiconductor device according to Embodiment 1.

[0058] Figure 21B This is a plan view of the semiconductor device according to Embodiment 1.

[0059] Figure 21C This is a plan view of the semiconductor device according to Embodiment 1.

[0060] Figure 21D This is a plan view of the semiconductor device according to Embodiment 1.

[0061] Figure 21E This is a plan view of the semiconductor device according to Embodiment 1.

[0062] Figure 21F This is a plan view of the semiconductor device according to Embodiment 1.

[0063] Figure 21G This is a plan view of the semiconductor device according to Embodiment 1.

[0064] Figure 21H This is a plan view of the semiconductor device according to Embodiment 1.

[0065] Figure 22A This is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0066] Figure 22B This is a plan view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0067] Figure 23 This is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0068] Figure 24 This is a circuit diagram illustrating an example of the structure of the battery protection system in Embodiment 2.

[0069] Figure 25A This is a schematic diagram showing the charging status of the battery cell by the battery protection system in Embodiment 2.

[0070] Figure 25B This is a schematic diagram illustrating the state of the battery cell being discharged by the battery protection system in Embodiment 2.

[0071] Figure 26 This is a circuit diagram illustrating an example of the structure of the battery protection system in Embodiment 2.

[0072] Figure 27 This is a circuit diagram illustrating an example of the structure of the battery protection system in Embodiment 2.

[0073] Figure 28 This is a circuit diagram illustrating an example of the structure of the battery protection system in Embodiment 3.

[0074] Figure 29A This is a schematic diagram illustrating the state in which the battery protection system of Embodiment 3 charges N battery cells in series.

[0075] Figure 29B This is a schematic diagram illustrating the state of N battery cells being discharged by the battery protection system of Embodiment 3.

[0076] Figure 29CThis is a schematic diagram illustrating the state in which the battery protection system of Embodiment 3 charges N battery cells in parallel.

[0077] Figure 30A This is a circuit diagram illustrating a specific example of the battery protection circuit in Embodiment 3.

[0078] Figure 30B This is a circuit diagram illustrating a specific example of a conventional battery protection circuit.

[0079] Figure 31A This is a circuit diagram illustrating a specific example of the battery protection circuit in Embodiment 3.

[0080] Figure 31B This is a circuit diagram illustrating a specific example of a conventional battery protection circuit.

[0081] Figure 32A This is a circuit diagram illustrating a specific example of the battery protection circuit in Embodiment 3.

[0082] Figure 32B This is a circuit diagram illustrating a specific example of a conventional battery protection circuit.

[0083] Figure 33A This is a schematic diagram illustrating the charging of three battery cells in series according to the battery protection system of Embodiment 3.

[0084] Figure 33B This is a schematic diagram illustrating the state in which the battery protection system of Embodiment 3 stops the series charging of the three battery cells and starts supplying the voltage of the positive terminal of one battery cell to the outside.

[0085] Figure 33C This is a schematic diagram showing the state of charging one battery cell by the battery protection system of Embodiment 3.

[0086] Figure 33D This is a schematic diagram illustrating the state in which the battery protection system of Embodiment 3 discharges three battery cells in parallel.

[0087] Figure 34 This is a circuit diagram illustrating an example of the structure of the battery protection system in Embodiment 4.

[0088] Figure 35A This is a schematic diagram illustrating the state in which the battery protection system of Embodiment 4 charges N-1 battery cells in series.

[0089] Figure 35B This is a schematic diagram illustrating the state of N-1 battery cells being discharged by the battery protection system of Embodiment 4.

[0090] Figure 35CThis is a schematic diagram illustrating the state in which the battery protection system of Embodiment 4 charges N-1 battery cells in parallel.

[0091] Figure 36 This is a circuit diagram illustrating a specific example of the battery protection circuit in Embodiment 4.

[0092] Figure 37A This is an example of a plan view of the semiconductor device in Embodiment 4.

[0093] Figure 37B This is an example of a plan view of the semiconductor device in Embodiment 4.

[0094] Figure 38A This is an example of a plan view of the semiconductor device in Embodiment 4.

[0095] Figure 38B This is an example of a plan view of the semiconductor device in Embodiment 4.

[0096] Figure 39 This is a circuit diagram illustrating a specific example of the battery protection circuit in Embodiment 4.

[0097] Figure 40 This is a circuit diagram illustrating a specific example of the battery protection circuit in Embodiment 4.

[0098] Figure 41A This is a schematic diagram illustrating the charging of three battery cells in series according to the battery protection system of Embodiment 4.

[0099] Figure 41B This is a schematic diagram illustrating the state in which the battery protection system of Embodiment 4 stops the series charging of the three battery cells and starts supplying the voltage of the positive terminal of one battery cell to the outside.

[0100] Figure 41C This is a schematic diagram showing the state of charging one battery cell by the battery protection system of Embodiment 4.

[0101] Figure 41D This is a schematic diagram illustrating the state in which the battery protection system of Embodiment 4 charges three battery cells in parallel.

[0102] Figure 42 This is a schematic diagram illustrating an example of the structure of the battery protection system according to Embodiment 5.

[0103] Figure 43 This is a schematic diagram illustrating an example of the structure of the battery protection system according to Embodiment 6.

[0104] Figure 44 This is a schematic diagram illustrating an example of the structure of the battery protection system according to Embodiment 7.

[0105] Figure 45 This is a schematic diagram illustrating an example of the structure of the power management system in Embodiment 8.

[0106] Figure 46 This is a schematic diagram illustrating an example of the structure of the power management system in Embodiment 9. Detailed Implementation

[0107] (The process of achieving the disclosed technical solution)

[0108] The inventors of this invention have advanced the development of a semiconductor device having multiple vertical MOS transistors, which are multiple vertical MOS transistors that share a common drain region and have different maximum current ratings.

[0109] The inventors of this invention have noticed that, among multiple vertical MOS transistors with different maximum current ratings, when the maximum current flows through each vertical MOS transistor and their on-resistances are equal, the localized heat generation in the region of the vertical MOS transistor with the larger maximum current rating is greater than that in the region of the vertical MOS transistor with the smaller maximum current rating. Therefore, it has been confirmed that an undesirable phenomenon of localized heating can occur in a semiconductor device.

[0110] Therefore, the inventors of this invention have conducted repeated experiments and research in order to realize a semiconductor device capable of suppressing localized heat generation in a semiconductor device having multiple vertical MOS transistors that make the drain regions common.

[0111] Typically, the heat generated by a transistor when a current I [A] flows through it and its on-resistance is R [Ω] is equal to R × I. 2 Proportional.

[0112] Therefore, the inventors of this invention have realized that in order to suppress localized heating in a semiconductor device having multiple vertical MOS transistors that make the drain region common, it is effective to make the on-resistance of the vertical MOS transistor smaller for the vertical MOS transistor with a larger maximum current rating, based on the maximum current rating of each vertical MOS transistor.

[0113] Therefore, based on this understanding, the inventors of the present invention conducted further repeated experiments and research. As a result, the inventors of the present invention conceived of the semiconductor device, etc., relating to this disclosure.

[0114] The semiconductor device disclosed herein is a chip-scale packaged semiconductor device capable of being mounted face-down, comprising: a semiconductor layer; and N vertical MOS transistors formed within the semiconductor layer, where N is an integer of 3 or more; each of the N vertical MOS transistors has a gate pad electrically connected to the gate electrode of the vertical MOS transistor and one or more source pads electrically connected to the source electrode of the vertical MOS transistor on the upper surface of the semiconductor layer; the semiconductor layer has a semiconductor substrate; the semiconductor substrate functions as a common drain region of the N vertical MOS transistors; corresponding to the maximum rated current of each of the N vertical MOS transistors, the larger the maximum rated current, the larger the area of ​​each of the N vertical MOS transistors in the plan view of the semiconductor layer.

[0115] For semiconductor devices with the above structure, the larger the maximum rated current of the vertical MOS transistor, the larger the area in the planar diagram of the semiconductor layer.

[0116] Typically, the on-resistance of a vertical MOS transistor is inversely proportional to the area of ​​the semiconductor layer in a planar configuration. Therefore, in semiconductor devices with the above-described structure, the larger the maximum rated current of a vertical MOS transistor, the smaller its on-resistance.

[0117] Therefore, a semiconductor device with the above structure can be provided that can suppress localized heat generation.

[0118] Alternatively, the area of ​​each of the N vertical MOS transistors in the planar diagram of the semiconductor layer may be proportional to the square of the maximum specification current of each of the N vertical MOS transistors.

[0119] Alternatively, the on-resistance of each of the N vertical MOS transistors when its maximum rated current flows is inversely proportional to the square of the maximum rated current of each of the N vertical MOS transistors.

[0120] Alternatively, one of the aforementioned N vertical MOS transistors may be a specific vertical MOS transistor whose maximum rated current is equal to the sum of the maximum rated currents of K vertical MOS transistors among the aforementioned N vertical MOS transistors, where K is an integer greater than 2 and less than N-1.

[0121] Alternatively, at least one of the aforementioned N vertical MOS transistors may be a specific vertical MOS transistor having one or more source pads as a single source pad; in the planar view of the aforementioned semiconductor layer, the gate pad and the single source pad of the aforementioned at least one specific vertical MOS transistor are respectively circular, and among the gate pads and the single or more source pads of the aforementioned N vertical MOS transistors, there are no gate pads and source pads whose area is intentionally reduced compared to the gate pads and single source pads of the aforementioned at least one specific vertical MOS transistor.

[0122] Alternatively, the semiconductor device may be rectangular in the plan view of the semiconductor layer; among the N vertical MOS transistors, the first inlet / outlet vertical MOS transistor located at the inlet or outlet of each of the current paths determined by the specifications and the second inlet / outlet vertical MOS transistor located at the outlet or inlet are adjacent to each other in the plan view of the semiconductor layer.

[0123] Alternatively, the semiconductor device may be rectangular in the plan view of the semiconductor layer; in the plan view of the semiconductor layer, the boundary lines of the first inlet / outlet vertical MOS transistor and the second inlet / outlet vertical MOS transistor in each of the more than one current path are parallel to the long side of the semiconductor device.

[0124] Alternatively, in the planar view of the semiconductor layer, the boundary lines of the first inlet / outlet vertical MOS transistor and the second inlet / outlet vertical MOS transistor in each of the more than one current path are not parallel to any of the four sides of the semiconductor device.

[0125] Alternatively, in the planar view of the semiconductor layer, the boundary lines of the first inlet / outlet vertical MOS transistor and the second inlet / outlet vertical MOS transistor in each of the above-mentioned one or more current paths can be formed by alternately connecting line segments parallel to the first side of the four sides of the semiconductor device and line segments parallel to the second side orthogonal to the first side.

[0126] Alternatively, in the N vertical MOS transistors, the first entrance / exit vertical MOS transistor located at the entrance or exit of the first current path, determined by specifications, and the second entrance / exit vertical MOS transistor located at the exit or entrance, are adjacent to each other in the plan view of the semiconductor layer; in the N vertical MOS transistors, the first entrance / exit vertical MOS transistor located at the entrance or exit of the second current path, determined by specifications, and the third entrance / exit vertical MOS transistor located at the exit or entrance, are adjacent to each other in the plan view of the semiconductor layer; in the N vertical MOS transistors, the second entrance / exit vertical MOS transistor located at the entrance or exit of the third current path, determined by specifications, and the third entrance / exit vertical MOS transistor located at the exit or entrance, are adjacent to each other in the plan view of the semiconductor layer; the gate pad of the third entrance / exit vertical MOS transistor is located on the extension line of the boundary line between the first entrance / exit vertical MOS transistor and the second entrance / exit vertical MOS transistor.

[0127] Alternatively, in the N vertical MOS transistors mentioned above, the first inlet / outlet vertical MOS transistor located at the entrance or exit of the first current path, determined by specifications, and the second inlet / outlet vertical MOS transistor located at the entrance or exit of the first current path, are adjacent to each other in the plan view of the semiconductor layer; in the N vertical MOS transistors mentioned above, the second inlet / outlet vertical MOS transistor located at the entrance or exit of the second current path, determined by specifications, and the third inlet / outlet vertical MOS transistor located at the entrance or exit of the second current path, are adjacent to each other in the plan view of the semiconductor layer; from the above... The current paths determined by the first and third entrance vertical MOS transistors do not match any of the current paths determined by the specifications; the first and third entrance vertical MOS transistors are adjacent to each other in the plan view of the semiconductor layer; the gate pad of the third entrance vertical MOS transistor is closer to the boundary line between the first and third entrance vertical MOS transistors than the boundary line between the second and third entrance vertical MOS transistors.

[0128] Alternatively, the upper surface of the semiconductor layer may also have a drain pad that is electrically connected to the semiconductor substrate.

[0129] A battery protection circuit according to the present disclosure includes: the aforementioned semiconductor device; a first terminal connected to one or more source pads of one of the N vertical MOS transistors in the semiconductor device; and N-1 battery cells, wherein the first electrode of either the positive or negative electrode is connected to one or more source pads of the N-1 vertical MOS transistors in the semiconductor device, excluding the terminal connected to the vertical MOS transistor; and the first electrode of the N-1 battery cells has the same polarity.

[0130] According to the battery protection circuit with the above structure, a battery protection circuit with a first semiconductor device capable of suppressing localized heat generation can be provided.

[0131] A battery protection circuit disclosed herein comprises: a first semiconductor device; a second semiconductor device having three vertical MOS transistors; N-1 battery cells connected in series; a first terminal connected to one or more source pads of one of the N vertical MOS transistors in the first semiconductor device, and a second terminal connected to one or more source pads of one of the three vertical MOS transistors in the second semiconductor device; a second terminal connected to the negative terminal of the N-1 battery cells; and a third terminal connected to the positive terminal of the battery cell located at the positive terminal end of the series connection among the N-1 battery cells; the N-1 battery cells... Each positive terminal of the cell is connected to one or more source pads of one or more of the N-1 vertical MOS transistors (excluding the vertical MOS transistor connected to the first terminal) in the first semiconductor device. The positive terminal of the first cell located at the negative terminal end in the series connection and the negative terminal of the second cell located next to the first cell in the series connection are respectively connected to one or more source pads of one or more of the three vertical MOS transistors (excluding the vertical MOS transistor connected to the second terminal) in the second semiconductor device. The first cell and the second cell are connected in series via the second semiconductor device.

[0132] According to the battery protection circuit with the above structure, a battery protection circuit with a first semiconductor device and a second semiconductor device capable of suppressing localized heat generation can be provided.

[0133] A battery protection circuit disclosed herein comprises: a first semiconductor device; a second semiconductor device having three vertical MOS transistors; N battery cells connected in series; a first terminal connected to one or more source pads of one of the N vertical MOS transistors in the first semiconductor device, and a second terminal connected to one or more source pads of one of the three vertical MOS transistors in the second semiconductor device; a second terminal connected to the negative terminal of the N battery cells; and a third terminal connected to the positive terminal of the battery cell located at the positive terminal end of the series connection among the N battery cells; the first terminal of the battery cell located at the negative terminal end of the series connection among the N battery cells is connected to the first terminal of the N vertical MOS transistors in the first semiconductor device, and the second terminal of the battery cell located at the positive terminal end of the series connection among the N battery cells is connected to the first terminal of the N vertical MOS transistors in the first semiconductor device, and the third ... first terminal of the N vertical MOS transistors in the first semiconductor device, and the third terminal of The positive terminals of each of the N-1 battery cells other than the pool cell are connected to one or more source pads of the N-1 vertical MOS transistors (excluding the vertical MOS transistor connected to the first terminal) of the first semiconductor device. The positive terminal of the first battery cell located at the negative terminal end of the series connection and the negative terminal of the second battery cell located next to the first battery cell in the series connection are respectively connected to one or more source pads of the two vertical MOS transistors (excluding the vertical MOS transistor connected to the second terminal) of the three vertical MOS transistors of the second semiconductor device. The first battery cell and the second battery cell are connected in series via the second semiconductor device.

[0134] According to the battery protection circuit with the above structure, a battery protection circuit with a first semiconductor device and a second semiconductor device capable of suppressing localized heat generation can be provided.

[0135] A battery protection circuit according to the present disclosure includes: a first semiconductor device having three vertical MOS transistors and one specific vertical MOS transistor; a second semiconductor device having three vertical MOS transistors and one specific vertical MOS transistor; a first terminal connected to one source pad of the specific vertical MOS transistor in the first semiconductor device; a second terminal and a third terminal connected to one or more source pads of two of the three vertical MOS transistors in the first semiconductor device, excluding the specific vertical MOS transistor; and a fourth terminal connected to the specific vertical MOS transistor in the second semiconductor device. The S-transistor is connected to one source pad; and terminals 5 and 6 are connected to the source pads of one or more of the three vertical MOS transistors (excluding the one specific vertical MOS transistor) in the second semiconductor device; terminal 3 is a terminal for connecting to the positive terminal of one or more battery cells; terminal 6 is a terminal for connecting to the negative terminal of one or more battery cells; terminals 1, 2, 4, and 5 are terminals for connecting to a power management circuit; the power management circuit, via terminals 2 and 5, directs charging current to one or more battery cells during charging and receives discharging current from one or more battery cells during discharging.

[0136] According to the battery protection circuit with the above structure, a battery protection circuit with a first semiconductor device and a second semiconductor device capable of suppressing localized heat generation can be provided.

[0137] A battery protection circuit disclosed herein comprises: a semiconductor device having three vertical MOS transistors and one specific vertical MOS transistor; a first terminal connected to one source pad of the specific vertical MOS transistor and one or more source pads of one of the three vertical MOS transistors (excluding the specific vertical MOS transistor); and a second terminal connected to one of the source pads of one of the three vertical MOS transistors (excluding the specific vertical MOS transistor). The first terminal is used to connect to the positive terminal of one or more battery cells; the third terminal is used to connect to the negative terminal of one or more battery cells; the second terminal and the fourth terminal are used to connect to a power management circuit; the power management circuit, via the second terminal and the fourth terminal, allows charging current to flow to one or more battery cells during charging, and receives discharging current from one or more battery cells during discharging.

[0138] According to the battery protection circuit with the above structure, a battery protection circuit with a first semiconductor device capable of suppressing localized heat generation can be provided.

[0139] A battery protection circuit disclosed herein comprises: a first semiconductor device having X+Y vertical MOS transistors, where X is an integer of 1 or more and Y is an integer of 2 or more; a second semiconductor device having 1+Y vertical MOS transistors; X first terminals connected to one or more source pads of each of the X+Y vertical MOS transistors in the first semiconductor device; Y second terminals connected to one or more source pads of each of the Y vertical MOS transistors (excluding the X vertical MOS transistors) in the first semiconductor device; and a third terminal connected to one or more source pads of one of the 1+Y vertical MOS transistors in the second semiconductor device. The source pads are connected; and Y fourth terminals are connected to the source pads of one or more of the Y vertical MOS transistors (excluding the one vertical MOS transistor) in the 1+Y of the second semiconductor device; the X first terminals are terminals for connecting to the positive terminals of the X battery cells; the third terminal is a terminal for connecting to the negative terminals of the X battery cells; the Y second terminals and the Y fourth terminals are terminals for connecting to the Y power management circuits; the Y power management circuits, respectively, via one of the Y second terminals and one of the Y fourth terminals, allow charging current to flow to at least one of the X battery cells during charging, and receive discharging current from the at least one battery cell during discharging.

[0140] According to the battery protection circuit with the above structure, a battery protection circuit with a first semiconductor device and a second semiconductor device capable of suppressing localized heat generation can be provided.

[0141] A power management circuit disclosed herein comprises: a semiconductor device having X+Y vertical MOS transistors, where X is an integer of 1 or more and Y is an integer of 2 or more; X terminals connected to one or more source pads of each of the X+Y vertical MOS transistors in the semiconductor device; and Y circuits connected to one or more source pads of each of the Y vertical MOS transistors (excluding the X vertical MOS transistors) in the semiconductor device; the X terminals being terminals for connecting to X external circuits respectively; and the Y circuits being power-separated from each other.

[0142] According to the power management circuit with the above structure, a power management circuit with a first semiconductor device capable of suppressing localized heat generation can be provided.

[0143] The semiconductor device disclosed herein is a chip-scale packaged semiconductor device capable of being mounted face-down, comprising: a semiconductor layer; and N vertical transistors formed within the semiconductor layer, where N is an integer of 3 or more; each of the N vertical transistors has a control pad electrically connected to a control electrode for controlling the conduction of the vertical transistor, and one or more external connection pads electrically connected to an external connection electrode for receiving or releasing current from the external source of the vertical transistor on the upper surface of the semiconductor layer; the semiconductor layer has a semiconductor substrate; on the main surface side of the semiconductor substrate opposite to the main surface on which the N vertical transistors are formed, a common electrode common to the N vertical transistors is provided; corresponding to the maximum specification current of each of the N vertical transistors, the larger the maximum specification current, the larger the area of ​​each of the N vertical transistors in the plan view of the semiconductor layer.

[0144] For semiconductor devices with the above structure, the larger the maximum rated current of the vertical transistor, the larger the area in the planar diagram of the semiconductor layer.

[0145] Typically, the on-resistance of a vertical transistor is inversely proportional to the area in the planar diagram of the semiconductor layer. Therefore, in the semiconductor device with the above structure, the larger the maximum rated current, the smaller the on-resistance of the vertical transistor.

[0146] Therefore, a semiconductor device with the above structure can be provided that can suppress localized heat generation.

[0147] Alternatively, the area of ​​each of the N vertical transistors in the planar diagram of the semiconductor layer may be proportional to the square of the maximum specification current of each of the N vertical transistors.

[0148] Alternatively, the on-resistance of each of the N vertical transistors when its maximum rated current flows through it can be inversely proportional to the square of the maximum rated current of each of the N vertical transistors.

[0149] Alternatively, a common terminal electrically connected to the common electrode may be provided on the upper surface side of the semiconductor layer.

[0150] Alternatively, each of the N vertical transistors may have one or more external connection pads that are external output terminals from which current flows out of the N vertical transistors; and the common terminal may be an external input terminal from which current flows into the N vertical transistors.

[0151] Hereinafter, specific examples of a semiconductor device or the like of a technical solution of this disclosure will be described with reference to the accompanying drawings. The embodiments shown herein are all specific examples of this disclosure. Therefore, the values, shapes, constituent elements, arrangements and connection patterns of constituent elements, and steps (processes) and their order shown in the following embodiments are merely examples and are not intended to limit this disclosure. Furthermore, the figures are schematic diagrams and are not necessarily strictly representational. In the figures, substantially identical structures are given the same reference numerals, and repeated descriptions are omitted or simplified.

[0152] (Implementation Method 1)

[0153] [1-1. Structure of a Semiconductor Device]

[0154] The structure of the semiconductor device according to Embodiment 1 will be described below. The semiconductor device of Embodiment 1 is a chip-size package (CSP) type semiconductor device that has N (N is an integer of 3 or more) vertical MOS (Metal Oxide Semiconductor) transistors formed thereon and can be mounted face down. The aforementioned N vertical MOS transistors are so-called trench MOSFETs (Field Effect Transistors).

[0155] In this disclosure, a vertical MOS transistor is used as an example of a vertical transistor in the embodiments, but the vertical transistor is not limited to a vertical MOS transistor; for example, it can also be a BJT or an IGBT. In the case of a BJT, the source is referred to as the emitter, the drain as the collector, and the body as the base. Furthermore, the gate electrode that controls conduction in this disclosure is referred to as the base electrode. Similarly, in the case of an IGBT, the source is referred to as the emitter and the drain as the collector.

[0156] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to Embodiment 1. Figure 2 This is a plan view showing an example of the structure of semiconductor device 1. Figure 1 express Figure 2 The I-I cut surface. Figure 3 This is a circuit diagram illustrating an example of the circuit structure of semiconductor device 1.

[0157] For ease of explanation, Figures 1-3 The diagram shows semiconductor device 1 when N is 3. Furthermore, in the case of using... Figures 1-3 In the description, it is assumed that N is 3, but semiconductor device 1 can be any N of 3 or more, and it is not necessary to limit it to the case that N is 3.

[0158] like Figures 1-3 As shown, the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, a protective layer 35, a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in region A1 within the semiconductor layer 40, a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in region A2 within the semiconductor layer 40, and a third vertical MOS transistor 37 (hereinafter also referred to as "transistor 37") formed in region A3 within the semiconductor layer 40.

[0159] In addition, although Figure 1 Although not illustrated, the region within the semiconductor layer 40 that forms the Nth vertical transistor is also referred to as region AN in this specification.

[0160] For ease of explanation, Figure 1 The diagram shows the semiconductor device 1 as a case where the semiconductor device 1 and the semiconductor layer 40 are rectangular in the plan view of the semiconductor layer 40, but the semiconductor device 1 is not limited to a structure where the semiconductor device 1 and the semiconductor layer 40 are rectangular in the plan view of the semiconductor layer 40.

[0161] The semiconductor layer 40 is formed by stacking a semiconductor substrate 32, a low-concentration impurity layer 33, and an oxide film 34.

[0162] The semiconductor substrate 32 is disposed on the lower surface side of the semiconductor layer 40 and is made of silicon containing impurities of the first conductivity type.

[0163] A low-concentration impurity layer 33 is disposed on the upper surface side of the semiconductor layer 40 and is formed in contact with the semiconductor substrate 32. It contains impurities of the first conductivity type at a lower concentration than the impurities of the first conductivity type in the semiconductor substrate 32. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0164] An oxide film 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with a low-concentration impurity layer 33.

[0165] The protective layer 35 is formed by contacting the upper surface of the semiconductor layer 40, covering at least a portion of the upper surface of the semiconductor layer 40.

[0166] The metal layer 30 is formed in contact with the lower surface of the semiconductor substrate 32, and can be made of silver, copper, nickel, or alloys thereof, or of a metallic material with good conductivity that can function as an electrode. Additionally, the metal layer 30 may contain trace amounts of elements other than metals that were introduced as impurities during the manufacturing process of the metallic material.

[0167] like Figure 2As shown, transistor 10 has one or more (here, five) first source pads 111 (here, first source pads 111a, 111b, 111c, 111d, and 111e) and a first gate pad 119 on the upper surface of semiconductor layer 40 in region A1 of the plan view of semiconductor layer 40, which are bonded to the mounting substrate via bonding members when mounted face-down. Furthermore, transistor 20 has one or more (here, five) second source pads 121 (here, second source pads 121a, 121b, 121c, 121d, and 121e) and a second gate pad 129 on the upper surface of semiconductor layer 40 in region A2 of the plan view of semiconductor layer 40, which are bonded to the mounting substrate via bonding members when mounted face-down. Furthermore, transistor 37 has one or more (here, two) third source pads 131 (here, third source pads 131a and 131b) and a third gate pad 139 on the upper surface of semiconductor layer 40 in region A3 of the plan view of semiconductor layer 40, which are bonded to the mounting substrate via bonding members when mounted face down.

[0168] Each of the first source pad 111, each of the second source pad 121, and each of the third source pad 131 is rectangular, oval, or circular in the plan view of the semiconductor layer 40. Furthermore, in this specification, the end shapes of the rectangles and ovals are not limited to square (corresponding to a rectangle) or semi-circular (corresponding to an oval), and can also be polygonal. The first gate pad 119, the second gate pad 129, and the third gate pad 139 are circular in the plan view of the semiconductor layer 40.

[0169] Furthermore, the number and shape of one or more first source pads 111, the number and shape of one or more second source pads 121, and the number and shape of one or more third source pads 131 are not necessarily limited to [specific details]. Figure 2 The quantity and shape are as illustrated.

[0170] like Figure 1 and Figure 2 As shown, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the first region A1 of the low-concentration impurity layer 33. Within the first body region 18, a first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed. The first source electrode 11 is composed of a portion 12 and a portion 13, with portion 12 connected to the first source region 14 and the first body region 18 via portion 13. The first gate conductor 15 is electrically connected to the first gate pad 119.

[0171] The portion 12 of the first source electrode 11 is a layer that bonds with solder during reflow when mounted face down. As an example without limitation, it may be made of any one or more metallic materials including nickel, titanium, tungsten, and palladium. The surface of the portion 12 may be plated with a layer of gold or the like.

[0172] The portion 13 of the first source electrode 11 is a layer that connects the portion 12 to the semiconductor layer 40. As an example without limitation, it may be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0173] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing impurities of a second conductivity type is formed. In the second body region 28, a second source region 24 containing impurities of a first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed. The second source electrode 21 is composed of a portion 22 and a portion 23, with portion 22 connected to the second source region 24 and the second body region 28 via portion 23. The second gate conductor 25 is electrically connected to the second gate pad 129.

[0174] The portion 22 of the second source electrode 21 is a layer that bonds with solder during reflow when mounted face down. As an example without limitation, it may be made of any one or more metallic materials including nickel, titanium, tungsten, and palladium. The surface of the portion 22 may be plated with a layer of gold or the like.

[0175] The portion 23 of the second source electrode 21 is a layer that connects portion 22 to the semiconductor layer 40. As an example that is not limited, it may be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0176] In the third region A3 of the low-concentration impurity layer 33, similar to the first region A1 and the second region A2 of the low-concentration impurity layer 33, a third body region (not shown) containing impurities of the second conductivity type is formed. In the third body region, a third source region (not shown), a third gate conductor (not shown), and a third gate insulating film (not shown) containing impurities of the first conductivity type are formed. The third source electrode 31 (in...) Figure 1 , Figure 2 No illustration is provided; please refer to [the source]. Figure 3 It consists of a first part (not shown) and a second part (not shown), the first part being connected to the third source region (not shown) and the third body region via the second part. The third gate conductor is electrically connected to the third gate pad 139.

[0177] The first part of the third source electrode 31 is a layer that bonds with solder during reflow when mounted face down. As an example without limitation, it may be made of any one or more metallic materials including nickel, titanium, tungsten, and palladium. The surface of the first part may be plated with a layer of gold or the like.

[0178] The second part of the third source electrode 31 is a layer that connects the first part to the semiconductor layer 40. As an example that is not limited, it may be made of any one or more metallic materials including aluminum, copper, gold and silver.

[0179] Based on the aforementioned structures of transistors 10, 20, and 37, the low-concentration impurity layer 33 and the semiconductor substrate 32 function as a common drain region that unifies the first drain region of transistor 10, the second drain region of transistor 20, and the third drain region of transistor 37. That is, the semiconductor substrate 32 functions as a common drain region for N (here, 3) vertical MOS transistors.

[0180] like Figure 1 As shown, the first body region 18 is covered by an oxide film 34 with an opening, and a portion 13 of a first source electrode 11 is provided that is connected to the first source region 14 through the opening of the oxide film 34. The oxide film 34 and the portion 13 of the first source electrode are covered by a protective layer 35 with an opening, and a portion 12 is provided that is connected to the portion 13 of the first source electrode through the opening of the protective layer 35.

[0181] The second body region 28 is covered by an oxide film 34 with an opening, and a portion 23 of a second source electrode 21 is provided that is connected to the second source region 24 through the opening of the oxide film 34. The oxide film 34 and the portion 23 of the second source electrode are covered by a protective layer 35 with an opening, and a portion 22 is provided that is connected to the portion 23 of the second source electrode through the opening of the protective layer 35.

[0182] The third body region, like the first body region 18 and the second body region 28, is covered by an oxide film 34 with an opening, and has a second portion of a third source electrode 31 that connects to the third source region through the opening in the oxide film 34. The oxide film 34 and the second portion of the third source electrode are covered by a protective layer 35 with an opening, and have a first portion that connects to the second portion of the third source electrode through the opening in the protective layer 35.

[0183] Therefore, one or more first source pads 111, one or more second source pads 121, and one or more third source pads 131 respectively refer to the areas where the first source electrode 11, the second source electrode 21, and the third source electrode 31 are partially exposed on the upper surface of the semiconductor device 1, the so-called terminal portions. Similarly, the first gate pad 119, the second gate pad 129, and the third gate pad 139 respectively refer to the areas where the first gate electrode 19 (in) is partially exposed on the upper surface of the semiconductor device 1, the so-called terminal portions. Figure 1 , Figure 2 No illustration is provided; please refer to [the source]. Figure 3 ), the second gate electrode 29 (in Figure 1 , Figure 2 No illustration is provided; please refer to [the source]. Figure 3 ) and the third gate electrode 39 (in Figure 1 , Figure 2 No illustration is provided; please refer to [the source]. Figure 3 The area partially exposed on the upper surface of semiconductor device 1, the so-called terminal portion.

[0184] In semiconductor device 1, for example, the first conductivity type can be set as N-type, the second conductivity type can be set as P-type, the first source region 14, the second source region 24, the third source region, the semiconductor substrate 32 and the low-concentration impurity layer 33 are N-type semiconductors, and the first body region 18, the second body region 28 and the third body region are P-type semiconductors.

[0185] Furthermore, in the semiconductor device 1, for example, the first conductivity type may be set as P-type, the second conductivity type may be set as N-type, the first source region 14, the second source region 24, the third source region, the semiconductor substrate 32 and the low-concentration impurity layer 33 may be P-type semiconductors, and the first body region 18, the second body region 28 and the third body region may be N-type semiconductors.

[0186] In the following description, it is assumed that transistors 10, 20 and 37 (i.e., all of the N vertical MOS transistors) are N-channel transistors with the first conductivity type being N-type and the second conductivity type being P-type, and the conduction operation of semiconductor device 1 will be described.

[0187] In semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage above a threshold is applied to the second gate electrode 29 with reference to the second source electrode 21, a conduction channel is formed near the second gate insulating film 26 in the second body region 28. As a result, a main current flows through the path of first source electrode 11 – first body region 18 – low-concentration impurity layer 33 – semiconductor substrate 32 – metal layer 30 – semiconductor substrate 32 – low-concentration impurity layer 33 – conduction channel formed in the second body region 28 – second source region 24 – second source electrode 21, and this path becomes conductive. In addition, a PN junction exists at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in this main current path, such as... Figure 3 As shown, it functions as a body diode.

[0188] Similarly, in semiconductor device 1, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage above a threshold is applied to the first gate electrode 19 with reference to the first source electrode 11, a conductive channel is formed near the first gate insulating film 16 in the first body region 18. As a result, a main current flows through the path of second source electrode 21 – second body region 28 – low-concentration impurity layer 33 – semiconductor substrate 32 – metal layer 30 – semiconductor substrate 32 – low-concentration impurity layer 33 – conductive channel formed in the first body region 18 – first source region 14 – first source electrode 11, thus making the path conductive. In addition, a PN junction exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in this main current path, such as Figure 3 As shown, it functions as a body diode.

[0189] Similarly, in semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the third source electrode 31, and a voltage above a threshold is applied to the third gate electrode 39 with reference to the third source electrode 31, then a main current flows through the path from the first source electrode 11 to the third source electrode 31, and this path becomes a conducting state.

[0190] Similarly, in semiconductor device 1, if a high voltage is applied to the third source electrode 31 and a low voltage is applied to the first source electrode 11, and a voltage above a threshold is applied to the first gate electrode 19 with reference to the first source electrode 11, then a main current flows through the path from the third source electrode 31 to the first source electrode 11, and this path becomes a conducting state.

[0191] Similarly, in semiconductor device 1, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the third source electrode 31, and a voltage above a threshold is applied to the third gate electrode 39 with reference to the third source electrode 31, then a main current flows through the path from the second source electrode 21 to the third source electrode 31, and this path becomes a conducting state.

[0192] Similarly, in semiconductor device 1, if a high voltage is applied to the third source electrode 31 and a low voltage is applied to the second source electrode 21, and a voltage above a threshold is applied to the second gate electrode 29 with reference to the second source electrode 21, then a main current flows through the path from the third source electrode 31 to the second source electrode 21, and this path becomes a conducting state.

[0193] Similarly, in semiconductor device 1, if a high voltage is applied to the first source electrode 11 and the second source electrode 21 and a low voltage is applied to the third source electrode 31, and a voltage above a threshold is applied to the third gate electrode 39 with reference to the third source electrode 31, then a main current flows through the path from the first source electrode 11 and the second source electrode 21 to the third source electrode 31, and this path becomes a conducting state.

[0194] Similarly, in semiconductor device 1, if a high voltage is applied to the third source electrode 31 and a low voltage is applied to the first source electrode 11 and the second source electrode 21, a voltage above a threshold is applied to the first gate electrode 19 with reference to the first source electrode 11, and a voltage above a threshold is applied to the second gate electrode 29 with reference to the second source electrode 21, then a main current flows through the path from the third source electrode 31 to the first source electrode 11 and the second source electrode 21, and this path becomes a conducting state.

[0195] Similarly, in semiconductor device 1, if a high voltage is applied to the second source electrode 21 and the third source electrode 31 and a low voltage is applied to the first source electrode 11, and a voltage above a threshold is applied to the first gate electrode 19 with reference to the first source electrode 11, then a main current flows through the path from the second source electrode 21 and the third source electrode 31 to the first source electrode 11, and this path becomes a conducting state.

[0196] Similarly, in semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21 and the third source electrode 31, and a voltage above a threshold is applied to the second gate electrode 29 with reference to the second source electrode 21, and a voltage above a threshold is applied to the third gate electrode 39 with reference to the third source electrode 31, then a main current flows through the path from the first source electrode 11 to the second source electrode 21 and the third source electrode 31, and this path becomes a conducting state.

[0197] Similarly, in semiconductor device 1, if a high voltage is applied to the third source electrode 31 and the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage above a threshold is applied to the second gate electrode 29 with reference to the second source electrode 21, then a main current flows through the path from the third source electrode 31 and the first source electrode 11 to the second source electrode 21, and this path becomes a conducting state.

[0198] Similarly, in semiconductor device 1, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the third source electrode 31 and the first source electrode 11, a voltage above a threshold is applied to the third gate electrode 39 with reference to the third source electrode 31, and a voltage above a threshold is applied to the first gate electrode 19 with reference to the first source electrode 11, then a main current flows through the path from the second source electrode 21 to the third source electrode 31 and the first source electrode 11, and this path becomes a conducting state.

[0199] [1-2. Relationship between maximum rated current and transistor area in a planar diagram]

[0200] N vertical MOS transistors (here, the first vertical MOS transistor 10, the second vertical MOS transistor 20, and the third vertical MOS transistor 37) are each specified with a maximum rated current. The specification refers to the product specification of the corresponding transistor, and the maximum rated current is usually the value recorded in the corresponding transistor's product datasheet. The value recorded in the datasheet can be the maximum rated current or a current equivalent to 50% of the maximum rated current. 50% of the maximum rated current is usually the current value recorded in the product datasheet when evaluating on-resistance. In this sense, the maximum rated current is not limited to 50% of the maximum rated current, but can be understood as the current value recorded in the product datasheet when evaluating on-resistance. Furthermore, the on-resistance recorded in the product datasheet can be the so-called on-resistance.

[0201] Corresponding to the maximum specification current of each of the N vertical MOS transistors, the larger the maximum specification current, the larger the area of ​​each of the N vertical MOS transistors in the planar diagram of semiconductor layer 40.

[0202] Furthermore, in this specification, it is defined that in the plan view of semiconductor layer 40, the portion constituting the Nth vertical MOS transistor is entirely disposed in the Nth region AN. That is, the area of ​​the Nth vertical MOS transistor can be regarded as the area of ​​the Nth region AN. In addition, based on the above definition, it is stated in advance that in the plan view of semiconductor layer 40, the semiconductor device 1 having N vertical MOS transistors is divided into N regions, and there is no part that does not belong to any region.

[0203] Furthermore, the area of ​​the Nth vertical MOS transistor is defined by its boundary with the adjacent vertical MOS transistors. Here, the boundary, in the planar view of semiconductor layer 40, for example when the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are adjacent, can be understood as an imaginary straight line along the central position of the gap between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21; it can also be understood as a metal wiring that does not have the function of allowing current to pass through, sometimes provided at this central position and called an EQR (EQuipotential Ring); or it can be understood as the gap itself of finite width. In the case of this gap, it can also be identified as a line to the naked eye or at low magnification.

[0204] Furthermore, the area of ​​the Nth vertical MOS transistor in the planar view of semiconductor layer 40 can also be the area of ​​the active region of the Nth vertical MOS transistor. The active region of a vertical MOS transistor refers to the region in the body region of the vertical MOS transistor through which the main current flows when the vertical MOS transistor is in the on state.

[0205] Here, in the plan view of semiconductor layer 40, the active region of each vertical MOS transistor is approximately the same size as the body region of each vertical MOS transistor. Furthermore, in the plan view of semiconductor layer 40, the size of the body region of each vertical MOS transistor is approximately the same as the size of the region where each vertical MOS transistor is formed (i.e., region A1 when the vertical MOS transistor is transistor 10, region A2 when it is transistor 20, and region A3 when it is transistor 37). Therefore, in the plan view of semiconductor layer 40, the area of ​​the active region of each vertical MOS transistor is approximately the same as the size of the region where each vertical MOS transistor is formed.

[0206] Hereinafter, the maximum current of the first vertical MOS transistor 10 will be referred to as I1, the maximum current of the second vertical MOS transistor 20 will be referred to as I2, ..., and the maximum current of the Nth vertical MOS transistor will be referred to as IN. In the planar view of the semiconductor layer 40, the area of ​​the first vertical MOS transistor 10 will be referred to as S1, the area of ​​the second vertical MOS transistor 20 will be referred to as S2, ..., and the area of ​​the Nth vertical MOS transistor will be referred to as SN. The on-resistance when the maximum current I1 flows through the first vertical MOS transistor 10 will be referred to as R1, the on-resistance when the maximum current I2 flows through the second vertical MOS transistor 20 will be referred to as R2, ..., and the on-resistance when the maximum current IN flows through the Nth vertical MOS transistor will be referred to as RN.

[0207] In this disclosure, the area of ​​the N vertical MOS transistors in the planar view of semiconductor layer 40 is proportional to the square of the maximum rated current of the N vertical MOS transistors. That is, S1:S2:…:SN = I1 2 :I2 2 :…:IN 2 .

[0208] Typically, the area of ​​a vertical MOS transistor in the planar diagram of semiconductor layer 40 is inversely proportional to its on-resistance. Therefore, the on-resistance of N vertical MOS transistors is inversely proportional to the square of the maximum rated current of those N vertical MOS transistors. That is, 1 / R1 : 1 / R2 : ... : 1 / RN = I1 2 :I2 2 :…:IN 2 .

[0209] The heat generated by each vertical MOS transistor is distributed through its power loss, P = R × I. 2 Find the answer.

[0210] As described above, in the semiconductor device 1 with the above structure, the on-resistance of the N vertical MOS transistors is inversely proportional to the square of the maximum rated current of the N vertical MOS transistors.

[0211] Therefore, in the semiconductor device 1 with the above structure, the heat generated by each vertical MOS transistor is equal when the maximum specification current flows through each vertical MOS transistor.

[0212] Therefore, the semiconductor device 1 with the above structure can suppress localized heating.

[0213] Furthermore, in the semiconductor device 1 with the above structure, in a current path where a large current is not required for the intended purpose, instead of allocating an unnecessary size of vertical MOS transistor from the beginning, it is possible to set an appropriately sized vertical MOS transistor, thus also having the advantage of miniaturizing the semiconductor device itself.

[0214] Furthermore, the on-resistance is typically measured as the on-resistance in a specification-determined current path among N vertical MOS transistors, flowing from one inlet / outlet vertical MOS transistor to the other inlet / outlet vertical MOS transistor. Therefore, the on-resistance RN of the Nth vertical MOS transistor when the maximum specification current IN flows through it is described in the transistor's product datasheet. When considering a current path where the Nth vertical MOS transistor forms an inlet / outlet vertical MOS transistor, the on-resistance of that current path when the maximum specification current IN flows through the Nth vertical MOS transistor is calculated by proportionally allocating the area of ​​the other inlet / outlet vertical MOS transistor (which forms the denominator) to the area of ​​the Nth vertical MOS transistor. For example, when the current path between the first vertical MOS transistor (area S1, maximum rated current I1, and on-resistance R1 at this time) and the second vertical MOS transistor (area S2, maximum rated current I2>I1, and on-resistance R2 at this time) is determined by specifications, and the on-resistance of the corresponding current path when current I1 flows between the first vertical MOS transistor and the second vertical MOS transistor is R12, the relationship R1=R12×S2 / (S1+S2) holds true.

[0215] [1-3. Preferred shapes of semiconductor devices]

[0216] In N vertical MOS transistors, the first inlet / outlet vertical MOS transistor located at the entrance or exit of each current path and the second inlet / outlet vertical MOS transistor located at the exit or entrance of each current path, which are determined by the specifications, are preferably adjacent to each other in the plan view of semiconductor layer 40.

[0217] This prevents the following situation: at the point when the maximum specification current flows through the other vertical MOS transistors sandwiched between the first and second vertical MOS transistors, current also flows through the current path between the first and second vertical MOS transistors, causing the other vertical MOS transistors to heat up to the extent that the maximum specification current flows.

[0218] Figure 4A and Figure 4BThese are plan views of the semiconductor device 1 when N is 3. The plan view shows an example of the shape of the semiconductor device 1 when the current path determined by the specifications is (1) the current path flowing between the first vertical MOS transistor (Tr1) and the second vertical MOS transistor (Tr2), and (2) the current path flowing between the first vertical MOS transistor (Tr1) and the third vertical MOS transistor (Tr3), and (3) the current path flowing between the second vertical MOS transistor (Tr2) and the third vertical MOS transistor (Tr3) is not the current path determined by the specifications.

[0219] according to Figure 4A The semiconductor device 1 shown has a shape in which Tr1 and Tr2 at the inlet or outlet of the current path determined by the specification are adjacent to each other, and Tr1 and Tr3 at the inlet or outlet of the current path determined by the specification are adjacent to each other.

[0220] In contrast, according to Figure 4B The semiconductor device 1 shown has a shape in which Tr1 and Tr2, located at the inlet or outlet of the current path determined by the specification, are adjacent to each other, but Tr1 and Tr3, located at the inlet or outlet of the current path determined by the specification, are not adjacent to each other. Furthermore, in the plan view of the semiconductor layer 40, Tr2 is located on the current path flowing between Tr1 and Tr3.

[0221] Therefore, the current path flowing between Tr1 and Tr2 is the same as the current path flowing between Tr1 and Tr3. At the point when the maximum specification current flows in Tr2, the maximum specification current also flows in Tr3. Thus, Tr2 heats up to the extent that only the maximum specification current of Tr2 flows in Tr2.

[0222] Therefore, it can be said that Figure 4A The shape of the semiconductor device 1 shown is larger than that of the semiconductor device 1 shown. Figure 4B The shape of the semiconductor device 1 shown is more preferred.

[0223] Furthermore, the current path determined by the specifications is the current path with on-resistance (connection resistance) presented in the corresponding transistor's product datasheet. Instead of arbitrarily setting the current path as any combination of N vertical MOS transistors, one or more current paths are designed according to the application, and the maximum specified current of each input / output vertical MOS transistor is recorded in the product datasheet.

[0224] In addition, in this specification, the first vertical MOS transistor will be referred to as Tr1, the second vertical MOS transistor as Tr2, ..., and the Nth vertical MOS transistor as TrN.

[0225] Furthermore, when the semiconductor device 1 is rectangular in the plan view of the semiconductor layer 40, in the plan view of the semiconductor layer 40, the boundary line between the first inlet / outlet vertical MOS transistor located at the inlet or outlet of each of the more than one current paths determined by the specifications and the second inlet / outlet vertical MOS transistor located at the outlet or inlet is more preferably parallel to the long side of the semiconductor device 1 than parallel to the short side of the semiconductor device 1.

[0226] Therefore, the current flow range between the first and second input / output vertical MOS transistors can be larger. That is, the on-resistance of the current path determined by the first and second input / output vertical MOS transistors can be lower.

[0227] Figure 5 and Figure 4A , Figure 4B Similarly, the plan view of the semiconductor device 1 with N=3 is an example of the shape of the semiconductor device 1 when the current path determined by the specifications is (1) the current path flowing between the first vertical MOS transistor (Tr1) and the second vertical MOS transistor (Tr2), and (2) the current path flowing between the first vertical MOS transistor (Tr1) and the third vertical MOS transistor (Tr3), and (3) the current path flowing between the second vertical MOS transistor (Tr2) and the third vertical MOS transistor (Tr3) is not the current path determined by the specifications.

[0228] according to Figure 5 The shape of the semiconductor device 1 shown in the plan view of the semiconductor layer 40 is such that the boundary lines between Tr1 and Tr2 and between Tr1 and Tr3 are parallel to the long side of the semiconductor device 1.

[0229] In contrast, according to Figure 4A The shape of the semiconductor device 1 shown in the plan view of the semiconductor layer 40 is such that the boundary lines between Tr1 and Tr2 and between Tr1 and Tr3 are parallel to the short side of the semiconductor device 1.

[0230] Therefore, in the planar view of semiconductor layer 40, Figure 5 The boundary line ratio of Tr1 and Tr2 under the shape of the semiconductor device 1 shown is... Figure 4A The length of the boundary line between Tr1 and Tr2 under the shape of the semiconductor device 1 shown is, and, Figure 5 The boundary line ratio of Tr1 and Tr3 under the shape of the semiconductor device 1 shown is... Figure 4A The length of the boundary line between Tr1 and Tr3 under the shape of the semiconductor device 1 shown.

[0231] Therefore, it can be said that Figure 5 The shape of the semiconductor device 1 shown is larger than that of the semiconductor device 1 shown. Figure 4A The shape of the semiconductor device 1 shown is more preferred.

[0232] Furthermore, in the plan view of semiconductor layer 40, the boundary line between the first inlet / outlet vertical MOS transistor located at the inlet or outlet of each of the more than one current paths determined by the specification and the second inlet / outlet vertical MOS transistor located at the outlet or inlet is more preferably not parallel to any of the four sides of semiconductor device 1 than parallel to one of the four sides of semiconductor device 1.

[0233] Therefore, the current flow range between the first and second input / output vertical MOS transistors can be larger. That is, the on-resistance of the current path determined by the first and second input / output vertical MOS transistors can be lower.

[0234] Figure 6 and Figure 4A , Figure 4B , Figure 5 Similarly, the plan view of the semiconductor device 1 with N=3 is an example of the shape of the semiconductor device 1 when the current path determined by the specifications is (1) the current path flowing between the first vertical MOS transistor (Tr1) and the second vertical MOS transistor (Tr2), and (2) the current path flowing between the first vertical MOS transistor (Tr1) and the third vertical MOS transistor (Tr3), and (3) the current path flowing between the second vertical MOS transistor (Tr2) and the third vertical MOS transistor (Tr3) is not the current path determined by the specifications.

[0235] according to Figure 6 In the plan view of the semiconductor layer 40, the boundary lines between Tr1 and Tr2 and between Tr1 and Tr3 are not parallel to any of the four sides of the semiconductor device 1. That is, the boundary lines between Tr1 and Tr2 and between Tr1 and Tr3 are inclined relative to any of the four sides of the semiconductor device 1.

[0236] In contrast, according to Figure 4A The shape of the semiconductor device 1 shown in the plan view of the semiconductor layer 40 is such that the boundary lines of Tr1 and Tr2 and the boundary lines of Tr1 and Tr3 are parallel to one of the four sides of the semiconductor device 1.

[0237] Therefore, in the planar view of semiconductor layer 40, Figure 6 The boundary line ratio of Tr1 and Tr2 under the shape of the semiconductor device 1 shown is... Figure 4AThe length of the boundary line between Tr1 and Tr2 under the shape of the semiconductor device 1 shown is, and, Figure 6 The boundary line ratio of Tr1 and Tr3 under the shape of the semiconductor device 1 shown is... Figure 4A The length of the boundary line between Tr1 and Tr3 under the shape of the semiconductor device 1 shown.

[0238] Therefore, it can be said that Figure 6 The shape of the semiconductor device 1 shown is larger than that of the semiconductor device 1 shown. Figure 4A The shape of the semiconductor device 1 shown is more preferred.

[0239] Figure 7A and Figure 7B These are plan views of the semiconductor device 1 when N is 3. They are plan views showing an example of the shape of the semiconductor device 1 when the current paths determined by the specifications are (1) the current path flowing between the first vertical MOS transistor (Tr1) and the second vertical MOS transistor (Tr2), (2) the current path flowing between the first vertical MOS transistor (Tr1) and the third vertical MOS transistor (Tr3), and (3) the current path flowing between the second vertical MOS transistor (Tr2) and the third vertical MOS transistor (Tr3).

[0240] according to Figure 7A The shape of the semiconductor device 1 shown in the plan view of the semiconductor layer 40 is such that the boundary lines of Tr1 and Tr2, Tr1 and Tr3, and Tr2 and Tr3 are parallel to one of the four sides of the semiconductor device 1.

[0241] In contrast, according to Figure 7B In the plan view of the semiconductor layer 40, the boundary lines between Tr1 and Tr2 and between Tr1 and Tr3 are not parallel to any of the four sides of the semiconductor device 1. That is, the boundary lines between Tr1 and Tr2 and between Tr1 and Tr3 are inclined relative to any of the four sides of the semiconductor device 1.

[0242] Therefore, in the planar view of semiconductor layer 40, Figure 7B The boundary line ratio of Tr1 and Tr2 under the shape of the semiconductor device 1 shown is... Figure 7A The length of the boundary line between Tr1 and Tr2 under the shape of the semiconductor device 1 shown is, and, Figure 7B The boundary line ratio of Tr1 and Tr3 under the shape of the semiconductor device 1 shown is... Figure 7A The length of the boundary line between Tr1 and Tr3 under the shape of the semiconductor device 1 shown. Furthermore, Figure 7B The boundary line ratio of Tr2 and Tr3 under the shape of the semiconductor device 1 shown Figure 7AThe length of the boundary line between Tr2 and Tr3 under the shape of the semiconductor device 1 shown.

[0243] Therefore, it can be said that Figure 7B The shape of the semiconductor device 1 shown is larger than that of the semiconductor device 1 shown. Figure 7A The shape of the semiconductor device 1 shown is more preferred.

[0244] Furthermore, in the plan view of semiconductor layer 40, the boundary lines of the first inlet / outlet vertical MOS transistor located at the inlet or outlet of each of the more than one current paths determined by the specifications, and the second inlet / outlet vertical MOS transistor located at the outlet or inlet, are preferably formed by alternating line segments parallel to the first side of the four sides of semiconductor device 1 and line segments parallel to the second side orthogonal to the first side. It is preferable that the boundary line is a single line segment parallel to one of the four sides of semiconductor device 1.

[0245] This allows for a wider range of current flow between the first and second input / output vertical MOS transistors. In other words, it reduces the on-resistance of the current path determined by the first and second input / output vertical MOS transistors.

[0246] Figure 8 and Figure 4A , Figure 4B , Figure 5 , Figure 6 Similarly, the plan view of the semiconductor device 1 with N=3 is an example of the shape of the semiconductor device 1 when the current path determined by the specifications is (1) the current path flowing between the first vertical MOS transistor (Tr1) and the second vertical MOS transistor (Tr2), and (2) the current path flowing between the first vertical MOS transistor (Tr1) and the third vertical MOS transistor (Tr3), and (3) the current path flowing between the second vertical MOS transistor (Tr2) and the third vertical MOS transistor (Tr3) is not the current path determined by the specifications.

[0247] according to Figure 8 The shape of the semiconductor device 1 shown in the plan view of the semiconductor layer 40 is formed by alternating line segments parallel to the first side of the four sides of the semiconductor device 1 and line segments parallel to the second side orthogonal to the first side. That is, these boundary lines are stepped in the plan view of the semiconductor layer 40.

[0248] In contrast, according to Figure 4AThe shape of the semiconductor device 1 shown in the plan view of the semiconductor layer 40 is such that the boundary lines between Tr1 and Tr2 and between Tr1 and Tr3 are a single line segment parallel to one of the four sides of the semiconductor device 1.

[0249] Therefore, in the planar view of semiconductor layer 40, Figure 8 The boundary line ratio of Tr1 and Tr2 under the shape of the semiconductor device 1 shown is... Figure 4A The length of the boundary line between Tr1 and Tr2 under the shape of the semiconductor device 1 shown is, and, Figure 8 The boundary line ratio of Tr1 and Tr3 under the shape of the semiconductor device 1 shown is... Figure 4A The length of the boundary line between Tr1 and Tr3 under the shape of the semiconductor device 1 shown.

[0250] Therefore, it can be said that Figure 8 The shape of the semiconductor device 1 shown is larger than that of the semiconductor device 1 shown. Figure 4A The shape of the semiconductor device 1 shown is more preferred.

[0251] Figure 9 and Figure 7A , Figure 7B Similarly, the plan view of the semiconductor device 1 with N=3 is an example of the shape of the semiconductor device 1 when the current path determined by the specifications is (1) the current path flowing between the first vertical MOS transistor (Tr1) and the second vertical MOS transistor (Tr2), (2) the current path flowing between the first vertical MOS transistor (Tr1) and the third vertical MOS transistor (Tr3), and (3) the current path flowing between the second vertical MOS transistor (Tr2) and the third vertical MOS transistor (Tr3).

[0252] according to Figure 9 The shape of the semiconductor device 1 shown in the plan view of the semiconductor layer 40 is formed by alternating line segments parallel to the first side of the four sides of the semiconductor device 1 and line segments parallel to the second side orthogonal to the first side. That is, these boundary lines are stepped in the plan view of the semiconductor layer 40.

[0253] In contrast, according to Figure 7A The shape of the semiconductor device 1 shown in the plan view of the semiconductor layer 40 is such that the boundary lines between Tr1 and Tr2 and between Tr1 and Tr3 are a single line segment parallel to one of the four sides of the semiconductor device 1.

[0254] Therefore, in the planar view of semiconductor layer 40, Figure 9 The boundary line ratio of Tr1 and Tr2 under the shape of the semiconductor device 1 shown is... Figure 7A The length of the boundary line between Tr1 and Tr2 under the shape of the semiconductor device 1 shown is, and, Figure 9 The boundary line ratio of Tr1 and Tr3 under the shape of the semiconductor device 1 shown is... Figure 7A The length of the boundary line between Tr1 and Tr3 under the shape of the semiconductor device 1 shown. Furthermore, Figure 9 The boundary line ratio of Tr2 and Tr3 under the shape of the semiconductor device 1 shown Figure 7A The length of the boundary line between Tr2 and Tr3 under the shape of the semiconductor device 1 shown.

[0255] Therefore, it can be said that Figure 9 The shape of the semiconductor device 1 shown is larger than that of the semiconductor device 1 shown. Figure 7A The shape of the semiconductor device 1 shown is more preferred.

[0256] [1-4. Specific examples of the shape of semiconductor devices]

[0257] Hereinafter, specific examples of the shape of semiconductor device 1 will be illustrated using the accompanying drawings.

[0258] In the following figure, XA (X is a number) refers to the maximum rated current [A] of the vertical MOS transistor located at that position.

[0259] Figure 10A , Figure 10B , Figure 10C , Figure 10D These are plan views of semiconductor device 1 when N is 3.

[0260] In the planar view of semiconductor layer 40, let the area of ​​the first vertical MOS transistor 10 be S1, the area of ​​the second vertical MOS transistor 20 be S2, ..., and the area of ​​the Nth vertical MOS transistor be SN.

[0261] Figure 10A This is an example of the case where I1 = I2 = I3, in which I1 = 1 [A], I2 = 1 [A], and I3 = 1 [A]. Therefore, S1:S2:S3 = 1. 2 :1 2 :1 2 .

[0262] Figure 10B This is an example of the case where I1 = I2 > I3. In this example, I1 = 1.5 [A], I2 = 1.5 [A], and I3 = 1 [A]. Therefore, the ratio of S1:S2:S3 = 1.5. 2 1.5 2 :1 2 .

[0263] Figure 10CThis is an example of the case where I1 > I2 = I3. In this example, I1 = 2[A], I2 = 1[A], and I3 = 1[A]. Therefore, the ratio is S1:S2:S3 = 2. 2 :1 2 :1 2 .

[0264] Figure 10D This is an example of the case where I1 > I2 > I3. In this example, I1 = 3 [A], I2 = 2 [A], and I3 = 1 [A]. Therefore, the ratio is S1:S2:S3 = 3. 2 :2 2 :1 2 .

[0265] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 11H , Figure 11I , Figure 11J These are plan views of semiconductor device 1 when N is 4.

[0266] Figure 11A , Figure 11B This is an example of the case where I1 = I2 = I3 = I4. In this example, I1 = 1 [A], I2 = 1 [A], I3 = 1 [A], and I4 = 1 [A]. Therefore, the ratio is S1:S2:S3:S4 = 1. 2 :1 2 :1 2 :1 2 .

[0267] Figure 11C , Figure 11D This is an example of the case where I1 = I2 = I3 > I4. In this example, I1 = 1 [A], I2 = 1 [A], I3 = 1 [A], and I4 = 0.3 [A]. Therefore, S1:S2:S3:S4 = 1. 2 :1 2 :1 2 0.3 2 .

[0268] Figure 11E This is an example of the case where I1 = I2 > I3 = I4. In this example, I1 = 1 [A], I2 = 1 [A], I3 = 0.6 [A], and I4 = 0.6 [A]. Therefore, the ratio is S1:S2:S3:S4 = 1. 2 :1 2 0.6 2 0.6 2 .

[0269] Figure 11F This is an example of the case where I1 > I2 = I3 = I4 and I1 ≠ I2 + I3 + I4. In this example, I1 = 1.5 [A], I2 = 0.8 [A], I3 = 0.8 [A], and I4 = 0.8 [A]. Therefore, the ratio is S1:S2:S3:S4 = 1.5. 2 0.8 2 0.8 2 0.8 2 .

[0270] Figure 11G This is an example of the case where I1 > I2 = I3 = I4 and I1 = I2 + I3 + I4. In this example, I1 = 3 [A], I2 = 1 [A], I3 = 1 [A], and I4 = 1 [A]. Therefore, the ratio is S1:S2:S3:S4 = 3. 2 :1 2 :1 2 :1 2 .

[0271] Figure 11H This is an example of the case where I1 > I2 > I3 = I4. In this example, I1 = 1.4 [A], I2 = 1.1 [A], I3 = 0.5 [A], and I4 = 0.5 [A]. Therefore, the ratio is S1:S2:S3:S4 = 1.4. 2 1.1 2 0.5 2 0.5 2 .

[0272] Figure 11I This is an example of the case where I1 > I2 > I3 > I4 and I1 = I2 + I3 + I4. In this example, I1 = 2.5 [A], I2 = 1.3 [A], I3 = 0.7 [A], and I4 = 0.5 [A]. Therefore, S1:S2:S3:S4 = 2.5 2 1.3 2 0.7 2 0.5 2 .

[0273] Figure 11J This is an example of the case where I1 > I2 > I3 > I4 and I1 ≠ I2 + I3 + I4. In this example, I1 = 1.7 [A], I2 = 1.3 [A], I3 = 0.7 [A], and I4 = 0.5 [A]. Therefore, the ratio is S1:S2:S3:S4 = 1.7. 2 1.3 2 0.7 2 0.5 2 .

[0274] The following describes a semiconductor device 1 in which the maximum rated current of N vertical MOS transistors meets specific conditions. For convenience, this semiconductor device 1 will also be referred to as the first specific semiconductor device.

[0275] The first specific semiconductor device refers to a semiconductor device 1 in which one of the N vertical MOS transistors is a specific vertical MOS transistor that satisfies the following condition: the maximum specification current is equal to the sum of the maximum specification currents of K (K is an integer of 2 to N-1) vertical MOS transistors out of the N vertical MOS transistors.

[0276] Such a first specific semiconductor device is suitable for the following relationship: when the maximum specification current of each of the K vertical MOS transistors flows through the current path between the specific vertical MOS transistor and each of the K vertical MOS transistors, the current flowing through the specific vertical MOS transistor is the maximum specification current of that specific vertical MOS transistor.

[0277] A specific example of the shape of the first particular semiconductor device when N is 4 is, for example... Figure 11G , Figure 11I Example in.

[0278] The following describes a semiconductor device 1 in which the maximum rated current of N vertical MOS transistors and the number and shape of the source pads meet specific conditions. For convenience, this semiconductor device 1 will also be referred to as the second specific semiconductor device.

[0279] The second specific semiconductor device refers to a semiconductor device 1 in which at least one of the N vertical MOS transistors is a specific vertical MOS transistor satisfying the following conditions: it has one source pad; in the plan view of the semiconductor layer 40, the gate pad and source pad are perfectly circular; and among the gate pads and source pads of each of the N vertical MOS transistors, there are no gate pads and source pads whose area is intentionally reduced compared to the gate pads and source pads of the specific vertical MOS transistor.

[0280] This second specific semiconductor device is suitable for cases where a specific vertical MOS transistor is used as a transistor to monitor the voltage of the common drain region of N vertical MOS transistors. This is because the specific vertical MOS transistor does not need to carry a large current; it only needs to carry a small current. Therefore, it is sufficient to have the minimum required number (i.e., one) and minimum size of the source pads of the specific vertical MOS transistor. Furthermore, by setting the source pad of the specific vertical MOS transistor to one and the minimum size, the area used for the source pads of other vertical MOS transistors can be maximized.

[0281] Figure 12 This is a plan view showing an example of the structure of the source pad of a second specific semiconductor device.

[0282] Figure 12 This is an example where N is 3 and the number of specific vertical MOS transistors is 1. It is an example where the third vertical MOS transistor formed in region A3 is a specific vertical MOS transistor, and the first vertical MOS transistor formed in region A1 and the second vertical MOS transistor formed in region A2 are vertical MOS transistors that are not specific vertical MOS transistors.

[0283] like Figure 12 As shown, the third vertical MOS transistor, which is a specific vertical MOS transistor, has only one source pad, the third source pad 131. In the plan view of the semiconductor layer 40, among the source pads and gate pads of the three vertical MOS transistors, there are no source pads and gate pads whose area is intentionally reduced compared to the third source pad 131 and the third gate pad 139 of the third vertical MOS transistor, which is a specific vertical MOS transistor.

[0284] Hereinafter, specific examples of the shape of the second particular semiconductor device will be illustrated using the accompanying drawings.

[0285] Figure 13A , Figure 13B These are plan views of semiconductor device 1 when N is 3, the number of specific vertical MOS transistors is 1, and the third vertical MOS transistor is a specific vertical MOS transistor.

[0286] Figure 13A This is an example of the case where I1 = I2. In this example, I1 = 1 [A], I2 = 1 [A], and I3 << 1 [A].

[0287] Figure 13B This is an example of the case where I1 > I2. In this example, I1 = 3 [A], I2 = 2 [A], and I3 << 1 [A].

[0288] Figure 14A , Figure 14B These are plan views of semiconductor device 1 with N = 4, the number of specific vertical MOS transistors = 2, and the third and fourth vertical MOS transistors being specific vertical MOS transistors.

[0289] Figure 14A This is an example of the case where I1 = I2. In this example, I1 = 1 [A], I2 = 1 [A], I3 << 1 [A], and I4 << 1 [A].

[0290] Figure 14BThis is an example of the case where I1 > I2. In this example, I1 = 3 [A], I2 = 2 [A], I3 << 1 [A], and I4 << 1 [A].

[0291] The preferred configuration position of the gate pad in semiconductor device 1 will be described below.

[0292] (1) In N vertical MOS transistors, the first entrance-exit vertical MOS transistor located at the entrance or exit of the first current path and the second entrance-exit vertical MOS transistor located at the exit or entrance are adjacent to each other in the plan view of semiconductor layer 40, as determined by the specifications. (2) In N vertical MOS transistors, the first entrance-exit vertical MOS transistor located at the entrance or exit of the second current path and the third entrance-exit vertical MOS transistor located at the exit or entrance are adjacent to each other in the plan view of semiconductor layer 40, as determined by the specifications. (3) In N vertical MOS transistors, the second entrance-exit vertical MOS transistor located at the entrance or exit of the third current path and the third entrance-exit vertical MOS transistor located at the exit or entrance are adjacent to each other in the plan view of semiconductor layer 40, as determined by the specifications. Preferably, the gate pad of the third entrance-exit vertical MOS transistor is located on the extension line of the boundary line between the first entrance-exit vertical MOS transistor and the second entrance-exit vertical MOS transistor.

[0293] Figure 15 This is a plan view of a semiconductor device 1 in which the gate pad 139 of the third inlet / outlet vertical MOS transistor is arranged in the above-mentioned preferred position when N is 3.

[0294] like Figure 15 As shown, in the plan view of semiconductor layer 40, the gate pad 139 of the third vertical MOS transistor, which is the third entrance vertical MOS transistor, is located on the extension line of the boundary line between the first entrance vertical MOS transistor and the second entrance vertical MOS transistor.

[0295] By placing the gate pad 139 of the third inlet / outlet vertical MOS transistor at the aforementioned location, in the plan view of the semiconductor layer 40, the area used to place the source pad 131 of the third inlet / outlet vertical MOS transistor can be maximized in the third region A3 on the second and third current paths, thus suppressing the resistance values ​​of the second and third current paths.

[0296] Furthermore, when the maximum rated current of the third input / output vertical MOS transistor is smaller than that of the first input / output vertical MOS transistor and the second input / output vertical MOS transistor, it is preferable that the gate pad of the first input / output vertical MOS transistor is not disposed near the boundary between the first input / output vertical MOS transistor and the third input / output vertical MOS transistor, and it is preferable that the gate pad of the second input / output vertical MOS transistor is not disposed near the boundary between the second input / output vertical MOS transistor and the third input / output vertical MOS transistor.

[0297] Figure 16 It is recorded in Figure 15 The diagram shows a plan view of the semiconductor device 1 in which the configuration of the gate pad 119 of the first and second vertical MOS transistors is not preferred when the maximum specification current of the third vertical MOS transistor is smaller than that of the first and second vertical MOS transistors.

[0298] exist Figure 16 In the above, region B1 is a region where the configuration of the gate pad 119 of the first entrance / exit vertical MOS transistor and the gate pad 129 of the second entrance / exit vertical MOS transistor is not preferred.

[0299] Furthermore, if the width of the first entrance / exit vertical MOS transistor in the planar view of semiconductor layer 40 is larger than twice the diameter of the gate pad 119 of the first entrance / exit vertical MOS transistor in a direction orthogonal to the boundary line of the first entrance / exit vertical MOS transistor and the second entrance / exit vertical MOS transistor, it is even more preferable that the gate pad 119 of the first entrance / exit vertical MOS transistor is not disposed near the boundary of the first entrance / exit vertical MOS transistor and the second entrance / exit vertical MOS transistor.

[0300] By not placing the gate pad 119 of the first inlet / outlet vertical MOS transistor in the aforementioned position, the situation where the gate pad 119 obstructs the current flowing in the first current path is suppressed, thus suppressing the resistance value of the first current path.

[0301] Similarly, if the width of the second entrance-exit vertical MOS transistor in the planar view of semiconductor layer 40 is larger than twice the diameter of the gate pad 129 of the second entrance-exit vertical MOS transistor in a direction orthogonal to the boundary line of the first entrance-exit vertical MOS transistor and the second entrance-exit vertical MOS transistor, it is further preferred that the gate pad 129 of the second entrance-exit vertical MOS transistor is not disposed near the boundary between the first entrance-exit vertical MOS transistor and the second entrance-exit vertical MOS transistor.

[0302] By not placing the gate pad 129 of the second inlet / outlet vertical MOS transistor in the aforementioned position, the situation where the gate pad 129 obstructs the current flowing in the first current path is suppressed, thus suppressing the resistance value of the first current path.

[0303] Figure 17 It is recorded Figure 15 The following is a plan view of the semiconductor device 1, showing a region in which the following is not preferred: In the plan view of the semiconductor layer 40, the width of the first entrance / exit vertical MOS transistor in a direction orthogonal to the boundary lines of the first entrance / exit vertical MOS transistor and the second entrance / exit vertical MOS transistor is larger than twice the diameter of the gate pad 119 of the first entrance / exit vertical MOS transistor, and the width of the second entrance / exit vertical MOS transistor in a direction orthogonal to the boundary lines of the first entrance / exit vertical MOS transistor and the second entrance / exit vertical MOS transistor is larger than twice the diameter of the gate pad 129 of the second entrance / exit vertical MOS transistor, in which case the arrangement of the gate pads 119 of the first entrance / exit vertical MOS transistor and the gate pads 129 of the second entrance / exit vertical MOS transistor is not preferred.

[0304] exist Figure 17 In the diagram, region B2 is a region where the configuration of the gate pad 119 of the first inlet / outlet vertical MOS transistor is not preferred, and region B3 is a region where the configuration of the gate pad 129 of the second inlet / outlet vertical MOS transistor is not preferred.

[0305] Furthermore, (1) in the N vertical MOS transistors, the first entrance / exit vertical MOS transistor located at the entrance or exit of the first current path and the second entrance / exit vertical MOS transistor located at the exit or entrance are adjacent to each other in the plan view of semiconductor layer 40, as determined by specifications; (2) in the N vertical MOS transistors, the second entrance / exit vertical MOS transistor located at the entrance or exit of the second current path and the third entrance / exit vertical MOS transistor located at the exit or entrance are adjacent to each other in the plan view of semiconductor layer 40. When the first and third vertical MOS transistors are adjacent to each other, and neither of the current paths determined by the first and third vertical MOS transistors corresponds to the current path determined by the specification, and the first and third vertical MOS transistors are adjacent to each other in the planar view of the semiconductor layer 40, the gate pad of the third vertical MOS transistor is preferably closer to the boundary line between the first and third vertical MOS transistors than the boundary line between the second and third vertical MOS transistors.

[0306] Figure 18This is a plan view of a semiconductor device 1 in which the gate pad of the third inlet / outlet vertical MOS transistor is arranged in the above-mentioned preferred position when N is 3.

[0307] like Figure 18 As shown in the plan view of semiconductor layer 40, the gate pad 139 of the third vertical MOS transistor, which is the third entrance vertical MOS transistor, is closer to the boundary line between the first entrance vertical MOS transistor and the third vertical MOS transistor than the boundary line between the second entrance vertical MOS transistor and the third vertical MOS transistor.

[0308] By placing the gate pad 139 of the third inlet / outlet vertical MOS transistor at the aforementioned location, the area in the third region A3 of the second current path used to place the source pad of the third inlet / outlet vertical MOS transistor can be maximized in the plan view of the semiconductor layer 40, thereby suppressing the resistance value of the second current path.

[0309] Furthermore, when the maximum rated current of the third input / output vertical MOS transistor is smaller than that of the first input / output vertical MOS transistor and the second input / output vertical MOS transistor, it is preferable that the gate pad of the second input / output vertical MOS transistor is not disposed near the boundary between the second input / output vertical MOS transistor and the third input / output vertical MOS transistor.

[0310] Figure 19 It is recorded in Figure 18 The diagram shows a plan view of the semiconductor device 1 in which the configuration of the gate pad 129 of the second-entry vertical MOS transistor is not preferred when the maximum specification current of the third-entry vertical MOS transistor is smaller than that of the first-entry vertical MOS transistor and the second-entry vertical MOS transistor.

[0311] exist Figure 19 In the middle, region B4 is the region where the configuration of the gate pad 129 of the second inlet / outlet vertical MOS transistor is not preferred.

[0312] Furthermore, in the planar view of semiconductor layer 40, if the width of the second entrance-exit vertical MOS transistor in the direction orthogonal to the boundary line of the first entrance-exit vertical MOS transistor and the second entrance-exit vertical MOS transistor is larger than twice the diameter of the gate pad 129 of the second entrance-exit vertical MOS transistor, it is even more preferable that the gate pad 129 of the second entrance-exit vertical MOS transistor is not disposed near the boundary between the first entrance-exit vertical MOS transistor and the second entrance-exit vertical MOS transistor.

[0313] By not placing the gate pad 129 of the second inlet / outlet vertical MOS transistor in the aforementioned position, the situation where the gate pad 129 obstructs the current flowing in the first current path is suppressed, thus suppressing the resistance value of the first current path.

[0314] Figure 20 It is recorded in Figure 18 The diagram shows a plan view of the semiconductor device 1 in which the width of the second entrance vertical MOS transistor in the semiconductor layer 40 is larger than twice the diameter of the gate pad 129 of the second entrance vertical MOS transistor in a direction orthogonal to the boundary lines of the first entrance vertical MOS transistor and the second entrance vertical MOS transistor, and the configuration of the gate pad 129 of the second entrance vertical MOS transistor is not preferred.

[0315] exist Figure 20 In the middle, region B5 is the region where the configuration of the gate pad 129 of the second entrance / exit vertical MOS transistor is not preferred.

[0316] Hereinafter, using the accompanying drawings, specific examples are illustrated of areas in which the gate pads in semiconductor devices 1 of various shapes are not preferably configured.

[0317] Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 21E , Figure 21F , Figure 21G , Figure 21H These are plan views of semiconductor device 1.

[0318] exist Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 21E , Figure 21F , Figure 21G , Figure 21H In the diagram, areas where the gate pad configuration is not preferred are shown as areas surrounded by shaded areas.

[0319] [1-5. Examples of structures with pads connected to the common drain region]

[0320] Semiconductor device 1 may also have a structure in which drain pads connected to the common drain regions of N vertical MOS transistors are also present on the upper surface of semiconductor layer 40.

[0321] Figure 22A This is a cross-sectional view showing an example of the structure of a semiconductor device 1 that also has a drain pad. Figure 22BThis is a plan view illustrating an example of the structure of a semiconductor device 1 that also has a drain pad. Figure 22A express Figure 22B Sectional view I-I in the middle.

[0322] like Figure 22B As shown, the semiconductor device 1 may also have a drain pad 141.

[0323] Semiconductor device 1, also having drain pad 141, such as Figure 22A As shown, it has a high-concentration impurity layer 38 and a drain electrode 81.

[0324] The drain electrode 81 is composed of a portion 82 and a portion 83, with portion 82 connected to the high-concentration impurity layer 38 (described later) via portion 83.

[0325] The portion 82 of the drain electrode 81, like the portion 12 of the first source electrode 11, is a layer that bonds with the solder during reflow when mounted face down. As an example without limitation, it can be made of any one or more metallic materials including nickel, titanium, tungsten, and palladium. The surface of the portion 82 can be plated with a layer of gold or the like.

[0326] The portion 83 of the drain electrode 81 is a layer that connects the portion 82 to the high-concentration impurity layer 38. As an example that is not limited, it may be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0327] Drain pad 141 refers to the area where the drain electrode 81 is partially exposed on the upper surface of the semiconductor device 1, also known as the terminal portion.

[0328] A high-concentration impurity layer 38 is formed in the semiconductor layer 40 in contact with the semiconductor substrate 32, the low-concentration impurity layer 33 and part of 83, and contains a higher concentration of first-conductivity type impurities than the first-conductivity type impurities in the semiconductor substrate 32.

[0329] Therefore, the high-concentration impurity layer 38, the semiconductor substrate 32 which functions as the common drain region of N vertical MOS transistors, and the low-concentration impurity layer 33 are electrically connected to the drain electrode 81.

[0330] Furthermore, the description up to this point is based on a vertical MOS transistor, but this disclosure is not intended to be limited to this. It is also valid to call a vertical MOS transistor a vertical transistor. Besides the vertical MOS transistor, other examples of vertical transistors include vertical bipolar transistors (BJTs) and vertical insulated-gate bipolar transistors (IGBTs). The basic structure and function of BJTs and IGBTs are well known to those skilled in the art, so detailed descriptions are omitted, but their similarity to MOS transistors can be understood as follows: In the case of a vertical BJT, in the above description, the source can be referred to as the emitter, the drain as the collector, and the body as the base. Furthermore, the gate electrode can be referred to as the base electrode. In the case of a vertical IGBT, in the above description, the source can be referred to as the emitter and the drain as the collector. Additionally, "vertical" refers to a structure in which a channel is formed in the vertical direction of the semiconductor device to allow current to flow.

[0331] Alternatively, if the semiconductor device 1 is a vertical transistor, it may not have a drain pad, but instead a common terminal formed by connecting to the metal layer 30 (i.e., the common electrode common to the N vertical transistors) formed on the lower surface of the semiconductor layer 40 and winding towards the upper surface of the semiconductor layer 40. The N vertical transistors originally have a control pad (gate pad in the example of a vertical MOS transistor) and one or more external connection pads (source pads in the example of a vertical MOS transistor) on the upper surface of the semiconductor layer 40. The control pads are connected to the control electrode (gate electrode in the example of a vertical MOS transistor) that controls the conduction of the vertical transistors, and the one or more external connection pads are connected to the external connection electrodes (source electrodes in the example of a vertical MOS transistor) that allow current to flow into or out of the N vertical transistors. In a semiconductor device 1 composed of N vertical transistors, a common terminal can be designated as an external input terminal from which current flows into the N vertical transistors, and each of the N vertical transistors can have one or more external connection pads designated as external output terminals from which current flows out of the N vertical transistors. The lower surface of the semiconductor layer 40 is the main surface opposite to the main surface of the side on which the N vertical transistors are formed.

[0332] Figure 23 This is a cross-sectional view showing an example of the structure of a semiconductor device 1 that also has a common terminal when the semiconductor device 1 is a vertical transistor.

[0333] like Figure 23 As shown, the semiconductor device 1 may have a structure that includes a common terminal 300 even when the semiconductor device 1 is a vertical transistor.

[0334] (Implementation Method 2)

[0335] The battery protection system of Embodiment 2 will be described below.

[0336] [2-1. Structure of the Battery Protection System]

[0337] Figure 24 This is a circuit diagram illustrating an example of the structure of the battery protection system 100 according to Embodiment 2.

[0338] like Figure 24 As shown, the battery protection system 100 includes a battery protection circuit 50 and a charge / discharge control IC 60.

[0339] In addition, the battery protection circuit 50 includes a first semiconductor device 1a, a second semiconductor device 1b, N-1 battery cells 5, a first terminal 61, and a second terminal 62.

[0340] The charge / discharge control IC 60 controls the first semiconductor device 1a and the second semiconductor device 1b to control the charging and discharging of N-1 battery cells 5.

[0341] The first semiconductor device 1a is the semiconductor device 1 described in detail in Embodiment 1, and includes N vertical MOS transistors. The on-state (ON state) and off-state (OFF state) of each vertical MOS transistor are controlled by the charge / discharge control IC 60.

[0342] exist Figure 24 From here on, arrows extending from the control IC to each semiconductor device indicate the situation where signals for controlling each semiconductor device are sent from the control IC. In practice, the control IC is electrically connected to the gate pads of the respective vertical MOS transistors constituting each semiconductor device to control the conduction state of each vertical MOS transistor, but... Figure 24 From now on, arrows will be used to avoid making the representation more complicated.

[0343] The second semiconductor device 1b is the semiconductor device 1 described in detail in Embodiment 1, and includes N vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by a charge / discharge control IC 60.

[0344] The first terminal 61 is connected to one of the N vertical MOS transistors of the first semiconductor device 1a and to one or more source pads of the vertical MOS transistor 2a.

[0345] The second terminal 62 is connected to one of the N vertical MOS transistors of the second semiconductor device 1b, and to one or more source pads of the vertical MOS transistor 2b.

[0346] The positive terminal of each of the N-1 battery cells 5 is connected to one or more source pads of the N-1 vertical MOS transistors (excluding the terminal-connected vertical MOS transistor 2a) in the first semiconductor device 1a.

[0347] Furthermore, the negative electrode of each of the N-1 battery cells 5 is connected to one or more source pads of the N-1 vertical MOS transistors (excluding the terminal-connected vertical MOS transistor 2b) in the second semiconductor device 1b.

[0348] [2-2. Operation of the Battery Protection System]

[0349] The operation of the battery protection system 100 with the above structure will be explained below.

[0350] Figure 25A This is a schematic diagram illustrating the charging status of the battery protection system 100 for N-1 battery cells 5. Figure 25A In the diagram, the dashed arrows represent the charging paths of each of the N-1 battery cells 5.

[0351] During charging, the charge / discharge control IC 60 connects N-1 vertical MOS transistors (excluding the terminal connected to the vertical MOS transistor 2a) of the first semiconductor device 1a. Figure 25A The vertical MOS transistor (surrounded by dashed lines) is set to the ON state, and the terminals of the second semiconductor device 1b are connected to the vertical MOS transistor 2b, thereby charging the N-1 battery cells 5 in parallel at the same time.

[0352] In addition, although Figure 25A Although not illustrated, the charge / discharge control IC 60 can also selectively charge only one or not all of the N-1 battery cells 5 simultaneously in parallel.

[0353] If the charge / discharge control IC 60 detects an abnormality related to charging during charging, it changes the connection of the terminal of the second semiconductor device 1b to the vertical MOS transistor 2b from the on state to the off state, thereby stopping the charging of N-1 battery cells 5.

[0354] This protects N-1 battery cells 5 from adverse effects caused by charging-related anomalies.

[0355] Furthermore, if the charge / discharge control IC 60 detects an abnormality related to charging during charging, it will connect N-1 vertical MOS transistors of the first semiconductor device 1a, excluding the terminal connected vertical MOS transistor 2a. Figure 25AThe vertical MOS transistor (surrounded by dashed lines) connected to the battery cell 5 related to the detected anomaly changes from the on state to the off state, thereby stopping the charging of the corresponding battery cell 5.

[0356] This protects the corresponding battery cell 5 from adverse effects caused by charging-related anomalies.

[0357] Figure 25B This is a schematic diagram illustrating the state of the battery protection system 100 discharging N-1 battery cells 5. Figure 25B In the diagram, the dashed arrows represent the discharge paths of each of the N-1 battery cells 5.

[0358] During discharge, the charge / discharge control IC 60 connects N-1 vertical MOS transistors of the second semiconductor device 1b, excluding the terminal connected to the vertical MOS transistor 2b. Figure 25B The vertical MOS transistor (surrounded by dashed lines) is set to the ON state, and the terminals of the first semiconductor device 1a are connected to the vertical MOS transistor 2a, thereby discharging N-1 battery cells 5 in parallel simultaneously.

[0359] In addition, although Figure 25B Although not illustrated, the charge / discharge control IC 60 can also selectively discharge only one or not all of the N-1 battery cells 5 simultaneously in parallel.

[0360] When the charge / discharge control IC 60 detects an abnormality related to discharge during discharge, it changes the connection between the terminal of the first semiconductor device 1a and the vertical MOS transistor 2a from the on state to the off state, thereby stopping the discharge of the N-1 battery cells 5.

[0361] This protects N-1 battery cells 5 from adverse effects caused by discharge-related anomalies.

[0362] Furthermore, if the charge / discharge control IC 60 detects an abnormality related to discharge during discharge, it will connect N-1 vertical MOS transistors of the second semiconductor device 1b, excluding the terminal connected vertical MOS transistor 2b. Figure 25B The vertical MOS transistor (surrounded by dashed lines) connected to the battery cell 5 related to the detected anomaly changes from the on state to the off state, thereby stopping the discharge of the corresponding battery cell 5.

[0363] This protects the corresponding battery cell 5 from adverse effects caused by discharge-related anomalies.

[0364] The semiconductor device 1a in Embodiment 2 will be described. In the product specification of semiconductor device 1a, N vertical MOS transistors are defined, with terminal-connected vertical MOS transistor 2a and N-1 other vertical MOS transistors (excluding terminal-connected vertical MOS transistor 2a) serving as input / output vertical MOS transistors for one and the other, respectively, forming N-1 current paths. Terminal-connected vertical MOS transistor 2a is an input / output vertical MOS transistor common to all of the defined N-1 current paths. In Embodiment 2, since the defined N-1 current paths are electrically equivalent, the maximum specification current (denoted as Ia[A]) of each of the N-1 vertical MOS transistors (excluding terminal-connected vertical MOS transistor 2a) is equal. Furthermore, the maximum specification current (denoted as In[A]) of terminal-connected vertical MOS transistor 2a is equal to the sum of the maximum specification currents Ia of each of the N-1 vertical MOS transistors (excluding terminal-connected vertical MOS transistor 2a) (In = Ia × (N-1)). Therefore, semiconductor device 1a is a first specific semiconductor device that connects the terminal to the vertical MOS transistor 2a as a specific vertical MOS transistor.

[0365] Furthermore, the product specification of semiconductor device 1a specifies the on-resistance (connection resistance) of each of the N-1 current paths when the maximum rated current In flows through the terminal-connected vertical MOS transistor 2a and the maximum rated current Ia flows through each of the N-1 vertical transistors other than the terminal-connected vertical MOS transistor 2a. Since the N-1 current paths are electrically equivalent, their on-resistance (connection resistance, denoted as Ran [Ω]) is all equal. Therefore, in the product specification, there are cases where only one on-resistance is specified to avoid repetition. Additionally, the product specification specifies the current value used to evaluate the on-resistance (connection resistance) for each of the N vertical MOS transistors. The current value used to evaluate the on-resistance (connection resistance) is a current value that is 50% of the maximum rated current specified for each of the N vertical MOS transistors, or a current value below that maximum rated current. When evaluating on-resistance, the current value specified in the product datasheet as the current flowing in each of the N vertical MOS transistors can be understood as the maximum rated current of each of the N vertical MOS transistors. Alternatively, the maximum rated current of each of the N vertical MOS transistors specified in the product datasheet can also be understood as the maximum rated current of each of the N vertical MOS transistors.

[0366] Furthermore, to ensure the N-1 current paths are electrically equivalent, it is preferable that the areas (denoted as Sa) of the N-1 vertical MOS transistors, excluding the terminal-connected vertical MOS transistor 2a, are all equal, thereby ensuring that the area of ​​the terminal-connected vertical MOS transistor 2a (denoted as Sn) is the largest among the N vertical MOS transistors (Sn>Sa). This is because the maximum rated current of the N-1 vertical MOS transistors, excluding the terminal-connected vertical MOS transistor 2a, is all equal, thus maximizing the maximum rated current of the terminal-connected vertical MOS transistor 2a. More specifically, it is preferable that Sa:Sn = Ia. 2 In 2 If the relationship holds true, the preferred value is Sa:Sn = 1:(N-1). 2 The relationship is valid. Furthermore, regarding the on-resistance Ra (Ra = Ran × Sn / (Sa + Sn)) of the N-1 vertical MOS transistors (excluding the terminal-connected vertical MOS transistor 2a) when the maximum specification current Ia flows through them, and the on-resistance Rn (Rn = Ran × Sa / (Sa + Sn)) of the terminal-connected vertical MOS transistor 2a when the maximum specification current In = Ia × (N-1) flows through it, Ia is preferred. 2 In 2 =1 / Ra : 1 / Rn holds true. By establishing this relationship, localized heating can be suppressed in semiconductor device 1a.

[0367] Furthermore, in Embodiment 2, the structure of the battery protection system 100, which has a first semiconductor device 1a on the positive electrode side of N-1 battery cells 5 and a second semiconductor device 1b on the negative electrode side, was described. In contrast, the battery protection system of Embodiment 2 may also have a structure in which the first semiconductor device 1a is only on the positive electrode side of N-1 battery cells 5, or it may have a structure in which the second semiconductor device 1b is only on the negative electrode side of N-1 battery cells 5.

[0368] Figure 26 This is a circuit diagram illustrating an example of the structure of the battery protection system 100a of Embodiment 2, which has a first semiconductor device 1a on the positive electrode side of N-1 battery cells 5.

[0369] like Figure 26 As shown, the battery protection system 100a is constructed by changing the battery protection circuit 50 to battery protection circuit 50a and changing the charge / discharge control IC 60 to charge control IC 60a from the battery protection system 100.

[0370] Furthermore, the battery protection circuit 50a is configured by removing the second semiconductor device 1b from the battery protection circuit 50 and changing the connection target of the second terminal 62 from one or more source pads of the terminal connected to the vertical MOS transistor 2b to the negative terminals of N-1 battery cells 5.

[0371] The charging control IC 60a controls the first semiconductor device 1a to control the charging of N-1 battery cells 5.

[0372] During charging, the charging control IC 60a sets N-1 vertical MOS transistors of the first semiconductor device 1a to the on state, except for the vertical MOS transistor 2a connected to the terminal, so as to charge N-1 battery cells 5 simultaneously in parallel.

[0373] In addition, although Figure 26 Although not illustrated, the charging control IC 60a can also selectively charge only one or not all of the N-1 battery cells 5 simultaneously in parallel.

[0374] When the charging control IC 60a detects an abnormality related to charging during charging, it changes the vertical MOS transistor connected to the battery cell 5 related to the detected abnormality from the on state to the off state among the N-1 vertical MOS transistors of the first semiconductor device 1a, excluding the vertical MOS transistor 2a connected to the terminal, and stops the charging of the corresponding battery cell 5.

[0375] This protects the corresponding battery cell 5 from adverse effects caused by charging-related anomalies.

[0376] Figure 27 This is a circuit diagram illustrating an example of the structure of the battery protection system 100b in Embodiment 2, which has a second semiconductor device 1b on the negative electrode side of N-1 battery cells 5.

[0377] like Figure 27 As shown, the battery protection system 100b is constructed by changing the battery protection circuit 50 to battery protection circuit 50b and changing the charge / discharge control IC 60 to discharge control IC 60b from the battery protection system 100.

[0378] Furthermore, the battery protection circuit 50b is configured by removing the first semiconductor device 1a from the battery protection circuit 50 and changing the connection target of the first terminal 61 from one or more source pads of the terminal connected to the vertical MOS transistor 2a to the positive terminals of N-1 battery cells 5.

[0379] The discharge control IC60b controls the second semiconductor device 1b to control the discharge of N-1 battery cells 5.

[0380] During discharge, the discharge control IC60b sets N-1 vertical MOS transistors of the second semiconductor device 1b to the on state, except for the vertical MOS transistor 2b connected to the terminal, so that the N-1 battery cells 5 are discharged in parallel at the same time.

[0381] In addition, although Figure 27 Although not illustrated, the discharge control IC60b can also selectively discharge only one or not all of the N-1 battery cells 5 simultaneously in parallel.

[0382] When the discharge control IC 60b detects an abnormality related to the discharge during discharge, it changes the vertical MOS transistor connected to the battery cell 5 related to the detected abnormality from the on state to the off state among the N-1 vertical MOS transistors of the second semiconductor device 1b, excluding the vertical MOS transistor 2b connected to the terminal, thereby stopping the charging of the corresponding battery cell 5.

[0383] This protects the corresponding battery cell 5 from adverse effects caused by discharge-related anomalies.

[0384] (Implementation Method 3)

[0385] The battery protection system of Embodiment 3 will be described below.

[0386] [3-1. Structure of the Battery Protection System]

[0387] Figure 28 This is a circuit diagram illustrating an example of the structure of the battery protection system 100c according to Embodiment 3.

[0388] like Figure 28 As shown, the battery protection system 100c includes a battery protection circuit 50c and a charge / discharge control IC 60c.

[0389] In addition, the battery protection circuit 50c includes a first semiconductor device 1c, a second semiconductor device 1d, N battery cells 5, 2N-2 semiconductor switching devices 9, a first terminal 61c, a second terminal 62c, and a third terminal 63c.

[0390] The charge / discharge control IC 60c controls the first semiconductor device 1c, the second semiconductor device 1d, and 2N-2 semiconductor switching devices 9 to control the charging and discharging of N battery cells 5.

[0391] The first semiconductor device 1c is the semiconductor device 1 described in detail in Embodiment 1, and includes N vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by a charge / discharge control IC 60c.

[0392] The second semiconductor device 1d is the semiconductor device 1 described in detail in Embodiment 1, and includes three vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by a charge / discharge control IC 60c.

[0393] The 2N-2 semiconductor switching devices 9 each have two vertical MOS transistors that share a common drain region. The on and off states of each vertical MOS transistor are controlled by the charge / discharge control IC 60c.

[0394] The current path from the source electrode of the other vertical MOS transistor to the source electrode of the other vertical MOS transistor becomes conductive when one of the vertical MOS transistors is in the ON state, and the current path from the source electrode of one vertical MOS transistor to the source electrode of the other vertical MOS transistor becomes conductive when the other vertical MOS transistor is in the ON state.

[0395] N battery cells are connected in series. In embodiment 3, among the N battery cells connected in series, N-1 battery cells 5, excluding battery cell 5a located at the negative electrode end, are connected in series via semiconductor switch device 9, and battery cell 5a and battery cell 5b located next to battery cell 5a in the series connection are connected in series via second semiconductor device 1d.

[0396] The first terminal 61c is connected to one of the N vertical MOS transistors of the first semiconductor device 1c and to one or more source pads of the vertical MOS transistor 2c, and the second semiconductor device 1d is connected to one of the three vertical MOS transistors of the second semiconductor device 1d and to one or more source pads of the vertical MOS transistor 2d.

[0397] The second terminal 62c is connected to the negative terminals of the N battery cells 5. In embodiment 3, the negative terminal of each battery cell 5 is connected to the second terminal 62c via a semiconductor switching device 9.

[0398] The third terminal 63c is connected to the positive terminal of the battery cell 5c located at the positive terminal end of the N battery cells 5 connected in series.

[0399] The positive electrode of each of the N-1 battery cells 5 (excluding battery cell 5a) is connected to one or more source pads of the N-1 vertical MOS transistors (excluding the terminal-connected vertical MOS transistor 2c) in the first semiconductor device 1c.

[0400] The positive electrode of battery cell 5a and the negative electrode of battery cell 5b are respectively connected to one or more source pads of two of the three vertical MOS transistors in the second semiconductor device 1d, excluding the vertical MOS transistor 2d which is connected to the terminal.

[0401] [3-2. Operation of the Battery Protection System]

[0402] The operation of the battery protection system 100c with the above structure will be explained below.

[0403] Figure 29A This is a schematic diagram illustrating the charging of N battery cells 5 in series by the battery protection system 100c. Figure 29A In the diagram, the dashed arrows represent the charging paths of the N battery cells 5.

[0404] During series charging, the charge / discharge control IC 60c sets the vertical MOS transistors on the side of the N-2 semiconductor switching devices 9 connected to the positive terminal of the battery cell 5 between the N-1 battery cells 5 (excluding battery cell 5a) sandwiched among the N battery cells 5 to the on state, sets the vertical MOS transistors on the side of the second semiconductor device 1d connected to the positive terminal of the battery cell 5a to the on state, and sets the vertical MOS transistors on the side of the semiconductor switching device 9 connected to the second terminal 62c sandwiched between the battery cell 5a and the second terminal 62c to the on state, thereby charging the N battery cells 5 in series simultaneously.

[0405] When the charge / discharge control IC 60c detects an abnormality related to charging during series charging, it changes the vertical MOS transistor on the side of the second semiconductor device 1d connected to the positive terminal of battery cell 5a from the on state to the off state, thereby stopping the charging of N battery cells.

[0406] Thus, the N battery cells 5 are protected from adverse effects caused by charging-related anomalies. Furthermore, when the series charging is stopped by switching the vertical MOS transistor on the side connected to the negative terminal of the semiconductor switching device 9 (which is connected to the negative terminal of the battery cell 5a during series charging) from the on state to the off state, the voltage on the positive terminal side of the battery cell 5a can be continuously supplied to the outside via the first terminal 61c from the vertical MOS transistor 2d connected to the terminal of the second semiconductor device 1d.

[0407] Figure 29B This is a schematic diagram illustrating the state of the battery protection system 100c discharging N battery cells 5. Figure 29B In the diagram, the dashed arrows represent the discharge paths of each of the N battery cells 5.

[0408] During discharge, the charge / discharge control IC 60c sets the vertical MOS transistors on the side of the N semiconductor switching devices 9 connected to the negative terminals of the N battery cells 5 to the on state, which are sandwiched between the negative terminals of the N battery cells 5 and the second terminal 62c, sets the terminal of the second semiconductor device 1d connected to the vertical MOS transistor 2d to the on state, and sets the terminal of the first semiconductor device 1c connected to the vertical MOS transistor 2c to the on state, thereby discharging the N battery cells 5 simultaneously in parallel.

[0409] In addition, although Figure 29B Although not illustrated, the charge / discharge control IC 60c can also selectively charge only one or not all of the N battery cells 5 simultaneously in parallel.

[0410] When the charge / discharge control IC 60c detects an abnormality related to the discharge during discharge, it changes the vertical MOS transistor on the side of the semiconductor switching device 9 connected to the negative terminal of the battery cell 5 associated with the detected abnormality from the on state to the off state, thereby stopping the discharge of the corresponding battery cell 5.

[0411] This protects the corresponding battery cell 5 from adverse effects caused by discharge-related anomalies.

[0412] Figure 29C This is a schematic diagram illustrating the parallel charging of N battery cells 5 by the battery protection system 100c. Figure 29C In the diagram, the dashed arrows represent the charging paths of each of the N battery cells 5.

[0413] When charging in parallel, the charge / discharge control IC 60c sets the vertical MOS transistors on the side connected to the second terminal 62c of the N semiconductor switching devices 9 that are sandwiched between the negative terminals of the N battery cells 5 and the second terminal 62c to the on state, sets the vertical MOS transistors connected to the positive terminal of the battery cell 5a of the second semiconductor device 1d to the on state, and sets the N-1 vertical MOS transistors of the first semiconductor device 1c, except for the vertical MOS transistor 2c connected to the terminal, to the on state, thereby charging the N battery cells 5 in parallel at the same time.

[0414] In addition, although Figure 29C Although not illustrated, the charge / discharge control IC 60c can also selectively charge only one or not all of the N battery cells 5 simultaneously in parallel.

[0415] When the charge / discharge control IC 60c detects an abnormality related to charging during parallel charging, it changes the vertical MOS transistor on the side of the semiconductor switching device 9 connected to the second terminal 62c of the semiconductor switching device 9 that is sandwiched between the negative terminal of each of the N battery cells 5 and the second terminal 62c from the on state to the off state, thereby stopping the charging of the corresponding battery cell 5.

[0416] This protects the corresponding battery cell 5 from adverse effects caused by charging-related anomalies.

[0417] The second semiconductor device 1d of this embodiment 3 will be described. In the product specification of the second semiconductor device 1d, three current paths are defined so that regardless of which two of the three vertical MOS transistors are selected, they become either the input / output vertical MOS transistors of one or the other. In this embodiment 3, the vertical MOS transistor connected to the negative terminal of battery cell 5b and the vertical MOS transistor connected to the positive terminal of battery cell 5a are used as either the input / output vertical MOS transistors of one or the other because... Figure 29A As shown, it is used for series charging, so a large current is passed. However, in each of the two current paths of the vertical MOS transistor 2d, which is connected to the terminal as one or the other as the input / output, a large current is not required. Therefore, the maximum specification current of the vertical MOS transistor connected to the negative terminal of battery cell 5b and the vertical MOS transistor connected to the positive terminal of battery cell 5a is equal (let's call it Ia[A]), which is greater than the maximum specification current of the vertical MOS transistor 2d connected to the terminal (let's call it It[A]) (Ia>It).

[0418] In the product specification of the second semiconductor device 1d, the on-resistances (contact resistances) of the three set current paths are described. For the current paths with the vertical MOS transistors connected to the negative electrode of the battery cell 5b and the vertical MOS transistors connected to the positive electrode of the battery cell 5a as the inlet / outlet vertical MOS transistors on one side or the other, the on-resistance (contact resistance, denoted as Raa [Ω]) when Ia flows is described. In addition, for the current paths with the vertical MOS transistors connected to the negative electrode of the battery cell 5b and the terminal-connected vertical MOS transistor 2d as the inlet / outlet vertical MOS transistors on one side or the other, the on-resistance (contact resistance, denoted as Rat [Ω]) when It flows is described. Similarly, for the current paths with the vertical MOS transistors connected to the positive electrode of the battery cell 5a and the terminal-connected vertical MOS transistor 2d as the inlet / outlet vertical MOS transistors on one side or the other, the on-resistance (contact resistance, Rat [Ω]) when It flows is described. Since the two current paths with the terminal-connected vertical MOS transistor 2d as the inlet / outlet vertical MOS transistor on one side or the other are equivalent, there is a case where only one on-resistance is described in the product specification to avoid duplication. In addition, for each of the three vertical MOS transistors, the current value for evaluating the on-resistance (contact resistance) is described in the product specification. The current value for evaluating the on-resistance (contact resistance) is the current value of 50% of the maximum rated current specified for each of the three vertical MOS transistors or a current value below the maximum rated current. When evaluating the on-resistance, the current value described in the product specification as the current value flowing in each of the three vertical MOS transistors can be understood as the maximum specification current of each of the three vertical MOS transistors. In addition, the maximum rated current of each of the three vertical MOS transistors described in the product specification can also be understood as the maximum specification current of each of the three vertical MOS transistors.

[0419] The vertical MOS transistors connected to the negative electrode of the battery cell 5b and the vertical MOS transistors connected to the positive electrode of the battery cell 5a that pass large currents respectively have the same area (denoted as Sa). Furthermore, the area of the terminal-connected vertical MOS transistor 2d that does not need to pass large currents (denoted as St) is preferably set to the smallest area among the three vertical MOS transistors (St < Sa). Further, it is preferable that Sa:St = Ia 2 : It 2The relationship is established. Furthermore, regarding the on-resistance Ra (Ra = Raa / 2) of each vertical MOS transistor when the maximum specification current Ia flows through the vertical MOS transistor connected to the negative terminal of battery cell 5b and the vertical MOS transistor connected to the positive terminal of battery cell 5a, and the on-resistance Rt (Rt = Rat × Sa / (Sa + Sn)) of the vertical MOS transistor 2d connected to the terminal when the maximum specification current It flows through it, Ia is preferred. 2 It 2 =1 / Ra:1 / Rt holds true. By establishing this relationship, localized heating can be suppressed in the second semiconductor device 1d.

[0420] [3-3. Specific Examples of Battery Protection Circuits]

[0421] Hereinafter, a specific example of the battery protection circuit 50c will be described using the accompanying drawings, while comparing it with previous examples.

[0422] Figure 30A , Figure 31A , Figure 32A This is a circuit diagram illustrating a specific example of the battery protection circuit of Embodiment 3 using semiconductor device 1.

[0423] Figure 30B , Figure 31B , Figure 32B This is a circuit diagram illustrating a specific example of a conventional battery protection circuit that does not utilize semiconductor device 1, but is composed solely of semiconductor switching device 9.

[0424] Figure 30A This is a circuit diagram of an example of the battery protection circuit of Embodiment 3, namely the first disclosed example, which enables the series charging and parallel discharging of two battery cells 5. Figure 30B This is a circuit diagram of a conventional battery protection circuit that can achieve the same function, namely the first conventional example.

[0425] By Figure 30A and Figure 30B A comparison shows that the first disclosed example can achieve the same function with fewer parts compared to the first prior example.

[0426] Figure 31A This is a circuit diagram of an example of the battery protection circuit of Embodiment 3, namely the second disclosed example, which enables the series charging and parallel discharging of the three battery cells 5. Figure 31B This is a circuit diagram of a conventional battery protection circuit that can achieve the same function, namely the second conventional example.

[0427] By Figure 31A and Figure 31BA comparison shows that the second disclosed example can achieve the same function with fewer parts compared to the second prior example.

[0428] Figure 32A This is a circuit diagram of an example of a battery protection circuit in Embodiment 3, namely the third disclosed embodiment, which enables series charging and parallel discharging of four battery cells 5. Figure 32B This is a circuit diagram of a conventional battery protection circuit that can achieve the same function, namely the third conventional example.

[0429] By Figure 32A and Figure 32B A comparison shows that the third disclosed example can achieve the same function with fewer parts compared to the third prior example.

[0430] Hereinafter, representative actions of the second disclosed example will be described using the accompanying drawings.

[0431] Figure 33A This is a schematic diagram showing the state in which the battery protection circuit 50ca of the second disclosed example charges the three battery cells 5 in series.

[0432] like Figure 33A As shown, the battery protection circuit 50ca can charge battery cells 5cc, 5cb and 5ca in series while supplying the voltage from the positive terminal of battery cell 5ca to the outside from the first terminal 61c by applying 15V to the third terminal 63c and grounding the second terminal 62c.

[0433] Figure 33B This is a schematic diagram showing the state in which the battery protection circuit 50ca stops the series charging of the three battery cells 5 and starts supplying voltage from the positive terminal of the battery cell 5ca to the outside from the first terminal 61c.

[0434] Figure 33C This is a schematic diagram showing the state of the battery protection circuit 50ca charging the battery cell 5ca.

[0435] like Figure 33C As shown, the battery protection circuit 50ca can charge the battery cell 5ca while supplying the voltage from the positive terminal of the battery cell 5ca to the outside from the first terminal 61c by applying 5V to the third terminal 63c and grounding the second terminal 62c.

[0436] Figure 33D This is a schematic diagram showing the situation where the battery protection circuit 50ca discharges the three battery cells 5 in parallel.

[0437] (Implementation Method 4)

[0438] The battery protection system of Embodiment 4 will be described below.

[0439] [4-1. Structure of the Battery Protection System]

[0440] Figure 34 This is a circuit diagram illustrating an example of the structure of the battery protection system 100d according to Embodiment 4.

[0441] like Figure 34 As shown, the battery protection system 100d includes a battery protection circuit 50d and a charge / discharge control IC 60d.

[0442] In addition, the battery protection circuit 50d includes a first semiconductor device 1e, a second semiconductor device 1f, N-1 battery cells 5, 2N-4 semiconductor switching devices 9, a first terminal 61d, a second terminal 62d, and a third terminal 63d.

[0443] The charge / discharge control IC 60d controls the first semiconductor device 1e, the second semiconductor device 1f, and 2N-4 semiconductor switching devices 9 to control the charging and discharging of N-1 battery cells 5.

[0444] The first semiconductor device 1e is the semiconductor device 1 described in detail in Embodiment 1, and includes N vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by the charge / discharge control IC 60d.

[0445] The second semiconductor device 1f is the semiconductor device 1 described in detail in Embodiment 1, and includes three vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by the charge / discharge control IC 60d.

[0446] The 2N-4 semiconductor switching devices 9 are controlled by the charge / discharge control IC 60d.

[0447] N-1 battery cells are connected in series. In embodiment 4, N-2 battery cells 5, excluding battery cell 5d located at the negative electrode end, are connected in series via semiconductor switch device 9. Battery cell 5d and battery cell 5e located next to battery cell 5d in the series connection are connected in series via a second semiconductor device 1f.

[0448] The first terminal 61d is connected to one of the N vertical MOS transistors of the first semiconductor device 1e and to one or more source pads of the vertical MOS transistor 2e, and the second semiconductor device 1f is connected to one of the three vertical MOS transistors of the second semiconductor device 1f and to one or more source pads of the vertical MOS transistor 2f.

[0449] The second terminal 62d is connected to the negative terminal of N-1 battery cells 5. In embodiment 4, the negative terminal of each battery cell 5 is connected to the second terminal 62d via a semiconductor switching device 9.

[0450] The third terminal 63d is connected to the battery cell 5f located at the positive electrode end of the N-1 battery cells 5 that are connected in series.

[0451] The positive terminal of each of the N-1 battery cells 5 is connected to one or more source pads of the N-1 vertical MOS transistors (excluding the terminal-connected vertical MOS transistor 2e) in the first semiconductor device 1e.

[0452] The positive electrode of battery cell 5d and the negative electrode of battery cell 5e are respectively connected to one or more source pads of two of the three vertical MOS transistors in the second semiconductor device 1f, excluding the vertical MOS transistor 2f which is connected to the terminal.

[0453] [4-2. Operation of the Battery Protection System]

[0454] The operation of the battery protection system 100d with the above structure will be explained below.

[0455] Figure 35A This is a schematic diagram showing the state in which the battery protection system 100d charges N-1 battery cells 5 in series. Figure 35A In the diagram, the dashed arrows represent the charging paths of N-1 battery cells 5.

[0456] During series charging, the charge / discharge control IC 60d sets the vertical MOS transistors on the side of the N-3 semiconductor switching devices 9 connected to the positive terminal of the battery cell 5 between the N-2 battery cells 5 (excluding battery cell 5d) sandwiched in the N-1 battery cells 5 to the on state, sets the vertical MOS transistors on the side of the second semiconductor device 1f connected to the positive terminal of the battery cell 5d to the on state, and sets the vertical MOS transistors on the side of the semiconductor switching device 9 connected to the side of the second terminal 62d sandwiched between the battery cell 5d and the second terminal 62d to the on state, thereby charging the N-1 battery cells 5 in series simultaneously.

[0457] When the charge / discharge control IC 60d detects an abnormality related to charging during series charging, it changes the vertical MOS transistor on the side of the second semiconductor device 1f connected to the positive terminal of the battery cell 5d from the on state to the off state, thereby stopping the charging of N-1 battery cells.

[0458] This protects N-1 battery cells 5 from adverse effects caused by charging-related anomalies.

[0459] Figure 35B This is a schematic diagram showing the state of the battery protection system 100d discharging N-1 battery cells 5. Figure 35B In the diagram, the dashed arrows represent the discharge paths of each of the N-1 battery cells 5.

[0460] During discharge, the charge / discharge control IC 60d sets the vertical MOS transistor on the side of the N-1 semiconductor switching devices 9 connected to the negative terminal of the battery cell 5, which is sandwiched between the negative terminal of each of the N-1 battery cells 5 and the second terminal 62d, to the on state, and sets the terminal of the first semiconductor device 1e connected to the vertical MOS transistor 2e to the on state, thereby discharging the N-1 battery cells 5 in parallel at the same time.

[0461] In addition, although Figure 35B Although not illustrated, the charge / discharge control IC 60d can also selectively discharge only one or not all of the N-1 battery cells 5 simultaneously in parallel.

[0462] When the charge / discharge control IC 60d detects an abnormality related to the discharge during discharge, it changes the vertical MOS transistor on the side of the semiconductor switch 9 connected to the negative terminal of the battery cell 5 associated with the detected abnormality from the on state to the off state in the N-1 semiconductor switch devices 9 sandwiched between the negative terminal of each of the N-1 battery cells 5 and the second terminal 62d, thereby stopping the discharge of the corresponding battery cell 5.

[0463] This protects the corresponding battery cell 5 from adverse effects caused by discharge-related anomalies.

[0464] Figure 35C This is a schematic diagram illustrating the parallel charging of N-1 battery cells 5 by the battery protection system 100d. Figure 35C In the diagram, the dashed arrows represent the charging paths of each of the N-1 battery cells 5.

[0465] When charging in parallel, the charge / discharge control IC 60d sets the vertical MOS transistors on the side connected to the second terminal 62d of the N-1 semiconductor switching devices 9, which are sandwiched between the negative terminals of the N-1 battery cells 5 and the second terminal 62d, to the on state, and sets the N-1 vertical MOS transistors of the first semiconductor device 1e, except for the vertical MOS transistor 2e connected to the terminal, to the on state, thereby charging the N-1 battery cells 5 in parallel at the same time.

[0466] In addition, although Figure 35CAlthough not illustrated, the charge / discharge IC60d can also selectively charge only one or not all of the N-1 battery cells 5 simultaneously in parallel.

[0467] When the charge / discharge control IC 60d detects an abnormality related to charging during parallel charging, it changes the vertical MOS transistor on the side of the semiconductor switch device 9 connected to the second terminal 62d in the N-1 semiconductor switch devices 9 sandwiched between the negative terminals of the N-1 battery cells 5 and the second terminal 62d from the on state to the off state, thereby stopping the charging of the corresponding battery cell 5.

[0468] This protects the corresponding battery cell 5 from adverse effects caused by charging-related anomalies.

[0469] [4-3. Specific Examples of Battery Protection Circuits]

[0470] The following is a detailed explanation of a specific example of the battery protection circuit 50d, using accompanying drawings, while comparing it with previous examples.

[0471] Figure 36 , Figure 39 , Figure 40 This is a circuit diagram illustrating a specific example of the battery protection circuit of embodiment 4 using semiconductor device 1.

[0472] Figure 36 This is a circuit diagram of an example of the battery protection circuit of Embodiment 4, namely the fourth disclosed example, which enables the series charging and parallel discharging of two battery cells 5. Figure 30B The first conventional example shown is an example of a battery protection circuit that does not utilize a semiconductor device 1 and has the same function.

[0473] By Figure 36 and Figure 30B As can be seen from the comparison, the fourth disclosed example can achieve the same function with fewer parts compared to the first prior example.

[0474] Figure 37A and Figure 37B This is an example of a plan view of the first semiconductor device 1 in the fourth disclosure example.

[0475] like Figure 37A and Figure 37B As shown, the preferred relationship between the area S1 of the terminal connection of the first semiconductor device 1 and the areas S2 and S3 of the other two vertical MOS transistors is S1:S2:S3 = 4:1:1.

[0476] Figure 38A and Figure 38BThis is an example of a plan view of the second semiconductor device 1 in the fourth disclosure example.

[0477] like Figure 38A and Figure 38B As shown, the area S1 of the terminal connection of the second semiconductor device 1 to the vertical MOS transistor is preferably smaller than the areas S2 and S3 of the other two vertical MOS transistors, and equal to the areas S2 and S3 of the other two vertical MOS transistors.

[0478] Figure 39 This is a circuit diagram of an example of the battery protection circuit of Embodiment 4, namely the fifth disclosed example, which enables the series charging and parallel discharging of the three battery cells 5. Figure 31B The second conventional example shown is an example of a battery protection circuit that does not utilize semiconductor device 1 and has the same function.

[0479] By Figure 39 and Figure 31B A comparison shows that the fifth disclosed example can achieve the same function with fewer parts compared to the second prior example.

[0480] Figure 40 This is a circuit diagram of an example of the battery protection circuit of Embodiment 4, namely the sixth disclosed example, which enables the series charging and parallel discharging of four battery cells 5. Figure 32B The third prior example shown is an example of a battery protection circuit that does not utilize semiconductor device 1 and has the same function.

[0481] By Figure 40 and Figure 32B A comparison shows that, compared with the third prior example, the sixth disclosed example can achieve the same function with fewer parts.

[0482] Hereinafter, with the aid of accompanying drawings, the representative actions of the fifth disclosed example will be described.

[0483] Figure 41A This is a schematic diagram showing the state in which the battery protection circuit 50da of the fifth disclosed example charges three battery cells 5 in series.

[0484] like Figure 41A As shown, the battery protection circuit 50da can charge battery cells 5dc, 5db, and 5da in series while simultaneously supplying the voltage from the positive terminal of battery cell 5da to the outside from the first terminal 61d by applying 15V to the third terminal 63d and grounding the second terminal 62d.

[0485] Figure 41BThis is a schematic diagram showing the state in which the battery protection circuit 50da stops the series charging of the three battery cells 5 and starts supplying voltage from the positive terminal of the battery cell 5da to the outside from the first terminal 61d.

[0486] Figure 41C This is a schematic diagram showing the state of the battery protection circuit 50da charging the battery cell 5da.

[0487] like Figure 41C As shown, the battery protection circuit 50da can charge the battery cell 5da while supplying the voltage from the positive terminal of the battery cell 5da to the outside from the first terminal 61d by applying 5V to the third terminal 63d and grounding the second terminal 62d.

[0488] Figure 41D This is a schematic diagram showing the state of the battery protection circuit 50da discharging three battery cells 5 in parallel.

[0489] (Implementation Method 5)

[0490] The battery protection system of Embodiment 5 will be described below.

[0491] Figure 42 This is a circuit diagram illustrating an example of the structure of the battery protection system 100e in Embodiment 5.

[0492] like Figure 42 As shown, the battery protection system 100e includes a battery protection circuit 50e, a battery cell 5, and a power management circuit 80. The power management circuit 80 includes an IC that supplies power to functional circuitry of a main device (not shown) further connected thereto. The functional circuitry of the main device may include, for example, Bluetooth (trademarked) circuitry, Wi-Fi (trademarked) circuitry, LiDAR circuitry, etc.

[0493] In addition, the battery protection circuit 50e includes a first semiconductor device 1ea, a second semiconductor device 1eb, a protection IC 70ea, a protection IC 70eb, a first terminal 71, a second terminal 72, a third terminal 73, a fourth terminal 74, a fifth terminal 75, and a sixth terminal 76.

[0494] The protection IC70ea controls the first semiconductor device 1ea based on the voltage of the battery cell 5, thereby controlling the charging and discharging of the battery cell 5.

[0495] The protection IC70eb controls the second semiconductor device 1eb based on the voltage of the battery cell 5, thereby controlling the charging and discharging of the battery cell 5.

[0496] The first semiconductor device 1ea is a second specific semiconductor device 1 having a specific vertical MOS transistor type in the semiconductor device 1 described in detail in Embodiment 1. The first semiconductor device 1ea has three vertical MOS transistors, one of which is a specific vertical MOS transistor. The on-state and off-state of each vertical MOS transistor are controlled by a protection IC 70ea. Alternatively, the on-state and off-state of only the specific vertical MOS transistor may be controlled by an IC in a power management circuit 80 that receives the output voltage of the specific vertical MOS transistor.

[0497] The second semiconductor device 1eb is a second specific semiconductor device 1 having a specific vertical MOS transistor type in the semiconductor device 1 described in detail in Embodiment 1. The first semiconductor device 1eb has three vertical MOS transistors, one of which is a specific vertical MOS transistor. The on / off state of each vertical MOS transistor is controlled by the protection IC 70eb. Alternatively, the on / off state of only the specific vertical MOS transistor may be controlled by an IC in the power management circuit 80 that receives the output voltage of the specific vertical MOS transistor.

[0498] The first terminal 71 is connected to the source pad of a specific vertical MOS transistor in the first semiconductor device 1ea. Alternatively, a current-limiting resistor may be provided between the source pad of the specific vertical MOS transistor in the first semiconductor device 1ea and the first terminal 71.

[0499] The second terminal 72 is connected to one or more source pads of one of the two vertical MOS transistors (excluding the specific vertical MOS transistor) among the three vertical MOS transistors included in the first semiconductor device 1ea. Alternatively, a current-limiting resistor may be provided between the source pad of the specific vertical MOS transistor in the first semiconductor device 1ea and the second terminal 72.

[0500] The third terminal 73 is connected to one or more source pads of the other vertical MOS transistor among the three vertical MOS transistors of the first semiconductor device 1ea, excluding the specific vertical MOS transistor.

[0501] Terminal 4 74 is connected to the source pad of a specific vertical MOS transistor in the second semiconductor device 1eb.

[0502] Terminal 75 is connected to one or more source pads of one of the two vertical MOS transistors (excluding the specific vertical MOS transistor) among the three vertical MOS transistors of the second semiconductor device 1eb.

[0503] The sixth terminal 76 is connected to one or more source pads of the other vertical MOS transistor among the three vertical MOS transistors of the second semiconductor device 1eb, excluding the specific vertical MOS transistor.

[0504] The positive terminal of battery cell 5 is connected to terminal 3 73, and the negative terminal is connected to terminal 6 76.

[0505] The power management circuit 80 is connected to terminal 1 71, terminal 2 72, terminal 4 74, and terminal 5 75. Through terminal 2 72 and terminal 5 75, and via battery protection circuit 50e, it directs charging current to battery cell 5 during charging and receives discharging current from battery cell 5 during discharging. Furthermore, the power management circuit 80 receives current through terminal 1 71 and terminal 4 74 that allows it to monitor the voltage level of battery cell 5.

[0506] Furthermore, in Embodiment 5, it is assumed that the battery protection circuit 50e of the battery protection system 100e has protection IC 70ea and protection IC 70eb, but the battery protection system 100e is not necessarily limited to the structure in which the battery protection circuit 50e has protection IC 70ea and protection IC 70eb.

[0507] The battery protection system 100e can also have a structure with protection IC 70ea and protection IC 70eb outside the battery protection circuit 50e.

[0508] (Implementation Method 6)

[0509] The battery protection system of Embodiment 6 will be described below.

[0510] Figure 43 This is a circuit diagram illustrating an example of the structure of the battery protection system 100f according to Embodiment 6.

[0511] like Figure 43 As shown, the battery protection system 100f includes a battery protection circuit 50f, a battery cell 5, and a power management circuit 80f. The power management circuit 80f includes an IC that has the function of supplying power to functional circuitry of a main device (not shown) further connected thereto.

[0512] In addition, the main device's functional circuits include Bluetooth (registered trademark) circuits, Wi-Fi (registered trademark) circuits, LiDAR circuits, and other functional circuits.

[0513] In addition, the battery protection circuit 50f includes a first semiconductor device 1fa, a semiconductor switch device 9, a protection IC 70fa, a protection IC 70fb, a first terminal 71f, a second terminal 72f, a third terminal 73f, and a fourth terminal 74f.

[0514] The protection IC70fa controls the first semiconductor device 1fa based on the voltage of the battery cell 5, thereby controlling the charging and discharging of the battery cell 5.

[0515] The protection IC70fb controls the semiconductor switching device 9 based on the voltage of the battery cell 5, thereby controlling the charging and discharging of the battery cell 5.

[0516] The first semiconductor device 1fa is a second specific semiconductor device 1 having a specific vertical MOS transistor, as detailed in Embodiment 1. The first semiconductor device 1fa has three vertical MOS transistors, one of which is a specific vertical MOS transistor. The on / off state of each vertical MOS transistor is controlled by a protection IC 70fa. A current path via the specific vertical MOS transistor is used when charging the battery cell 5 with a current smaller than the normal charging current. Similarly, a current path via the specific vertical MOS transistor is used when discharging the battery cell 5 with a current smaller than the normal discharging current. This "small current" can be a current adjusted by the on-resistance of the specific vertical MOS transistor, a resistor provided on the source pad side of the specific vertical MOS transistor, or a current adjusted by pulsedly controlling the voltage applied to the gate pad of the specific vertical MOS transistor.

[0517] The conduction and non-conducting states of each vertical MOS transistor in the semiconductor switching device 9 are controlled by the protection IC 70fb.

[0518] The first terminal 71f is connected to one or more source pads of one of the two vertical MOS transistors (excluding the specific vertical MOS transistor) among the three vertical MOS transistors provided in the first semiconductor device 1fa. Additionally, a sensing resistor and other battery protection circuitry may be provided between the first terminal 71f and the first semiconductor device 1fa.

[0519] The second terminal 72f is connected to one or more source pads of the other vertical MOS transistor among the three vertical MOS transistors of the first semiconductor device 1fa, excluding the specific vertical MOS transistor.

[0520] The third terminal 73f is connected to one or more source pads of one of the two vertical MOS transistors of the semiconductor switching device 9.

[0521] Terminal 4 74f is connected to one or more source pads of the other of the two vertical MOS transistors in the semiconductor switching device 9.

[0522] The positive terminal of battery cell 5 is connected to terminal 1 71f, and the negative terminal is connected to terminal 3 73f.

[0523] The power management circuit 80f is connected to the second terminal 72f and the fourth terminal 74f. Through the second terminal 72f and the fourth terminal 74f, and through the battery protection circuit 50f, the charging current flows to the battery cell 5 during charging, and the discharging current is received from the battery cell 5 during discharging.

[0524] Furthermore, in Embodiment 6, it is assumed that the battery protection circuit 50f of the battery protection system 100f includes protection IC 70fa and protection IC 70fb, but the battery protection system 100f is not necessarily limited to the structure in which the battery protection circuit 50f includes protection IC 70fa and protection IC 70fb.

[0525] The battery protection system 100f can also be structured with protection IC 70fa and protection IC 70fb external to the battery protection circuit 50f.

[0526] (Implementation Method 7)

[0527] The battery protection system of Embodiment 7 will be described below.

[0528] Figure 44 This is a circuit diagram illustrating an example of the structure of the battery protection system 100g according to Embodiment 7.

[0529] like Figure 44 As shown, the battery protection system 100g includes a battery protection circuit 50g, X (X is an integer of 1 or more) battery cells 5, and Y (Y is an integer of 2 or more) power management circuits 80g. The power management circuit 80g includes an IC that has the function of supplying power to functional circuitry of a main device (not shown) further connected thereto.

[0530] In addition, the main device's functional circuits include Bluetooth (registered trademark) circuits, Wi-Fi (registered trademark) circuits, LiDAR circuits, and other functional circuits.

[0531] In addition, the battery protection circuit 50g includes a first semiconductor device 1ga, a second semiconductor device 1gb, a protection IC 70ga, a protection IC 70gb, X first terminals 71g, Y second terminals 72g, a third terminal 73g, and Y fourth terminals 74g.

[0532] The protection IC70ga controls the first semiconductor device 1ga based on the voltage of each of the X battery cells 5, thereby controlling the charging and discharging of the X battery cells 5.

[0533] The protection IC 70GB controls the second semiconductor device 1GB based on the voltage of each of the X battery cells 5, and controls the charging and discharging of the X battery cells 5.

[0534] The first semiconductor device 1ga is the semiconductor device 1 whose details were described in Embodiment 1, and it includes X+Y vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by a protection IC 70ga.

[0535] The second semiconductor device 1gb is the semiconductor device 1 described in detail in Embodiment 1, and includes 1+Y vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by the protection IC 70gb.

[0536] X first terminals 71g are respectively connected to one or more source pads of X vertical MOS transistors among the X+Y vertical MOS transistors of the first semiconductor device 1ga.

[0537] The Y second terminals 72g are respectively connected to one or more source pads of the Y vertical MOS transistors (excluding the aforementioned X vertical MOS transistors) among the X+Y vertical MOS transistors provided in the first semiconductor device 1ga.

[0538] The third terminal 73g is connected to one or more source pads of one of the 1+Y vertical MOS transistors in the second semiconductor device 1gb.

[0539] Y fourth terminals 74g are respectively connected to one or more source pads of Y vertical MOS transistors (excluding the aforementioned 1 vertical MOS transistor) among the 1+Y vertical MOS transistors provided in the second semiconductor device 1gb.

[0540] Each of the X battery cells 5 has its positive terminal connected to one of the X first terminals 71g, and its negative terminal connected to the third terminal 73g.

[0541] Y power management circuits 80g are respectively connected to each of the Y second terminals 72g and the Y fourth terminals 74g. Through one of the Y second terminals 72g and one of the Y fourth terminals 74g, and through the battery protection circuit 50g, the charging current flows to at least one of the X battery cells 5 during charging, and receives the discharge current from at least one of the X battery cells 5 during discharging.

[0542] The battery protection system 100g with the above structure can realize the charging and discharging of X battery cells 5 using Y power management circuits 80g.

[0543] For example, when the charging current supplied by one power management circuit 80g is 6A, the vertical MOS transistor connected to the third terminal 73g in the 1+Y vertical MOS transistors of the semiconductor device 1gb has a current of (6A×Y)A. Therefore, in the 1+Y vertical MOS transistors of the semiconductor device 1gb, the vertical MOS transistor connected to the third terminal 73g has an area that is (6A×Y) times the square of the vertical MOS transistor connected to the fourth terminal 74g in the plan view of the semiconductor device, which can avoid local heat generation and realize the semiconductor device 1gb in an optimal size.

[0544] Furthermore, the battery protection system 100g with the above structure, when the protection IC 70ga or the protection IC 70gb detects an abnormality related to charging or discharging of one of the X battery cells 5, stops the charging or discharging of the corresponding battery cell 5 by controlling the first semiconductor device 1ga or the second semiconductor device 1gb.

[0545] This protects the corresponding battery cell 5 from adverse effects caused by abnormalities related to charging or discharging.

[0546] Furthermore, in Embodiment 7, it is assumed that the battery protection circuit 50g of the battery protection system 100g is equipped with protection IC 70ga and protection IC 70gb. However, the battery protection system 100g is not necessarily limited to the structure in which the battery protection circuit 50g is equipped with protection IC 70ga and protection IC 70gb.

[0547] The battery protection system 100g can also be structured with protection IC 70ga and protection IC 70gb external to the battery protection circuit 50g.

[0548] (Implementation Method 8)

[0549] The power management system of Embodiment 8 will be described below.

[0550] Figure 45 This is a circuit diagram illustrating an example of the structure of the power management system 200 in Embodiment 8.

[0551] like Figure 45 As shown, the power management system 200 includes a power management circuit 51 and X (where X is an integer greater than or equal to 1) external circuits 8 (corresponding to...). Figure 45 External circuits 8a to 8d (in the circuit).

[0552] Furthermore, the power management circuit 51 includes a first semiconductor device 1h and Y (where Y is an integer of 2 or more) circuits 6 (corresponding to...). Figure 45The circuits 6a to 6d, control unit 7, and X terminals 71h are included.

[0553] The control unit 7 controls the first semiconductor device 1h and controls the connection status of X external circuits 8 and Y circuits 6.

[0554] The first semiconductor device 1h is the semiconductor device 1 described in detail in Embodiment 1, and includes X+Y vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by the control unit 7.

[0555] Each of the X terminals 71h is connected to one or more source pads of the X+Y vertical MOS transistors in the first semiconductor device 1h.

[0556] The Y circuits 6 are each connected to one or more source pads of the Y vertical MOS transistors (excluding the aforementioned X vertical MOS transistors) among the X+Y vertical MOS transistors included in the first semiconductor device 1h. In embodiment 8, one or more source pads of the aforementioned Y vertical MOS transistors among the X+Y vertical MOS transistors included in the first semiconductor device 1h are each connected to the power supply terminal of each of the Y circuits 6.

[0557] The Y circuits 6 are, for example, functional circuits of the main device such as Bluetooth circuits, Wi-Fi circuits, and LiDAR circuits, and battery cells that can change the voltage supplied with power to charge the battery cells or have protection function circuits attached to the main device. Each circuit 6 is power-separated and interconnected via a semiconductor device 1.

[0558] X external circuits 8 are respectively connected to X terminals 71h. In embodiment 8, the X external circuits 8 are power supply source circuits or power receiving target circuits, and the X terminals 71h are respectively connected to the power terminals of the X external circuits 8 that serve as power supply source circuits or power receiving target circuits.

[0559] X external circuits 8, serving as power supply source circuits, such as AC adapters, USB 5V circuits, wireless chargers, etc., and as power receiving target circuits, such as external devices, etc.

[0560] The power management system 200 with the above-described structure can supply power from power supply source circuits in X external circuits 8 to one of Y circuits 6, and from one of Y circuits 6 to power receiving target circuits in X external circuits 8. When a charging current is supplied from an external circuit 8 at a voltage capable of charging a battery cell, high-efficiency charging can be achieved by directly supplying the charging current to the circuit 6 of the battery cell with battery protection via the semiconductor device 1h, avoiding power loss that occurs during voltage conversion circuitry. When a charging current is to be supplied from an external circuit 8 at a voltage that cannot charge a battery cell, the circuit 6 of the battery cell with battery protection is not directly charged; instead, the voltage is supplied to the circuit 6 with voltage conversion function via the semiconductor device 1h, converting it to a voltage capable of supplying power to the battery cell. Then, a charging current is supplied to the circuit 6 of the battery cell with battery protection at a voltage capable of supplying power to the battery cell.

[0561] Furthermore, in Embodiment 8, it is assumed that the power management circuit 51 of the power management system 200 has a control unit 7, but the power management system 200 is not necessarily limited to the structure in which the power management circuit 51 has a control unit 7.

[0562] The power management system 200 may, for example, have a control unit 7 external to the power management circuit 51.

[0563] (Implementation Method 9)

[0564] The power management system of Embodiment 9 will be described below.

[0565] Figure 46 This is a circuit diagram illustrating an example of the structure of the power management system 200a according to Embodiment 9.

[0566] like Figure 46 As shown, the power management system 200a includes a power management circuit 51a and a power circuit 8e.

[0567] Furthermore, the power management circuit 51a includes a first semiconductor device 1i and Y (where Y is an integer of 2 or more) circuits 6a (corresponding to...). Figure 46 The circuits 6aa to 6ad) are included, as are the control unit 7a, the DC / DC circuit 90, and the terminal 71i.

[0568] DC / DC circuit 90 converts the output voltage of power supply circuit 8e into the voltage used by Y circuits 6a.

[0569] The control unit 7a controls the first semiconductor device 1i and controls the connection status between the DC / DC circuit 90 and the Y circuits 6.

[0570] The first semiconductor device 1i is the semiconductor device 1 whose details were described in Embodiment 1, and it includes 1+Y vertical MOS transistors. The on-state and off-state of each vertical MOS transistor are controlled by the control unit 7a.

[0571] Terminal 71i is connected to one of the terminals (voltage input terminals) of the DC / DC circuit 90.

[0572] The other terminal (voltage output terminal) of the DC / DC circuit 90 is connected to one or more source pads of one of the 1+Y vertical MOS transistors of the first semiconductor device 1i.

[0573] Each of the Y circuits 6a is connected to one or more source pads of each of the Y vertical MOS transistors (excluding the aforementioned one) among the 1+Y vertical MOS transistors included in the first semiconductor device 1i. In Embodiment 9, it is assumed that one or more source pads of the aforementioned Y vertical MOS transistors among the 1+Y vertical MOS transistors included in the first semiconductor device 1i are connected to the power supply terminals of each of the Y circuits 6a.

[0574] Y circuits 6a are, for example, Bluetooth (registered trademark) circuits, Wi-Fi (registered trademark) circuits, LiDAR circuits, and other circuits whose power supplies are separated from other circuits.

[0575] The power supply circuit 8e is connected to terminal 71i and outputs voltage to terminal 71i.

[0576] The power management system 200a with the above structure can supply the voltage converted by the DC / DC circuit 90 to the circuit 6a that needs to supply voltage among the Y circuits 6a.

[0577] Therefore, the power consumption caused by the Y circuits 6a can be suppressed.

[0578] (Replenish)

[0579] The semiconductor device, battery protection circuit, and power management circuit of the present disclosure have been described above based on embodiments 1 to 9, but the present disclosure is not limited to these embodiments. Various modifications conceived by those skilled in the art, or forms constructed by combining the constituent elements of different embodiments, are also included within the scope of one or more technical solutions of the present disclosure, as long as they do not depart from the spirit of the present disclosure.

[0580] Industrial applicability

[0581] This disclosure can be widely applied to semiconductor devices, battery protection circuits, and power management circuits.

[0582] Label Explanation

[0583] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1ea, 1eb, 1fa, 1ga, 1gb, 1h, 1i Semiconductor devices

[0584] Terminals 2a, 2b, 2c, 2d, 2e, and 2f are connected to a vertical MOS transistor.

[0585] 5, 5a, 5b, 5c, 5d, 5e, 5f, 5ca, 5cb, 5cc, 5da, 5db, 5dc battery cells

[0586] Circuits 6, 6a, 6b, 6c, 6d, 6aa, 6ab, 6ac, 6ad

[0587] 7.7a Control Section

[0588] External circuits for 8, 8a, 8b, 8c, and 8d

[0589] 8e power supply circuit

[0590] 9 Semiconductor switching devices

[0591] 10 Transistors (First Vertical Type MOS Transistor)

[0592] 11 First source electrode

[0593] Parts 12, 13, 22, 23, 82, and 83

[0594] 14 First source region

[0595] 15 First gate conductor

[0596] 16 First gate insulating film

[0597] 18 First Body Region

[0598] 19 Gate electrode 1

[0599] 20 Transistors (Second Vertical Type MOS Transistor)

[0600] 21 Second source electrode

[0601] 24 Second source region

[0602] 25 Second gate conductor

[0603] 26 Second gate insulating film

[0604] 28. Second body region

[0605] 29 Second gate electrode

[0606] 30 metal layers

[0607] 31 Third source electrode

[0608] 32 Semiconductor substrate

[0609] 33 Low-concentration impurity layer

[0610] 34 Oxide film

[0611] 35 Protective Layer

[0612] 37 Transistor (3rd Vertical Type MOS Transistor)

[0613] 38 High-concentration impurity layer

[0614] 39 Third gate electrode

[0615] 40 Semiconductor layer

[0616] Battery protection circuits for models 50, 50a, 50b, 50c, 50d, 50e, 50f, 50g, 50ca, and 50da.

[0617] 51, 51a Power Management Circuit

[0618] 60, 60c, 60d charge / discharge control ICs

[0619] 60A Charging Control IC

[0620] 60b Discharge Control IC

[0621] 61, 61c, 61d, 71, 71f, 71g Terminal 1

[0622] 62, 62c, 62d, 72, 72f, 72g 2nd terminal

[0623] Terminal 3 of 63c, 63d, 73, 73f, 73g

[0624] 70ea, 70eb, 70fa, 70fb, 70ga, 70gb protection ICs

[0625] 71h, 71i terminals

[0626] 74, 74f, 74g Terminal 4

[0627] 75 Terminal 5

[0628] 76 Terminal 6

[0629] 80, 80F, 80G power management circuits

[0630] 81 Drain electrode

[0631] 90 DC / DC circuit

[0632] Battery protection systems for models 100, 100a, 100b, 100c, 100d, 100e, 100f, and 100g.

[0633] 111, 111a, 111b, 111c, 111d, 111e Source pad #1

[0634] 119 Gate Pad 1 (Gate Pad)

[0635] 121, 121a, 121b, 121c, 121d, 121e Second source pad

[0636] 129 Second gate pad (gate pad)

[0637] 131, 131a, 131b 3rd source pad

[0638] 139 Third gate pad (gate pad)

[0639] 141 Drain pad

[0640] 200, 200a Power Management System

[0641] 300 common terminal

[0642] Areas A1, A2, A3, B1, B2, B3, B4, B5

Claims

1. A semiconductor device, a chip-scale packaged semiconductor device capable of being mounted face-down, characterized in that, have: Semiconductor layer; and N vertical MOS transistors are formed in the above semiconductor layer, where N is an integer greater than or equal to 3; The aforementioned N vertical MOS transistors each have a gate pad electrically connected to the gate electrode of the vertical MOS transistor and one or more source pads electrically connected to the source electrode of the vertical MOS transistor on the upper surface of the aforementioned semiconductor layer. The aforementioned semiconductor layer has a semiconductor substrate; The aforementioned semiconductor substrate functions as the common drain region for the aforementioned N vertical MOS transistors; Corresponding to the maximum specification current of each of the above N vertical MOS transistors, the larger the maximum specification current, the larger the area of ​​each of the above N vertical MOS transistors in the planar diagram of the above semiconductor layer; The area of ​​each of the N vertical MOS transistors in the planar diagram of the aforementioned semiconductor layer is proportional to the square of the maximum specification current of each of the N vertical MOS transistors. One of the aforementioned N vertical MOS transistors is a specific vertical MOS transistor whose maximum rated current is equal to the sum of the maximum rated currents of K vertical MOS transistors among the aforementioned N vertical MOS transistors, where K is an integer greater than 2 and less than N-1.

2. The semiconductor device as claimed in claim 1, characterized in that, The on-resistance of each of the above N vertical MOS transistors when the maximum rated current flows through it is inversely proportional to the square of the maximum rated current of each of the above N vertical MOS transistors.

3. A semiconductor device, a chip-scale packaged semiconductor device capable of being mounted face-down, characterized in that, have: Semiconductor layer; as well as N vertical MOS transistors are formed in the above semiconductor layer, where N is an integer greater than or equal to 3; The aforementioned N vertical MOS transistors each have a gate pad electrically connected to the gate electrode of the vertical MOS transistor and one or more source pads electrically connected to the source electrode of the vertical MOS transistor on the upper surface of the aforementioned semiconductor layer. The aforementioned semiconductor layer has a semiconductor substrate; The aforementioned semiconductor substrate functions as the common drain region for the aforementioned N vertical MOS transistors; Corresponding to the maximum specification current of each of the above N vertical MOS transistors, the larger the maximum specification current, the larger the area of ​​each of the above N vertical MOS transistors in the planar diagram of the above semiconductor layer; The area of ​​each of the N vertical MOS transistors in the planar diagram of the aforementioned semiconductor layer is proportional to the square of the maximum specification current of each of the N vertical MOS transistors. At least one of the above N vertical MOS transistors is a specific vertical MOS transistor having one or more source pads as a single source pad; In the planar view of the semiconductor layer, at least one of the aforementioned specific vertical MOS transistors has a gate pad and a source pad that are perfectly circular. Among the gate pads and more than one source pad of the aforementioned N vertical MOS transistors, there are no gate pads and source pads whose area is intentionally reduced compared to the gate pads and source pads of the aforementioned specific vertical MOS transistors.

4. A semiconductor device, a chip-scale packaged semiconductor device capable of being mounted face-down, characterized in that, have: Semiconductor layer; as well as N vertical MOS transistors are formed in the above semiconductor layer, where N is an integer greater than or equal to 3; The aforementioned N vertical MOS transistors each have a gate pad electrically connected to the gate electrode of the vertical MOS transistor and one or more source pads electrically connected to the source electrode of the vertical MOS transistor on the upper surface of the aforementioned semiconductor layer. The aforementioned semiconductor layer has a semiconductor substrate; The aforementioned semiconductor substrate functions as the common drain region for the aforementioned N vertical MOS transistors; Corresponding to the maximum specification current of each of the above N vertical MOS transistors, the larger the maximum specification current, the larger the area of ​​each of the above N vertical MOS transistors in the planar diagram of the above semiconductor layer; The area of ​​each of the N vertical MOS transistors in the planar diagram of the aforementioned semiconductor layer is proportional to the square of the maximum specification current of each of the N vertical MOS transistors. The aforementioned semiconductor device is rectangular in the plan view of the aforementioned semiconductor layer; In the above N vertical MOS transistors, the first inlet / outlet vertical MOS transistor located at the inlet or outlet of each of the more than one current paths determined by the specifications, and the second inlet / outlet vertical MOS transistor located at the outlet or inlet, are adjacent to each other in the plan view of the above semiconductor layer.

5. The semiconductor device as claimed in claim 4, characterized in that, The aforementioned semiconductor device is rectangular in the plan view of the aforementioned semiconductor layer; In the plan view of the semiconductor layer, the boundary lines of the first inlet / outlet vertical MOS transistor and the second inlet / outlet vertical MOS transistor in each of the above-mentioned one or more current paths are parallel to the long side of the semiconductor device.

6. The semiconductor device as claimed in claim 4, characterized in that, In the plan view of the semiconductor layer, the boundary lines of the first inlet / outlet vertical MOS transistor and the second inlet / outlet vertical MOS transistor in each of the above-mentioned one or more current paths are not parallel to any of the four sides of the semiconductor device.

7. The semiconductor device as claimed in claim 4, characterized in that, In the plan view of the semiconductor layer, the boundary lines of the first inlet / outlet vertical MOS transistor and the second inlet / outlet vertical MOS transistor in each of the above-mentioned one or more current paths are formed by alternately connecting line segments parallel to the first side of the four sides of the semiconductor device and line segments parallel to the second side orthogonal to the first side.

8. A semiconductor device, a chip-scale packaged semiconductor device capable of being mounted face-down, characterized in that, have: Semiconductor layer; and N vertical MOS transistors are formed in the above semiconductor layer, where N is an integer greater than or equal to 3; The aforementioned N vertical MOS transistors each have a gate pad electrically connected to the gate electrode of the vertical MOS transistor and one or more source pads electrically connected to the source electrode of the vertical MOS transistor on the upper surface of the aforementioned semiconductor layer. The aforementioned semiconductor layer has a semiconductor substrate; The aforementioned semiconductor substrate functions as the common drain region for the aforementioned N vertical MOS transistors; Corresponding to the maximum specification current of each of the above N vertical MOS transistors, the larger the maximum specification current, the larger the area of ​​each of the above N vertical MOS transistors in the planar diagram of the above semiconductor layer; The area of ​​each of the N vertical MOS transistors in the planar diagram of the aforementioned semiconductor layer is proportional to the square of the maximum specification current of each of the N vertical MOS transistors. In the above N vertical MOS transistors, the first inlet / outlet vertical MOS transistor located at the inlet or outlet of the first current path and the second inlet / outlet vertical MOS transistor located at the outlet or inlet are adjacent to each other in the plan view of the above semiconductor layer, as determined by the specifications. In the above N vertical MOS transistors, the first inlet / outlet vertical MOS transistor located at the entrance or exit of the second current path and the third inlet / outlet vertical MOS transistor located at the exit or entrance are adjacent to each other in the plan view of the above semiconductor layer, as determined by the above specifications. In the above N vertical MOS transistors, the second inlet / outlet vertical MOS transistor located at the entrance or exit of the third current path and the third inlet / outlet vertical MOS transistor located at the exit or entrance are adjacent to each other in the plan view of the above semiconductor layer, as determined by the above specifications. The gate pad of the third inlet / outlet vertical MOS transistor is located on the extension line of the boundary line between the first inlet / outlet vertical MOS transistor and the second inlet / outlet vertical MOS transistor.

9. A semiconductor device, a chip-scale packaged semiconductor device capable of being mounted face-down, characterized in that, have: Semiconductor layer; and N vertical MOS transistors are formed in the above semiconductor layer, where N is an integer greater than or equal to 3; The aforementioned N vertical MOS transistors each have a gate pad electrically connected to the gate electrode of the vertical MOS transistor and one or more source pads electrically connected to the source electrode of the vertical MOS transistor on the upper surface of the aforementioned semiconductor layer. The aforementioned semiconductor layer has a semiconductor substrate; The aforementioned semiconductor substrate functions as the common drain region for the aforementioned N vertical MOS transistors; Corresponding to the maximum specification current of each of the above N vertical MOS transistors, the larger the maximum specification current, the larger the area of ​​each of the above N vertical MOS transistors in the planar diagram of the above semiconductor layer; The area of ​​each of the N vertical MOS transistors in the planar diagram of the aforementioned semiconductor layer is proportional to the square of the maximum specification current of each of the N vertical MOS transistors. In the above N vertical MOS transistors, the first inlet / outlet vertical MOS transistor located at the inlet or outlet of the first current path and the second inlet / outlet vertical MOS transistor located at the outlet or inlet are adjacent to each other in the plan view of the above semiconductor layer, as determined by the specifications. In the above N vertical MOS transistors, the second inlet / outlet vertical MOS transistor located at the entrance or exit of the second current path and the third inlet / outlet vertical MOS transistor located at the exit or entrance are adjacent to each other in the plan view of the above semiconductor layer, as determined by the above specifications. The current path determined by the first and third inlet vertical MOS transistors does not match any of the current paths determined by the above specifications. The first inlet / outlet vertical MOS transistor and the third inlet / outlet vertical MOS transistor are adjacent to each other in the planar view of the semiconductor layer. The gate pad of the third inlet / outlet vertical MOS transistor is closer to the boundary line between the first inlet / outlet vertical MOS transistor and the third inlet / outlet vertical MOS transistor than the boundary line between the second inlet / outlet vertical MOS transistor and the third inlet / outlet vertical MOS transistor.

10. The semiconductor device according to any one of claims 1, 3, 4, 8, and 9, characterized in that, The upper surface of the aforementioned semiconductor layer also has a drain pad that is electrically connected to the aforementioned semiconductor substrate.

11. A battery protection circuit, characterized in that, have: The semiconductor device according to claim 1; The first terminal is connected to one of the N vertical MOS transistors in the aforementioned semiconductor device, and to one or more source pads of the vertical MOS transistor; and The first electrode of one of the positive and negative electrodes of the N-1 battery cells is connected to one or more source pads of the N-1 vertical MOS transistors (excluding the terminal-connected vertical MOS transistors) in the semiconductor device. The polarity of the first electrode of each of the above N-1 battery cells is the same.

12. A battery protection circuit, characterized in that, have: The first semiconductor device is the semiconductor device according to claim 1; The second semiconductor device is the semiconductor device according to claim 1, wherein the second semiconductor device has three vertical MOS transistors; N-1 battery cells are connected in series with each other; The first terminal is connected to the first terminal of one of the N vertical MOS transistors of the first semiconductor device, which is connected to one or more source pads of the vertical MOS transistor, and the second terminal of one of the three vertical MOS transistors of the second semiconductor device is connected to one or more source pads of the vertical MOS transistor. The second terminal is connected to the negative terminal of the aforementioned N-1 battery cells; and The third terminal is connected to the positive terminal of the battery cell located at the positive terminal end in the series connection of the above N-1 battery cells. The positive terminal of each of the above-mentioned N-1 battery cells is connected to one or more source pads of the above-mentioned N-1 vertical MOS transistors (excluding the vertical MOS transistor connected to the first terminal) of the above-mentioned first semiconductor device. The positive electrode of the first battery cell located at the negative electrode side end in the series connection of the above N-1 battery cells and the negative electrode of the second battery cell located next to the first battery cell in the series connection are respectively connected to the source pads of one or more of the three vertical MOS transistors in the second semiconductor device, excluding the vertical MOS transistor connected to the second terminal. The first battery cell and the second battery cell are connected in series via the second semiconductor device.

13. A battery protection circuit, characterized in that, have: The first semiconductor device is the semiconductor device according to claim 1; The second semiconductor device is the semiconductor device according to claim 1, wherein the second semiconductor device comprises three vertical MOS transistors; N battery cells are connected in series with each other; The first terminal is connected to the first terminal of one of the N vertical MOS transistors of the first semiconductor device, which is connected to one or more source pads of the vertical MOS transistor, and the second terminal of one of the three vertical MOS transistors of the second semiconductor device is connected to one or more source pads of the vertical MOS transistor. The second terminal is connected to the negative terminal of the aforementioned N battery cells; and The third terminal is connected to the positive terminal of the battery cell located at the positive terminal end in the series connection of the above N battery cells. The positive terminals of the N-1 battery cells, excluding the first battery cell located at the negative terminal end in the series connection, are connected to one or more source pads of the N-1 vertical MOS transistors, excluding the vertical MOS transistor connected to the first terminal, in the first semiconductor device. The positive electrode of the first battery cell located at the negative electrode side end in the series connection of the above N battery cells and the negative electrode of the second battery cell located next to the first battery cell in the series connection of the above N battery cells are respectively connected to one or more source pads of the two vertical MOS transistors other than the vertical MOS transistor connected to the second terminal in the above second semiconductor device. The first battery cell and the second battery cell are connected in series via the second semiconductor device.

14. A battery protection circuit, characterized in that, have: The first semiconductor device is the semiconductor device according to claim 3, wherein the first semiconductor device has three vertical MOS transistors and one specific vertical MOS transistor; The second semiconductor device is the semiconductor device according to claim 3, wherein the second semiconductor device has three vertical MOS transistors and one specific vertical MOS transistor; The first terminal is connected to a source pad of one of the aforementioned specific vertical MOS transistors in the first semiconductor device. The second terminal and the third terminal are connected to the source pads of one or more of the three vertical MOS transistors (excluding the specific vertical MOS transistor) in the first semiconductor device. The fourth terminal is connected to a source pad of one of the aforementioned specific vertical MOS transistors in the second semiconductor device; and Terminals 5 and 6 are connected to the source pads of one or more of the three vertical MOS transistors (excluding the one specific vertical MOS transistor) in the second semiconductor device. The third terminal mentioned above is used to connect to the positive terminal of one or more battery cells; The sixth terminal mentioned above is used to connect to the negative terminal of one or more battery cells mentioned above; Terminal 1, terminal 2, terminal 4, and terminal 5 are terminals used to connect to the power management circuit. The power management circuit described above, via the second terminal and the fifth terminal, allows charging current to flow to one or more battery cells during charging, and receives discharging current from one or more battery cells during discharging.

15. A battery protection circuit, characterized in that, have: The semiconductor device is the semiconductor device according to claim 3, wherein the semiconductor device has three vertical MOS transistors and one specific vertical MOS transistor; The first terminal is connected to one source pad of one of the aforementioned specific vertical MOS transistors in the aforementioned semiconductor device and one or more source pads of one of the two vertical MOS transistors (excluding the aforementioned specific vertical MOS transistor) among the three aforementioned vertical MOS transistors in the aforementioned semiconductor device. The second terminal is connected to one or more source pads of the other vertical MOS transistor among the three vertical MOS transistors of the semiconductor device, excluding the one specific vertical MOS transistor described above. Terminal 3; and Terminal 4; The aforementioned first terminal is used to connect to the positive terminal of one or more battery cells; The third terminal mentioned above is used to connect to the negative terminal of one or more battery cells mentioned above; The second and fourth terminals mentioned above are terminals used for connection to the power management circuit; The power management circuit described above, via the second terminal and the fourth terminal, allows charging current to flow to one or more battery cells during charging, and receives discharging current from one or more battery cells during discharging.

16. A battery protection circuit, characterized in that, have: The first semiconductor device is the semiconductor device according to claim 1, wherein the first semiconductor device has X+Y vertical MOS transistors, where X is an integer greater than or equal to 1 and Y is an integer greater than or equal to 2. The second semiconductor device is the semiconductor device according to claim 1, wherein the second semiconductor device comprises 1+Y vertical MOS transistors; X first terminals are connected to each of the source pads of one or more of the X+Y vertical MOS transistors in the first semiconductor device described above. Y second terminals are connected to each of the source pads of one or more of the Y vertical MOS transistors (excluding the X vertical MOS transistors) in the X+Y of the first semiconductor device described above. The third terminal is connected to one or more source pads of one of the 1+Y vertical MOS transistors in the second semiconductor device described above; and Y fourth terminals are connected to the source pads of one or more of the Y vertical MOS transistors (excluding the one vertical MOS transistor) in the 1+Y types of the second semiconductor device described above. The aforementioned X first terminals are terminals used to connect to the positive terminals of the X battery cells respectively; The third terminal mentioned above is used to connect to the negative terminal of the X battery cells mentioned above; The aforementioned Y second terminals and Y fourth terminals are terminals used to connect to the Y power management circuits respectively; The aforementioned Y power management circuits, via one of the aforementioned Y second terminals and one of the aforementioned Y fourth terminals, respectively, cause charging current to flow to at least one of the aforementioned X battery cells during charging, and receive discharging current from the aforementioned at least one battery cell during discharging.

17. A power management circuit, characterized in that, have: The semiconductor device is the semiconductor device according to claim 1, wherein the semiconductor device has X+Y vertical MOS transistors, where X is an integer of 1 or more and Y is an integer of 2 or more. X terminals are connected to each of the source pads of one or more of the X+Y vertical MOS transistors in the aforementioned semiconductor device; and Y circuits are connected to the source pads of one or more of the Y vertical MOS transistors (excluding the X vertical MOS transistors) in the above-mentioned semiconductor device (X+Y). The aforementioned X terminals are used to connect to X external circuits respectively; The Y circuits mentioned above are each isolated from each other by a power source.

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