Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate having a dielectric layer thereon, the dielectric layer comprising: a second region and a first region located above the second region, the first region having a plurality of mutually discrete initial first nanowires, and the second region having a plurality of mutually discrete initial second nanowires; etching the dielectric layer and initial first nanowires in the first region to form a first opening in the first region, and causing the initial first nanowires to become first nanowires; etching the dielectric layer and initial second nanowires at the bottom of the first opening to form a second opening in the second region, and causing the initial second nanowires to become second nanowires; forming a second source-drain layer in the second opening; forming an isolation layer on the surface of the second source-drain layer; and forming the first source-drain layer in the first opening. The semiconductor structure formed by the method has good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] As the semiconductor industry enters nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs of multi-gate field-effect transistors.

[0003] Conventional FinFETs are limited in further increasing their operating current. Specifically, since only the area near the top surface and sidewalls of the fin is used as the channel region, the volume of the fin used as the channel region is relatively small, which limits the increase in the operating current of the FinFET. Therefore, a FinFET with a gate-all-around (GAA) structure is proposed, which increases the volume of the channel region and further increases the operating current of the FinFET with a gate-all-around structure.

[0004] Building on the proposed FinFET with a gate-all-around (GAA) structure, the complementary FinFET (CFET) with multiple vertically stacked GAA pairs was proposed to further improve device density. The complementary FinFET layout places an N-type GAA above or below a P-type GAA, and the stacked N-type and P-type GAAs share a gate that penetrates and covers each channel region, further reducing the area of ​​the integrated circuit.

[0005] However, the performance of complementary FinFETs formed using existing processes is still poor. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0007] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, a dielectric layer provided on the substrate, the dielectric layer comprising: a second region and a first region located on the second region, wherein the first region has a plurality of mutually discrete first nanowires, and the second region has a plurality of mutually discrete second nanowires; a first opening located in the first region and a first source-drain layer located in the first opening; a second opening located in the second region and a second source-drain layer located in the second opening; and an isolation layer located between the first source-drain layer and the second source-drain layer.

[0008] Optionally, the first nanowire and the second nanowire extend along a first direction.

[0009] Optionally, along the first direction, the first opening is located between the adjacent first nanowires.

[0010] Optionally, along the first direction, the second opening is located between the adjacent second nanowires.

[0011] Optionally, the first source-drain layer contains first ions, the second source-drain layer contains second ions, and the first ions and the second ions have opposite conductivity types.

[0012] Optionally, the first nanowire contains a third ion, the second nanowire contains a fourth ion, and the third ion and the fourth ion have opposite conductivity types, the third ion and the first ion have opposite conductivity types, and the fourth ion and the second ion have opposite conductivity types.

[0013] Optionally, a material of the first source / drain layer includes silicon phosphide, silicon, silicon carbide or silicon oxycarbide, and a material of the second source / drain layer includes silicon germanium or germanium.

[0014] Optionally, a material of the first source / drain layer includes silicon germanium or germanium, and a material of the second source / drain layer includes silicon phosphide, silicon, silicon carbide or silicon oxycarbide.

[0015] Optionally, the material of the dielectric layer includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0016] Optionally, the material of the isolation layer includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide or silicon nitride oxide.

[0017] Optionally, the isolation layer has a thickness ranging from 10 angstroms to 100 angstroms.

[0018] Optionally, along a direction perpendicular to a side wall of the first opening, the first opening has a first width, and along a direction perpendicular to a side wall of the second opening, the second opening has a second width, and the second width is smaller than the first width.

[0019] Optionally, the substrate further includes two source and drain regions arranged along the first direction, and a gate region located between the two source and drain regions, and the first nanowire and the second nanowire are located in the gate region.

[0020] Optionally, the method further includes: a gate structure located on the gate region, the gate structure surrounding the first nanowire and the second nanowire, and the gate structure extending along a second direction, which is perpendicular to the first direction.

[0021] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate having a dielectric layer thereon, the dielectric layer including: a second region and a first region located on the second region, and the first region having a number of mutually discrete initial first nanowires, and the second region having a number of mutually discrete initial second nanowires; etching the dielectric layer and the initial first nanowires in the first region to form a first opening in the first region, and causing the initial first nanowires to form first nanowires; etching the dielectric layer and the initial second nanowires at the bottom of the first opening to form a second opening in the second region, and causing the initial second nanowires to form second nanowires; forming a second source-drain layer in the second opening; forming an isolation layer on the surface of the second source-drain layer; and forming a first source-drain layer in the first opening.

[0022] Optionally, the first nanowire and the second nanowire extend along a first direction.

[0023] Optionally, along the first direction, the first opening is located between the adjacent first nanowires.

[0024] Optionally, along the first direction, the second opening is located between the adjacent second nanowires.

[0025] Optionally, the method of etching the dielectric layer and the initial first nanowire in the first region includes: forming a patterned layer on the surface of the dielectric layer, and the patterned layer exposes a portion of the surface of the dielectric layer; using the patterned layer as a mask, etching the dielectric layer and the initial first nanowire in the dielectric layer until the surface of the dielectric layer in the second region is exposed, forming the first opening in the first region, and forming the initial first nanowire into a first nanowire.

[0026] Optionally, it also includes: after forming the first opening and before forming the second opening, forming a protective layer on the side wall surface of the first opening, and the material of the protective layer is different from the material of the dielectric layer; after forming the second source and drain layer and before forming the first source and drain layer, removing the protective layer.

[0027] Optionally, the method for forming the protective layer includes: forming a protective material film on the sidewall surface and the bottom surface of the first opening; and etching back the protective material film until the bottom surface of the first opening is exposed to form the protective layer.

[0028] Optionally, the material of the protective layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0029] Optionally, the material of the dielectric layer includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0030] Optionally, in the process of etching the dielectric layer at the bottom of the first opening and the initial second nanowire, the etching rate of the protective layer is lower than the etching rate of the dielectric layer, and the etching rate of the protective layer is lower than the etching rate of the initial second nanowire.

[0031] Optionally, the process of etching the dielectric layer at the bottom of the first opening and the initial second nanowire is a dry etching process.

[0032] Optionally, the method for forming an isolation layer on the surface of the second source / drain layer includes: forming an isolation material film in the first opening and on the surface of the dielectric layer; planarizing the isolation material film until the dielectric layer is exposed to form an initial isolation layer; after the planarization process, etching the initial isolation layer to form the isolation layer.

[0033] Optionally, the method of forming the second source-drain layer in the second opening includes: forming a second epitaxial layer in the second opening using a selective epitaxial growth process; and doping second ions into the second epitaxial layer to form the second source-drain layer.

[0034] Optionally, the process of forming the first source-drain layer in the first opening includes: forming a first epitaxial layer in the first opening using a selective epitaxial growth process; and doping first ions into the first epitaxial layer to form the first source-drain layer.

[0035] Optionally, the substrate further includes two source and drain regions arranged along the first direction, and a gate region located between the two source and drain regions, and the first nanowire and the second nanowire are located in the gate region.

[0036] Optionally, the method further includes: before forming the second source / drain layer, forming a gate structure on the gate region, wherein the gate structure surrounds the first nanowire and the second nanowire, and the gate structure extends along a second direction perpendicular to the first direction.

[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0038] In the semiconductor structure of the technical solution of the present invention, the first source-drain layer is located in the first opening, and the first opening is used to limit the volume of the first source-drain layer; the second source-drain layer is located in the second opening, and the second opening is used to limit the volume of the second source-drain layer; the first opening and the second opening can make the volume difference between the first source-drain layer and the second source-drain layer within a controllable range, thereby meeting process requirements.

[0039] Furthermore, the isolation layer is located between the first source-drain layer and the second source-drain layer. The isolation layer is made of insulating material and can electrically isolate the first source-drain layer and the second source-drain layer, thereby forming an effective complementary fin field-effect transistor between the first region and the second region.

[0040] Furthermore, the thickness of the isolation layer ranges from 10 angstroms to 100 angstroms. The significance of selecting this thickness range is that if the thickness is less than 10 angstroms, the isolation layer is too thin and cannot fully isolate the first source-drain layer and the second source-drain layer, resulting in poor performance of the formed semiconductor structure. If the thickness is greater than 100 angstroms, while ensuring good isolation, the isolation layer is too thick and occupies a large space, resulting in a small volume of the first source-drain layer and the second source-drain layer, which is not conducive to improving the integration density of the integrated circuit and the increase of the drive current.

[0041] The method for forming a semiconductor structure of the technical solution of the present invention forms a first opening in the first region and a second opening in the second region. The first opening can provide space for the subsequent formation of a first source-drain layer, thereby limiting the volume of the first source-drain layer. The second opening can provide space for the formation of a second source-drain layer, thereby limiting the volume of the second source-drain layer. The first opening and the second opening can make the volume difference between the first source-drain layer and the second source-drain layer within a controllable range, thereby meeting process requirements.

[0042] Furthermore, the method for forming the semiconductor structure also includes: after forming the first opening and before forming the second opening, forming a protective layer on the side wall surface of the first opening, the protective layer covering the first nanowire exposed on the side wall of the first opening. On the one hand, it can protect the surface of the first nanowire and avoid etching damage to the first nanowire during the subsequent etching process to form the second opening, thereby improving the performance of the semiconductor structure; on the other hand, the first nanowire is covered by the protective layer, which can avoid the second source and drain layer being epitaxially grown with the surface exposed by the first nanowire as a seed layer during the subsequent formation of the second source and drain layer in the second opening, so that the formed second source and drain layer is located in the second opening, so that the first nanowire in the first region and the second nanowire in the second region do not interfere with each other.

[0043] Furthermore, the isolation layer is located between the first source-drain layer and the second source-drain layer. The isolation layer is made of insulating material and can electrically isolate the first source-drain layer and the second source-drain layer, thereby forming an effective complementary fin field-effect transistor between the first region and the second region. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figures 1 to 12 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0045] As described in the background art, complementary FinFETs with multiple vertically stacked GAA pairs are implemented to further reduce the area of ​​integrated circuits. However, the performance of the conventional complementary FinFETs is still relatively poor.

[0046] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, wherein the method includes: first, etching the dielectric layer and the initial first nanowire in the first region to form a first opening in the first region; etching the dielectric layer and the initial second nanowire at the bottom of the first opening to form a second opening in the second region; then, forming a second source and drain layer in the second opening; forming an isolation layer on the surface of the second source and drain layer; forming a first source and drain layer in the first opening, the first opening providing space for the first source and drain layer, and the second opening providing space for the second source and drain layer, so that the first opening and the second opening can make the volume difference between the first source and drain layer and the second source and drain layer within a controllable range, thereby meeting the process requirements.

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figures 1 to 12 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0049] Please refer to Figure 1 and Figure 2 , Figure 2 for Figure 1 Schematic diagram of the cross section along the AA tangent direction, Figure 1 To omit the three-dimensional diagram of the dielectric layer and the substrate, a substrate 200 is provided, on which a dielectric layer 201 is provided. The dielectric layer 201 includes: a second region II and a first region I located on the second region II, and the first region I has a plurality of mutually discrete initial first nanowires 210, and the second region II has a plurality of mutually discrete initial second nanowires 220.

[0050] The substrate 200 is made of a semiconductor material.

[0051] In this embodiment, the substrate 200 is made of silicon.

[0052] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0053] In other embodiments, the substrate has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

[0054] The initial first nanowires 210 and the initial second nanowires 220 extend along a first direction X.

[0055] In this embodiment, the material of the initial first nanowire 110 and the initial second nanowire 120 is silicon.

[0056] In other embodiments, the materials of the initial first nanowire and the initial second nanowire include silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0057] In this embodiment, the initial first nanowire 210 contains a third ion, the initial second nanowire 220 contains a fourth ion, and the third ion and the fourth ion have opposite conductivity types.

[0058] Specifically, in this embodiment, the third ion is an N-type ion, and the third ion includes a phosphorus ion, an arsenic ion, or an antimony ion; the fourth ion is a P-type ion, and the fourth ion includes a boron ion, BF 2- ions or indium ions.

[0059] In other embodiments, the third ion is a P-type ion, and the third ion includes boron ions, BF 2- ions or indium ions; the fourth ions are N-type ions, and the fourth ions include phosphorus ions, arsenic ions or antimony ions.

[0060] In this embodiment, the method for forming the initial first nanowires 210, the initial second nanowires 220 and the dielectric layer 201 includes: forming a first material layer (not shown in the figure) on the surface of the substrate 200; forming a plurality of mutually discrete initial second nanowires 220 on the surface of the first material layer; forming a second material layer (not shown in the figure) on the surfaces of the initial second nanowires 220 and the first material layer, and the top surface of the second material layer is higher than the top surface of the first material layer; forming a plurality of mutually discrete initial first nanowires 210 on the surface of the second material layer; forming a third material layer (not shown in the figure) on the surfaces of the initial first nanowires 210 and the second material layer, and the top surface of the third material layer is higher than the top surface of the initial first nanowires 210.

[0061] The first material layer, the second material layer, and the third material layer constitute the dielectric layer 201 .

[0062] In this embodiment, the material of the dielectric layer 201 includes silicon oxide.

[0063] In other embodiments, the material of the dielectric layer includes silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride.

[0064] The substrate 200 further includes two source and drain regions (not shown in the figure) arranged along the first direction X, and a gate region (not shown in the figure) located between the two source and drain regions.

[0065] The method for forming the semiconductor structure further includes: before subsequently forming the second source and drain layer, forming a gate structure 230 on the gate region, wherein the gate structure 230 surrounds the initial first nanowire 210 and the initial second nanowire 220, and the gate structure 230 extends along a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0066] Next, the dielectric layer 201 and the initial first nanowire 210 in the first region I are etched to form a first opening in the first region I, and the initial first nanowire 210 is formed into a first nanowire. For details on the process of forming the first opening and the first nanowire, please refer to Figures 3 and 4 .

[0067] Please refer to Figure 3 , a patterned layer 240 is formed on the surface of the dielectric layer 201 , and the patterned layer 240 exposes a portion of the surface of the dielectric layer 201 .

[0068] The patterned layer 240 serves as a mask for subsequent etching of the dielectric layer 201 in the first region I.

[0069] Specifically, the patterned layer 240 has a pattern (not shown in the figure), and the pattern exposes the surface of the dielectric layer 201 on the initial first nanowire 210 on the source and drain regions.

[0070] The material of the patterned layer 240 includes: a hard mask material or a photoresist. In this embodiment, the material of the patterned layer 240 is photoresist.

[0071] Please refer to Figure 4 Using the patterned layer 240 as a mask, the dielectric layer 201 and the initial first nanowire 210 in the dielectric layer 201 are etched until the surface of the dielectric layer 201 in the second region I is exposed, and the first opening 251 is formed in the first region I, so that the initial first nanowire 210 is transformed into the first nanowire 211.

[0072] The first opening 251 can provide space for the subsequent formation of a first source / drain layer, thereby limiting the volume of the first source / drain layer.

[0073] Since the initial first nanowire 210 extends along the first direction X, the first nanowire 211 formed by etching a portion of the initial first nanowire 210 extends along the first direction X.

[0074] Specifically, along the first direction X, the first opening 251 is located between the adjacent first nanowires 211 .

[0075] The process of etching the dielectric layer 201 and the initial first nanowires 210 in the dielectric layer 201 includes: a dry etching process and a wet etching process, or a combination of the two.

[0076] In this embodiment, the process of etching the dielectric layer 201 and the initial first nanowire 210 in the dielectric layer 201 is a dry etching process, which is beneficial to improving the morphology of the formed first opening 251. The sidewall of the first opening 251 is preferably perpendicular to the bottom of the first opening 251, and the morphology of the formed first nanowire 210 is better, which is beneficial to improving the performance of the formed semiconductor structure.

[0077] Next, a protective layer is formed on the sidewall surface of the first opening 251, and the material of the protective layer is different from the material of the dielectric layer. For the specific process of forming the protective layer, please refer to Figures 5 and 6 .

[0078] Please refer to Figure 5 A protective material film 260 is formed on the sidewall surfaces and the bottom surface of the first opening 251 .

[0079] The protective material film 260 provides a material layer for subsequently forming a protective layer.

[0080] In this embodiment, the protective material film 260 is also located on the surface of the patterned layer 240 on the surface of the dielectric layer 201 .

[0081] The protective material film 260 and the dielectric layer 201 are made of different materials.

[0082] In this embodiment, the material of the protective material film 260 is silicon nitride. In other embodiments, the material of the protective material film is silicon oxide, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0083] The protective material film 260 is formed by a process including a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0084] In this embodiment, the formation process of the protective material film 260 is an atomic layer deposition process. The protective material film 260 formed by the atomic layer deposition process has good density and high quality, so that the subsequent protective layer can better protect the dielectric layer 201 and the first nanowire 211 on the side wall of the first opening 251.

[0085] Please refer to Figure 6 , the protective material film 260 is etched back until the bottom surface of the first opening 251 is exposed to form the protective layer 261 .

[0086] Since the protective layer 261 is formed by etching the protective material film 260, the material of the protective layer 261 is different from that of the dielectric layer 201. In this embodiment, the material of the protective layer 261 is silicon nitride. In other embodiments, the material of the protective layer is silicon oxide, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon oxynitride.

[0087] By forming a protective layer 261 on the side wall surface of the first opening 251, the protective layer 261 covers the first nanowire 211 exposed on the side wall of the first opening 251. On the one hand, it can protect the surface of the first nanowire 211 and avoid etching damage to the first nanowire 211 during the subsequent etching to form the second opening, thereby improving the performance of the semiconductor structure; on the other hand, the first nanowire 211 is covered by the protective layer 261, which can avoid the second source and drain layer being epitaxially grown with the surface exposed by the first nanowire 211 as the seed layer during the subsequent formation of the second source and drain layer in the second opening, so that the formed second source and drain layer is located in the second opening, so that there is no interference between the first nanowire 211 in the first region I and the second nanowire in the second region II.

[0088] Please refer to Figure 7After forming the protection layer 261 , the dielectric layer 201 and the initial second nanowire 220 at the bottom of the first opening 251 are etched to form a second opening 252 in the second region II, and the initial second nanowire 220 is transformed into a second nanowire 221 .

[0089] The second opening 252 can provide space for the subsequent formation of a second source / drain layer, thereby limiting the volume of the second source / drain layer.

[0090] In this embodiment, the dielectric layer 201 and the initial second nanowires 220 in the dielectric layer 201 are etched using the patterned layer 240 and the protective layer 261 as masks.

[0091] Since the initial second nanowire 220 extends along the first direction X, the second nanowire 221 formed by etching a portion of the initial second nanowire 220 extends along the first direction X.

[0092] Specifically, along the first direction X, the second opening 252 is located between the adjacent second nanowires 221 .

[0093] In a direction perpendicular to the sidewall of the first opening 251 , the first opening 251 has a first width, and in a direction perpendicular to the sidewall of the second opening 252 , the second opening 252 has a second width.

[0094] The process of etching the dielectric layer 201 and the initial second nanowire 220 at the bottom of the first opening 251 has a lower etching rate for the protective layer 261 than for the dielectric layer 201 , and the etching rate for the protective layer 261 is lower than for the initial second nanowire 220 .

[0095] The process of etching the dielectric layer 201 at the bottom of the first opening 251 and the initial second nanowire 220 includes: a dry etching process and a wet etching process, or a combination of the two.

[0096] In this embodiment, the process of etching the dielectric layer 201 at the bottom of the first opening 251 and the initial second nanowire 220 is a dry etching process, which is beneficial to improving the morphology of the formed second opening 252. The sidewall of the second opening 252 is relatively perpendicular to the bottom of the second opening 252, and the morphology of the formed second nanowire 221 is better, which is beneficial to improving the performance of the formed semiconductor structure.

[0097] Please refer to Figure 8 After forming the second opening 252 and the second nanowire 221 , a second source-drain layer 282 is formed in the second opening 252 .

[0098] A second epitaxial layer is formed in the second opening 252 by adopting a selective epitaxial growth process; and second ions are doped into the second epitaxial layer to form the second source-drain layer 282 .

[0099] The second nanowires 221 serve as a seed layer for forming a film layer, thereby forming the second source / drain layer 282 in the second opening 252 .

[0100] In this embodiment, after forming the second source-drain layer 282, the process further includes: etching a portion of the second source-drain layer 282 to reduce the height of the second source-drain layer 282 so that the height of the second source-drain layer 282 meets the process requirements; at the same time, the etched second source-drain layer 282 is located within the second opening 252 to avoid subsequent contact with the first nanowire 211 located on the side wall of the first opening 251.

[0101] In this embodiment, the material of the second source / drain layer 282 is germanium silicon, and the second ions are P-type ions, which include boron ions, BF 2- ions or indium ions.

[0102] In other embodiments, the material of the second source / drain layer is silicon phosphide, and the second ions are N-type ions, which include phosphorus ions, arsenic ions, or antimony ions.

[0103] Next, an isolation layer is formed on the surface of the second source / drain layer 282. For details on the process of forming the isolation layer, please refer to Figures 9 and 10 .

[0104] Please refer to Figure 9 , forming an isolation material film (not shown in the figure) in the first opening 251 and on the surface of the dielectric layer 201 ; planarizing the isolation material film until the dielectric layer 201 is exposed to form an initial isolation layer 270 .

[0105] The initial isolation layer 270 provides a material layer for subsequently forming an isolation layer.

[0106] In this embodiment, the material of the initial isolation layer 270 is the same as that of the dielectric layer 201, that is, silicon oxide. In other embodiments, the material of the initial isolation layer is different from that of the dielectric layer.

[0107] Specifically, in this embodiment, the planarization process is performed until the surface of the patterned layer 240 on the dielectric layer 201 is exposed.

[0108] Please refer to Figure 10 After the planarization process, the initial isolation layer 270 is etched to form the isolation layer 271.

[0109] The thickness of the isolation layer 271 ranges from 10 angstroms to 100 angstroms.

[0110] The significance of selecting the thickness range is that if the thickness is less than 10 angstroms, the isolation layer 271 is too thin and cannot fully isolate the first source-drain layer and the second source-drain layer 282 formed subsequently, and the performance of the formed semiconductor structure is still poor; if the thickness is greater than 100 angstroms, while ensuring that it can play a good isolation role, the isolation layer 271 is too thick and occupies a large space, resulting in a smaller volume of the first source-drain layer and the second source-drain layer 282, which is not conducive to improving the integration of integrated circuits, nor is it conducive to increasing the driving current.

[0111] In this embodiment, the isolation layer 271 and the protection layer 261 are made of different materials. The isolation layer 271 is made of silicon oxide.

[0112] In other embodiments, the material of the isolation layer may also be silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0113] During the etching of the initial isolation layer 270 , the etching rate of the protective layer 261 is relatively low. The protective layer 261 can protect the dielectric layer 201 and the first nanowire 211 , avoiding damage to the dielectric layer 201 and the first nanowire 211 , thereby improving the performance of the formed semiconductor structure.

[0114] Please refer to Figure 11 After forming the second source / drain layer 282 , the protection layer 261 is removed.

[0115] In this embodiment, after the second source / drain layer 282 and the isolation layer 271 are formed, the protection layer 261 is removed.

[0116] In this embodiment, the method further includes: after forming the second source / drain layer 282 , removing the patterned layer 240 .

[0117] In other embodiments, the protection layer is removed after the second source / drain layer is formed and before the isolation layer is formed.

[0118] Please refer to Figure 12 After forming the isolation layer 271 , a first source / drain layer 281 is formed in the first opening 251 .

[0119] A first epitaxial layer (not shown in the figure) is formed in the first opening 251 by adopting a selective epitaxial growth process; first ions are doped into the first epitaxial layer to form the first source-drain layer 281 .

[0120] In this embodiment, after the isolation layer 271 is formed and the protection layer 261 is removed, the first nanowire 211 is exposed. The first nanowire 211 serves as a seed layer for forming a film layer, thereby forming the first source / drain layer 281 in the first opening 251 .

[0121] In other embodiments, after forming the first source / drain layer, the method further includes: etching a portion of the first source / drain layer to reduce a height of the first source / drain layer, wherein the height of the first source / drain layer meets process requirements.

[0122] Specifically, the first source-drain layer 281 is located on the surface of the isolation layer 271 , and the isolation layer 271 is located between the first source-drain layer 281 and the second source-drain layer 282 .

[0123] The isolation layer 271 is located between the first source-drain layer 281 and the second source-drain layer 282 . The isolation layer 271 is made of insulating material and can electrically isolate the first source-drain layer 271 and the second source-drain layer 282 , thereby forming a complementary fin field-effect transistor between the first region I and the second region II.

[0124] The first ions and the second ions have opposite conductivity types.

[0125] In this embodiment, the material of the first source / drain layer 281 is silicon phosphide, and the first ions are N-type ions, which include phosphorus ions, arsenic ions, or antimony ions.

[0126] In other embodiments, the material of the first source and drain layer is germanium silicon, and the first ions are P-type ions, and the P-type ions include: boron ions, BF 2- ions or indium ions.

[0127] By forming a first opening 251 in the first region I and a second opening 252 in the second region II, the first opening 251 can provide space for forming a first source-drain layer 281, thereby limiting the volume of the first source-drain layer 281, and the second opening 252 can provide space for forming a second source-drain layer 282, thereby limiting the volume of the second source-drain layer 282. The first opening 251 and the second opening 252 can make the volume difference between the first source-drain layer 281 and the second source-drain layer 282 within a controllable range, thereby meeting the process requirements.

[0128] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 1 and 12, comprising: a substrate 200, wherein the substrate 200 has a dielectric layer 201, the dielectric layer 201 including: a second region II and a first region I located on the second region II, wherein the first region I has a plurality of mutually discrete first nanowires 211, and the second region II has a plurality of mutually discrete second nanowires 221; a first opening 251 located in the first region I and a first source-drain layer 281 located in the first opening 251; a second opening 252 located in the second region II and a second source-drain layer 282 located in the second opening 252; and an isolation layer 271 located between the first source-drain layer 281 and the second source-drain layer 282.

[0129] The first source-drain layer 281 is located in the first opening 251, and the first opening 251 is used to limit the volume of the first source-drain layer 281. The second source-drain layer 282 is located in the second opening 252, and the second opening 252 is used to limit the volume of the second source-drain layer 282. The first opening 251 (as shown in FIG. Figure 7 as shown) and a second opening 252 (as shown) Figure 7 As shown), the volume difference between the first source and drain layer 281 and the second source and drain layer 282 can be within a controllable range, thereby meeting process requirements.

[0130] The following is a detailed description with reference to the accompanying drawings.

[0131] The first nanowire 211 and the second nanowire 221 extend along a first direction X.

[0132] Along the first direction X, the first opening 251 is located between the adjacent first nanowires 211 .

[0133] Along the first direction X, the second opening 252 is located between the adjacent second nanowires 221 .

[0134] The first source-drain layer 281 contains first ions, and the second source-drain layer 282 contains second ions, and the first ions and the second ions have opposite conductivity types.

[0135] The first nanowire 211 contains a third ion, the second nanowire 221 contains a fourth ion, and the third ion and the fourth ion have opposite conductivity types, the third ion and the first ion have opposite conductivity types, and the fourth ion and the second ion have opposite conductivity types.

[0136] In this embodiment, the first ion is an N-type ion, which includes phosphorus ions, arsenic ions, or antimony ions; the second ion is a P-type ion, which includes boron ions, BF 2-ions or indium ions; the third ions are P-type ions, and the third ions include boron ions, BF 2- ions or indium ions; the fourth ions are N-type ions, and the fourth ions include phosphorus ions, arsenic ions or antimony ions.

[0137] In other embodiments, the first ion is a P-type ion, and the first ion includes:

[0138] In this embodiment, the material of the first source / drain layer 281 includes silicon phosphide, silicon, silicon carbide, or silicon oxycarbide, and the material of the second source / drain layer 282 includes silicon germanium or germanium.

[0139] In other embodiments, the material of the first source / drain layer includes silicon germanium or germanium, and the material of the second source / drain layer includes silicon phosphide, silicon, silicon carbide, or silicon oxycarbide.

[0140] The material of the dielectric layer 201 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon oxynitride.

[0141] The material of the isolation layer 271 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon oxynitride.

[0142] The thickness of the isolation layer 271 ranges from 10 angstroms to 100 angstroms.

[0143] The isolation layer 271 is located between the first source-drain layer 281 and the second source-drain layer 282. The isolation layer 271 is made of insulating material and can electrically isolate the first source-drain layer 281 and the second source-drain layer 282, thereby forming an effective complementary fin field-effect transistor between the first region I and the second region II.

[0144] The first opening 251 has a first width along a direction perpendicular to the sidewall of the first opening 251 . The second opening 252 has a second width along a direction perpendicular to the sidewall of the second opening 252 . The second width is smaller than the first width.

[0145] The substrate 200 further includes two source and drain regions arranged along a first direction X, and a gate region located between the two source and drain regions. The first nanowire 211 and the second nanowire 221 are located in the gate region.

[0146] The semiconductor structure further includes a gate structure 230 located on the gate region. The gate structure 230 surrounds the first nanowire 211 and the second nanowire 221 , and extends along a second direction Y perpendicular to the first direction X.

Claims

1. A semiconductor structure, characterized in that include: A substrate having a dielectric layer thereon, the dielectric layer comprising: a second region and a first region located on the second region, wherein the first region has a plurality of mutually discrete first nanowires, and the second region has a plurality of mutually discrete second nanowires; a first opening located in the first region and a first source / drain layer located in the first opening; a second opening located in the second region and a second source / drain layer located in the second opening; an isolation layer located between the first source-drain layer and the second source-drain layer; The first nanowire and the second nanowire extend along a first direction; along the first direction, the first opening is located between the adjacent first nanowires; along the first direction, the second opening is located between the adjacent second nanowires; along the second direction, the first opening has a first width, the second opening has a second width, and the second width is smaller than the first width; the second direction is perpendicular to the first direction and the side walls of the first opening and the second opening.

2. The semiconductor structure according to claim 1, wherein The first source-drain layer contains first ions, the second source-drain layer contains second ions, and the first ions and the second ions have opposite conductivity types.

3. The semiconductor structure according to claim 2, wherein: The first nanowire contains a third ion, the second nanowire contains a fourth ion, and the third ion and the fourth ion have opposite conductivity types, the third ion and the first ion have opposite conductivity types, and the fourth ion and the second ion have opposite conductivity types.

4. The semiconductor structure according to claim 1, wherein: The material of the first source / drain layer includes silicon phosphide, silicon, silicon carbide or silicon oxycarbide, and the material of the second source / drain layer includes silicon germanium or germanium.

5. The semiconductor structure according to claim 1, wherein The material of the first source / drain layer includes: silicon germanium or germanium, and the material of the second source / drain layer includes: silicon phosphide, silicon, silicon carbide or silicon oxycarbide.

6. The semiconductor structure according to claim 1, wherein The material of the dielectric layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

7. The semiconductor structure according to claim 1, wherein: The material of the isolation layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

8. The semiconductor structure according to claim 1, wherein: The thickness of the isolation layer ranges from 10 angstroms to 100 angstroms.

9. The semiconductor structure according to claim 1, wherein: The substrate further includes two source and drain regions arranged along a first direction, and a gate region located between the two source and drain regions, and the first nanowire and the second nanowire are located in the gate region.

10. The semiconductor structure according to claim 9, wherein: Also includes: A gate structure is located on the gate region, the gate structure surrounds the first nanowire and the second nanowire, and the gate structure extends along a second direction perpendicular to the first direction.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a dielectric layer thereon, the dielectric layer comprising: a second region and a first region located on the second region, wherein the first region has a plurality of mutually discrete initial first nanowires, and the second region has a plurality of mutually discrete initial second nanowires; Etching the dielectric layer and the initial first nanowire in the first region to form a first opening in the first region and forming the initial first nanowire into a first nanowire; Etching the dielectric layer and the initial second nanowire at the bottom of the first opening to form a second opening in the second region, and forming the initial second nanowire into a second nanowire; forming a second source / drain layer in the second opening; forming an isolation layer on a surface of the second source / drain layer; forming a first source / drain layer in the first opening; The first nanowire and the second nanowire extend along a first direction; along the first direction, the first opening is located between the adjacent first nanowires; along the first direction, the second opening is located between the adjacent second nanowires; along the second direction, the first opening has a first width, the second opening has a second width, and the second width is smaller than the first width; the second direction is perpendicular to the first direction and the side walls of the first opening and the second opening.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for etching the dielectric layer and the initial first nanowire in the first region includes: forming a patterned layer on the surface of the dielectric layer, and the patterned layer exposes a portion of the dielectric layer surface; using the patterned layer as a mask, etching the dielectric layer and the initial first nanowire in the dielectric layer until the dielectric layer surface in the second region is exposed, forming the first opening in the first region, and forming the initial first nanowire into a first nanowire.

13. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: After forming the first opening and before forming the second opening, a protective layer is formed on the sidewall surface of the first opening, and the material of the protective layer is different from the material of the dielectric layer; after forming the second source and drain layer and before forming the first source and drain layer, the protective layer is removed.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the protective layer includes: forming a protective material film on the sidewall surface and the bottom surface of the first opening; and etching back the protective material film until the bottom surface of the first opening is exposed to form the protective layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the protective layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon oxynitride.

16. The method for forming a semiconductor structure according to claim 11, wherein: The material of the dielectric layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

17. The method for forming a semiconductor structure according to claim 13, wherein: In the process of etching the dielectric layer at the bottom of the first opening and the initial second nanowire, the etching rate of the protective layer is lower than the etching rate of the dielectric layer, and the etching rate of the protective layer is lower than the etching rate of the initial second nanowire.

18. The method for forming a semiconductor structure according to claim 17, wherein: The process of etching the dielectric layer at the bottom of the first opening and the initial second nanowire is a dry etching process.

19. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming an isolation layer on the surface of the second source / drain layer includes: forming an isolation material film in the first opening and on the surface of the dielectric layer; planarizing the isolation material film until the dielectric layer is exposed to form an initial isolation layer; after the planarization process, etching the initial isolation layer to form the isolation layer.

20. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the second source-drain layer in the second opening includes: forming a second epitaxial layer in the second opening by adopting a selective epitaxial growth process; and doping second ions into the second epitaxial layer to form the second source-drain layer.

21. The method for forming a semiconductor structure according to claim 11, wherein: The process of forming the first source-drain layer in the first opening includes: forming a first epitaxial layer in the first opening by adopting a selective epitaxial growth process; and doping first ions into the first epitaxial layer to form the first source-drain layer.

22. The method for forming a semiconductor structure according to claim 11, wherein: The substrate further includes two source and drain regions arranged along a first direction, and a gate region located between the two source and drain regions, and the first nanowire and the second nanowire are located in the gate region.

23. The method for forming a semiconductor structure according to claim 22, wherein: Also includes: Before forming the second source / drain layer, a gate structure is formed on the gate region. The gate structure surrounds the first nanowire and the second nanowire, and the gate structure extends along a second direction perpendicular to the first direction.

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