Growth of amorphous silicon and oxidized thin oxide layers

Abstract

A method for forming an oxide layer includes forming an interface layer on a substrate, forming an amorphous silicon layer on the interface layer, performing a direct oxidation process to selectively oxidize the formed amorphous silicon layer, and performing a thermal oxidation process to oxidize the formed amorphous silicon layer.

Description

background Technical Field

[0002] The various embodiments described herein generally relate to the fabrication of semiconductor devices, and more specifically, to methods for forming high-quality thin oxide layers in high aspect ratio semiconductor structures. Background Technology

[0004] The production of silicon integrated circuits presents challenging requirements for manufacturing processes to increase device count while minimizing the smallest feature size on the chip. These requirements have extended to manufacturing processes that involve depositing layers onto complex topologies while maintaining device reliability. For example, recessed channel array transistors (RCATs) used in dynamic random access memory (DRAM) devices can have aspect ratios of 10:1 or higher and require thin, reliable gate oxide layers.

[0005] Conventional methods for forming oxide layers in such structures suffer from one or both of two problems. The first problem is the high silicon consumption of thermal oxidation growth. That is, for high aspect ratio structures, a thin oxide layer may not be formed. The second problem is the low quality of the deposited oxide layer, which may contain defects and traps, leading to reduced device reliability.

[0006] Therefore, there is a need for improved processes to form thin, high-quality oxide layers that minimize silicon consumption and defects in the formed oxide layers. Summary of the Invention

[0007] Several embodiments of this disclosure provide a method for forming an oxide layer. This method includes: forming an interface layer on a substrate, forming an amorphous silicon layer on the interface layer, performing a direct oxidation process to selectively oxidize the formed amorphous silicon layer, and performing a thermal oxidation process to oxidize the formed amorphous silicon layer.

[0008] Several embodiments of this disclosure also provide methods for forming oxide layers. These methods include forming an amorphous silicon layer on a substrate and performing a thermal oxidation process to oxidize the formed amorphous silicon layer.

[0009] Several embodiments of this disclosure further provide a method for forming an oxide layer. This method includes: forming an amorphous silicon layer on a silicon substrate by exposing a silicon substrate to a silicon precursor in an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process, and performing a thermal oxidation process to oxidize the formed amorphous silicon layer to form an oxide layer on the silicon substrate. Attached Figure Description

[0010] To gain a more detailed understanding of the above-described features of this disclosure, a more specific description of the disclosure, which has been briefly summarized above, can be obtained by referring to several embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate several typical embodiments of this disclosure and should not be construed as limiting the scope of this disclosure, as this disclosure may allow for several other equivalent embodiments.

[0011] Figure 1 This is a schematic diagram of a substrate processing system according to one embodiment.

[0012] Figure 2 This is a schematic diagram of a substrate processing system according to one embodiment.

[0013] Figure 3 This is a process flow diagram of a method for forming an oxide layer in a semiconductor structure according to one embodiment.

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E This is a schematic diagram of a recessed channel array transistor (RCAT) structure according to one embodiment.

[0015] To facilitate understanding, the same reference numerals are used where possible to refer to the same elements common in the figures. Elements and features of one embodiment are contemplated to be beneficially incorporated into several other embodiments without further description. Detailed Implementation

[0016] Several embodiments described herein relate to methods for forming high-quality thin oxide layers in semiconductor devices, such as recessed channel array transistors (RCATs) and thin nanowire field-effect transistors (FETs) used in dynamic random access memory (DRAM) devices. Thin oxide layers that can be used as gate oxide layers in such devices can be formed by first depositing amorphous silicon on a substrate and then oxidizing the amorphous silicon using direct plasma oxidation and thermal oxidation processes.

[0017] The methods described herein for forming oxide layers reduce silicon consumption and improve the quality of the formed oxide layers. The methods also provide the ability to selectively adjust the thickness of the oxide layer. For example, by directing plasma ions to the bottom of a concave feature structure in a substrate, the oxide layer formed in the concave feature structure can be made thicker at the bottom of the concave feature structure as needed.

[0018] Figure 1A substrate processing system 100 is schematically illustrated that can be used to perform aspects of the methods described herein. The substrate processing system 100 may be a decoupled plasma oxidation (DPO) reactor available from Applied Materials, Inc., Santa Clara, California.

[0019] The substrate processing system 100 includes a chamber 102, which has cylindrical sidewalls 104 and a ceiling 106, the ceiling 106 being dome-shaped (e.g., Figure 1 (As shown), flat or other geometries. The substrate processing system 100 can provide low-ion energy plasma via an inductively coupled plasma (ICP) source power applicator driven by a pulsed or continuous wave (CW) RF power generator. The ICP source power applicator includes a coil antenna 108 disposed above a top plate 106 and coupled to an RF power source via an impedance matching network 110. The RF power source includes an RF power generator 112 and a gate 114 at the output of the RF power generator 112, the gate 114 being controlled by a pulse signal having a selected duty cycle. Other plasma source power applicators that generate low-ion energy, such as remote RF or microwave plasma sources, are also contemplated. Alternatively, the power generator may be a pulsed DC generator. The substrate processing system 100 may include a transformer-coupled plasma (TCP) source or a microwave plasma source.

[0020] The substrate processing system 100 further includes a substrate support base 116, such as an electrostatic chuck or other suitable substrate support, for holding the substrate W, for example, a 200mm or 300mm semiconductor wafer or the like. The substrate support base 116 typically includes heating equipment, such as a heater 118 located beneath the top surface of the substrate support base 116. The heater 118 can be a single-zone or multi-zone heater, such as a dual radial zone heater having a radially inner heating element 118A and a radially outer heating element 118B, as shown below. Figure 1 drawn.

[0021] The substrate processing system 100 further includes a gas injection system 120 and a vacuum pump 122 coupled to the interior of chamber 102. The gas injection system 120 supplies one or more processing gas sources, for example, an oxidizing gas container 124 for supplying an oxidizing gas comprising O2, N2O, NO, NO2, H2O, H2, and H2O2, a reducing gas container 126 for supplying a reducing gas such as hydrogen, or other processing gas sources required for a particular application, for example, gases such as He, Ar, or nitriding gases such as N2. Flow control valves 130, 132, and 134 are coupled to gas sources (e.g., oxidizing gas container 124, reducing gas container 126, etching gas container 128, and similar gases), which can be used to selectively supply processing gases or mixtures of processing gases to the interior of chamber 102 during processing. Other gas sources (not shown) may also be provided for supplying additional gases, such as inert gases (helium, argon, or similar gases), gaseous mixtures, or similar gases. The chamber pressure can be controlled by the throttle valve 136 of the vacuum pump 122.

[0022] The duty cycle of the pulsed RF power output at gate 114 can be controlled by controlling the duty cycle of pulse generator 138, the output of which is coupled to gate 114. Plasma is generated in ion generation region 140, which corresponds to the space below top plate 106 surrounded by coil antenna 108. Since the plasma is formed in the upper region of chamber 102 at a distance from substrate W, the plasma is referred to as quasi-remote plasma (e.g., the plasma has the benefits of remote plasma formation but is formed within the same process chamber 102 as substrate W).

[0023] In operation, the substrate processing system 100 can be used to perform an oxidation process according to various embodiments of the invention. Plasma is formed in the ion generation region 140 of the chamber 102 by inductive coupling of RF energy from a coil antenna 108 disposed on the top plate 106, thereby providing low ion energy (e.g., less than about 5 eV for pulsed plasma and less than 25 eV for CW plasma).

[0024] In some implementations, power of approximately 25 watts to 5000 watts can be supplied to the coil antenna 108 at a suitable frequency to form plasma (for example, in the MHz or GHz range, or approximately 13.56 MHz or higher). Power can be supplied in continuous wave or pulsed mode with a duty cycle of approximately 2% to 70%.

[0025] For example, in some embodiments, plasma can be generated during consecutive "on" times and the ion energy of the plasma can be allowed to decay during consecutive "off" intervals. The "off" intervals separate consecutive "on" intervals, and the "on" and "off" intervals define a controllable duty cycle. The duty cycle limits the kinetic ion energy at the surface of the substrate to below a predetermined threshold energy. In some embodiments, the predetermined threshold energy is equal to or less than about 5 eV.

[0026] For example, during the "on" period of the pulsed RF power, the plasma energy increases, while during the "off" period, the plasma energy decreases. During the short "on" period, plasma is generated in an ion generation region 140, which loosely corresponds to the space surrounded by the coil antenna 108. The ion generation region 140 is elevated by a significant distance L above the substrate W. D The plasma generated in the ion generation region 140 near the top plate 106 during the "on" period maintains an average velocity V during the "off" period. D The electrons drift towards the substrate W. During each "off" time, the fastest electrons diffuse to the chamber wall, allowing the plasma to cool. The highest-energy electrons drift at a speed V that is faster than the plasma ion drift velocity. D The plasma diffuses to the chamber walls at a much faster rate. Therefore, during the "off" time, the plasma ion energy decreases significantly before the ions reach the substrate W. During the next "on" time, more plasma is generated in the ion generation region 140, and the entire cycle repeats itself. As a result, the energy of the plasma ions reaching the substrate W is significantly reduced. At lower chamber pressures, approximately 10 mT and below, the plasma energy in the pulsed RF case is significantly lower than that in the continuous RF case.

[0027] The "off" time of the pulsed RF power waveform and the distance L between the ion generation region 140 and the substrate W D Both must be sufficient to deplete the plasma generated in the ion generation region 140 with enough plasma energy to cause little or no ion bombardment damage or defects upon arrival at the substrate W. Specifically, the "off" time is defined by a pulse frequency between approximately 2 and 30 kHz or approximately 10 kHz and an "on" duty cycle between approximately 5% and 20%. Thus, in some embodiments, the "on" interval may last between approximately 5 microseconds and approximately 50 microseconds, or approximately 20 microseconds, while the "off" interval may last between approximately 50 microseconds and approximately 95 microseconds, or approximately 80 microseconds. The "off" time is important for allowing discharge and neutralization of charge species at wafer feature structures, so that ions can travel further without being deflected.

[0028] The generated plasma can be formed in a low-pressure process, thereby reducing the likelihood of defects caused by contamination. For example, in some embodiments, chamber 102 can be maintained at a pressure between about 2 mTorr and about 500 mTorr. Furthermore, defects such as clipping caused by ion collisions that are to be expected at such low chamber pressures of less than about 10 mTorr can be limited or prevented by using a quasi-remote plasma source and optionally by pulsed plasma source power as described above.

[0029] The substrate can be maintained at approximately room temperature (approximately 22 degrees Celsius), or at a temperature between approximately 20 degrees Celsius and 750 degrees Celsius, or below approximately 700 degrees Celsius, or below approximately 600 degrees Celsius. In some embodiments, higher temperatures may also be used, such as below approximately 800 degrees Celsius in remote plasma oxidation processes.

[0030] Figure 2 The illustration schematically depicts a substrate processing system 200 that can be used to perform aspects of the methods described herein. The substrate processing system 200 may be a rapid thermal processing (RTP) device, such as, but not limited to, an RTP device available from Applied Materials, Inc., Santa Clara, California. Other types of thermal reactors, such as the EPI available from Applied Materials in Santa Clara, California. It can replace RTP equipment. Other suitable plasma reactors can also be used, including Remote Plasma Oxidation (RPO) reactors available from Applied Materials, Inc. in Santa Clara, California.

[0031] The substrate processing system 200 includes a heat treatment chamber 202 and a precursor activator 204, the precursor activator 204 being coupled to the heat treatment chamber 202 and used to remotely provide free radicals of plasma to a processing region 206 of the heat treatment chamber 202. The precursor activator 204 can also be used to provide an activated plasma gas mixture, for example, by applying energy to the gas to generate a high radical-rich mixture with negligible ions. The processing region 206 is surrounded by one or more sidewalls 208 (e.g., four sidewalls) and a base 210. The upper portions of the sidewalls 208 may be sealed to a window assembly 212 (e.g., via an O-ring). A radiation energy assembly 214 is positioned above and coupled to the window assembly 212. The radiation energy assembly 214 has a plurality of lamps 216, which may be tungsten filament halogen lamps, each lamp being mounted in a socket 218 and positioned to emit electromagnetic radiation into the processing region 206. Figure 2The window assembly 212 has a plurality of light tubes 220, but the window assembly 212 may have only a flat, solid window without light tubes. The window assembly 212 has an outer wall 222 (e.g., a cylindrical outer wall) that forms a circumference surrounding the edge of the window assembly 212. The window assembly 212 also has a first window 224 and a second window 226, the first window 224 covering a first end of the plurality of light tubes 220 and the second window 226 covering a second end of the plurality of light tubes 220 opposite to the first end. The first window 224 and the second window 226 extend to the outer wall 222 of the window assembly 212 and engage with the outer wall 222 of the window assembly 212 to surround and seal the interior of the window assembly 212, the interior of which contains the plurality of light tubes 220. In this case, when using a light tube, a vacuum can be applied to one of the multiple light tubes 220 through a conduit 228 passing through the outer wall 222. This light tube is then fluidly connected to the remaining light tubes, thereby creating a vacuum in the multiple light tubes 220.

[0032] The substrate W is supported in the heat treatment chamber 202 by a support ring 230 within the processing region 206. The support ring 230 is mounted on a rotatable cylinder 232. Rotation of the rotatable cylinder 232 causes the support ring 230 and the substrate W to rotate during processing. The base 210 of the heat treatment chamber 202 has a reflective surface 234 for reflecting energy to the back side of the substrate W during processing. Alternatively, a separate reflector (not shown) may be provided between the base 210 of the heat treatment chamber 202 and the support ring 230. The heat treatment chamber 202 may include a plurality of temperature probes 236 disposed through the base 210 of the heat treatment chamber 202 to detect the temperature of the substrate W. In the case of using a separate reflector as described above, the temperature probes 236 are also disposed through the separate reflector for optical contact with electromagnetic radiation from the substrate W.

[0033] A rotatable cylinder 232 is supported by a magnetic rotor 238, a cylindrical member with a ledge 240, which rests on when both members are mounted in the heat treatment chamber 202. The magnetic rotor 238 has multiple magnets in a magnetic region 242 below the ledge 240. The magnetic rotor 238 is disposed in an annular well 244 along the base 210 in the surrounding area of ​​the heat treatment chamber 202. A cover 246 rests on the surrounding portion of the base 210 and extends over the annular well 244 toward the rotatable cylinder 232 and the support ring 230, leaving a tolerance gap between the cover 246 and the rotatable cylinder 232 and / or the support ring 230. The cover 246 generally protects the magnetic rotor 238 from exposure to the process environment in the treatment area 206.

[0034] The magnetic rotor 238 rotates by magnetic energy from a magnetic stator 248 disposed around the base 210. The magnetic stator 248 has a plurality of electromagnets 250, which are powered according to a rotation mode during processing of the substrate W to form a rotating magnetic field that provides magnetic energy to rotate the magnetic rotor 238. The magnetic stator 248 is coupled to a linear actuator 252 via a support 254. Operating the linear actuator 252 moves the magnetic stator 248 along an axis 256 of the heat treatment chamber 202, which in turn moves the magnetic rotor 238, the rotatable cylinder 232, the support ring 230, and the substrate W along the axis 256.

[0035] Processing gas is supplied to the heat treatment chamber 202 through chamber inlet 258 and discharged through chamber outlet oriented outside the chamber and generally along the same plane as chamber inlet 258 and support ring 230. Figure 2 (Not shown). The substrate is formed in the sidewall 208 and in Figure 2 The rear side diagram shows the entrance / exit 260 for entering and exiting the heat treatment chamber 202.

[0036] The precursor activator 204 has a body 262 surrounding an internal space 264 in which a plasma 266 of ions, radicals, and electrons can be formed. A liner 268 made of quartz or sapphire protects the body 262 from the chemical attack of the plasma. The internal space 264 is preferably free of any potential gradient that could attract charged particles (e.g., ions). A gas inlet 270 is located at a first end 272 of the body 262 and opposite a gas outlet 274 located at a second end 276 of the body 262. When the precursor activator 204 is coupled to a heat treatment chamber 202, the gas outlet 274 is in fluid communication with the heat treatment chamber 202 via a delivery line 278 to a chamber inlet 258, such that the radicals of the plasma 266 generated within the internal space 264 are supplied to the treatment area 206 of the heat treatment chamber 202. Gas outlet 274 may have a larger diameter than gas inlet 270 to allow excited free radicals to be efficiently discharged at a target flow rate and to minimize contact between free radicals and liner 268. For specific purposes, a separate orifice may be inserted into liner 268 at gas outlet 274 to reduce the internal dimensions of internal space 264 at gas outlet 274. The diameter of gas outlet 274 (or orifice, if used) may be selected to provide a pressure differential between processing zone 206 and precursor activator 204. The pressure differential may be selected to generate a composition of ions, free radicals, and molecules flowing into heat treatment chamber 202 suitable for the process performed in heat treatment chamber 202.

[0037] To provide gas for plasma processing, a first gas source 280 is coupled to a gas inlet 270 via a first input of a four-way valve 282 and a valve 284, which controls the flow rate of the gas released from the first gas source 280. A second input of the four-way valve 282 can be coupled to a second gas source 286. A third input of the four-way valve can be coupled to a third gas source 288. Each of the first gas source 280, the second gas source 286, and the third gas source 288 may be or may contain one or more of nitrogen-containing gases, oxygen-containing gases, silicon-containing gases, hydrogen-containing gases, or plasma-forming gases (e.g., argon or helium). A flow controller 290 is connected to the four-way valve 282 to switch the valve between different positions according to the process to be performed. The flow controller 290 also controls the switching of the four-way valve 282.

[0038] In some implementations, a second hydrogen source (not shown) is fluidly coupled to the heat treatment chamber 202. The second hydrogen source delivers hydrogen to the treatment zone 206, where the hydrogen is activated by a remote plasma containing oxygen and argon, delivered from the precursor activator 204 to the treatment zone 206. In some implementations targeting a high percentage of hydrogen, hydrogen may be supplied to the treatment zone 206 via both a third gas source 288 and the second hydrogen source.

[0039] In some implementations, a second argon source (not shown) is coupled to the heat treatment chamber 202. The second argon source delivers argon to the treatment region 206, where the argon is activated by a remote plasma delivered from the precursor activator 204 to the treatment region 206. In some implementations targeting a high percentage of argon, argon may be supplied to the treatment region 206 via both a second gas source 286 and the second argon source.

[0040] Figure 3 This is a process flow diagram of method 300 for forming an oxide layer in a semiconductor structure according to one or more implementations of this disclosure, wherein the semiconductor structure is, for example... Figure 4A The recessed channel array transistor (RCAT) structure 400 or any subset thereof shown in the diagram. Figure 4B , Figure 4C , Figure 4D and Figure 4E This is a cross-sectional view of a portion of the RCAT structure 400 corresponding to each stage of method 300. The RCAT structure 400 can be used in dynamic random access memory (DRAM) devices. Additionally, method 300 can be used to form RCAT structures with different configurations or other semiconductor devices requiring high-quality thin oxide layers, such as nanowires. Furthermore, it should be understood that... Figure 3 The operations described in the text can be performed simultaneously and / or with... Figure 3The different sequences of execution are described in the text.

[0041] The RCAT structure 400 may include a substrate 402 having an isolation layer pattern 404 formed thereon. In some implementations, the substrate 402 may have a substantially flat surface, a non-flat surface, or a substantially flat surface on which a structure is formed. The substrate 402 may be, for example, crystalline silicon (e.g., Si). <100> or Si <111> Materials include, but are not limited to, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 402 can have various shapes and sizes, such as wafers with a diameter of 200 mm or 300 mm and rectangular or square panels. Unless otherwise stated, many implementations and examples described herein refer to a substrate with a diameter of 300 mm. In some implementations, the substrate 402 can be a crystalline silicon substrate (e.g., monocrystalline or polycrystalline silicon).

[0042] An isolation layer pattern 404 defines an active region 402A of a substrate 402. The isolation layer pattern 404 can be formed by a shallow trench isolation process. One or more trenches 406 are formed on the upper surface of the active region 402A. The trenches 406 may have a width between about 15 nm and about 60 nm, and a depth between about 200 nm and about 400 nm, thus having an aspect ratio between about 8:1 and about 10:1.

[0043] A gate oxide layer 408 is formed on the upper surface of the substrate 402 and the inner surface of the trench 406. A gate electrode 410 is formed on the gate oxide layer 408. Source / drain regions 412 are formed on both sides of the gate electrode 410 by an impurity ion implantation process. The source / drain regions 412 are electrically isolated from the gate electrode 410 through the gate oxide layer 408.

[0044] In the conventional method of forming the gate oxide layer 408 by thermal oxidation of silicon in substrate 402 into silicon oxide, the oxidation reaction at the bottom 406A of trench 406 may be weakened due to stress, and therefore the thickness of the gate oxide layer 408 on the bottom 406A of trench 406 may be less than the thickness of the gate oxide layer 408 on the sidewall 406B of trench 406. Consequently, the leakage current flowing through the bottom 406A of trench 406 may increase. This thinning of the gate oxide layer 408 (referred to as "geometric thinning") can be overcome by a direct plasma oxidation process, in which plasma ions are guided to the bottom 406A of trench 406, thereby increasing the inflow of oxidant.

[0045] Furthermore, the thickness of the gate oxide layer 408 formed by thermal oxidation and direct plasma oxidation processes can be between approximately 4 nm and approximately 8 nm, for example, approximately 6 nm (i.e., the width of the trench 406 is reduced by approximately 12 nm), and it may not be thinner than approximately 4 nm due to direct tunneling gate leakage. Additionally, some silicon may be lost at the edges of the trench 406, thus forming undesirable contacts in the RCAT structure 400 and reducing device reliability. In smaller-size feature structures with high aspect ratios and high device density, such as modern 14 / 10 / 7 nm nodes, a thinner gate oxide layer 408 with a width between approximately 6 nm and approximately 7 nm is required to avoid leakage current.

[0046] In another conventional method, where silicon oxide is deposited using an ALD or CVD process with vapor-phase silicon-containing and oxygen-containing precursors to form the gate oxide layer 408, the thickness of the gate oxide layer 408 can be reduced to approximately [missing information]. With the agreement Between, for example, about Furthermore, due to the conformal deposition capability of materials in ALD or CVD processes, geometric thinning of the gate oxide layer 408 at the bottom 406A of trench 406 may not occur. However, the deposited silicon oxide may contain stoichiometric and structural defects (due to interruptions in the tetrahedral crystal structure of silicon oxide formed by ALD or CVD processes), approximately from the interface with substrate 402. With the agreement Boundary traps at the distance between them, and interface traps at the interface (e.g., approximately at the distance from the interface). This leads to a decrease in the device reliability of the RCAT structure 400. The deposited silicon oxide can be treated with direct plasma oxidation and / or post-annealing processes to reduce defects in the deposited silicon oxide. However, this treatment only applies to the top surface of the deposited silicon oxide to approximately [missing information]. With the agreement The depth between them is effective, so it may not significantly improve device reliability.

[0047] In several embodiments described herein, a gate oxide layer 408 is formed by first depositing an amorphous silicon layer on a substrate 402, and then oxidizing the deposited amorphous silicon using a direct plasma oxidation process and a thermal oxidation process. The method 300 described herein includes the deposition of amorphous silicon, which provides a sacrificial Si source for thermal oxidation growth and increases the average distance between adjacent devices. Therefore, silicon consumption for forming the gate oxide layer 408 can be reduced. Furthermore, method 300 does not involve the deposition of silicon oxide, thus the formed gate oxide layer 408 is free of defects and traps.

[0048] Method 300 begins at frame 310, where an interface layer 414 is formed on the exposed surface of substrate 402 to fill or at least partially fill trench 406, such as Figure 4B As shown. The interface layer 414 can be formed of silicon dioxide (SiO2) and has a properties between approximately With the agreement The thickness between, for example, is approximately This corresponds to a monolayer of one or more silicon oxides grown by thermal oxidation. The interface layer 414 prevents the deposited silicon from crystallizing in subsequent steps of method 300, thus forming amorphous silicon.

[0049] In frame 320, amorphous silicon, such as hydrogenated amorphous silicon (a-Si:H), is conformally deposited on interface layer 414 by an ALD or CVD process, wherein a substrate 401 having interface layer 414 formed thereon is exposed to a silicon precursor. Figure 4C As shown, an amorphous silicon layer 416 is conformally formed on the interface layer 414. Due to the nature of the ALD or CVD process, the thickness of the amorphous silicon layer 416 at the bottom 406A of the trench 406 is substantially the same as its thickness on the sidewall 406B of the trench 406. The thickness of the amorphous silicon layer 416 can be approximately... With the agreement between.

[0050] Suitable silicon precursors include, but are not limited to, polysilanes (Si... x H y For example, polysilanes include disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H6). 10 ), isotetrasilane, neoopentasilane (Si5H) 12 ), cyclopentasilane (Si5H) 10 hexasilane (C6H) 14 ), cyclohexane (Si6H) 12 ) or usually Si x H y And x = 2 or more, and the combinations mentioned above.

[0051] In box 330, through the processing system (e.g.) Figure 1The direct plasma oxidation process in the substrate processing system 100 (shown) oxidizes the amorphous silicon layer 416 to form a first oxide layer 418 of thickness on the bottom 406A of the trench 406. In the direct plasma oxidation process, oxygen plasma ions are directed to the bottom 406A of the trench 406, therefore the oxidation of the amorphous silicon layer 416 preferentially occurs before the bottom 406A of the trench 406, as... Figure 4D As shown. In some embodiments, the direct plasma oxidation process may use oxidants comprising oxygen (O2), nitric oxide (NO), nitrous oxide (N2O), or similar substances. These may be used alone or in combination. Furthermore, the direct plasma oxidation process may use source gases for generating plasma, comprising, among others, helium (He), argon (Ar), and / or xenon (Xe). These may be used alone or in combination. In some embodiments, the direct plasma oxidation process may allow the oxidation reaction to be carried out at temperatures above about 400°C to ensure high quality of silicon oxide. In some embodiments, oxygen plasma ions may be directed to another selected portion of substrate 402 to selectively thicken the first oxide layer 418 at the selected portion of substrate 402.

[0052] In several embodiments, the direct plasma oxidation process can be performed at a pressure between approximately 5 mTorr and approximately 100 mTorr. The pressure can control the inflow of oxidant introduced into trench 406. Specifically, the inflow of oxidant to the bottom 406A of trench 406 can be reduced proportionally to the pressure drop during the direct plasma oxidation process. Oxidant inflow to the bottom 406A of trench 406 can also be controlled by applying a bias voltage during the direct plasma oxidation process. Therefore, the thickness of the first oxide layer 418 at the bottom 406A of trench 406 can be controlled and adjusted as needed.

[0053] In some embodiments, the first oxide layer 418 consumes an amorphous silicon layer 416 to a depth of about 2 nm to about 6 nm, for example, about 4 nm, on the bottom 406A of the trench 406, and consumes an amorphous silicon layer 416 to a depth of about 1 nm to about 3 nm on the sidewall 406B of the trench 406.

[0054] In frame 340, the remaining portion 416A of the amorphous silicon layer 416 on the sidewall 406B of trench 406 is oxidized by a thermal oxidation process in a processing system such as substrate processing system 200. The thermal oxidation process can be performed using thermal radical oxidation with a 10 Torr low-pressure H2+O2 combustion process or a plasma source (e.g., a remote plasma source of the precursor activator 204 in substrate processing system 200) to provide oxygen radicals (O*). In the thermal oxidation process, oxidation of the amorphous silicon layer 416 occurs preferentially over the sidewall 406B of trench 406; therefore, the combination of the direct plasma oxidation process in frame 340 and the thermal oxidation process in frame 350 results in the gate oxide layer 408 having the same thickness on the bottom 406A of trench 406 as it does on the sidewall 406B of trench 406.

[0055] In some embodiments, the heat treatment process can be performed at a temperature higher than that of the direct plasma oxidation process. For example, the heat treatment process can be performed at a temperature between about 700°C and about 1050°C.

[0056] In the various embodiments described herein, the RCAT structure 400 with trench 406 (i.e., concave) serves as an example structure that can benefit from the method 300 for forming a high-quality thin oxide layer. Method 300 can also be used, for example, in thin nanowire field-effect transistors (FETs) to form a high-quality thin oxide layer in a structure having convex feature structures (e.g., protrusions) or flat feature structures. In this case, geometric thinning of the oxide layer may not occur, thus allowing the formation of a high-quality thin oxide layer without the direct plasma oxidation process in box 330.

[0057] In several embodiments described herein, methods are provided for forming high-quality thin oxide layers in semiconductor devices, such as recessed channel array transistors (RCATs) used in dynamic random access memory (DRAM) devices, and thin nanowire field-effect transistors (FETs). In the methods described herein, the thin oxide layer can be formed by first depositing amorphous silicon on a substrate and then oxidizing the amorphous silicon using direct plasma oxidation and thermal oxidation processes. The methods described herein for forming oxide layers reduce silicon consumption and improve the quality of the formed oxide layer. The methods described herein also provide the ability to adjust the thickness of the oxide layer in selected portions of the substrate.

[0058] Although the foregoing describes several embodiments of this disclosure, many other and further embodiments of this disclosure may be designed without departing from the basic scope of this disclosure, and the scope of this disclosure is determined by the appended claims.

Claims

1. A method for forming an oxide layer, comprising the following steps: An interface layer is formed on the substrate; An amorphous silicon layer is formed on the interface layer; A direct plasma oxidation process is performed to selectively oxidize only a portion of the formed amorphous silicon layer; and A thermal oxidation process is performed to oxidize the remaining unoxidized portion of the formed amorphous silicon layer.

2. The method of claim 1, wherein The substrate comprises crystalline silicon, and The substrate includes several concave feature structures, and the oxide layer is formed within the several concave feature structures.

3. The method of claim 1, wherein the interface layer comprises silicon oxide and has a thickness between 2 Å and 20 Å.

4. The method of claim 1, wherein the step of forming the amorphous silicon layer comprises the steps of: The substrate is exposed to silicon precursors in an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

5. The method of claim 1, wherein the amorphous silicon layer has a thickness between 10 Å and 50 Å.

6. The method of claim 1, wherein the direct plasma oxidation process comprises the following steps: Oxygen plasma ions are directed to selected portions of the substrate.

7. The method of claim 1, wherein the thermal oxidation process comprises the following steps: This exposes the substrate to oxygen free radicals.

8. A method for forming an oxide layer, comprising the following steps: An amorphous silicon layer is formed on the substrate; Perform a direct plasma oxidation process to selectively oxidize only a portion of the formed amorphous silicon layer; and A thermal oxidation process is performed by directly exposing the formed amorphous silicon layer to oxygen free radicals to oxidize the remaining unoxidized portion of the formed amorphous silicon layer.

9. The method of claim 8, wherein the substrate comprises crystalline silicon.

10. The method of claim 8, further comprising the following steps: An interface layer is formed on the substrate, wherein the interface layer comprises silicon oxide and has a thickness between 2 Å and 20 Å.

11. The method of claim 8, wherein the step of forming the amorphous silicon layer comprises the following steps: The substrate is exposed to silicon precursors in an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

12. The method of claim 8, wherein the amorphous silicon layer has a thickness between 20 Å and 50 Å.

13. The method of claim 8, wherein the thermal oxidation process includes exposing the substrate to oxygen free radicals.

14. The method of claim 8, wherein the direct plasma oxidation process comprises the following steps: Oxygen plasma ions are directed to selected portions of the substrate.

15. A method for forming an oxide layer, comprising the following steps: An amorphous silicon layer is formed on the silicon substrate by exposing the silicon substrate to a silicon precursor in an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. Perform a direct plasma oxidation process to selectively oxidize only a portion of the formed amorphous silicon layer; and A thermal oxidation process is performed by directly exposing the formed amorphous silicon layer to oxygen free radicals to oxidize the remaining unoxidized portion of the formed amorphous silicon layer to form an oxide layer on the silicon substrate.

16. The method of claim 15, further comprising the following steps: Prior to the step of forming the amorphous silicon layer on the silicon substrate, an interface layer is formed on the silicon substrate.

17. The method of claim 16, wherein the interface layer comprises silicon oxide and has a thickness between 2 Å and 20 Å.

18. The method of claim 15, wherein the amorphous silicon layer has a thickness between 10 Å and 40 Å.

19. The method of claim 15, wherein the thermal oxidation process comprises the following steps: This exposes the silicon substrate to oxygen free radicals.

20. The method of claim 15, wherein the direct plasma oxidation process comprises the following steps: Oxygen plasma ions are directed to selected portions of the silicon substrate.

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