Circuit board engineering drawing tin point marking method and device thereof

Abstract

The application discloses a method for marking tin points on a circuit board engineering drawing, which comprises the following steps: obtaining circuit board data and a circuit board engineering drawing, wherein the circuit board data comprises part names, and the circuit board engineering drawing comprises a tin coating area; searching for first opening coordinates according to the part names; converting the first opening coordinates into second opening coordinates corresponding to the circuit board engineering drawing by using a conversion matrix; and displaying the second opening coordinates in a pattern with warning features when the second opening coordinates fall into the tin coating area.

Description

Technical Field

[0001] This invention relates to the technical field of circuit board engineering drawing marking, and in particular to a method and apparatus for marking solder points on circuit board engineering drawings to determine whether the coordinates of openings fall within the soldering area. Background Technology

[0002] AutoCAD is a drafting software developed by Autodesk, Inc. in the United States for the application of computer-aided design technology on computers. It is now widely used in industrial design, and its file format ".dwg" has become a commonly used standard format for drafting.

[0003] When AutoCAD is used for circuit layout, for example, the circuit may be designed with multiple layers, such as solder mask, stencil, and text layers. The circuit board includes solder joint locations and via locations. The via locations correspond to the opening locations on the stencil. The via locations provide a place for dual in-line package (DIP) components to be inserted. After the DIP component is inserted into the via location, the stencil is then attached to the circuit board, and the DIP component is soldered. Surface mounted devices (SMDs) are attached to the solder joint locations and then heated. If an engineer makes an error in creating the circuit board schematic based on the layers, that is, if the engineer creates an incorrect solder layer in the bill of materials (BOM), the positions where holes should be in the circuit board schematic will be filled with solder dots. During the surface mount technology (SMT) stage, solder will be applied to the hole positions on the stencil layer. The through-hole positions will be filled with solder, making it impossible to insert dual in-line package (DIP) components. The original solder dot positions will be without solder, causing surface mount components and DIP components to be unable to be placed in the correct positions. This will interrupt the subsequent circuit board manufacturing process and affect the circuit board production process. Summary of the Invention

[0004] Based on the foregoing, the present invention provides a method and apparatus for marking solder joints in circuit board engineering drawings to solve the problem of circuit board process interruption caused by incorrect circuit board engineering drawings.

[0005] A method for marking solder joints on a circuit board drawing according to an embodiment of the present invention includes: obtaining circuit board data and a circuit board drawing, wherein the circuit board data includes component names and the circuit board drawing includes solderable areas; finding the coordinates of a first opening based on the component names; converting the coordinates of the first opening into the coordinates of a second opening in the corresponding circuit board drawing using a transformation matrix; and displaying the coordinates of the second opening in a pattern with warning features when the coordinates of the second opening fall into the solderable area.

[0006] A circuit board schematic solder joint marking device according to an embodiment of the present invention includes a memory, a processor, and a screen. The memory stores circuit board data and a circuit board schematic; the circuit board data includes component names, and the circuit board schematic includes solderable areas. The processor is coupled to the memory. The processor locates the coordinates of a first aperture based on the component names and uses a transformation matrix to convert the first aperture coordinates into the coordinates of a second aperture corresponding to the circuit board schematic. The screen is coupled to the processor. When the processor determines that the second aperture coordinates fall within the solderable area, the screen displays a pattern with a warning feature at the second aperture coordinates.

[0007] In summary, the circuit board drawing solder dot marking method and apparatus of the present invention finds the first hole coordinates based on the circuit board data, and uses a transformation matrix to convert the first hole coordinates into second hole coordinates. It then determines whether the second hole coordinates fall within the soldering area of ​​the circuit board drawing, thereby determining whether there are errors in the hole and soldering area of ​​the circuit board drawing. This allows engineers to correct erroneous circuit board drawings in a timely manner, thus avoiding circuit board process interruptions caused by erroneous circuit board drawings.

[0008] The foregoing description of the disclosure and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide a further explanation of the scope of the patent application of the present invention. Attached Figure Description

[0009] Figure 1 This is a system block diagram of a circuit board drawing solder dot marking device according to an embodiment of the present invention.

[0010] Figure 2 This is a flowchart of one embodiment of the circuit board engineering drawing solder dot marking method of the present invention.

[0011] Figure 3 This is a schematic diagram of a candidate part of one embodiment of the present invention.

[0012] Figure 4 This is a circuit board engineering diagram of one embodiment of the present invention.

[0013] In the attached figures, the following labels are used:

[0014] 10: Memory

[0015] 20: Processor

[0016] 30: Screen

[0017] B: Circuit board

[0018] CD1: Coordinates of the candidate part

[0019] CP1~CP4: Candidate Part Names

[0020] D: Circuit board engineering drawing

[0021] D': Engineering drawing already marked

[0022] DD: Dual In-line Package (DIC) component

[0023] H1, H2: Openings

[0024] I: Circuit Board Data

[0025] P1: Coordinates of the first opening

[0026] P2: Coordinates of the second opening

[0027] PD1, PD2: Coordinates of the candidate first aperture

[0028] PI1, PI2: Pins

[0029] S11~S19: Steps

[0030] TB: Shangxi area

[0031] TE1~TE4: Candidate package names

[0032] W1: Prompt Pattern

[0033] W2: Warning Features Detailed Implementation

[0034] The following detailed description of the features and advantages of the present invention in the embodiments is sufficient to enable anyone skilled in the art to understand the technical content of the present invention and implement it accordingly. Based on the disclosure, patent claims, and drawings in this specification, anyone skilled in the art can easily understand the related objectives and advantages of the present invention. The following embodiments are further detailed in illustrating the points of view of the present invention, but are not intended to limit the scope of the present invention in any way.

[0035] It should be understood that although the terms "first," "second," etc., may be used in this invention to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or portion from another element, component, region, layer, and / or portion.

[0036] Additionally, the terms "comprising" and / or "including" refer to the presence of the stated features, areas, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components, and / or combinations thereof.

[0037] Please see Figure 1This is a system block diagram of the circuit board drawing solder dot marking device of the present invention in one embodiment. Figure 1 As shown, the circuit board drawing solder joint device of the present invention includes a memory 10, a processor 20, and a screen 30. The memory 10 stores circuit board data I, circuit board drawing D, and drawing software, such as AutoCAD. The processor 20 is coupled to the memory 10. The processor 20 obtains a first aperture coordinate P1 based on the circuit board data I. The processor 20 uses a transformation matrix to convert the first aperture coordinate P1 into a second aperture coordinate P2 corresponding to the circuit board drawing D. The processor 20 marks the second aperture coordinate P2 on the circuit board drawing D to form a marked drawing D'. The screen 30 displays the marked drawing D'. Details of obtaining the first aperture coordinate P1 will be described later.

[0038] The memory 10 can be flash memory, hard disk drive (HDD), solid-state drive (SSD), dynamic random access memory (DRAM), static random access memory (SRAM), or other non-volatile memory. The processor 20 can be a central processing unit, a programmable logic controller, or other processor. The screen 30 can be an organic light-emitting diode display, a micro light-emitting diode display, or a light-emitting diode display. The aforementioned components of the memory 10, processor 20, and screen 30 are merely examples and are not limited to the scope stated in this invention.

[0039] Please see Figure 2 This is a flowchart of an embodiment of the circuit board engineering drawing solder dot marking method of the present invention. Figure 2 As shown, the combination Figure 1 Taking AutoCAD drawing software as an example, the circuit board engineering drawing solder point marking method of the present invention includes steps S11 to S19.

[0040] Step S11: Obtain circuit board data I and circuit board drawing D using the circuit board drawing solder joint device. Circuit board data I includes component names. In one embodiment, the file format of the circuit board data is the corresponding software AutoCAD. Circuit board data I includes a first part and a second part. The first part may include multiple sets of first combinations, which may respectively include candidate component names, candidate package names, and candidate component coordinates. The second part may include multiple sets of second combinations and other layers (which may be text layers, solder layers), which may respectively include candidate package names and candidate first aperture coordinates. Please refer to [further details to be added]. Figure 3As shown, the candidate part name can be, for example, the part name CP1 corresponding to the dual in-line package (DIP) part DD. The candidate part coordinates CD1 can be, for example, the position of the DIP part DD on the circuit board B. The candidate first aperture coordinates PD1 and PD2 are the positions of the apertures H1 and H2 on the circuit board B where the pins PI1 and PI2 of the DIP part DD are inserted. The candidate package name TE1 can be a conjunction used to connect multiple first combinations and multiple second combinations. For example, if the candidate part is a capacitor and the candidate part name is CP1, assuming the shape of the circuit board B is rectangular and the origin (0,0) is set at one vertex of the rectangle, the candidate part coordinates CD1 are (11,13), the candidate package name is TE1, and the candidate first aperture coordinates PD1 and PD2 are (10,12) and (12,12), and both the first combination and the second combination have a candidate package name TE1, the processor can find the TE1 of the second combination based on the candidate package name of the first combination's TE1, and thus obtain the candidate first aperture coordinates PD1 and PD2. The coordinates of the candidate part CD1 and the coordinates of the candidate first opening PD1 and PD2 will change depending on the setting of the origin. The description of the candidate part coordinates and the candidate first opening coordinates PD1 and PD2 is only to enable those with ordinary knowledge in the relevant technical field to understand the difference between the two and is not intended to limit them.

[0041] Because of the numerous components on circuit board B, the data file for circuit board I is enormous. In this embodiment, both the first and second parts contain package names. The processor 20 uses the package name to find the corresponding first aperture coordinates, thus shortening the time required to find the first aperture coordinates.

[0042] In the above embodiments, the data within the circuit board data I is divided into a first part and a second part, but this is not intended to limit the present invention, and the data types included in the first part and the second part are also not intended to limit the present invention. In other embodiments, the circuit board data I may not need to be divided into a first part and a second part, and it may only include multiple candidate part names, multiple candidate part coordinates, and multiple candidate aperture coordinates. Each candidate part name has one candidate part coordinate and multiple aperture coordinates corresponding to the candidate part name, and the processor 20 can find multiple aperture coordinates based on a single part name.

[0043] The circuit board data I and circuit board schematic D can be pre-stored in memory 10, or they can be imported from an external source (e.g., a USB flash drive or cloud platform) by production line personnel. Circuit board schematic D is a schematic created by engineers based on circuit board data I, ensuring that circuit board data I is correct. Circuit board schematic D includes multiple soldering areas TB (please refer to [reference needed]). Figure 4And multiple circuit wirings, each soldering area TB can be the location where surface mount components are to be placed, the area of ​​each soldering area TB is adjusted according to the size of the surface mount components, and the areas of multiple soldering areas TB can be the same or different from each other.

[0044] Step S12: The processor 20 reads the circuit board data I. Specifically, the processor 20 can open the circuit board data I using the drawing software AutoCAD. When reading the circuit board data, the processor 20 obtains the name of each candidate component, the coordinates of each candidate component, the name of each candidate package, and the coordinates of each candidate first aperture. The processor 20 uses the method of reading the circuit board data I to determine whether the circuit board data I is damaged or whether the file format of the circuit board data I is incorrect. If the circuit board data I is damaged or the file format of the circuit board data I is incorrect, the processor 20 cannot open the circuit board data I using the drawing software AutoCAD; if the circuit board data I is not damaged or the file format of the circuit board data I is correct, the processor 20 successfully opens the circuit board data I using the drawing software AutoCAD.

[0045] Step S13: The processor 20 searches for a first combination of part names from the first part based on the part name, and obtains a candidate package name for the corresponding part name from the corresponding first combination. Specifically, the part name can be the name corresponding to the part to be searched. The processor 20 searches from these first combinations based on the part name, and compares the part name with the candidate part names in each first combination to find the first combination of the corresponding part name. For example, if the part is a capacitor and the part name is CP1, these first combinations include 4 sets of candidate part names / candidate package names / candidate part coordinates, which are CP1 / TE1 / (16,25), CP2 / TE2 / (16,24), CP3 / TE3 / (16,40), and CP4 / TE4 / (15,24). The processor 20 selects the first combination containing CP1 / TE1 / (16,25) based on CP1, and the processor 20 uses TE1 as the candidate package name for the corresponding part name.

[0046] Step S14: Starting from the second part, the processor 20 searches for the second combination of corresponding part names based on the candidate package names. The processor 20 obtains the candidate first aperture coordinates as the first aperture coordinates P1 from the second combination of corresponding part names. In detail, the processor 20 has obtained the candidate package names from the first combination of corresponding part names. Since there is no second combination in the first part, the processor 20 starts searching from the second part and finds the second combination of corresponding part names based on the candidate package names. The processor 20 obtains the first aperture coordinates P1 from the second combination of corresponding part names. For example, the part name is CP1. The processor 20 has obtained the candidate package name TE1 from the first combination of CP1. These second combinations include 5 sets of candidate package names / candidate first aperture coordinates, namely TE1 / (10,12)(12,12), TE2 / (7,10)(12,16), TE3 / (10,18)(12,14), and TE4 / (10,15)(12,18). The processor 20 selects the second combination including TE1 / (10,12)(12,12) in the second part according to TE1. The processor 20 obtains the candidate first aperture coordinates (10,12) and (12,12) from the second combination of TE1 / (10,12)(12,12). The processor 20 uses the candidate first aperture coordinates (10,12) and (12,12) as the two first aperture coordinates P1. It should be mentioned that, depending on the part type corresponding to the part name, there can be multiple first aperture coordinates P1 corresponding to the part name; in other words, the processor 20 finds the corresponding first combination based on the part name to obtain the candidate package name, and then the processor 20 finds the corresponding second combination based on the package name of the first combination to obtain multiple first aperture coordinates P1.

[0047] Step S15: The processor 20 uses a transformation matrix to convert the first hole coordinates P1 into the corresponding second hole coordinates P2 of the circuit board drawing D. Specifically, the processor 10 uses the transformation matrix to execute a transformation program on the first hole coordinates P1 to generate the corresponding second hole coordinates P2 of the circuit board data D. Since the number of first hole coordinates P1 is determined according to the part type corresponding to the part name, the number of second hole coordinates P2 is also multiple. For example, two first hole coordinates are (10,12) and (12,12), and two second hole coordinates are (50,30) and (40,30). It should be noted that the coordinate system of the multiple candidate first hole coordinates is the coordinate system of the corresponding AutoCAD software, while the coordinate system of the circuit board drawing D is not the coordinate system of the AutoCAD software. The origin of the AutoCAD software coordinate system does not correspond to the origin of the circuit board drawing, and the first hole coordinates provided by the AutoCAD software are not the hole positions of the circuit board drawing. Therefore, the processor 20 needs to transform the coordinate system of the first hole coordinate P1 to the coordinate system of the circuit board drawing D. The processor 20 uses a transformation matrix to map the first hole coordinate P1 to the circuit board drawing D, and then generates the corresponding second hole coordinate P2. The transformation matrix can be built into the AutoCAD software. The transformation matrix adjusts the scale of the second hole coordinate P2 according to the image size of the circuit board drawing D.

[0048] Step S16: The processor 20 marks the second hole coordinate P2 on the circuit board drawing D. It should be noted that since there are multiple second hole coordinates P2 corresponding to a single part name, the processor 20 marks multiple second hole coordinates P2 on the circuit board drawing D, thereby forming a marked drawing D', and the screen 30 will display the marked drawing D'.

[0049] Step S17: The processor 20 determines whether the coordinates P2 of the second aperture fall within the soldering area TB. Specifically, as follows... Figure 4 As shown, the processor 20 first finds the soldering region TB adjacent to the second aperture coordinate P2. The processor 20 compares multiple soldering coordinates of the adjacent soldering region TB with the single second aperture coordinate P2. The processor 20 compares each soldering coordinate with the single second aperture coordinate P2 one by one (other second aperture coordinates P2 are also compared with each of their adjacent soldering coordinates). At this time, as shown... Figure 4A prompt pattern W1 is displayed on the screen 30, indicating that the processor 20 is comparing the second aperture coordinate P2 with multiple solder coordinates of the solder area TB. The prompt pattern W1 can be a yellow circle or other colors and shapes. If the processor 20 determines that the second aperture coordinate P2 overlaps with one of the multiple solder coordinates, is located between two adjacent solder coordinates, or is located at the boundary of the solder area TB, that is, the processor 20 determines that the second aperture coordinate P2 is located within the adjacent solder area TB, the processor 20 proceeds to step S18; if the processor 20 determines that the second aperture coordinate P2 does not overlap with one of the multiple solder coordinates or is located outside the boundary of the solder area TB, that is, the processor 20 determines that the second aperture coordinate P2 is not located within the adjacent solder area TB, the processor 20 proceeds to step S19.

[0050] Step S18: Display a pattern with warning feature W2 on screen 30 at the second opening coordinate P2. Specifically, based on the judgment of processor 20, screen 30... Figure 4 The diagram shows a pattern with warning feature W2 at the second aperture coordinate P2, displaying a warning message. Warning feature W2 can be presented using color or shape. The warning message reads, "Caution: Please confirm whether this component has an aperture during surface mounted technology (SMT)." This means that the soldered area TB overlaps with the second aperture coordinate P2, and the component corresponding to the soldered area TB may not be an SMT component, thus affecting the subsequent manufacturing of DIP components. The engineer's circuit board drawing D is incorrect, and the engineer needs to review and revise the circuit board drawing. For example, the pattern of warning feature W2 could be a green circle with the soldered area TB in gray, or the pattern of warning feature W2 could be a red rectangle with the soldered area TB in black.

[0051] Step S19: Display a prompt message on screen 30. Specifically, the prompt message displayed on screen 30 may be "Check complete", meaning that the processor 20 has compared the multiple soldering coordinates and multiple second hole coordinates P2 of a single soldering area TB, and confirmed that there are no holes set in this soldering area TB. The circuit board engineering drawing D designed by the engineer is correct, and the engineer can hand over the circuit board engineering drawing D to the production line personnel for subsequent processes.

[0052] In summary, the circuit board drawing solder dot marking method and apparatus of the present invention finds the first hole coordinate P1 according to the circuit board data I, and uses a transformation matrix to convert the first hole coordinate P1 into the second hole coordinate P2. It then determines whether the second hole coordinate P2 falls into the soldering area TB of the circuit board drawing, thereby determining whether the hole and soldering area TB of the circuit board drawing D are incorrect, so that the engineer can correct the incorrect circuit board drawing D in time to avoid circuit board process interruption problems caused by the incorrect circuit board drawing.

[0053] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Any modifications and refinements made without departing from the spirit and scope of the invention are within the scope of patent protection of the present invention. For details regarding the scope of protection defined in the present invention, please refer to the appended claims.

Claims

1. A method for marking solder joints on a circuit board engineering drawing, characterized in that, include: Obtain circuit board data and circuit board engineering drawing, wherein the circuit board data includes a component name and the circuit board engineering drawing includes a soldering area. Based on the part name, locate the coordinates of the first opening; Using a transformation matrix, the coordinates of the first aperture are converted into the coordinates of a second aperture corresponding to the circuit board drawing; and When the coordinates of the second opening fall into the tinning area, the coordinates of the second opening are displayed in a pattern with a warning feature.

2. The circuit board engineering drawing solder joint marking method as described in claim 1, characterized in that, The circuit board data includes a first part and a second part. The first part includes multiple first combinations, each including a candidate component name and a candidate package name. The second part includes multiple second combinations, each including the candidate package name and candidate first aperture coordinates. Finding the first aperture coordinates includes: Based on the part name, locate one of the first combinations where the part name matches the candidate part name of the located first combination, and extract the candidate package name from the first combination corresponding to the part name; and Based on the candidate package name corresponding to the part name, find the second group corresponding to the part name, and use the candidate first opening coordinates in the second group corresponding to the part name as the first opening coordinates.

3. The circuit board engineering drawing solder joint marking method as described in claim 2, characterized in that, After finding the first combination that corresponds to the part name, start searching for the second combination that corresponds to the part name from the second part.

4. The circuit board engineering drawing solder joint marking method as described in claim 1, characterized in that, The warning feature can be either color or shape.

5. The circuit board engineering drawing solder joint marking method as described in claim 1, characterized in that, If the coordinates of the second opening do not fall within the tinning area, a prompt message will be displayed.

6. A circuit board drawing solder joint marking device, characterized in that, include: A memory that stores circuit board data and a circuit board schematic, the circuit board data including a component name and the circuit board schematic including a solderable area. A processor, coupled to the memory, finds a first aperture coordinate based on the part name, and uses a transformation matrix to convert the first aperture coordinate into a second aperture coordinate corresponding to the circuit board drawing. as well as A screen, coupled to the processor; When the processor determines that the coordinates of the second opening fall within the soldering area, the screen displays a pattern with a warning feature at the coordinates of the second opening.

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