A picosecond equivalent sampling method for time domain reflectometry soil moisture measurement

Abstract

The present invention discloses a method for achieving picosecond equivalent sampling in time domain reflection measurement of soil moisture content. First, two independent temperature-compensated crystal oscillators with a frequency error of 0.5 ppm are selected, the crystal oscillators are powered by a low-noise drive circuit, and a low-pass filter is added to the front end of the crystal oscillator output clock signal to reduce the crystal oscillator clock jitter; secondly, a high-frequency pulse signal is generated, a 30MHz temperature-compensated crystal oscillator is used as the DDS system clock, and the frequency control word of the DDS is controlled by FPGA to adjust the output signal frequency to 10.001MHz; then, a 50MHz temperature-compensated crystal oscillator is used as the FPGA system clock, and the FPGA internal phase-locked loop is used to output 10MHz as a low-speed ADC sampling clock signal; finally, the time difference between the sampling signal and the signal to be sampled is 10ps, and sampling is performed once per cycle of the signal to be sampled. After several cycles, a complete cycle of the original signal can be collected. This method uses two independent temperature-compensated crystal oscillators to maintain a small frequency difference between the sampling signal and the clock frequency of the signal to be sampled, thereby achieving an equivalent sampling rate of 100GSPS.

Description

Technical Field

[0001] The present invention belongs to the field of soil parameter detection, and in particular relates to a method for realizing picosecond equivalent sampling in time domain reflectometry measurement of soil moisture content. Background Art

[0002] Soil water is a vital component of the soil and has a significant impact on the healthy growth of crops. Excessive soil moisture can easily cause crop root decay and rot, leading to abnormal growth and even death. Low soil moisture, resulting in drought and water shortages, prevents crops from photosynthesizing properly, impacting yield and quality. Therefore, rapid and accurate measurement of soil moisture content provides a comprehensive understanding of soil moisture trends and distribution patterns. Time-domain reflectometry (TDRM) is used for soil moisture measurement due to its rapidity, accuracy, and robustness. Sampling picosecond-level reflection signals is crucial for accurate TDR soil moisture measurements.

[0003] Because the rising edge of the reflected signal required to measure soil moisture using the time domain reflectometry method is generally in the order of picoseconds, ADC chips cannot meet the requirements of high real-time sampling rates while meeting the analog bandwidth requirements. Equivalent sampling is a sampling method that samples a periodic signal multiple times at different signal periods and concatenates the sampled data to reconstruct the signal waveform. Existing equivalent sampling methods include using an FPGA to control the generation of the sampling signal, but requiring the sampling signal to be synchronized with the signal to be sampled in terms of rise and fall time, phase, and amplitude; using an FPGA phase-locked loop and counter to achieve step delay, but requiring strict timing requirements between the pulse signal generator and the sampling signal; and using a specific delay chip to achieve step delay. These methods all require a step delay system or require the sampling signal to be synchronized with the clock signal, which increases the complexity of the equivalent sampling system. Summary of the Invention

[0004] To solve the above problems, the present invention discloses a method for realizing picosecond equivalent sampling in time-domain reflection measurement of soil moisture content, which solves the problem that real-time sampling cannot meet the sampling rate requirements. There is no need to synchronize the sampling clock signal with the clock signal to be sampled, nor is there a need for a specific delay chip to realize step delay, thereby reducing the complexity of the equivalent sampling system.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A method for achieving picosecond equivalent sampling in time domain reflectometry soil moisture measurement includes the following steps:

[0007] Step S1: Design two stable crystal oscillator circuits, with 50 MHz as the sampling signal clock source and 30 MHz as the input signal clock source. The clock source frequency error does not exceed ±0.5 ppm.

[0008] Step S2: The 30MHz crystal oscillator outputs a clock signal as the system clock of the DDS. The FPGA is used to write a frequency control word into the DDS register to adjust the signal frequency to 10.001MHz. The high-speed comparator performs edge shaping on the signal to obtain the picosecond rising edge required for time domain reflectometry to measure soil moisture content.

[0009] Step S3: The 50MHz crystal oscillator outputs a clock signal as the FPGA system clock, which is divided by the FPGA internal phase-locked loop and output to the 10MHz clock terminal of the low-speed ADC to control the low-speed ADC sampling;

[0010] Step S4: The frequency difference between the input signal and the sampling signal is maintained at 1kHz. In the time domain, the sampling clock signal maintains a time difference of 10ps with the input signal.

[0011] Step S5: In each sampling period, the input signal is sampled by the low-speed ADC. After N sampling periods, a complete period of the input signal is collected, thus completing the 100 GSPS high-speed equivalent sampling.

[0012] Furthermore, in step S1, the 50MHz crystal oscillator and the 30MHz crystal oscillator use temperature-compensated crystal oscillators with a frequency stability of ±0.5ppm. The crystal oscillator noise is reduced by using a low-noise drive circuit to power the crystal oscillator, and the clock signal jitter is reduced by adding a 7th-order low-pass filter at the front end of the crystal oscillator output clock signal to filter out high-frequency noise.

[0013] Furthermore, in step S2, the signal frequency is adjusted by writing a frequency control word into the DDS. Specifically, the DDS output frequency f out The relationship with the frequency control word Δphase is as follows:

[0014] f out =Δphase×180 / 2 32 .

[0015] Furthermore, in step S3, the ADC sampling clock is set to 10 MHz through the FPGA phase-locked loop after frequency division. The real-time sampling rate of the low-speed ADC should be greater than 10 MSPS, the bandwidth should be greater than the bandwidth of the picosecond rising edge reflection signal to be measured, and the input impedance should match the impedance of the output end of the reflection signal to be measured.

[0016] Furthermore, in step S4, the frequency difference between the input signal and the sampling signal is controlled by adjusting the DDS output signal frequency and the FPGA internal phase-locked loop frequency division output frequency, which is reflected in the time domain as a ps-level step delay Δt. Different equivalent sampling rates are achieved by adjusting the step delay Δt by adjusting the frequency difference.

[0017] Furthermore, in step S5, equivalent sampling is performed on the periodic reflected signal to be sampled. After passing the trigger point, the sampling clock samples at different periods and phases of the signal. Since the time relationship between the sampling data of different phases of the signal to be sampled is fixed and known, the sampling data is rearranged according to the phase relationship to reconstruct the original waveform of the signal to be sampled. The specific steps are as follows:

[0018] In the first step, assuming that the clock period of the signal to be sampled is T, during the sequential equivalent sampling process, each sampling trigger time is delayed by Δt compared to the previous trigger time, and Δt is called the fixed step delay.

[0019] In the second step, assume that the sampling signal clock frequency after control is f trigger , with a period of T trigger , the clock frequency of the signal to be sampled is f data , with a period of T data , the frequency difference Δf between the two, and the sampling signal clock frequency is less than the clock frequency of the signal to be sampled. The specific calculation formula is as follows:

[0020]

[0021] Δf=f data -f trigger

[0022] Δt=Δf / [f data ×(f data +Δf)]

[0023] The third step is to control the frequency difference between the sampling signal and the signal to be sampled to be extremely small, which is reflected in the time domain as a step delay Δt. The step delay is set to 10ps, and the input signal is sampled through a low-speed ADC. After N sampling cycles, a complete cycle of the input signal is collected, completing the high-speed equivalent sampling of 100GSPS.

[0024] Beneficial effects of the present invention:

[0025] The present invention provides a method for achieving picosecond equivalent sampling in time-domain reflectometry of soil moisture content. Two independent stable crystal oscillator circuits are designed as clock sources for the sampling signal and the signal to be sampled. The output signal frequency is controlled by adjusting the DDS frequency control word, and the sampling signal frequency is controlled by the internal phase-locked loop of the FPGA. The frequency difference between the sampling signal and the signal to be sampled is controlled to adjust the step delay, thereby achieving an equivalent sampling rate of 100GSPS. This solves the problem that real-time sampling cannot meet the rate requirement. There is no need to synchronize the sampling clock signal and the clock signal to be sampled, nor is there a need for a specific delay chip to achieve the step delay, thereby reducing the complexity of the equivalent sampling system. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1It is a block diagram of the equivalent sampling system of the present invention.

[0027] Figure 2 This is the crystal oscillator circuit block diagram.

[0028] Figure 3 This is the equivalent sampling principle diagram. DETAILED DESCRIPTION

[0029] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0030] like Figure 1 As shown, the present invention provides a method for implementing picosecond equivalent sampling in time domain reflectometry soil moisture measurement, which specifically includes the following implementation steps:

[0031] Step S1: Design two stable crystal oscillator circuits, with 50 MHz as the clock source for the sampling signal and 30 MHz as the clock source for the input signal. The frequency error of the clock sources does not exceed ±0.5 ppm.

[0032] Specifically, in order to provide a high stable clock signal, such as Figure 2 As shown, the 50MHz and 30MHz crystal oscillators in the two independent stable crystal oscillator circuits are both composed of temperature-compensated crystal oscillators with a frequency stability of ±0.5ppm. The crystal oscillator noise is reduced by using a low-noise drive circuit to power the crystal oscillator. The clock signal jitter is reduced by adding a 7th-order low-pass filter at the front end of the crystal oscillator output clock signal to filter out high-frequency noise, thereby outputting a stable and jitter-free clock signal.

[0033] Step S2: The 30MHz crystal oscillator outputs a clock signal as the clock source for the DDS. The FPGA is used to write a frequency control word into the DDS register to adjust the signal frequency to 10.001MHz. The high-speed comparator is used to perform edge shaping on the signal to obtain the picosecond rising edge required for the time domain reflectometry method to measure soil moisture content.

[0034] Specifically, the DDS output frequency f out The relationship with the frequency control word Δphase is as follows:

[0035] f out =Δphase×180 / 2 32

[0036] The DDS chip used in this invention has a 32-bit frequency control word and can output a minimum clock frequency of 0.042 Hz. The DDS output signal is edge-shaped by a high-speed comparator to obtain the picosecond rising edge required for time domain reflectometry to measure soil moisture.

[0037] Step S3: The 50MHz crystal oscillator outputs a clock signal as the FPGA clock source, which is divided by the FPGA internal phase-locked loop and output to the low-speed ADC clock terminal to control the low-speed ADC sampling;

[0038] Specifically, the IP core circuit inside the phase-locked loop is a pre-designed circuit module inside the FPGA, with additional feedback modules such as a divider, a multiplier, and a mixer. By writing the phase-locked loop module code in Verilog, the 10MHz clock signal can be quickly and accurately adjusted to output as the sampling clock; the real-time sampling rate of the low-speed ADC should be greater than 10MSPS, the bandwidth should be greater than the bandwidth of the picosecond rising edge reflection signal to be measured, and the input impedance should match the impedance of the output end of the reflection signal to be measured.

[0039] Step S4: The frequency difference between the input signal and the sampling signal is maintained at 1 kHz. Reflected in the time domain, the sampling clock signal maintains a time difference of 10 ps with the input signal.

[0040] Specifically, by adjusting the DDS frequency control word to control the output signal frequency and the FPGA internal phase-locked loop to control the sampling signal frequency, the frequency difference between the sampling signal and the input signal is controlled to be Δf, which is reflected in the time domain as a step delay Δt. The present invention achieves a 100GSPS equivalent sampling rate with a step delay of 10ps.

[0041] Step S5: In each sampling period, the input signal is sampled by the low-speed ADC. After N sampling periods, a complete period of the input signal is collected, thus completing the 100 GSPS high-speed equivalent sampling.

[0042] Specifically, such as Figure 3 As shown in the figure, during the equivalent sampling process, each time the sampling is triggered, it is delayed by Δt compared to the previous trigger. Sampling with a fixed step delay of Δt is performed in each cycle of the input signal. After N cycles of sampling, the signal to be sampled can be reconstructed.

[0043] Furthermore, in order to achieve the highest equivalent sampling rate of 100 GSPS in this embodiment, the specific calculation formula is as follows:

[0044]

[0045] Δf=f data -f trigger

[0046] Δt=Δf / [f data ×(f data +Δf)]

[0047] In this implementation example, the ADC real-time sampling rate used is 10MS / s, f trigger =10MHz, period Ttrigger =100000ps. To achieve an equivalent sampling rate of 100GSPS, Δt = 10ps, then the period of the corresponding signal to be sampled is T data =T trigger -Δt=99990ps,f data =10001000Hz=10.001MHz.

[0048] Furthermore, after determining the equivalent sampling rate, the clock frequency of the signal to be sampled and the clock frequency of the sampling signal are calculated and determined. The output signal frequency is controlled to 10.001 MHz by adjusting the DDS frequency control word and the sampling signal frequency is controlled to 10 MHz by the FPGA internal phase-locked loop. The low-speed ADC is used to perform a sample once in each cycle of the signal to be sampled. After several cycles, a complete cycle of the original signal is collected to reconstruct the original signal.

[0049] It should be noted that the above content merely illustrates the technical idea of ​​the present invention and cannot be used to limit the scope of protection of the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications all fall within the scope of protection of the claims of the present invention.

Claims

1. A method for achieving picosecond equivalent sampling in time domain reflectometry soil moisture measurement, characterized in that: The following steps are involved: Step S1: Design two stable crystal oscillator circuits, with 50 MHz as the clock source for the sampling signal and 30 MHz as the clock source for the input signal, and the clock source frequency error does not exceed ±0.5 ppm; The stable crystal oscillator circuit requires a temperature-compensated crystal oscillator with a frequency stability of ±0.5 ppm, a low-noise drive circuit to power the crystal oscillator to reduce crystal oscillator noise, and a 7th-order low-pass filter to filter out high-frequency noise and reduce jitter at the front end of the crystal oscillator output clock signal; Step S2: The 30 MHz crystal oscillator outputs a clock signal as the system clock of the DDS. The FPGA is used to write a frequency control word into the DDS register to adjust the signal frequency to 10.001 MHz. The high-speed comparator is used to perform edge shaping on the signal to obtain the picosecond rising edge required for the time domain reflectometry method to measure soil moisture content. Step S3: The 50MHz crystal oscillator outputs a clock signal as the FPGA system clock, which is divided by the FPGA internal phase-locked loop and output to the 10MHz low-speed ADC clock terminal to control low-speed ADC sampling; Step S4: The frequency difference between the input signal and the sampling signal is maintained at 1 kHz. In the time domain, the sampling clock signal maintains a time difference of 10 ps with the input signal. The picosecond time difference between the input signal and the sampling signal in the time domain is achieved by maintaining the frequency difference in the frequency domain. The input signal frequency is adjusted by controlling the DDS frequency control word through the FPGA, and the output clock signal frequency is adjusted by changing the FPGA internal phase-locked loop frequency division ratio, so that the FPGA controls the sampling signal and the input signal to maintain a small frequency difference. Step S5: In each sampling period, the input signal is sampled by the low-speed ADC. After N sampling periods, a complete period of the input signal is collected, thus completing the 100 GSPS high-speed equivalent sampling.

2. The method for achieving picosecond equivalent sampling in soil moisture measurement using time domain reflectometry according to claim 1, characterized in that: Different equivalent sampling rates can be achieved by adjusting the frequency difference between the sampling signal and the input signal.

3. The method for achieving picosecond equivalent sampling in soil moisture measurement using time domain reflectometry according to claim 1, characterized in that: The maximum real-time sampling rate of the ADC in step S5 is higher than 10 MSPS, and the analog input bandwidth is greater than the pulse signal bandwidth.

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