An adaptive synchronous parallel bus interface device and timing calibration method
By using an adaptive synchronous parallel bus interface device, the clock and data delays can be adjusted independently, which solves the stability problem of the parallel synchronous bus interface under layout and routing and environmental changes, and improves device compatibility and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN SIDANDE INFORMATION TECH CO LTD
- Filing Date
- 2023-02-28
- Publication Date
- 2026-06-23
AI Technical Summary
Existing parallel synchronous bus interfaces face challenges in placement and routing, timing correction, and device compatibility. They are particularly unstable in miniaturization and high/low temperature environments, and their adjustment is complex and lacks adaptability.
An adaptive synchronous parallel bus interface device is adopted, including a transmitting device and a receiving device. Through the combination of a calibration data transmitting module, a data selection module, a clock module, a calibration control module, a sequence verification module, and a timing adjustment module, adaptive timing calibration is achieved. The clock and data delays are adjusted independently, and the timing is automatically adjusted to meet the interface requirements.
It improves the adaptability and flexibility of the bus interface, reduces human interference, enhances device compatibility and yield, adapts to different environmental changes, and simplifies the layout and routing process.
Smart Images
Figure CN116303201B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of wired digital communication and relates to an adaptive synchronous parallel bus interface device and a timing calibration method. Background Technology
[0002] Currently, parallel synchronous bus interfaces remain widely used in wired digital communication systems. Existing bus protocols primarily employ a single-clock, multiple-data parallel transmission mode, commonly used in LVDS synchronous clock transmission and synchronous parallel port transmission. With increasing system throughput and speed, the requirements for bus signal integrity (signal timing) are becoming increasingly stringent. If layout and routing are strictly performed according to interface requirements, transmission is generally stable. However, in practical engineering, not all application scenarios can be laid out and routed according to bus requirements. For example, due to board miniaturization, it is difficult to meet the requirement of equal-length data routing. Furthermore, changes in the parallel data transmission and reception timing of devices under high and low temperature environments can lead to bit errors.
[0003] Therefore, the current bus has the following problems:
[0004] 1. High requirements for layout and routing. High timing requirements, and routing constraints such as equal length, which cannot be met in some small-scale scenarios.
[0005] 2. Timing calibration is tedious and difficult. It mostly uses delayed data, requiring a high-precision, high-bandwidth oscilloscope to observe and adjust the delay time. Once the hardware is finalized, if timing issues are discovered during debugging, the hardware traces cannot be changed. High and low temperature environments can cause equipment transmission and reception abnormalities, resulting in data that is debugged at room temperature potentially exhibiting bit errors and poor stability under extreme temperatures.
[0006] 3. Requirements for device consistency, poor compatibility, complex adjustment, poor adaptability, and impact on yield.
[0007] 4. Even with some adaptive adjustment methods, the data lines are still required to have synchronous phase, that is, the data lines must be of equal length. Summary of the Invention
[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide an adaptive synchronous parallel bus interface device and timing calibration method, which has strong adaptability, does not require human interference during use, has high flexibility, and allows for independent adjustment of clock data.
[0009] To achieve the above objectives, the present invention employs the following technical solution:
[0010] An adaptive synchronous parallel bus interface device includes a transmitting device and a receiving device;
[0011] The transmitting device includes a calibration data transmitting module, a data selection module, and a clock module; the receiving device includes a calibration control module, a sequence verification module, a timing adjustment module, and a receive data selection module.
[0012] The output of the calibration data transmission module is connected to the input of the data selection module. The outputs of the clock module and the data selection module are both connected to the input of the timing adjustment module. The output of the timing adjustment module is connected to the input of the receiving data selection module. The output of the receiving data selection module is connected to the input of the sequence verification module. The output of the sequence verification module is connected to the input of the calibration control module. The output of the calibration control module is connected to the inputs of the clock module timing adjustment module and the receiving data selection module, respectively.
[0013] The calibration data transmission module is used to transmit preset data, the clock module is used to generate the accompanying data clock, and the data selection module is used to receive service data and control the switching between service data and calibration data.
[0014] The calibration control module controls the timing adjustment module to make corresponding delay control based on the verification result fed back by the sequence verification module of the received data. The timing adjustment module is used to adjust the timing of data and / or clock according to the calibration control module. The sequence verification module is used to verify whether the sampling has obtained correct received data. The received data selection module is used to select, under the control of the calibration control module, whether to send the received data to the sequence verification module or to output it in the form of service data.
[0015] An adaptive timing calibration method based on the above-mentioned device includes the following process:
[0016] S1, the calibration control module is set to timing calibration mode, the data source is selected as multi-channel calibration data, and multi-channel calibration data is sent;
[0017] S2, the calibration control module is set to the timing calibration mode, the data is output to the sequence verification module, multiple calibration data are received, and the multiple calibration data are compared;
[0018] S3, the sequence verification module feeds back verification information to the calibration control module. If each path passes, the timing configuration mode is considered feasible, and the timing configuration parameters at this moment are latched.
[0019] S4, adjust the data or clock delay, repeat steps S1 to S3, and record the verification results and configuration in this state;
[0020] S5, among the feasible configurations, select the configuration with the largest timing margin as the configuration for normal business mode;
[0021] S6, the receiving and transmitting devices enter normal service mode, the data is selected as normal service data, and the calibration ends.
[0022] Preferably, the calibration data consists of eight square wave signals transmitted in parallel.
[0023] Preferably, the preset data is fixed data, pseudo-random data, or incremental data.
[0024] Preferably, in S3, the verification information is whether the data is 00 and FF alternating.
[0025] Preferably, if the verification result is incorrect, the calibration control module adjusts the delay value of the calibration data of that channel and sends it to the timing adjustment module. The sequence verification module verifies the sampled data under the new delay until the verification result is correct.
[0026] Furthermore, after the verification result under the new delay is correct, the correct delay value is latched, the delay calibration continues to accumulate, the correct calibration result values are latched in sequence, and any correct value is selected as the delay value for configuration.
[0027] Furthermore, if the calibration result is still incorrect after adjusting one cycle, the delayed clock method is used. The delayed value is sent to the clock module, and the sequence verification module continues to perform the calibration process on the new delay data, accumulating the delay value until the verification result is correct.
[0028] Preferably, after timing calibration is completed, timing calibration is performed again if any of the following conditions exist;
[0029] During use, inconsistencies occurred between the data and the expected results; changes in ambient temperature were detected; business data results were unsatisfactory, and calibration results were not met; the set time was reached during idle periods.
[0030] Compared with the prior art, the present invention has the following beneficial effects:
[0031] The device described in this invention is highly adaptable, requires no human intervention during use, is highly flexible, and allows for independent adjustment of clock data. It boasts strong compatibility, improving yield for batch production. It also offers advantages such as high portability and modularity. Each data channel has its own independently optimized clock, offering high freedom and flexibility; it has good environmental adaptability, does not require parallel bus length, and facilitates layout and wiring; it can replace components from any batch and different manufacturers, does not require component consistency, and has good compatibility. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the synchronous parallel bus interface device of the present invention;
[0033] Figure 2 This is the timing adjustment diagram for the present invention;
[0034] Figure 3 This is a block diagram of the adaptive calibration of the present invention;
[0035] Figure 4 This is a control flow diagram of the present invention. Detailed Implementation
[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0037] It should be noted that the terms “front,” “back,” “left,” “right,” “up,” and “down” used in the following description refer to the directions shown in the attached diagram, while the terms “inside” and “outside” refer to the directions toward or away from the geometric center of a specific component, respectively.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0039] like Figure 1 As shown, the adaptive synchronous parallel bus interface device of the present invention includes a transmitting device and a receiving device.
[0040] The transmitting device includes a calibration data transmission module, a data selection module, and a clock module.
[0041] The receiving device includes a calibration control module, a sequence verification module, a timing adjustment module, and a received data selection module.
[0042] The output of the calibration data transmission module is connected to the input of the data selection module. The outputs of both the clock module and the data selection module are connected to the input of the timing adjustment module. The output of the timing adjustment module is connected to the input of the receiving data selection module. The output of the receiving data selection module is connected to the input of the sequence verification module. The output of the sequence verification module is connected to the input of the calibration control module. The output of the calibration control module is connected to both the clock module timing adjustment module and the receiving data selection module input.
[0043] The calibration data transmission module is used to transmit preset data, the clock module is used to generate the accompanying data clock, and the data selection module is used to receive service data and control the switching between service data and calibration data.
[0044] The calibration control module controls the timing adjustment module to make corresponding delay control based on the verification result fed back by the sequence verification module of the received data. The timing adjustment module is used to adjust the timing of data and / or clock according to the calibration control module. The sequence verification module is used to verify whether the sampling has obtained correct received data. The received data selection module is used to select, under the control of the calibration control module, whether to send the received data to the sequence verification module or to output it in the form of service data.
[0045] like Figure 2 As shown, the calibration control module can send data delay commands to the timing adjustment module and clock delay commands to the clock module. The timing adjustment function has a module where both data delay and clock delay are independently adjustable delay parameters.
[0046] The timing adjustment module includes multiple delay modules and samplers; the clock module includes multiple delay modules (also referred to as clock delay modules in this paper); the receive data selection module includes multiple switches; and the sequence verification module includes multiple verifiers.
[0047] like Figure 3 As shown, the data received by the delay module is collected by the sampler module, and the calibrator receives the calibration data and sends the calibration result to the calibration control module. The calibration control module adjusts the delay module and the time delay module based on the feedback result from the calibrator, adjusting the delay of each data channel in sequence.
[0048] like Figure 4 As shown, the working process of the adaptive synchronous parallel bus interface device of the present invention is as follows:
[0049] First, after powering on, it enters calibration mode. After calibration is completed, it enters normal business mode. In normal business mode, if the calibration trigger condition is detected to be met, it will re-enter calibration mode.
[0050] Timing calibration mode step description
[0051] S1, the calibration control module of the adaptive transmission interface module is set to timing calibration mode, that is, the data source selects calibration data as preset data and sends preset data.
[0052] S2, the calibration control module of the adaptive receiving interface module is set to the timing calibration mode, that is, the data is output to the sequence verification module, the preset data of the calibration data is received, and the preset data is compared.
[0053] S3, the calibration sequence verifier feeds back the verification information to the calibration control module. If each path passes, the timing configuration mode is considered feasible, and the timing configuration parameters at this moment are latched.
[0054] S4, adjust the delay of the data delay module and / or clock delay module, repeat steps S1~S3, and record the verification results and configuration in this state. Each data channel has an independent clock pair to adjust the sampling time, allowing for a high degree of adjustment flexibility.
[0055] S5: Among the feasible configurations, select the configuration with the largest timing margin as the configuration for normal business mode.
[0056] S6, the receiving and transmitting devices enter normal service mode, the data is selected as normal service data, and the calibration ends.
[0057] Specific examples are as follows:
[0058] S1 is the preset calibration data transmission module. The calibration data consists of eight parallel square wave signals, followed by a 125MHz clock. The service data is an incremental number transmitted periodically from 0 to 255. A data selector selects the calibration data to transmit during the verification process.
[0059] S2, the receiving device receives data from the transmitting end. Under the control of the calibration control module, the timing adjustment module adjusts the phase of each clock through the internal buffer taps of the clock delay module. The data selector selects to output the sampled data to the calibration sequence verification module.
[0060] S3, the calibration sequence verification module checks whether the sampled data alternates between 00 and FF, and feeds back the verification result to the calibration control module.
[0061] S4. If the calibration result is correct, the receiving device generates a feedback signal, the transmitting device's data selection module selects the incremental number of the transmitted service data, and the receiving device switches the switch to the service data receiving mode.
[0062] If the calibration result is incorrect, it means there is a deviation in the data sampling verified by the calibrator. The calibrator sends this verification result to the calibration control module. The calibration control module adjusts the data delay value of this channel and sends it to the delay module. The calibrator verifies the sampled data under the new delay until the calibrator's verification result is correct. The correct delay value is latched, and the delay calibration continues to accumulate. The correctly calibrated result values are latched sequentially. An arbitrary value is selected from the correct values as the delay value for configuration.
[0063] If the calibration result is still incorrect after adjusting one cycle using the data delay method, the delayed clock method is used, and the delay value is sent to the clock delay module. The verifier continues the calibration process for the new delay data, accumulating the delay value. This continues until the verifier's verification result is correct. The correct delay value is latched, and the delay calibration continues to accumulate. The correctly calibrated results are latched sequentially. An arbitrary value is selected from the correct values as the delay value for configuration.
[0064] S5, in feasible configurations, latches the delayed results. Selecting the result with the largest timing margin requires saving multiple sets of adjustment results. Selecting the intermediate delay value. Configure accordingly.
[0065] S6, both the receiving and transmitting devices simultaneously enter normal service mode, and the calibration ends.
[0066] In the above specific embodiments, the following changes can be made according to application requirements.
[0067] 1. The transmitting device sends preset data, which can be fixed data, pseudo-random data, incremental data, etc., enabling the receiving end to have a corresponding identification mechanism. There are no restrictions on the preset data.
[0068] 2. The receiving device receives the square wave data from the transmitting device. Following the requirements of step S2, an additional follower (BUF) can be added to optimize the accompanying clock and send it to the delay module, generating accompanying clocks for N data streams. At this point, the received data is sent to separate delay modules. No adjustments are made by default.
[0069] 3. During the calibration process, the received results need to be re-verified each time the delay parameters and delay conditions are changed. This process is consistent. After changing the delay parameters, the waiting time in the above example is 1 second for statistical verification of the results; this condition should be set according to the actual application.
[0070] 4. After the initial calibration is completed, the possible triggering conditions for recalibration include, but are not limited to: during use, if the data is found to be inconsistent with the expected results, the calibration mode can be re-entered; if a change in ambient temperature is detected, the calibration data mode can be re-entered; if the business data results are not ideal and the calibration results are not met; or during idle periods, recalibration can be performed.
[0071] 5. As shown in the block diagram, the receiver uses multiple selection switches and multiple verifier modules. If there are requirements for FPGA resources, low cost requirements, and limited chip resources, a time-division switching method can be used to poll the results of N data and clock signals using one selection switch and one verifier.
[0072] 6. The receiver's calibration control module can provide feedback to the transmitter's calibration control module via a feedback signal. Alternatively, other mechanisms can be used, such as allowing the transceiver program to simultaneously enter normal service mode after power-on and waiting for a certain period, thus eliminating the need for a feedback signal. The receiver has corresponding registers that the transmitter can query or configure.
[0073] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0074] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed inventive subject matter.
Claims
1. An adaptive timing calibration method for an adaptive synchronous parallel bus interface device, characterized in that, The adaptive synchronous parallel bus interface device includes a transmitting device and a receiving device; The transmitting device includes a calibration data transmitting module, a data selection module, and a clock module; the receiving device includes a calibration control module, a sequence verification module, a timing adjustment module, and a receive data selection module. The output of the calibration data transmission module is connected to the input of the data selection module. The outputs of the clock module and the data selection module are both connected to the input of the timing adjustment module. The output of the timing adjustment module is connected to the input of the receiving data selection module. The output of the receiving data selection module is connected to the input of the sequence verification module. The output of the sequence verification module is connected to the input of the calibration control module. The output of the calibration control module is connected to the inputs of the clock module timing adjustment module and the receiving data selection module, respectively. The calibration data transmission module is used to transmit preset data, the clock module is used to generate the accompanying data clock, and the data selection module is used to receive service data and control the switching between service data and calibration data. The calibration control module is used to control the timing adjustment module to make corresponding delay control based on the verification result fed back by the sequence verification module of the received data. The timing adjustment module is used to adjust the timing of data and / or clock according to the calibration control module. The sequence verification module is used to verify whether the sampling has obtained correct received data. The received data selection module is used to select, under the control of the calibration control module, whether to send the received data to the sequence verification module or to output it in the form of service data. Adaptive timing calibration method The process includes the following: S1, the calibration control module is set to timing calibration mode, the data source is selected as multi-channel calibration data, and multi-channel calibration data is sent; S2, the calibration control module is set to the timing calibration mode, the data is output to the sequence verification module, multiple calibration data are received, and the multiple calibration data are compared; S3, the sequence verification module feeds back verification information to the calibration control module. If each path passes, the timing calibration mode is considered feasible, and the timing calibration mode parameters at this moment are latched. The verification information is whether the data alternates between 00 and FF; If the verification result is incorrect, the calibration control module adjusts the delay value of the calibration data of that channel and sends it to the timing adjustment module. The sequence verification module verifies the sampled data under the new delay until the verification result is correct. If the calibration result is still incorrect after adjusting one cycle, the delayed clock method is used. The delayed value is sent to the clock module, and the sequence verification module continues to perform the calibration process on the new delay data, accumulating the delay value until the verification result is correct. After timing calibration is completed, timing calibration should be performed again if any of the following conditions exist; During use, inconsistencies occurred between the data and the expected results; changes in ambient temperature were detected; business data results were unsatisfactory, and calibration results were not met; the set time was reached during idle periods. After the verification result under the new delay is correct, the correct delay value is latched, the delay calibration continues to be accumulated, the correct calibration result values are latched in sequence, and any correct value is selected as the delay value for configuration. S4, adjust the data or clock delay, repeat steps S1 to S3, and record the verification results and configuration in the current state; S5, among the feasible configurations, select the configuration with the largest timing margin as the configuration for normal business mode; S6, the receiving and transmitting devices enter normal service mode, the data is selected as normal service data, and the calibration ends.
2. The adaptive timing calibration method according to claim 1, characterized in that, The calibration data consists of eight square wave signals transmitted in parallel.
3. The adaptive timing calibration method according to claim 1, characterized in that, The preset data can be fixed data, pseudo-random data, or incremental data.