A gallium nitride vertical trench mosfet device, method of fabrication and chip

Abstract

This application belongs to the field of semiconductor technology and provides a gallium nitride vertical trench MOSFET device, fabrication method, and chip. By forming a first P-type isolation region between the gallium nitride drift layer and the gate insulating layer, and forming multiple second P-type isolation regions between the gallium nitride drift layer and the first N-type doped region, and multiple second P-type isolation regions between the gallium nitride drift layer and the second N-type doped region, the first P-type isolation region and the second P-type isolation region form a depletion region with the gallium nitride drift layer with only one photomask layer. At the same time, the electric field between the source and drain of the device is homogenized, and the electric field is avoided from concentrating on the gate insulating layer, thereby achieving the purpose of improving the breakdown voltage of the gallium nitride vertical trench MOSFET device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a gallium nitride vertical trench MOSFET device, its fabrication method, and its chip. Background Technology

[0002] As a representative of third-generation semiconductor materials, gallium nitride (GaN) possesses many excellent properties, such as a high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and good high-temperature operating capability. Vertical gallium nitride trench metal-oxide-semiconductor field-effect transistors (TG-MOSFETs) are extremely popular in high-power applications, and due to the simplicity of the GaN growth epitaxial process and device fabrication process, they have potential advantages in structural improvement.

[0003] However, the biggest challenge of TG-MOSFETs is that the peak electric field of its bottom trench exceeds the critical breakdown electric field strength of GaN material, resulting in a low breakdown voltage and greatly limiting the application range of TG-MOSFETs. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a gallium nitride vertical trench MOSFET device, its fabrication method, and a chip, aiming to solve the problem of low breakdown voltage in TG-MOSFETs fabricated based on GaN materials.

[0005] The first aspect of this application provides a gallium nitride vertical trench MOSFET device, the gallium nitride vertical trench MOSFET device comprising:

[0006] Gallium nitride substrate;

[0007] A gallium nitride drift layer is disposed on the front side of the gallium nitride substrate;

[0008] A first N-type doped region, a second N-type doped region, and a gate insulating layer are disposed on the gallium nitride drift layer; wherein the gate insulating layer is concave, and the first N-type doped region and the second N-type doped region are respectively disposed on both sides of the gate insulating layer;

[0009] A gate material layer is disposed within a groove of the gate insulating layer;

[0010] A first P-type base region and a first P-type doped layer are disposed on the first N-type doped region;

[0011] A second P-type base region and a second P-type doped layer are disposed on the second N-type doped region;

[0012] The first source doped region and the second source doped region are respectively disposed on the first P-type base region and the second P-type base region;

[0013] The source metal layer is in contact with the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region;

[0014] A dielectric layer is disposed between the source metal layer and the gate material layer;

[0015] A drain metal layer is disposed on the back side of the gallium nitride substrate;

[0016] A first P-type isolation region is disposed between the gate insulating layer and the gallium nitride drift layer;

[0017] Multiple second P-type isolation regions are respectively disposed between the first N-type doped region and the gallium nitride drift layer, and between the second N-type doped region and the gallium nitride drift layer.

[0018] In one embodiment, a plurality of second P-type isolation regions are respectively disposed on both sides of the first P-type isolation region, and the doping concentrations of the first P-type isolation region and the second P-type isolation region are equal.

[0019] In one embodiment, the doping concentration of the second P-type isolation region is negatively correlated with the first spacing distance;

[0020] Wherein, the first interval distance is the distance between the second P-type isolation zone and the first P-type isolation zone.

[0021] In one embodiment, the spacing width between a plurality of second P-type isolation zones on a first side of the first P-type isolation zone is equal;

[0022] The spacing width between the plurality of second P-type isolation zones on the second side of the first P-type isolation zone is equal.

[0023] In one embodiment, the spacing width between the plurality of second P-type isolation zones is negatively correlated with the second spacing distance;

[0024] Wherein, the second interval distance is the distance between the second P-type isolation zone and the first P-type isolation zone.

[0025] In one embodiment, the width of the second P-type isolation zone is negatively correlated with the second interval distance;

[0026] Wherein, the second interval distance is the distance between the second P-type isolation zone and the first P-type isolation zone.

[0027] In one embodiment, the width of the first P-type isolation region is greater than the width of the second P-type isolation region; and / or

[0028] The thickness of the first P-type isolation region and the second P-type isolation region are equal.

[0029] In one embodiment, the number of second P-type isolation zones on the first side of the first P-type isolation zone is equal to the number of second P-type isolation zones on the second side of the first P-type isolation zone.

[0030] A second aspect of this application also provides a method for fabricating a gallium nitride vertical trench MOSFET device, comprising:

[0031] A gallium nitride drift layer is formed on the front side of the gallium nitride substrate;

[0032] A photomask is used to cover the front side of the gallium nitride drift layer to implant P-type dopant ions in a designated area on the front side of the gallium nitride drift layer to form a first P-type isolation region and a plurality of second P-type isolation regions; wherein, the plurality of second P-type isolation regions are respectively disposed on both sides of the first P-type isolation region;

[0033] An N-type doped layer is formed on the gallium nitride drift layer;

[0034] A P-type doped layer is formed on the N-type doped layer, and a P-type base region and a source doped layer are formed within the P-type doped layer, dividing the P-type doped layer into a first P-type doped layer and a second P-type doped layer.

[0035] Etching is performed on the source doped layer to form a deep trench extending into the gallium nitride drift layer, so as to divide the source doped layer into a first source doped region and a second source doped region, divide the P-type base region into a first P-type base region and a second P-type base region, and divide the N-type doped layer into a first N-type doped region and a second N-type doped region.

[0036] A gate insulating layer is formed on the inner wall of the deep trench, and a gate material layer is formed within the gate insulating layer;

[0037] A dielectric layer is formed on the gate material layer, and a source metal layer is formed in contact with the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region; wherein the dielectric layer is disposed between the source metal layer and the gate material layer;

[0038] A drain metal layer is formed on the back side of the gallium nitride substrate.

[0039] A third aspect of this application also provides a chip that integrates a gallium nitride vertical trench MOSFET device as described in any of the above embodiments; or includes a gallium nitride vertical trench MOSFET device prepared by the preparation method described in the above embodiments.

[0040] The beneficial effects of this application embodiment compared with the prior art are as follows: by forming a first P-type isolation region between the gallium nitride drift layer and the gate insulating layer, and forming multiple second P-type isolation regions between the gallium nitride drift layer and the first N-type doped region, and forming multiple second P-type isolation regions between the gallium nitride drift layer and the second N-type doped region, the first P-type isolation region and the second P-type isolation region form a depletion region with the gallium nitride drift layer with only one photomask layer. At the same time, the electric field between the source and drain of the device is homogenized, and the electric field is avoided from concentrating on the gate insulating layer, thereby achieving the purpose of improving the breakdown voltage of the gallium nitride vertical trench MOSFET device. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the vertical cross-sectional structure of a gallium nitride-based gallium nitride vertical trench MOSFET device provided in one embodiment of this application;

[0042] Figure 2 This is a schematic flowchart of a method for fabricating a gallium nitride-based gallium nitride vertical trench MOSFET device according to an embodiment of this application;

[0043] Figure 3 This is a schematic diagram of a gallium nitride drift layer 200 formed on a gallium nitride substrate 100 according to an embodiment of this application;

[0044] Figure 4 This is a schematic diagram of the structure of multiple P-type isolation regions provided in one embodiment of this application;

[0045] Figure 5 This is a schematic diagram of the structure forming a first P-type doped layer 510, a second P-type doped layer 520, a P-base region 600, and a source doped layer 700 according to an embodiment of this application;

[0046] Figure 6 This is a schematic diagram of the structure after forming a deep trench 801 and a gate insulating layer 810 according to an embodiment of this application;

[0047] Figure 7 This is a schematic diagram of the structure after forming a gate material layer 820, a dielectric layer 830, a source metal layer 840, and a drain metal layer 850, according to an embodiment of this application. Detailed Implementation

[0048] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0049] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0050] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0052] In this application specification, references to "one embodiment," "some embodiments," or "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," "in a particular embodiment," "in a particular application," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0053] As a representative of third-generation semiconductor materials, gallium nitride (GaN) possesses many excellent properties, including a high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and good high-temperature operating capability. Third-generation semiconductor devices based on gallium nitride, such as high electron mobility transistors (HEMTs) and heterojunction field-effect transistors (HFETs), have already been applied, showing significant advantages, especially in radio frequency and microwave applications requiring high power and high frequency.

[0054] The biggest challenge of TG-MOSFETs is that the peak electric field of its bottom trench exceeds the critical breakdown electric field strength of GaN material, resulting in a low breakdown voltage and greatly limiting the application range of TG-MOSFETs.

[0055] To address the aforementioned technical problems, this application provides a gallium nitride vertical trench MOSFET device, which aims to improve the breakdown voltage of gallium nitride-based vertical trench MOSFET devices.

[0056] In one embodiment, combined Figure 1 As shown, the gallium nitride vertical trench MOSFET device in this embodiment includes: a gallium nitride substrate 100, a gallium nitride drift layer 200, a first N-type doped region 410, a second N-type doped region 420, a gate insulating layer 810, a gate material layer 820, a first P-type base region 610, a first P-type doped layer 510, a second P-type base region 620, a second P-type doped layer 520, a first source doped region 710, a second source doped region 720, a source metal layer 840, a dielectric layer 830, a drain metal layer 850, a first P-type isolation region 320, and a plurality of second P-type isolation regions 310.

[0057] Specifically, a gallium nitride drift layer 200 is disposed on the front side of a gallium nitride substrate 100, a drain metal layer 850 is disposed on the back side of the gallium nitride substrate 100, a first N-type doped region 410, a second N-type doped region 420, and a gate insulating layer 810 are disposed on the gallium nitride drift layer 200. The gate insulating layer 810 is concave, and the first N-type doped region 410 and the second N-type doped region 420 are respectively disposed on both sides of the gate insulating layer 810; a gate material layer 820 is disposed within the recess of the gate insulating layer 810; a first P-type base region 610 and a first P-type doped layer 510 are disposed on the first N-type doped region 410; and a second P-type base region 620 and a second P-type doped layer 520 are disposed on the second N-type doped region 420. On the 0; the first source doped region 710 and the second source doped region 720 are respectively disposed on the first P-type base region 610 and the second P-type base region 620; the source metal layer 840 is in contact with the first P-type doped layer 510, the second P-type doped layer 520, the first source doped region 710 and the second source doped region 720; the dielectric layer 830 is disposed between the source metal layer 840 and the gate material layer 820; the first P-type isolation region 320 is disposed between the gate insulating layer 810 and the gallium nitride drift layer 200; a plurality of second P-type isolation regions 310 are respectively disposed between the first N-type doped region 410 and the gallium nitride drift layer 200 and between the second N-type doped region 420 and the gallium nitride drift layer 200.

[0058] In this embodiment, by forming a first P-type isolation region 320 between the gallium nitride drift layer 200 and the gate insulating layer 810, and forming a plurality of second P-type isolation regions 310 between the gallium nitride drift layer 200 and the first N-type doped region 410, and forming a plurality of second P-type isolation regions 310 between the gallium nitride drift layer 200 and the second N-type doped region 420, the first P-type isolation region 320 and the second P-type isolation region 310 form a depletion region with the gallium nitride drift layer 200 with only one photomask layer, and at the same time, the electric field between the source and drain of the device is homogenized, avoiding the electric field concentration on the gate insulating layer 810, thereby achieving the purpose of improving the breakdown voltage of the gallium nitride vertical trench MOSFET device.

[0059] In one embodiment, a dielectric layer 830 is disposed between the source metal layer 840 and the gate material layer 820 to isolate the source metal layer 840 and the gate material layer 820, and to bond them together. Figure 1 As shown, the source metal layer 840 has a concave structure, and the dielectric layer 830 is located in the groove of the source metal layer 840.

[0060] In one embodiment, the dielectric layer 830 is further disposed between the gate insulating layer 810 and the source metal layer 840.

[0061] In one embodiment, the width of the dielectric layer 830 is greater than the width of the gate insulating layer 810.

[0062] In one embodiment, the thickness of the gate insulating layer 810 is equal to the sum of the thicknesses of the first N-type doped region 410, the first P-type base region 610, and the first source doped region 710.

[0063] In one embodiment, the first N-type doped region 410 and the second N-type doped region 420 are symmetrically arranged.

[0064] In one embodiment, the first P-type base region 610 and the second P-type base region 620 are symmetrically arranged.

[0065] In one embodiment, the first source doped region 710 and the second source doped region 720 are symmetrically arranged.

[0066] In one embodiment, the first side of the first source doped region 710 is flush with the first side of the first P-type base region 610 and contacts the first side of the gate insulating layer 810. The gate insulating layer 810 has a concave structure consisting of a bottom, a first side, and a second side.

[0067] In one embodiment, the width of the first source doped region 710 is greater than the width of the first P-type base region 610.

[0068] In one embodiment, both the gallium nitride substrate 100 and the gallium nitride drift layer 200 are N-type doped gallium nitride.

[0069] In one embodiment, the doping concentration of the gallium nitride substrate 100 is greater than the doping concentration of the gallium nitride drift layer 200.

[0070] In one embodiment, a plurality of second P-type isolation regions 310 are respectively disposed on both sides of the first P-type isolation region 320, and the doping concentrations of the first P-type isolation region 320 and the second P-type isolation region 310 are equal.

[0071] Combination Figure 1 As shown, the multiple second P-type isolation regions 310 do not contact each other, and the second P-type isolation region 310 on the first side of the first P-type isolation region 320 is in contact with the first N-type doped region 410, and the second P-type isolation region 310 on the second side of the first P-type isolation region 320 is in contact with the second N-type doped region 420.

[0072] In one embodiment, the doping concentration of the second P-type isolation region 310 is negatively correlated with the first spacing distance; wherein, the first spacing distance is the distance between the second P-type isolation region 310 and the first P-type isolation region 320.

[0073] In this embodiment, the doping concentration of the second P-type isolation region 310 is smaller the farther away from the first P-type isolation region 320, and the doping concentration of the second P-type isolation region 310 is larger the closer to the first P-type isolation region 320.

[0074] In one embodiment, the spacing width between the plurality of second P-type isolation zones 310 on the first side of the first P-type isolation zone 320 is equal; the spacing width between the plurality of second P-type isolation zones 310 on the second side of the first P-type isolation zone 320 is also equal.

[0075] In one embodiment, the spacing width between the plurality of second P-type isolation zones 310 is negatively correlated with the second spacing distance; wherein, the second spacing distance is the distance between the second P-type isolation zone 310 and the first P-type isolation zone 320.

[0076] In this embodiment, the farther away from the first P-type isolation zone 320, the smaller the interval between adjacent second P-type isolation zones 310; the closer to the first P-type isolation zone 320, the larger the interval between adjacent second P-type isolation zones 310.

[0077] In one embodiment, the first P-type isolation region 320 can be a stepped structure. For example, the first P-type isolation region 320 is composed of multiple P-type isolation layers forming a trapezoidal structure. The bottom of the trapezoidal structure is in contact with the gate insulating layer 810, and the top of the trapezoidal structure is away from the gate insulating layer 810.

[0078] In one embodiment, an isolation metal layer can be disposed within each P-type isolation layer. Since the distance between the P-type isolation layer and the gate insulating layer 810 is inversely proportional to the width of the P-type isolation layer, and each P-type isolation layer contains an isolation metal layer, the P-type isolation layers and isolation metal layers of varying lengths can form a stepped sharp corner at the interface with the gallium nitride drift layer 200. This results in multiple electric field peaks within the gallium nitride drift layer 200, which share the electric field accumulation caused by the sharp corner structure of the gate insulating layer 810. This achieves the purpose of homogenizing the electric field, reducing the electric field peaks borne by the gate insulating layer 810, and preventing the electric field from concentrating on the gate insulating layer 810, thereby improving the breakdown voltage of the high-voltage gallium nitride MOSFET device.

[0079] In one embodiment, as the distance between the P-type isolation layer and the bottom of the gate insulating layer 810 gradually increases or decreases, the width of the P-type isolation layer also gradually decreases. Specifically, the width of each P-type isolation layer below the first P-type isolation layer is smaller than the width of the adjacent upper P-type isolation layer, and the two sides of each P-type isolation layer below the first P-type isolation layer are located inside the two sides of the adjacent upper P-type isolation layer, thereby forming a stepped structure between adjacent P-type isolation layers.

[0080] In one embodiment, the isolation metal layer is located within the corresponding P-type isolation layer, and the width of the multiple isolation metal layers gradually decreases according to their distance from the gate insulating layer 810. Specifically, the farther the isolation metal layer is from the bottom of the gate insulating layer 810, the smaller the width of the isolation metal layer.

[0081] In this embodiment, multiple P-type isolation layers with a wider top and a narrower bottom are formed between the gate insulating layer 810 and the gallium nitride drift layer 200. On the one hand, multiple electric field peaks can be formed at the sharp corners of the P-type isolation layers to homogenize the electric field of the gallium nitride drift layer 200 and improve the breakdown voltage of the device. On the other hand, it can shield the Miller capacitance Cgd of the device, reduce the switching loss of the device, and also suppress the increase of parasitic capacitance Cds in the device as much as possible.

[0082] In one embodiment, the width of the second P-type isolation zone 310 is negatively correlated with the second interval distance; wherein the second interval distance is the distance between the second P-type isolation zone 310 and the first P-type isolation zone 320.

[0083] In this embodiment, the farther the second P-type isolation region 310 is from the first P-type isolation region 320, the smaller the width of the second P-type isolation region 310; the closer it is to the first P-type isolation region 320, the larger the width of the second P-type isolation region 310.

[0084] In one embodiment, the width of the first P-type isolation region 320 is greater than the width of the second P-type isolation region 310.

[0085] In this embodiment, the width of the first P-type isolation region 320 is greater than the width of the polysilicon material layer 820. At this time, a depletion region is formed between the first P-type isolation region 320 and the gallium nitride drift layer 200. The first P-type isolation region 320 can protect the sharp corners on both sides of the bottom of the gate insulating layer 810. At the same time, multiple second P-type isolation regions 310 homogenize the electric field between the drain metal layer 850 and the source metal layer 840, avoiding the electric field from concentrating on the gate insulating layer 810, thereby achieving the purpose of improving the breakdown voltage of the device.

[0086] In one embodiment, the thickness of the first P-type isolation region 320 and the second P-type isolation region 310 is equal.

[0087] In one embodiment, the number of second P-type isolation zones 310 on the first side of the first P-type isolation zone 320 is equal to the number of second P-type isolation zones 310 on the second side of the first P-type isolation zone 320.

[0088] In this embodiment, by setting the first P-type isolation region 320 and the second P-type isolation region 310, the electric field between the source and drain of the device is more uniform. At this time, when the device is working, the current flowing from the drain to the source is dispersed, thereby dispersing the potential borne by the gate insulating layer 810, so as to improve the breakdown voltage of the device.

[0089] This application also provides a method for fabricating a gallium nitride vertical trench MOSFET device, see [link to relevant documentation]. Figure 2 As shown, the preparation method in this embodiment includes steps S10 to S90.

[0090] In step S10, a gallium nitride drift layer is formed on the front side of the gallium nitride substrate.

[0091] Combination Figure 3 As shown, the gallium nitride drift layer 200 is formed on the front side of the gallium nitride substrate 100. Specifically, the gallium nitride drift layer 200 can be formed on the front side of the gallium nitride substrate 100 by epitaxial growth.

[0092] In one embodiment, the thickness of the gallium nitride drift layer 200 is greater than the thickness of the gallium nitride substrate 100.

[0093] In one embodiment, both the gallium nitride drift layer 200 and the gallium nitride substrate 100 are N-type gallium nitride, wherein the doping concentration of the N-type dopant in the gallium nitride drift layer 200 is less than the doping concentration of the N-type dopant in the gallium nitride substrate 100.

[0094] In one embodiment, the N-type dopant element in the gallium nitride drift layer 200 and the gallium nitride substrate 100 can be silicon.

[0095] In step S20, a photomask is used to cover the front side of the gallium nitride drift layer to inject P-type dopant ions into a designated area on the front side of the gallium nitride drift layer to form a first P-type isolation region and a plurality of second P-type isolation regions.

[0096] In this embodiment, combined with Figure 4 As shown, by forming a photomask on the surface of the gallium nitride drift layer 200, and then injecting P-type dopant ions into the surface of the gallium nitride drift layer 200 under the cover of the photomask, a plurality of P-type isolation regions are formed on the surface of the gallium nitride drift layer 200. There are multiple second P-type isolation regions 310, and the multiple second P-type isolation regions 310 are respectively disposed on both sides of the first P-type isolation region 310.

[0097] In one embodiment, the P-type dopant ion can be a magnesium ion.

[0098] In step S30, an N-type doped layer is formed on the gallium nitride drift layer.

[0099] Combination Figure 5 As shown, an N-type doped layer 400 can be formed on the gallium nitride drift layer 200 by injecting N-type dopant ions into the front side of the gallium nitride drift layer 200, or an N-type doped layer 400 can be formed on the gallium nitride drift layer 200 by epitaxial growth.

[0100] In step S40, a P-type doped layer is formed on the N-type doped layer, and a P-type base region and a source doped layer are formed within the P-type doped layer, dividing the P-type doped layer into a first P-type doped layer and a second P-type doped layer.

[0101] Combination Figure 5 As shown, P-type dopant ions are implanted on the front side of the N-type doped layer 400 or a P-type doped layer is formed by epitaxial growth. Then, a P-base region 600 and a source doped layer 700 are formed at the center of the P-type doped layer. At this time, the P-type doped layer is divided into a first P-type doped layer 510 and a second P-type doped layer 520. The first P-type doped layer 510 and the second P-type doped layer 520 are located on both sides of the P-base region 600 and the source doped layer 700, respectively.

[0102] In one embodiment, the width of the source doped layer 700 is greater than the width of the P-type base region 600, and the two side boundaries of the source doped layer 700 are located outside the two side boundaries of the P-type base region 600.

[0103] In one embodiment, the P-type doped layer and the P-type base region can be P-type gallium nitride, and the source doped layer can be N-type gallium nitride.

[0104] Specifically, N-type gallium nitride can be formed by doping gallium nitride with silicon, while P-type gallium nitride can be formed by doping gallium nitride with magnesium.

[0105] In one embodiment, the doping concentration of P-type elements in the P-type doped layer is greater than the doping concentration of P-type elements in the P-type base region.

[0106] In step S50, etching is performed on the source doped layer to form a deep trench extending into the gallium nitride drift layer, so as to divide the source doped layer into a first source doped region and a second source doped region, divide the P-type base region into a first P-type base region and a second P-type base region, and divide the N-type doped layer into a first N-type doped region and a second N-type doped region.

[0107] In this embodiment, combined with Figure 6 As shown, a deep trench 801 is etched on the source doped layer 700, extending into the first P-type isolation region 320 in the gallium nitride drift layer 200. At this time, the source doped layer 700 is divided into a first source doped region 710 and a second source doped region 720 by the deep trench 801, the P-type base region 600 is divided into a first P-type base region 610 and a second P-type base region 620 by the deep trench 801, and the N-type doped layer 400 is divided into a first N-type doped region 410 and a second N-type doped region 420 by the deep trench 801.

[0108] In one embodiment, the widths of the first source doped region 710 and the second source doped region 720 on both sides of the deep trench 801 are equal.

[0109] In one embodiment, the widths of the first P-type base region 610 and the second P-type base region 620 on both sides of the deep groove 801 are equal.

[0110] In one embodiment, the widths of the first N-type doped region 410 and the second N-type doped region 420 on both sides of the deep trench 801 are equal.

[0111] In step S60, a gate insulating layer is formed on the inner wall of the deep trench, and a gate material layer is formed within the gate insulating layer.

[0112] In this embodiment, combined with Figure 6 As shown, a gate insulating layer 810 is formed on the inner wall of the deep trench 801, combined with... Figure 7 As shown, after the gate insulating layer 810 is formed on the inner wall of the deep trench 801, the gate material layer 820 can be formed in the trench formed by filling the gate insulating layer 810 with gate material.

[0113] In step S70, a dielectric layer is formed on the gate material layer, and a source metal layer is formed that contacts the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region.

[0114] In this embodiment, combined with Figure 7As shown, the dielectric layer 830 is disposed between the source metal layer 840 and the gate material layer 820. Specifically, the dielectric layer 830 and the gate insulating layer 810 form a sealed space, and the gate material layer 820 is located within the sealed space formed by the dielectric layer 830 and the gate insulating layer 810, thereby isolating the gate material layer 820 by the dielectric layer 830 and the gate insulating layer 810.

[0115] In one embodiment, the width of the dielectric layer 830 is greater than the width of the gate insulating layer 810.

[0116] In one embodiment, the thickness of the gate insulating layer 810 is equal to the sum of the thicknesses of the first N-type doped region 410, the first P-type base region 610, and the first source doped region 710.

[0117] In step S80, a drain metal layer is formed on the back side of the gallium nitride substrate.

[0118] In this embodiment, combined with Figure 7 As shown, a drain metal layer 850 can be formed on the back side of a gallium nitride substrate 100 by metal deposition.

[0119] This application also provides a chip that integrates a gallium nitride vertical trench MOSFET device as described in any of the above embodiments.

[0120] In one embodiment, the chip integrates a gallium nitride vertical trench MOSFET device fabricated by the fabrication method described in the above embodiments.

[0121] In this embodiment, the chip includes a chip substrate, on which one or more gallium nitride vertical trench MOSFET devices are disposed. The gallium nitride vertical trench MOSFET devices can be fabricated by the fabrication method in any of the above embodiments, or the gallium nitride vertical trench MOSFET devices in any of the above embodiments can be disposed on the chip substrate.

[0122] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the gallium nitride vertical trench MOSFET device.

[0123] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0124] The beneficial effects of this application embodiment compared with the prior art are as follows: by forming a first P-type isolation region between the gallium nitride drift layer and the gate insulating layer, and forming multiple second P-type isolation regions between the gallium nitride drift layer and the first N-type doped region, and forming multiple second P-type isolation regions between the gallium nitride drift layer and the second N-type doped region, the first P-type isolation region and the second P-type isolation region form a depletion region with the gallium nitride drift layer with only one photomask layer. At the same time, the electric field between the source and drain of the device is homogenized, and the electric field is avoided from concentrating on the gate insulating layer, thereby achieving the purpose of improving the breakdown voltage of the gallium nitride vertical trench MOSFET device.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions is used as an example. In practical applications, the above-described functional areas can be assigned to different doped regions as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above.

[0126] In the embodiments, the doped regions can be integrated into one functional region, or each doped region can exist independently, or two or more doped regions can be integrated into one functional region. The integrated functional region can be implemented using the same type of dopant ion or multiple types of dopant ions. Furthermore, the specific names of each doped region are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the doped region in the fabrication method of the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0127] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gallium nitride vertical trench MOSFET device, characterized by, The gallium nitride vertical trench MOSFET device includes: Gallium nitride substrate; A gallium nitride drift layer is disposed on the front side of the gallium nitride substrate; A first N-type doped region, a second N-type doped region, and a gate insulating layer are disposed on the gallium nitride drift layer; wherein the gate insulating layer is concave, and the first N-type doped region and the second N-type doped region are respectively disposed on both sides of the gate insulating layer; A gate material layer is disposed within a groove of the gate insulating layer; A first P-type base region and a first P-type doped layer are disposed on the first N-type doped region; A second P-type base region and a second P-type doped layer are disposed on the second N-type doped region; The first source doped region and the second source doped region are respectively disposed on the first P-type base region and the second P-type base region; The source metal layer is in contact with the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region; A dielectric layer is disposed between the source metal layer and the gate material layer; A drain metal layer is disposed on the back side of the gallium nitride substrate; A first P-type isolation region is disposed between the gate insulating layer and the gallium nitride drift layer; Multiple second P-type isolation regions are respectively disposed between the first N-type doped region and the gallium nitride drift layer, and between the second N-type doped region and the gallium nitride drift layer; The doping concentration of the second P-type isolation region is negatively correlated with the first spacing distance; Wherein, the first interval distance is the distance between the second P-type isolation zone and the first P-type isolation zone.

2. The gallium nitride vertical trench MOSFET device of claim 1, wherein, Multiple second P-type isolation regions are respectively disposed on both sides of the first P-type isolation region, and the doping concentrations of the first P-type isolation region and the second P-type isolation region are equal.

3. The gallium nitride vertical trench MOSFET device of claim 1, wherein, The spacing width between the plurality of second P-type isolation zones on the first side of the first P-type isolation zone is equal; The spacing width between the plurality of second P-type isolation zones on the second side of the first P-type isolation zone is equal.

4. The gallium nitride vertical trench MOSFET device of claim 1, wherein, The spacing width between multiple second P-type isolation zones is negatively correlated with the second spacing distance; Wherein, the second interval distance is the distance between the second P-type isolation zone and the first P-type isolation zone.

5. The gallium nitride vertical trench MOSFET device of claim 1, wherein, The width of the second P-type isolation zone is negatively correlated with the second interval distance; Wherein, the second interval distance is the distance between the second P-type isolation zone and the first P-type isolation zone.

6. The gallium nitride vertical trench MOSFET device of any of claims 1-5, wherein, The width of the first P-type isolation region is greater than the width of the second P-type isolation region; and / or The thickness of the first P-type isolation region and the second P-type isolation region are equal.

7. The gallium nitride vertical trench MOSFET device of any of claims 1-4, wherein, The number of second P-type isolation zones on the first side of the first P-type isolation zone is equal to the number of second P-type isolation zones on the second side of the first P-type isolation zone.

8. A method of fabricating a gallium nitride vertical trench MOSFET device, comprising: The preparation method is used to prepare the gallium nitride vertical trench MOSFET device as described in any one of claims 1-7, comprising: A gallium nitride drift layer is formed on the front side of the gallium nitride substrate; A photomask is used to cover the front side of the gallium nitride drift layer to implant P-type dopant ions in a designated area on the front side of the gallium nitride drift layer to form a first P-type isolation region and a plurality of second P-type isolation regions; wherein, the plurality of second P-type isolation regions are respectively disposed on both sides of the first P-type isolation region; An N-type doped layer is formed on the gallium nitride drift layer; A P-type doped layer is formed on the N-type doped layer, and a P-type base region and a source doped layer are formed within the P-type doped layer, dividing the P-type doped layer into a first P-type doped layer and a second P-type doped layer. Etching is performed on the source doped layer to form a deep trench extending into the gallium nitride drift layer, so as to divide the source doped layer into a first source doped region and a second source doped region, divide the P-type base region into a first P-type base region and a second P-type base region, and divide the N-type doped layer into a first N-type doped region and a second N-type doped region. A gate insulating layer is formed on the inner wall of the deep trench, and a gate material layer is formed within the gate insulating layer; A dielectric layer is formed on the gate material layer; A source metal layer is formed in contact with the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region; wherein, the dielectric layer is disposed between the source metal layer and the gate material layer; A drain metal layer is formed on the back side of the gallium nitride substrate.

9. A chip, characterized by The chip integrates a gallium nitride vertical trench MOSFET device as described in any one of claims 1-7; or includes a gallium nitride vertical trench MOSFET device prepared by the preparation method described in claim 8.

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