Time-to-digital converter

Abstract

A time-to-digital converter circuit (700, 700) is disclosed that includes a plurality of delay stages (810-N) connected to form a delay line (815), a plurality of event counters (860-N), an encoder circuit (890) for triggering the delay line, and a binning circuit (845) for associating an event with an event counter from the plurality of event counters. The binning circuit selects an event counter based on a signal from the delay line, and wherein the encoder circuit is configured to sequentially trigger different delay stages of the plurality of delay stages. Also disclosed is a time-of-flight sensor implementing the time-to-digital converter circuit, and associated apparatuses and methods.

Description

Technical Field

[0001] This disclosure belongs to the field of time-to-digital converters, and specifically relates to time-to-digital converter circuits for time-of-flight sensors. Background Technology

[0002] Devices such as smartphones and tablets can incorporate time-of-flight sensors to detect the distance to a target. This distance determination can be useful, for example, for accurately adjusting the focus of a camera implemented on the device to enable focused imaging of a target within a certain distance range from the camera.

[0003] A time-of-flight sensor can be implemented using one or more radiation-emitting elements configured to emit radiation toward a target. Such a time-of-flight sensor can also incorporate one or more radiation-sensitive elements for detecting radiation reflected from the target. The time-of-flight measurement (e.g., the round-trip time of radiation emitted from the radiation-emitting element and received at the radiation-sensitive element) can indicate the distance to the target.

[0004] To accurately determine the distance to a target, precise and accurate measurement of time of flight is necessary. Some time-of-flight sensors implement arrays of single-photon avalanche diodes (SPADs) for detecting reflected radiation. Such time-of-flight sensors can implement circuitry to indicate the intensity of reflected radiation detected by the SPAD array within a specific time period.

[0005] Some such time-of-flight sensors implement time-to-digital converters, which can be configured to provide a digital representation of elapsed time, and in some cases can be used to form histogram-based time-of-flight sensors.

[0006] Any errors in the digital representation of elapsed time from the time-to-digital converter can affect the accuracy of distance determination for a target. Time-to-digital converters are known to exhibit differential nonlinearity errors, which can be caused at least in part by mismatches between devices, propagation delays, and other layout-related effects within the circuitry implementing the time-to-digital converter.

[0007] To address these issues, some existing time-to-digital converters have employed large-scale devices to mitigate the effects of device mismatch. However, such large devices can increase the overall die size, leading to higher costs and increased power consumption. Other existing solutions may require complex circuitry or advanced post-processing of data to attempt to correct or compensate for errors that may be caused by device mismatch.

[0008] Therefore, it is desirable to provide an accurate, low-cost, and low-complexity time-to-digital converter suitable for time-of-flight sensors. Furthermore, it is desirable to provide a method for reducing errors in such a time-to-digital converter.

[0009] Therefore, the purpose of at least one embodiment of at least one aspect of this disclosure is to eliminate or at least mitigate at least one of the aforementioned disadvantages of the prior art. Summary of the Invention

[0010] This disclosure belongs to the field of time-to-digital converters, and specifically relates to time-to-digital converters for time-of-flight sensors, such as those used to determine the distance to a target in a camera-based device (such as a smartphone).

[0011] According to a first aspect of this disclosure, a time-to-digital converter circuit is provided, comprising: a plurality of delay stages connected to form a delay line; a plurality of event counters; an encoder circuit for triggering the delay line; and a binning circuit for associating events with event counters from the plurality of event counters. The encoder circuit is configured to sequentially trigger different delay stages among the plurality of delay stages. The binning circuit selects an event counter based on a signal from the delay line. Advantageously, sequentially triggering different delay stages among the plurality of delay stages avoids consecutively associating the same delay stage with the same event counter. Therefore, system errors that may arise from mismatches between components within the time-to-digital converter (which can manifest as differential nonlinearity in the performance of the time-to-digital converter) can be mitigated by averaging the effects of such errors across the plurality of event counters.

[0012] The encoder circuit can be configured to generate a first offset relative to the first stage of the delay line. The first offset may correspond to the entry point for triggering the delay line.

[0013] Advantageously, this encoder provides a means to supplement existing delay-line based time-to-digital converter circuits without requiring extensive redesign. That is, the vast majority of the existing delay-line based time-to-digital converter circuitry can remain unchanged; only the delay-line triggering circuitry needs modification to implement the encoder.

[0014] Furthermore, this encoder can be implemented entirely using digital circuitry without adding or modifying any analog circuitry. This allows the encoder circuitry to be easily adapted to and portable across different technology nodes.

[0015] The encoder circuit may include a one-hot converter configured to convert the output from the counter into data corresponding to a first offset. For example, the one-hot converter may be a unary or binary-to-one-hot converter. For instance, the counter may be a binary counter, and the converter may be a binary-to-one-hot converter.

[0016] The compartmentalization circuit may include decoder circuitry for generating a second offset for selection of the offset event counter.

[0017] The encoder circuit can be configured to provide data to the decoder circuit. For example, the encoder circuit can be configured to provide the output of a counter to the decoder circuit. A second offset can be used to compensate for the first offset. The second offset can have the same magnitude but opposite sign as the first offset; for example, for a first offset of +31, the second offset could be -31.

[0018] The decoder may include multiplexer circuitry configured to associate detected events with any of a plurality of event counters. The configuration of the multiplexer circuitry system may correspond to a second offset.

[0019] The compartmentalization circuit may include a thermometer-to-one-hot code converter configured to convert a signal from a delay line into a signal for selecting a single event counter. For example, the compartmentalization circuit may include a unary code-to-one-hot code converter configured to convert a signal from a delay line into a signal for selecting a single event counter.

[0020] Multiple event counters can be configured to correspond to a histogram memory. Each event counter may include a ripple counter, such as an n-bit ripple counter.

[0021] Each delay stage may include a delay element configured to receive a regulated current. The timing of the delay element may depend on the regulated current.

[0022] According to a second aspect of the invention, a time-of-flight sensor is provided, comprising: an array of single-photon avalanche diodes (SPADs); and at least one time-to-digital converter circuit according to a first aspect. The array of SPADs is coupled to at least one time-to-digital converter circuit, and the at least one time-to-digital converter circuit is configured to associate SPAD events with event counters from a plurality of event counters.

[0023] The time-of-flight sensor may include multiple time-to-digital converter circuits; and a global delay-locked loop (DLL) configured to provide control current to each of the multiple time-to-digital converter circuits. The propagation delay of each delay stage may be limited by the control current.

[0024] According to a third aspect of the invention, an apparatus is provided, comprising: a time-of-flight sensor according to a second aspect; a camera; and processing circuitry coupled to the time-of-flight sensor and the camera. The processing circuitry may be configured to adjust the focus of the camera and / or adjust the image captured by the camera in response to a distance to a target determined by the time-of-flight sensor.

[0025] The device can be one of the following: a smartphone; a cellular phone; a tablet computer; a laptop computer, etc.

[0026] According to a fourth aspect of the present invention, a method for reducing errors in a time-to-digital converter circuit is provided, the time-to-digital converter circuit including a delay line, a compartmentalization circuit, and a plurality of event counters, wherein the method includes:

[0027] Configure triggers for the delay line to sequentially trigger different delay stages of the delay line; and

[0028] Configure the compartmentalization circuit to select an event counter from multiple event counters based on the signal from the delay line.

[0029] The method may include the step of configuring decoder circuitry to generate an offset for selecting an event counter.

[0030] The above description of the invention is intended to be exemplary only and not restrictive. This disclosure includes one or more corresponding aspects, embodiments, or features, either alone or in various combinations, whether specifically stated (including claimed) in such combination or individually. It should be understood that the features defined above according to any aspect of this disclosure or hereinafter associated with any particular embodiment of this disclosure may be used alone or in combination with any other defined features in any other aspect or embodiment, or to form further aspects or embodiments of this disclosure. Attached Figure Description

[0031] These and other aspects of this disclosure will now be described by way of example only with reference to the accompanying drawings, in which:

[0032] Figure 1 A global delay line loop is depicted that provides control current to multiple time-to-digital converters;

[0033] Figure 2 The implementation of the time-to-digital converter is described;

[0034] Figure 3 A high-level schematic diagram of a time-to-digital converter is depicted;

[0035] Figure 4 A timing diagram illustrating the measurement cycle of the time-to-digital converter is depicted;

[0036] Figure 5 The implementation details of the ideal delay line are described;

[0037] Figure 6 The implementation details of the non-ideal delay line are described;

[0038] Figure 7 An overview of a time-to-digital converter according to an embodiment of the present invention is described;

[0039] Figure 8 A time-to-digital converter according to an embodiment of the present invention is described;

[0040] Figure 9 A schematic diagram of an encoder and decoder for a time-to-digital converter according to an embodiment of the present invention is depicted;

[0041] Figure 10 A schematic diagram of the decoder logic is shown;

[0042] Figure 11 The delay line level and clock buffer logic according to an embodiment of the present invention are described;

[0043] Figure 12 The implementation details of the delay line implementation according to an embodiment of the present invention are described;

[0044] Figure 13 An example apparatus according to an embodiment of the present invention is depicted; and

[0045] Figure 14 A method for reducing errors in a time-to-digital converter circuit according to an embodiment of the present invention is described. Detailed Implementation

[0046] Figure 1 An arrangement 100 is depicted, including a global delay line loop (DLL) 110 configured to provide control current to multiple time-to-digital converters (TDCs) 120-0, 120-1, ..., 120-N. Such an arrangement 100 can be implemented, for example, in a time-of-flight sensor. The time base is efficiently generated by the global DLL 110, which is configured to generate regulating current to control the delay lines of each TDC 120-0, 120-1, ..., 120-N. See below for reference. Figure 5In more detail, regulating the current can control an NMOS device to limit the propagation delay of the delay stage that forms the delay line.

[0047] Figure 2 An example implementation of TDC 200 is depicted. TDC 200 can correspond to Figure 1 One of the TDCs 120-0, 120-1, ..., 120-N described in the text.

[0048] An example implementation of TDC 200 includes a first sub-block 205. The first sub-block includes multiple delay stages 210-0, 210-1, 210-2, 210-3, ..., 210-N coupled to form a delay line 215. A regulating current 220 is provided to the delay line 215, as referenced. Figure 1 and Figure 5 As described. The regulating current 220 limits the timing of the delay line 215.

[0049] A trigger clock signal 225 is provided to trigger the delay line 215. In use, the measurement window is triggered by the rising edge of the trigger clock signal 225, which defines the start of the measurement period.

[0050] The rising edge effectively propagates through delay line 215. The propagation delay for each element is limited by the regulating current 220 provided by global DLL 110. The propagation delay is regulated to a value, for example a defined value, that represents the least significant bit (LSB) of TDC 200.

[0051] The output of delay line 215 is a thermometer code, such as a unary code. That is, the output of delay line 215 may include, for example, a code corresponding to the number of delay stages through which the trigger clock signal 225 has propagated. For example, the output of delay line 215 may be sequentially: 0000…0, 1000…0, 1100…0, 1110…0, …, 1111…0, …, 1111…1.

[0052] An example implementation of TDC 200 includes a second sub-block 230. The second sub-clock 230 includes a thermometer-to-unique-thermal code converter 235. The thermometer-to-unique-thermal code converter 235 is configured to convert thermometer code at the output of delay line 215 into unique-thermal code, wherein only a single bit among a plurality of bits within the unique-thermal code is asserted. For example, in some embodiments, the thermometer-to-unique-thermal code converter 235 can convert input thermometer code 0000…0, 1000…0, 1100…0, 1110…0, …, 1111…0, …, 1111…1 into output unique-thermal code 0000…0, 1000…0, 0100…0, 0010…0, …, 0001…0, …, 1111…1. In some embodiments... Figure 2In the example, the thermometer-to-isothermal code converter 235 is formed by multiple dual-input AND gates, each with an inverting input.

[0053] An example implementation of TDC 200 includes a third sub-block 240. The third sub-block 240 includes compartmenting circuitry 245, such as compartmenting logic. The thermometer-to-isothermal code converter 235 of the second sub-block 230 may provide a gating signal to the compartmenting circuitry 245 as follows.

[0054] The compartmentalization circuit 245 consists of multiple latches 250-0, 250-1, 250-2, 250-3, ..., 250-N, which are selected by a unique thermal code (e.g., an active strobe signal) from the thermometer-to-unique thermal code converter 235. For simplicity, in Figure 2 In the example implementation, each latch 250-0, 250-1, 250-2, 250-3, ..., 250-N is represented as a switch. Due to the unique thermal code from the thermometer-to-unique thermal code converter 235, only a single latch 250-0, 250-1, 250-2, 250-3, ..., 250-N is enabled at a time. That is, the unique thermal code can be provided to the enable input of multiple latches 250-0, 250-1, 250-2, 250-3, ..., 250-N, such that only one latch is effectively transparent at a time.

[0055] The second input (e.g., D input) of each of the multiple latches 250-0, 250-1, 250-2, 250-3, ..., 250-N can be connected to one or more signals from a radiation sensor. In the example of a time-of-flight sensor, the second input of each of the multiple latches 250-0, 250-1, 250-2, 250-3, ..., 250-N can be connected to an array of single-photon avalanche detectors (SPADs). That is, the SPAD event signal 255 can be connected to each of the multiple latches 250-0, 250-1, 250-2, 250-3, ..., 250-N in the compartment circuit 245. Therefore, the SPAD event signal 255 will be coupled to only one transparent latch 250-1, 250-2, 250-3, 250-4, ..., 250-N at a time.

[0056] An example implementation of TDC 200 includes a fourth subblock 265. The fourth subblock 265 includes a histogram memory. The histogram memory can be implemented as multiple event counters 260-0, 260-1, 260-2, 260-3, ..., 260-N. Figure 2In the example, each event counter 260-0, 260-1, 260-2, 260-3, ..., 260-N (e.g., each bin) is implemented as a ripple counter. Each of the multiple event counters 260-0, 260-1, 260-2, 260-3, ..., 260-N is coupled to the output of an associated latch from a plurality of latches 250-0, 250-1, 250-2, 250-3, ..., 250-N. As described above, the SPAD event signal 255 will be coupled to only one transparent latch 250-0, 250-1, 250-2, 250-3, 250-4, ..., 250-N at a time, and thus can propagate to the associated event counters in the multiple event counters 260-0, 260-1, 260-2, 260-3, ..., 260-N. Therefore, in use, the compartmentalization circuit classifies SPAD events into the correct event counters 260-0, 260-1, 260-2, 260-3, ..., 260-N.

[0057] For the sake of completeness, Figure 3 Depicting Figure 2 The TDC 200 includes: a first sub-block 205, which includes a delay line 215; a second sub-block 230, which includes a thermometer-to-unique-code converter 235; a third sub-block 240, which includes a compartmentalization circuit 245; and a fourth sub-block 265, which includes a histogram memory implemented as a plurality of event counters 260-0, 260-1, 260-2, 260-3, ..., 260-N. Figure 2 The signals between each sub-block 205, 230, 240, and 250 are depicted. For example, multiple outputs 270 from the delay line are represented as "DL_OUT". <n>In the example implementation, the delay line can include 32 delay stages, and therefore the output range of 270 can be from "DL_OUT". <0> "to "DL_OUT <31> The output 270 from the first sub-block 205 provides the thermometer code as the input to the second sub-block 230.

[0058] exist Figure 3 In the example implementation, output 275 from the second sub-block 230 is provided as a one-hot code to the third sub-block 240 as input; for example, only a single output of multiple outputs 275 is asserted. Output 375 from the second sub-block 230 is represented as "DL_OUT_HOT1". <n>".

[0059] The third sub-block 240 to the fourth sub-block 265 are provided as "BIN" <0> "To "BIN <n>Multiple signals 280. As described above, the SPAD event signal 255 will be coupled to an event counter once through the compartment circuit 245 of the third sub-block 240.

[0060] Figure 4 It is a timing diagram depicting the measurement cycle of the time-to-digital converter 200.

[0061] The rising edge of the trigger clock signal 225 (denoted as "TRIGGER_CLK") propagates through delay line 215, thus incrementing the thermometer code at the output each time the rising edge of the trigger clock signal 225 passes through delay stages 210-0, 210-1, 210-2, 210-3, ..., 210-N. Therefore, the thermometer-to-unique-thermal-code converter 235 generates a propagating "1", which limits the gating window of the corresponding event counter at the compartment circuit 245. That is, DL_OUT_HOT1. <0> Assertioned, then DL_OUT_HOT1 <1> Asserted and DL_OUT_HOT1 <0> Negate the assertion, and for all DL_OUT_HOT1 <0> To DL_OUT_HOT1 <n>And so on.

[0062] The propagation "1" enables switches such as latches 250-0, 250-1, 250-2, 250-3, ..., 250-N, thereby coupling the SPAD event signal 255 (represented as "SPAD_EVENT") to the histogram memory of the fourth sub-block 265. The SPAD event signal 255 is coupled to the SPAD array.

[0063] For illustrative purposes, Figure 5 The implementation details of the ideal delay line are described.

[0064] As described above, the TDC 200 implements a delay line 215 to define the LSB of the TDC 200. Each delay stage 210-0, 210-1, 210-2, 210-3, ..., 210-N of the delay line 200 includes two inverters 510, 520. Each inverter 510, 520 uses a current-starved NMOS device 530 to control the propagation delay of the delay line 215, such as the LSB of the TDC. Multiple delay stages 210-0, 210-1, 210-2, 210-3, ..., 210-N are coupled in series to construct the delay line 215 of the TDC 200.

[0065] Under ideal conditions, for example, for a TDC 200 unaffected by device mismatch or layout-related effects, each delay stage 210-0, 210-1, 210-2, 210-3, ..., 210-N will have exactly the same propagation delay. Therefore, using a control signal (e.g., from denoted as "DL_OUT")... <n>The output 270 of the delay line controls the compartmentalization circuit 245 to apply a uniformly distributed number of events during the measurement period. That is, the propagation delay (LSB) associated with each delay level 210-0, 210-1, 210-2, 210-3, ..., 210-N will be equal, and therefore the code density test of the TDC will result in a uniformly distributed count of the histogram data 540. In other words, all event counters in the histogram memory will be filled to the same count level, and DNL will not be detected.

[0066] In practice, delay line 215 is non-ideal, at least in part, due to device mismatch and / or layout-related effects. Generally, the smaller the device, the greater the error due to mismatch. Furthermore, due to the large TDC required for large pixel arrays, potentially covering hundreds or even thousands of areas, small devices are mandatory to ensure cost-effectiveness and low power consumption.

[0067] If a non-ideal delay line control signal is used to control the compartmentation circuit, the LSB error of the delay line will be projected onto the compartmentation counting error in the histogram memory, such as the event counter error. This is in Figure 6 The description in the middle, Figure 6 The diagram illustrates a non-ideal delay line, such as one with some degree of device mismatch and / or layout-related effects, where the propagation delay (LSB) of each delay level can be different. Therefore, the code density test of TDC will result in a non-uniform distribution of the histogram data 640 counts.

[0068] Figure 7 An overview of a TDC circuit 700 according to an embodiment of the present invention is described. Similar to... Figure 2 The TDC 200 and TDC circuit 700 are based on a delay stage, and the time base (LSB) is limited by an NMOS current-controlled delay element due to the regulation current provided by the global DLL. However, compared with... Figure 2 In contrast, the counter 710 and the first offset circuit 720 can be configured to provide a means of incrementally injecting a clock signal into each stage of the delay line, for example, to delay line stage 0 of TDC 740, then stage 1, then stage 2, and so on. That is, the entry point of the trigger signal into the delay line can be incremented by applying a first offset generated by the counter 710 and the first offset circuit 720. Furthermore, an additional second offset circuit 730 can be added to compensate for the effect of the first offset and ensure that SPAD events are routed to the correct event counter in the histogram memory 750, as referenced. Figure 8 To describe in more detail: The first offset circuit can apply a positive first offset, and the second offset circuit can apply a negative second offset, and vice versa.

[0069] Figure 8 A TDC circuit 800 according to an embodiment of the present invention is depicted. The TDC circuit 800 includes a plurality of delay stages 810-0, 810-1, 810-2, 810-3, ..., 810-N coupled to form a delay line 815. A regulating current is provided to the delay line 815, as referenced... Figure 2 The example implementation is described, where the adjustment current limits the timing of the delay line 815.

[0070] A trigger clock signal 825 is provided to trigger the delay line 815. In use, the measurement window is triggered by the rising edge of the trigger clock signal 825, which defines the start of the measurement period.

[0071] The rising edge effectively propagates through delay line 815. The propagation delay for each element is limited by a regulating current provided by a global DLL (e.g., global DLL 110). The propagation delay is adjusted to a value, such as a defined value, that represents the least significant bit (LSB) of the TDC circuit 800.

[0072] and Figure 2 Compared to TDC 200, TDC circuit 800 includes encoder circuit 890, which is configured to sequentially trigger different delay stages among a plurality of delay stages 810-0, 810-1, 810-2, 810-3, ..., 810-N. Encoder circuit 890 is used to generate a control signal defining the entry point of delay line 815. Encoder circuit 890 is configured to generate a count defining an offset relative to a first delay stage 810-0 of delay line 815. The offset is used to define the entry point of delay line 815. The count is also provided to decoder circuit 895 to compensate for the offset. Thus, encoder circuit 890 can be configured to sequentially trigger different delay stages among a plurality of delay stages 810-0, 810-1, 810-2, 810-3, ..., 810-N, as described in more detail below.

[0073] The output of delay line 815 is a thermometer code, such as a unary code. That is, the output of delay line 815 may include, for example, a code corresponding to the number of delay stages through which the trigger clock signal 825 has propagated.

[0074] The TDC circuit 800 includes a thermometer-to-unique-thermal code converter 835. The thermometer-to-unique-thermal code converter 835 is configured to convert thermometer code at the output of delay line 815 into unique-thermal code, wherein only a single bit of a plurality of bits within the unique-thermal code is asserted. Figure 8 In an example embodiment, the thermometer-to-unique-thermal code converter 835 is formed by a plurality of dual-input AND gates, each having an inverting input. Thus, the signal from the delay line (e.g., the thermometer code subsequently converted to unique-thermal code) can be used by the compartment circuit 425 to select an event counter, as described below.

[0075] Example embodiments of the TDC circuit 800 include a compartmentalization circuit 845. A thermometer-to-isothermal code converter 835 can efficiently provide a strobe signal to the compartmentalization circuit 845 as follows.

[0076] The compartmentalization circuit 845 consists of multiple latches 850-0, 850-1, 850-2, 850-3, ..., 850-N, which are selected by a unique thermal code (e.g., an active strobe signal) from the thermometer-to-unique thermal code converter 835. For simplicity, in Figure 8 In this embodiment, each latch 850-0, 850-1, 850-2, 850-3, ..., 850-N is represented as a switch. Due to the unique thermal code from the thermometer-to-unique thermal code converter 835, only a single latch 850-0, 850-1, 850-2, 850-3, ..., 850-N is enabled at a time. That is, the unique thermal code can be provided as an enable input to multiple latches 850-0, 850-1, 850-2, 850-3, ..., 850-N, such that only one latch is effectively transparent at a time.

[0077] The second input (e.g., D input) of each of the multiple latches 850-0, 850-1, 850-2, 850-3, ..., 850-N can be connected to the SPAD array. That is, the SPAD event signal 855 can be connected to each of the multiple latches 850-0, 850-1, 850-2, 850-3, ..., 850-N of the compartment circuit 845. Therefore, the SPAD event signal 855 will be coupled to only one transparent latch 850-1, 850-2, 850-3, 850-4, ..., 850-N at a time.

[0078] The compartmentalization circuit 845 also includes a decoder circuit 895. The decoder circuit is configured to apply an offset to compensate for the offset used to define the entry point of the delay line 815, as referenced. Figure 9 and Figure 10 To describe in more detail.

[0079] The TDC circuit 800 also includes a histogram memory. The histogram memory can be implemented as multiple event counters 860-0, 860-1, 860-2, 860-3, ..., 860-N. Figure 8 In this embodiment, each event counter is implemented as a ripple counter. Each of the plurality of event counters 860-0, 860-1, 860-2, 860-3, ..., 860-N is coupled to the output from the decoder circuit 895. As described above, the SPAD event signal 855 will be coupled to only one transparent latch 850-0, 850-1, 850-2, 850-3, 850-4, ..., 850-N at a time, and thus can propagate through the decoder circuit 895, where an offset can be applied to route the SPAD event signal 855 to the associated event counter among the plurality of event counters 860-0, 860-1, 860-2, 860-3, ..., 860-N. Therefore, in use, taking into account the entry point of delay line 815, the sub-marketing logic classifies SPAD events into the correct event counters 860-0, 860-1, 860-2, 860-3, ..., 860-N.

[0080] Figure 9 An embodiment of the invention is depicted. Figure 8 More details about the TDC circuit 800, especially the encoder circuit 890 and decoder circuit 895. For simplicity, in Figure 9 In this circuit, the delay line 815, the thermometer-to-isothermal code converter 835, and multiple latches 850-0, 850-1, 850-2, 850-3, ..., 850-N are represented as a single block, denoted as TDC 905.

[0081] Encoder circuit 890 includes counter 910. In some embodiments, counter 910 may be a ripple counter. Figure 9 In the example embodiment, counter 910 is a 5-bit counter that provides a 5-bit binary output 915. It should be understood that in other embodiments, the counter may have more or less than 5 bits, and therefore may provide an output 915 including more or less than 5 bits.

[0082] The value of output 915 is used to limit the offset of the count from the first delay stage of the TDC circuit 900, for example, from Figure 8 The delay stage 810-0 is offset. Output 915 is connected to a binary-to-one-hot code converter 920. Output 925 from the binary-to-one-hot code converter provides triggering to the delay line of the TDC circuit 900 (e.g., a block denoted as TDC 905). Continuing with the example embodiment of the 5-bit counter 910, output 925 from the binary-to-one-hot code converter 920 is a 32-bit output, where only a single bit of the 32-bit output 925 is asserted based on the current count of the 5-bit counter 910. Return to Reference Figure 8 This is depicted as the sequence "1,0,0,0,…,0", where arrow 875 indicates the propagation of "1", such that subsequent outputs will be "0,1,0,0,…,0" followed by "0,0,1,0,…,0", and so on. Therefore, the encoder circuit 890 operates in a manner similar to a shift register. The 32-bit output 920 defines a stage for the delay line, which will be used as the first stage, such as the entry point for the delay line. See below for reference. Figure 11 Describe the delay stage in more detail (e.g., Figure 8 The implementation of the delay level (810-N).

[0083] Figure 9 The example embodiment also shows a multiplexer 930 for defining a source for incrementing the counter 910. For example, an internal clock source or an external clock source (denoted as INT_CLK and EXT_CLK, respectively) can be provided to increment the counter 910.

[0084] The output 915 from counter 910 is also provided as an input to decoder circuit 895. Decoder circuit 895 can effectively operate as a multiplexer, shifting latches in the cascading circuit (e.g., such as...) depending on the output 915 from counter 910. Figure 8 The latches shown (850-0, 850-1, 850-2, 850-3, 850-4, ..., 850-N) receive the input signals. This continues with a 5-bit counter 910. Figure 9 In an example embodiment, decoder circuit 895 can shift all input signals from latches in the compartment circuit from 0 to 31 based on the output 915 from counter 910. For example:

[0085] - If the value of output 915 from counter 905 is 0b00000, then the input of decoder circuit 895... <n>This can correspond to the output of the decoder circuit 955. <n>;

[0086] - If the value of output 915 from counter 905 is 0b00001, then the input of decoder circuit 985... <n>This can correspond to the output of the decoder circuit 955. <n-1>;

[0087] - If the value of output 915 from counter 905 is 0b11111, then the input of decoder circuit 895... <n>This can correspond to the output of the decoder circuit 955. <n-31>.

[0088] The output 940 from the decoder block 895 is connected to the histogram memory 950, such as multiple event counters 860-0, 860-1, 860-2, 860-3, ..., 860-N.

[0089] Figure 10 An example implementation of decoder circuit 895 is shown. A 5-bit binary output 915 from an incrementing counter 910 provides control over decoder circuit 895, selecting which input 935 is connected to which output 940. Thus, decoder circuit 895 operates as a 1 to N multiplexer, configured to connect the input to any one of all possible outputs.

[0090] It should be understood that this is for illustrative purposes only. Figure 9 The example implementation uses a 32-bit encoder 890, a 32-bit decoder 895, and a 5-bit counter 905, which can enable other dimensions, for example, with fewer or more bits.

[0091] As described above, delay line 815 consists of N delay stages 810-0, 810-1, 810-2, 810-3, ..., 810-N, each stage having a propagation delay controlled by a control current provided by a global DLL (e.g., global DLL 110). In embodiments of the invention, feedback from the last delay stage 810-N to the first delay stage 810-0 can be used to form a loop in a manner similar to a ring oscillator. Delay line 815 includes an even number of stages.

[0092] Figure 11 A delay line stage 1000 and a clock buffer logic 1070 according to an embodiment of the present invention are depicted. The delay line stage 1000 may correspond to Figure 8 and Figure 9 Any delay level among the delay levels 810-0, 810-1, 810-2, 810-3, ..., 810-N.

[0093] Delay line stage 1000 includes a first inverter 1005 and a second inverter 1010 coupled to provide delay. The input 1015 of delay line stage 1000 is coupled to the preceding delay line stage. The output 1020 of delay line stage 1000 is coupled to the next delay line stage.

[0094] A bias voltage 1020 is provided to the gate of transistor 1025, which is coupled to the power supply of the first inverter 1005 and the second inverter 1010. Thus, the bias voltage 1020 can control the propagation delay of the first inverter 1005 and the second inverter 1010. In some embodiments, the bias voltage 1020, or the current used to derive the bias voltage 1020, may be provided by a global DLL (such as global DLL 110).

[0095] In some embodiments, delay line stage 1000 is coupled to clock buffer logic 1070. Clock buffer logic 1070 may include buffer 1075, which is configured to buffer input clock signal 1080 to provide buffered output clock signal 1085. In some embodiments, bias voltage 1020 may be provided to the gate of transistor 1090, which is a power supply coupled to buffer 1075. Thus, bias voltage 1020 may also control the propagation delay of buffer 1075.

[0096] The delay line stage 1000 also includes a multiplexer circuit 1030. A first multiplexer control input 1035 is coupled to the gate of a transistor 1045, wherein the first multiplexer control input 1035 is configured to couple the input of a first inverter 1005 to the output from the previous stage of the delay line.

[0097] A second multiplexer control input 1040, inverted from the first multiplexer control input 1035, is coupled to the gate of a transistor 1055, wherein the second multiplexer control input 1040 configures the transistor 1055 to couple the input of the first inverter 1005 to an input clock signal 1060. In some embodiments, the input clock signal 1060 is a buffered output clock signal 1085.

[0098] Therefore, the first multiplexer control input 1035 and the second multiplexer control input 1040 can select whether the delay line stage 1000 operates as an entry point for a clock signal (e.g., the input clock signal 1060 is the output of the clock buffer logic 1050), or select whether the delay line stage 1000 operates as a delay line stage, wherein the input 1015 from the previous delay line stage propagates through the delay line stage with a delay primarily defined by the first inverter 1005 and the second inverter 1010.

[0099] In other words, in some embodiments:

[0100] - If multiplexer control input 1035 "N_EN" = 0, stage 1000 operates as an entry point element. The input from the previous delay line stage is disconnected, and clock input 1015 is connected to stage 1000. The rising edge at the clock input propagates the signal into delay line stage 1000, eventually setting all elements to 1. The falling edge of the clock resets the delay line, causing all elements to 0.

[0101] - If multiplexer control input 1035"N_EN" = 1, then delay line 1000 operates as a delay stage. Inputs from the previous stage are delayed and sent to the output.

[0102] Another inverter 1095 is coupled to the output of the first inverter 1005. The output from the other inverter 1095 is the output of the thermometer-to-unique-code converter from the delay line stage 1000 to the TDC, for example, as... Figure 3 The Chinese representation is "DL_OUT" <n>"The output of the delay line is 270".

[0103] Figure 12 Implementation details of a delay line according to an embodiment of the present invention are depicted. Each element of the delay line 1200 includes the components described above. Figure 11 The described delay line level 1000. That is, each delay level of delay line 1200 has additional inputs for programming the delay level as an entry level or a follower level.

[0104] In some embodiments, the entry levels are sequentially incremented. Thus, in the initial cycle (cycle 1), the sequence of delay levels can be level 1 through level 31. In the subsequent cycle (cycle 2), the sequence of delay levels can be level 2 through level 1. In the subsequent cycle (cycle 3), the sequence of delay levels can be level 3 through level 2, and so on. In this way, each delay level functions at least once as level 1, level 2, level 3, ... As a result, the LSB error of each level will reach an average value. This mitigates the impact of device mismatch and layout-related LSB errors.

[0105] Therefore, in the case of non-ideal components where the propagation delay (LSB) may differ at each delay stage, the LSB error is minimized due to the linear increase in the entry stage as described above. In some embodiments, the integration period needs to be an M×series number, where M is an integer.

[0106] Therefore, the code density test of the TDC according to an embodiment of the present invention will result in a uniform distribution of counts in histogram 1220.

[0107] Figure 13 A device 1300 according to an embodiment of the present invention is depicted. For illustrative purposes only, device 1300 is a smartphone. It should be understood that the time-to-digital converter circuit described herein is also applicable to other devices, such as cellular phones, tablet computers, laptops, or portable devices.

[0108] The device includes a time-of-flight sensor 1310. The time-of-flight sensor includes an array 1315 of single-photon avalanche diodes (SPADs) and multiple time-to-digital converter circuits 1320. The time-to-digital converter circuits 1320 may be as described above. Figure 7 , Figure 8 and Figure 9 The described time-to-digital converter circuits 700, 800, and 900. An array 1315 of SPADs is coupled to multiple TDC circuits 1320. Each of the multiple TDC circuits 1320 is configured to associate a SPAD event with an event counter from multiple event counters.

[0109] Example device 1300 also includes a camera 1325 and processing circuitry 1330 coupled to time-of-flight sensor 1310 and camera 1325. In some embodiments, processing circuitry 1330 is configured to adjust the focus of camera 1325 and / or adjust images captured by camera 1325 in response to the distance to a target determined by time-of-flight sensor 1310.

[0110] Figure 14 A method for reducing errors in a time-to-digital converter circuit is described, the time-to-digital converter circuit including a delay line, a cascading circuit, and a plurality of event counters. The method includes step 1410 of configuring triggers for the delay line to sequentially trigger different delay stages of the delay line. The method also includes step 1420 of configuring the cascading circuit to select an event counter from the plurality of event counters based on signals from the delay line. It should be understood that, in embodiments, either step may be performed first, or both steps may be performed simultaneously.

[0111] Although this disclosure has been described with reference to specific embodiments as described above, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. Modifications and substitutions will be able to be made by those skilled in the art in light of this disclosure, and such modifications and substitutions are considered to fall within the scope of the appended claims. Each feature disclosed or shown in this specification may be incorporated into any embodiment, either alone or in any suitable combination with any other feature disclosed or shown herein.

[0112] List of reference numerals

[0113] 100 layout with 215 delay lines

[0114] 110DLL 220 Adjustable Current

[0115] 120-N TDC 225 trigger clock signal

[0116] 200TDC 35 230 Second Sub-block

[0117] 205 First Sub-block 235 Thermometer to Unique Thermal Code Converter

[0118] 210-N delay stage 240 third sub-block

[0119] 245 compartmentalized circuit 915 output

[0120] 250-N latch 920 binary to unique hot code converter

[0121] 255SPAD event signal 925 output

[0122] 260-N event counter 35 930 multiplexer

[0123] 265 Fourth sub-block 940 Output

[0124] 270 Output 950 Histogram Memory

[0125] 275 Output 1000 Delay Line

[0126] 280 signal 1005 First inverter

[0127] 510 inverter 40 1010 second inverter

[0128] 520 inverter, 1015 input

[0129] 540 Histogram data 1020 Bias voltage

[0130] 640 histogram data, 1025 transistors

[0131] 700TDC circuit 1030 multiplexer circuit

[0132] 710 counter 45 1035 first multiplexer control input

[0133] 720 First Offset Circuit

[0134] 730 Second Offset Circuit 1040 Second Multiplexer Control Input

[0135] 740TDC

[0136] 750 histogram memory, 1045 transistors

[0137] 800TDC circuit 50 1050 output

[0138] 810-N delay stage 1055 transistor

[0139] 815 Delay Line 1060 Input Clock Signal

[0140] 825 trigger clock signal, 1070 clock buffer logic

[0141] 835 thermometer to independent thermal code converter 1075 buffer

[0142] 845 compartmentalization circuit 55 1080 input clock signal

[0143] 850-N latch 1085 output clock signal

[0144] 860-N Event Counter 1090 Transistors

[0145] 855SPAD event signal 1095 another inverter

[0146] 890 encoder circuit with 1200 delay lines

[0147] 895 decoder circuit 60 1220 histogram

[0148] 905TDC 1300 device

[0149] 910 counter 1310 time of flight sensor

[0150] 1315SPAD

[0151] 1320TDC circuit

[0152] 1325 camera

[0153] 1330 Processing Circuit

[0154] Step 1410

[0155] 1420 steps< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A time-to-digital converter circuit (700, 800), comprising: Multiple delay stages are connected to form a delay line (815). Multiple event counters; Encoder circuit (890) is used to trigger the delay line; as well as The compartmentalization circuit (845) is used to propagate the single-photon avalanche diode (SPAD) event signal to the associated event counters in the plurality of event counters. The encoder circuit is configured to sequentially trigger different delay stages among the plurality of delay stages, and the compartmentalization circuit selects the event counter based on a signal from the delay line. The compartmentalization circuit (845) includes a decoder circuit (895) for generating a second offset for the selection of the event counter. The encoder circuit (890) is configured to generate a first offset relative to the delay line (815) at a first stage, the first offset corresponding to the entry point for triggering the delay line, and The encoder circuit (890) is configured to provide data to the decoder circuit (895) such that the second offset is used to compensate for the first offset.

2. The time-to-digital converter circuit (700, 800) according to claim 1, wherein the encoder circuit (890) includes a one-hot code converter configured to convert the output from the counter (910) into data corresponding to the first offset.

3. The time-to-digital converter circuit (700, 800) of claim 1, wherein the decoder circuit (895) includes a multiplexer circuit configured to associate a detected event with any of the plurality of event counters.

4. The time-to-digital converter circuit (700, 800) according to any one of claims 1-3, wherein the compartment circuit (845) includes a thermometer-to-isothermal code converter (835) configured to convert a signal from the delay line (815) into a signal for selecting a single event counter.

5. The time-to-digital converter circuit (700, 800) according to any one of claims 1-3, wherein the plurality of event counters are configured to correspond to a histogram memory, and wherein each event counter includes a ripple counter.

6. The time-to-digital converter circuit (700, 800) according to any one of claims 1-3, wherein each delay stage includes a delay element configured to receive a regulating current, wherein the timing of the delay element depends on the regulating current.

7. A time-of-flight sensor, comprising: An array of single-photon avalanche diodes (SPADs); as well as At least one time-to-digital converter circuit according to any one of claims 1 to 6; The array of SPADs is coupled to at least one time-to-digital converter circuit, and the at least one time-to-digital converter circuit is configured to associate SPAD events with event counters from the plurality of event counters.

8. The time-of-flight sensor according to claim 7, comprising: Multiple time-to-digital converter circuits; as well as A global DLL is configured to provide control current to each of the plurality of time-to-digital converter circuits. The propagation delay of each delay stage is defined by the control current.

9. An apparatus (1300) comprising: The time-of-flight sensor (1310) according to claim 7 or 8. Camera (1325); as well as Processing circuitry (1330) coupled to the time-of-flight sensor and the camera. The processing circuitry is configured to adjust the camera's focus and / or adjust the image captured by the camera in response to the distance to the target determined by the time-of-flight sensor.

10. The apparatus of claim 9, wherein the apparatus is one of the following: Smartphone; Cellular phone; Tablet PC; or Laptop.

11. A method for reducing errors in a time-to-digital converter circuit (700, 800), the time-to-digital converter circuit including a delay line (815), a compartmentalization circuit (845), an encoder circuit (890), and a plurality of event counters, the method comprising: The encoder circuit (890) is configured to sequentially trigger different delay stages of the delay line; as well as The compartmentalization circuit is configured to select an event counter from a plurality of event counters based on a signal from the delay line. The compartmentalization circuit (845) includes a decoder circuit (895) for generating a second offset for selecting the event counter. The encoder circuit (890) is configured to generate a first offset relative to the delay line (815) at a first stage, the first offset corresponding to the entry point for triggering the delay line, and The encoder circuit (890) is configured to provide data to the decoder circuit (895) such that the second offset is used to compensate for the first offset.

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