Configurable Bit-Interleaved Downlink Synchronization State Machine for Optical Line Terminal in High-Speed Passive Optical Network

Abstract

A method implemented by an optical network unit (ONU) in a passive optical network (PON). The method includes: receiving a coded downstream (DS) signal from an optical line terminal (OLT); searching for a physical synchronization sequence (PSync) pattern among all possible alignments in the downstream signal for all possible OLT bit interleaving patterns; and once the PSync pattern is found, transitioning to a pre-synchronized state.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims the priority of the U.S. Provisional Patent Application filed by Liu Xiang et al. on October 14, 2020, with application number 63 / 091,657 and invention title "Optical Line Terminal (OLT) Configurable Bit - Interleaved Downstream Synchronization State Machine for High - Speed Passive Optical Networks (PONs)", which is incorporated herein by reference. Technical field

[0003] The present disclosure generally relates to the field of optical networks, and more particularly to optional interleaving in optical networks. Background art

[0004] An optical network is a network that uses optical signals to carry data. A light source such as a laser generates an optical signal. A modulator modulates the optical signal with data to generate a modulated optical signal. Various optical network components transmit, propagate, amplify, receive, and process the modulated optical signal. Optical networks can use multiplexing to achieve high bandwidth. Optical networks are implemented in data centers, metropolitan area networks, PONs, long - haul transmission systems, and other applications. Summary of the invention

[0005] The disclosed aspects / embodiments provide techniques for an optical network unit (ONU) that receives a downstream signal to detect whether an optical line terminal (OLT) has implemented non - interleaving or bit - interleaving when formulating the downstream signal. The ONU searches for a physical synchronization sequence (PSync) pattern in all possible alignments in the downstream signal for all possible OLT bit - interleaving patterns. The ONU performs this pattern search to determine whether the OLT has encoded the downstream signal sent to the ONU using non - interleaving or some bit - interleaving pattern.

[0006] A first aspect relates to a method implemented by an optical network unit (ONU) in a passive optical network (PON), including: receiving an encoded downstream (DS) signal from an optical line terminal (OLT); searching for a physical synchronization sequence (PSync) pattern in all possible alignments in the downstream signal for all possible OLT bit - interleaving patterns; and transitioning to a pre - synchronization state once the PSync pattern is found.

[0007] Optionally, in the first aspect, according to another implementation of this aspect, all possible OLT bit interleaving patterns include a non-interleaving pattern and an m-fold bit interleaving pattern, where, in the m-fold bit interleaving pattern, m adjacent forward error correction (FEC) codewords are interleaved bit by bit.

[0008] Optionally, in any of the above aspects, according to another implementation of this aspect, m is set to 4.

[0009] Optionally, in any of the above aspects, according to another implementation of this aspect, the FEC is based on low-density parity-check (LDPC).

[0010] Optionally, in any of the above aspects, according to another implementation of this aspect, the FEC codeword length is 17,280 bits.

[0011] Optionally, in any of the above aspects, according to another implementation of this aspect, during the search, the ONU switches between the non-deinterleaving mode and the m-fold bit deinterleaving mode every N consecutive failures to find the PSync pattern, where N is at least the length of a physical layer (PHY) frame, and where the m-fold bit deinterleaving mode includes deinterleaving the m adjacent FEC codewords bit by bit.

[0012] Optionally, in any of the above aspects, according to another implementation of this aspect, m is set to 4.

[0013] Optionally, in any of the above aspects, according to another implementation of this aspect, the FEC is based on low-density parity-check (LDPC).

[0014] Optionally, in any of the above aspects, according to another implementation of this aspect, the FEC codeword length is 17,280 bits.

[0015] Optionally, in any of the above aspects, according to another implementation of this aspect, the length of the PHY frame includes 6,220,800 bits.

[0016] Optionally, in any of the above aspects, according to another implementation of this aspect, the ONU is in the Hunt state when performing the search.

[0017] Optionally, in any of the above aspects, according to another implementation of this aspect, the ONU is out of sync when in the Hunt state.

[0018] Optionally, in any of the above aspects, according to another implementation of the aspect, all possible alignments include one or more of bit alignment and byte alignment.

[0019] Optionally, in any of the above aspects, according to another implementation of the aspect, the downlink signal includes one or more physical layer (PHY) frames.

[0020] Optionally, in any of the above aspects, according to another implementation of the aspect, searching for the PSync pattern includes: fault-tolerant pattern matching.

[0021] Optionally, in any of the above aspects, according to another implementation of the aspect, searching for the PSync pattern includes: verifying the superframe counter (SFC) hybrid error control (HEC).

[0022] Optionally, in any of the above aspects, according to another implementation of the aspect, when a PSync pattern with the maximum number (K) of bit errors is detected, the PSync pattern is found.

[0023] The second aspect relates to an optical network unit (ONU) in a passive optical network (PON), including: a memory for storing instructions; and one or more processors coupled to the memory, wherein the one or more processors are configured to execute the instructions to cause the ONU to perform the following operations: receive an encoded downlink (DS) signal from an optical line terminal (OLT); search for a physical synchronization sequence (PSync) pattern among all possible alignments in the downlink signal for all possible OLT bit interleaving patterns; and once the PSync pattern is found, transition to a pre-synchronized state.

[0024] Optionally, in any of the above aspects, according to another implementation of the aspect, all possible OLT bit interleaving patterns include a non-interleaved pattern and an m-fold bit interleaved pattern, wherein in the m-fold bit interleaved pattern, m adjacent forward error correction (FEC) codewords are interleaved bit by bit.

[0025] Optionally, in any of the above aspects, according to another implementation of the aspect, m is set to 4.

[0026] Optionally, in any of the above aspects, according to another implementation of this aspect, during the search, the ONU is configured to: switch between a non-deinterleaving mode and an m-fold bit deinterleaving mode every N consecutive failures to find the PSync pattern, where N is at least the length of a physical layer (PHY) frame, and where the m-fold bit deinterleaving mode includes deinterleaving the m adjacent FEC codewords bit by bit.

[0027] Optionally, in any of the above aspects, according to another implementation of this aspect, the length of the PHY frame includes 6,220,800 bits.

[0028] Optionally, in any of the above aspects, according to another implementation of this aspect, the ONU is in a Hunt state when performing the search.

[0029] Optionally, in any of the above aspects, according to another implementation of this aspect, the ONU is out of sync when in the Hunt state.

[0030] Optionally, in any of the above aspects, according to another implementation of this aspect, all possible alignments include one or more of bit alignment and byte alignment.

[0031] Optionally, in any of the above aspects, according to another implementation of this aspect, the downstream signal includes one or more physical layer (PHY) frames.

[0032] Optionally, in any of the above aspects, according to another implementation of this aspect, searching for the PSync pattern includes: error-tolerant pattern matching.

[0033] Optionally, in any of the above aspects, according to another implementation of this aspect, searching for the PSync pattern includes: verifying the superframe counter (SFC) hybrid error control (HEC).

[0034] Optionally, in any of the above aspects, according to another implementation of this aspect, when a PSync pattern with the maximum number (K) of bit errors is detected, the PSync pattern is found.

[0035] A third aspect relates to a passive optical network (PON), including: an optical line terminal (OLT) for transmitting an encoded downstream (DS) signal; and an optical network unit (ONU) communicating with the OLT, where the ONU is configured to perform the method in any of the disclosed embodiments.

[0036] A fourth aspect relates to an optical network unit (ONU) device in a passive optical network (PON), including: a memory device for storing instructions; and a processing device for executing the instructions to cause the ONU device to perform the following operations: receiving an encoded downstream (DS) signal from an optical line terminal (OLT); searching for a physical synchronization sequence (PSync) pattern in all possible alignments in the downstream signal for all possible OLT bit interleaving patterns; and transitioning to a pre-synchronized state once the PSync pattern is found.

[0037] For clarity, any of the above embodiments may be combined with any one or more of the other above embodiments to create new embodiments within the scope of the present disclosure.

[0038] These and other features will be more clearly understood from the following detailed description in conjunction with the drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] To understand the present disclosure more thoroughly, reference is now made to the following description of the drawings in conjunction with the detailed description and specific embodiments, in which like reference numerals represent like components.

[0040] Figure 1 A schematic diagram of a passive optical network (PON).

[0041] Figure 2 A schematic diagram showing data path functions including optional interleaving and deinterleaving in a downstream (DS) signal.

[0042] Figure 3 A schematic diagram of a downstream synchronization state machine.

[0043] Figure 4 A schematic diagram of a downstream synchronization state machine provided by an embodiment of the present disclosure for adapting to optional interleaving and deinterleaving.

[0044] Figure 5 A schematic diagram of data path functions provided by an embodiment of the present disclosure.

[0045] Figure 6 A schematic diagram of data path functions provided by an embodiment of the present disclosure.

[0046] Figure 7 A method implemented by an optical network unit (ONU) in a passive optical network provided by an embodiment of the present disclosure.

[0047] Figure 8 A schematic diagram of a network device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] First, it should be understood that although illustrative implementations of one or more embodiments are provided below, the disclosed systems and / or methods may be implemented using any number of techniques, whether currently known or available. The present disclosure should in no way be limited to the illustrative implementations, drawings, and techniques set forth below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the full scope of the appended claims and their equivalents.

[0049] In a high-speed PON (HSP), such as a 50-gigabit-capable passive optical network (50G-PON), bit-interleaving multiple adjacent forward error correction (FEC) codewords is an optional feature of a downstream signal (also referred to as a downstream transmission). Thus, when formulating a downstream signal, an optical line terminal (OLT) may choose to switch between using non-interleaving and using bit-interleaving. Unfortunately, an optical network unit (ONU) receiving the downstream signal currently cannot detect whether the OLT has implemented non-interleaving or bit-interleaving when formulating the downstream transmission.

[0050] The techniques disclosed herein enable an ONU receiving a downstream signal to detect whether the OLT has implemented non-interleaving or a certain bit-interleaving pattern when formulating the downstream signal. The ONU searches for a physical synchronization sequence (PSync) pattern in all possible alignments in the downstream signal for all possible OLT bit-interleaving patterns. The ONU performs this pattern search to determine whether the OLT has encoded the downstream signal sent to the ONU using non-interleaving or a certain bit-interleaving pattern.

[0051] Figure 1 FIG. 100 is a schematic diagram of a PON 100. The PON 100 includes an OLT 110, an ONU 120, and an ODN 130. The ODN 130 couples the OLT 110 to the ONU 120. The PON 100 is a communication network that may not require active devices to distribute data between the OLT 110 and the ONU 120. Instead, the PON 100 may use passive optical devices in the ODN 130 to distribute data.

[0052] The OLT 110 communicates with other networks and the ONU 120. For example, the OLT 110 transmits data from other networks to the ONU 120 and transmits data from the ONU 120 to other networks. The OLT 110 is typically located at a central location, such as a central office (CO), but may also be located at other suitable locations.

[0053] The ODN 130 is a data distribution network, including optical fiber cables, couplers, splitters, distributors, and other suitable components. The components include passive optical devices that do not require power to distribute data between the OLT 110 and the ONU 120. The ODN 130 can extend from the OLT 110 to the ONU 120 in the configuration shown in the figure, or can be configured in any other suitable point-to-multipoint (P2MP) configuration.

[0054] The ONU 120 communicates with the OLT 110 and customers. For example, the ONU 120 transmits data from the OLT 110 to customers and transmits data from customers to the OLT 110. The ONU 120 is similar to an optical network terminal (ONT), and the terms can be used interchangeably. The ONU 120 is usually located in a distributed location, such as a customer's premises, but can also be located in other suitable locations.

[0055] Figure 2 FIG. 200 is a schematic diagram showing the data path function including optional interleaving and deinterleaving in the downstream (DS) signal. As shown in the sequence 201 above, data 202 is obtained by an OLT (e.g., OLT 110). The OLT performs FEC encoding on the data 202 through, for example, low-density parity-check (LDPC) encoding 204. Then, the OLT scrambles the encoded data 206. The OLT may or may not perform interleaving 208 on the encoded data. That is, the interleaving 208 is optional. When the interleaving 208 is performed, consecutive LDPC codewords need to be interleaved bit by bit, herein simply referred to as m-fold bit interleaving. Preferably, 4-fold bit interleaving is performed. For example, through 4-fold bit interleaving, every 4 adjacent LDPC codewords with a codeword length of 17,280 bits, denoted as [A 1 A 2 ……A 17280 B 1 B 2 ……B 17280 C 1 C 2 ……C 17280 D 1 D 2 ……D 17280 , are interleaved into [A 1 B 1 C 1 D 1 A 2 B 2 C2 D 2 ……A 17280 B 17280 C 17280 D 17280 . The function of the interleaver 208 is to mitigate the performance degradation of the FEC in the presence of correlation errors that may be introduced by channel equalization. After the interleaver 208, the downlink signal is transmitted through the transmission channel 210 (also known as the PON physical channel), minimizing the impact on the common transmission convergence layer (ComTC). Then, the OLT transmits the encoded data to one or more ONUs (e.g., ONU 120) through the transmission channel 210.

[0056] When receiving the encoded data, the ONU can de-interleave the encoded data received from the OLT through the transmission channel 210 or not de-interleave it, depending on whether interleaving is detected in the encoded data. That is, if the OLT 110 performs interleaving, the ONU 120 must perform the de-interleaving 212. When performing, the de-interleaving 212 is performed bit by bit on consecutive LDPC codewords, herein simply referred to as m-fold bit de-interleaving. Preferably, 4-fold bit de-interleaving is performed. For example, through 4-fold bit de-interleaving, every 4 adjacent LDPC codewords with a codeword length of 17,280 bits, represented as [A 1 B 1 C 1 D 1 A 2 B 2 C 2 D 2 ……A 17280 B 17280 C 17280 D 17280 , is de-interleaved into [A 1 A 2 ……A 17280 B 1 B 2 ……B 17280 C 1 C 2 ……C 17280 D 1 D 2 ……D 17280 , which is exactly the original data sequence before the interleaver 208 is performed. The ONU descrambles the encoded data 214. After descrambling the encoded data 214, the ONU decodes the encoded data by using LDPC decoding 216, etc.

[0057] In one embodiment, the descrambling is performed by a descrambler within the ONU. The descrambler uses the scrambling polynomial x 58 +x 39 +1. In one embodiment, the descrambler uses a variable starting bit sequence derived from a superframe counter (SFC). In one embodiment, the SFC is obtained after FEC decoding. In one embodiment, the variable starting sequence is [1111111SFC].

[0058] It should be noted that the order of operations performed in the above sequence 201 can be changed, as shown in the following sequence 203. In the following sequence, data 202 is obtained by the OLT (e.g., OLT 110). The OLT scrambles the data 206. Then, the OLT encodes the scrambled data through LDPC encoding 204, etc. The OLT may or may not perform interleaving 208 on the encoded data. That is, the interleaving 208 is optional. After that, the OLT transmits the encoded data to one or more ONUs (e.g., ONU 120) through a transmission channel 210.

[0059] When receiving the encoded data, the ONU may or may not perform deinterleaving 212 on the encoded data received from the OLT through the transmission channel 210. That is, the deinterleaving 212 is optional. The ONU decodes the encoded data by using LDPC decoding 216, etc. Then, the ONU descrambles the data after LDPC decoding 214.

[0060] When 4-fold bit interleaving is adopted in the above sequence 201 or the following sequence 203, the physical synchronization sequence (PSync) S 1 S 2 S 3 ……S 63 S 64 becomes S 1 xxxS 2 xxxS 3 xxx……S 63 xxxS 64 xxx. Wherein, S represents the bits of the PSync, and x represents the data bits interleaved into the PSync. Since the PSync pattern changes when optional 4-fold bit interleaving is adopted, the downlink state machine needs to be modified to accommodate the optional 4-fold bit interleaving.

[0061] Figure 3It is a schematic diagram of a downlink synchronization state machine 300. The downlink synchronization state machine 300 can be implemented by an ONU in HSPPON, such as 50G-PON. The ONU starts from the search state 302. The ONU is out of sync when in the search state 302. When in the search state 302, the ONU searches for the PSync pattern among all possible alignments (bit alignment and byte alignment) in the downlink signal. In one embodiment, all possible OLT bit interleaving patterns include a non-interleaving pattern and an m-fold bit interleaving pattern, where, in the m-fold bit interleaving pattern, m adjacent forward error correction (FEC) codewords are interleaved bit by bit. m is set to 4, the FEC is based on LDPC, and / or the FEC codeword length is 17,280 bits. In one embodiment, during the search, the ONU switches between the non-deinterleaving pattern and the m-fold deinterleaving pattern every N consecutive failures to find the PSync pattern, where, in the m-fold deinterleaving pattern, m adjacent FEC codewords are deinterleaved bit by bit. N is at least the length of a PHY frame, m is set to 4, the FEC is based on LDPC, and / or the FEC codeword length is 17,280 bits. Once the ONU determines to a suitable extent that the PSync pattern has been found at the start of the frame, the ONU transitions to the pre-sync state 304. Searching for the PSync pattern can include, for example, fault-tolerant pattern matching and verifying other protocol elements, such as SFC hybrid error control (HEC).

[0062] Once in the pre-sync state 304, the ONU is still out of sync. However, to achieve synchronization, the ONU performs a synchronization verification on the received data. When there are too many failures (also referred to as too many errors) during the synchronization verification process, the ONU returns to the search state 302. When there are only tolerable failures (also referred to as tolerable errors) during the synchronization verification process, the ONU can remain in the pre-sync state 304 until the ONU achieves sufficient success or experiences too many failures. When sufficient success is achieved during the synchronization verification process, the ONU transitions to the sync state 306. Once in the sync state 306, the ONU is synchronized.

[0063] As long as the synchronization verification process continues to be successful, the ONU remains in the sync state 306. When the synchronization verification process fails, the ONU transitions to the re-sync state 308. Once in the re-sync state 308, the ONU remains synchronized. When the synchronization verification process is successful, the ONU continues to perform the synchronization verification process and transitions back to the sync state 306. When there are too many failures during the synchronization verification process, the ONU declares that the downlink synchronization is lost and returns to the search state 302.

[0064] Unfortunately, Figure 3 the downstream synchronization state machine 300 in

[0065] Figure 4 FIG. 400 is a schematic diagram of a downstream synchronization state machine 400 provided by an embodiment of the present disclosure for adapting to optional interleaving and deinterleaving. The downstream synchronization state machine 400 can be implemented by an ONU in an HSP PON, such as 50G-PON. The ONU starts from a search state 402. The ONU is out of sync when in the search state 402. When in the search state 402, the ONU searches for a PSync pattern in all possible alignments (bit alignment and byte alignment) in the downstream signal for all possible OLT bit interleaving patterns. For example, when the OLT has two interleaving patterns (e.g., non-interleaving pattern and 4-fold bit interleaving pattern), the ONU switches between non-deinterleaving and 4-fold bit deinterleaving once every N consecutive PSync failures in the received data path to find the PSync pattern. Wherein, N is at least the length of a physical layer (PHY) frame. In one embodiment, N is set to the length of the PHY frame. In one embodiment, the length of the frame includes 6,220,800 bits.

[0066] Once the ONU has found the PSync pattern at the start of a frame (e.g., a PHY frame) to an appropriate extent, the ONU transitions to a pre-sync state 404. Searching for the PSync pattern may include, for example, error-tolerant pattern matching and verifying other protocol elements, such as superframe counter (SFC) hybrid error control (HEC).

[0067] In one embodiment, in the search state 402, each ONU detects whether the OLT has enabled a bit interleaving pattern (e.g., 4-fold bit interleaving pattern). In one embodiment, this can be achieved through PSync matching to find the correct PSync position and interleaving state by using R 1 R 5 R 9 ……R 249 R 253 and R 1 R 2 R 3 ……R 63 R 64 Wherein, R nis the nth bit received by the ONU. In one embodiment, a single correlator is used to perform PSync matching successively with and without 4-fold bit interleaving. In another embodiment, the received data is processed with and without deinterleaving and searched for a match with the PSync pattern S 1 S 2 S 3 ……S 63 S 64 over the length of at least one PHY frame to detect PSync. Regardless of the actual implementation, the essence is to find the PSync match through trial and error with and without deinterleaving.

[0068] Figure 4 The pre-sync state 404, sync state 406, and re-sync state 408 in Figure 3 are similar to the pre-sync state 304, sync state 306, and re-sync state 308 in

[0069] Once in the pre-sync state 404, the ONU is still out of sync. However, to achieve synchronization, the ONU performs a sync verification on the received data. When PSync fails, the ONU returns to the search state 402. When PSync matches with a given maximum number K of bit errors, the ONU transitions to the sync state 406. In one embodiment, K is set to 7. However, in practical applications, K can have other values. Once in the sync state 406, the ONU is synchronized.

[0070] In the sync state 406, both the PSync pattern and the SFC after FEC decoding are verified simultaneously. When the PSync pattern or the SFC after FEC decoding fails the verification, the ONU transitions to the re-sync state 408. When the PSync pattern or the SFC after FEC decoding passes the verification (e.g., the sync verification process is successful), the ONU continues to perform the sync verification process and transitions back to the sync state 406. When the PSync pattern or the SFC after FEC decoding still fails the verification, the ONU remains in the re-sync state 408.

[0071] The downstream sync state machine 400 enables the sync and correct deinterleaving process in the receive data path. Thus, subsequent data path processing can continue to recover the bits of the downstream signal without interruption.

[0072] Figure 5 FIG. 500 is a schematic diagram of the data path function provided by an embodiment of the present disclosure. As shown in the figure, data 502 is obtained by an OLT (e.g., OLT 110). The OLT encodes the data 502 through LDPC encoding 504, etc. Then, the OLT scrambles the encoded data 506. The OLT may or may not perform interleaving 508 on the encoded data. That is, the interleaving 508 is optional. When interleaving is performed, it needs to be performed immediately before the downstream signal is transmitted through the transmission channel 510 (also referred to as the PON physical channel). After that, the OLT transmits the encoded data to the ONU (e.g., ONU 120) through the transmission channel 510.

[0073] When receiving the encoded data, each ONU uses a downstream synchronization state machine (e.g., downstream synchronization state machines 300 and 400) for correct synchronization and bit deinterleaving 512. When the ONU determines that the OLT has used bit interleaving (e.g., 4-fold bit interleaving), it performs bit deinterleaving. The ONU descrambles the encoded data 514. After descrambling the encoded data 514, the ONU decodes the encoded data through LDPC decoding 516, etc. After that, the data is recovered 518.

[0074] Figure 6 FIG. 600 is a schematic diagram of the data path function provided by an embodiment of the present disclosure. It should be noted that, relative to Figure 5 the schematic diagram 500 of the data path function described in

[0075] As shown in the figure, data 602 is obtained by an OLT (e.g., OLT 110). The OLT scrambles the data 604. Then, the OLT encodes the scrambled data through LDPC encoding 606, etc. The OLT may or may not perform interleaving 608 on the encoded data. That is, for the OLT, the interleaving 608 is optional. When interleaving is performed, it needs to be performed immediately before the downstream signal is transmitted through the transmission channel 610. After that, the OLT transmits the encoded data to the ONU (e.g., ONU 120) through the transmission channel 610.

[0076] When receiving the encoded data, each ONU uses a downstream synchronization state machine (e.g., downstream synchronization state machines 300 and 400) to perform correct synchronization and bit deinterleaving 612. Bit deinterleaving is only performed when the ONU determines that the OLT has used bit interleaving (e.g., 4-fold bit interleaving). Then, the ONU decodes the encoded data through LDPC decoding 616 and the like. After decoding 616 the encoded data, the ONU descrambles the LDPC-decoded data 614. After that, the data is recovered 618.

[0077] Figure 7 FIG. 700 shows a method implemented by an ONU (e.g., ONU 120) in a passive optical network according to an embodiment of the present disclosure. The method 700 can be executed by the ONU to recover the encoded data.

[0078] In block 702, the ONU receives an encoded DS signal from an optical line terminal (e.g., OLT 110). In block 704, the ONU searches for a PSync pattern in all possible alignments in the downstream signal for all possible OLT bit interleaving patterns. In one embodiment, the downstream signal includes one or more PHY frames. In one embodiment, searching for the PSync pattern includes error-tolerant pattern matching.

[0079] In one embodiment, all possible alignments include bit alignment and byte alignment. In one embodiment, all possible OLT bit interleaving patterns include a non-interleaving pattern and a 4-fold bit interleaving pattern. In one embodiment, searching for the PSync pattern includes verifying the SFC HEC.

[0080] In one embodiment, during the search, the ONU switches between a non-deinterleaving mode and a 4-fold deinterleaving mode every N consecutive failures to find the PSync pattern, where N is at least the length of a PHY frame. In one embodiment, the length of the PHY frame includes 6,220,800 bits. In one embodiment, the ONU is in a search state when performing the search.

[0081] In block 706, once the PSync pattern is found, the ONU transitions to a pre-synchronization state. In one embodiment, the PSync pattern is found when a PSync pattern with the maximum number (K) of bit errors is detected.

[0082] Figure 8Schematic diagram of a network device 800 (e.g., ingress router, egress router, or network equipment). The network device 800 is adapted to implement the disclosed embodiments as described herein. The network device 800 includes: an ingress port / ingress device 810 and a receiving unit (Rx) / receiving device 820 for receiving data; a processor, logic unit, or central processing unit (CPU) / processing device 830 for processing data; a transmitting unit (Tx) / transmitting device 840 and an egress port / egress device 850 for transmitting data; and a memory / memory device 860 for storing data. The network device 800 may further include optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to the ingress port / ingress device 810, the receiving unit / receiving device 820, the transmitting unit / transmitting device 840, and the egress port / egress device 850 for outputting or inputting optical or electrical signals.

[0083] The processor / processing device 830 is implemented by hardware and software. The processor / processing device 830 may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and a digital signal processor (DSP). The processor / processing device 830 communicates with the ingress port / ingress device 810, the receiving unit / receiving device 820, the transmitting unit / transmitting device 840, the egress port / egress device 850, and the memory / memory device 860. The processor / processing device 830 includes a synchronization module 870. The synchronization module 870 is capable of implementing the methods disclosed herein. Thus, by including the synchronization module 870, the functions of the network device 800 are greatly improved, and the transition of the network device 800 to different states is achieved. Alternatively, the synchronization module 870 is implemented as instructions stored in the memory / memory device 860 and executed by the processor / processing device 830.

[0084] The network device 800 may further include an input and / or output (I / O) device / I / O apparatus 880 for transmitting data to a user or transmitting data from the user. The I / O device / I / O apparatus 880 may include an output device, for example, a display for displaying video data and a speaker for outputting audio data. The I / O device / I / O apparatus 880 may further include an input device, for example, a keyboard, a mouse, and a trackball, and / or corresponding interfaces for interacting with such output devices.

[0085] The memory / memory device 860 includes one or more disks, one or more tape drives, and one or more solid state drives, and may be used as an overflow data storage device to store such programs when a program is selected for execution, and to store instructions and data read during the execution of the program. The memory / memory device 860 may be volatile and / or non-volatile, and may be a read-only memory (ROM), a random access memory (RAM), a ternary content-addressable memory (TCAM), and / or a static random access memory (SRAM).

[0086] Although the present disclosure provides multiple specific embodiments, it should be understood that the disclosed systems and methods may also be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The examples should be illustrative and not restrictive, and are not intended to be limited to the details given herein. For example, various elements or components may be combined or incorporated in another system, or certain features may be omitted or not implemented.

[0087] In addition, without departing from the scope of the present disclosure, the various technologies, systems, subsystems, and methods described and illustrated as discrete or separate in the various embodiments may be combined or integrated with other systems, components, technologies, or methods. Other changes, substitutions, and alternations are obvious to those skilled in the art and do not depart from the spirit and scope disclosed herein.

Claims

1. A method implemented by an optical network unit (ONU) in a passive optical network (PON), characterized in that, it includes: receiving a coded downstream DS signal from an optical line terminal (OLT); searching for a physical synchronization sequence (PSync) pattern among all possible alignments in the downstream signal for all possible OLT bit interleaving patterns; and once the PSync pattern is found, transitioning to a pre-synchronized state.

2. The method according to claim 1, characterized in that, the all possible OLT bit interleaving patterns include a non-interleaving pattern and an m-fold bit interleaving pattern, wherein, in the m-fold bit interleaving pattern, m adjacent forward error correction (FEC) codewords are interleaved bit by bit.

3. The method according to claim 2, characterized in that, m is set to 4.

4. The method according to claim 2 or 3, characterized in that, the FEC is based on low density parity check (LDPC).

5. The method according to claim 2 or 3, characterized in that, the FEC is based on low density parity check (LDPC), and the FEC codeword length is 17,280 bits.

6. The method according to claim 2, characterized in that, during the search, the ONU switches between a non-deinterleaving pattern and an m-fold bit deinterleaving pattern every N consecutive failures to find the PSync pattern, where N is at least the length of a physical layer (PHY) frame, and wherein the m-fold bit deinterleaving pattern includes deinterleaving the m adjacent FEC codewords bit by bit.

7. The method according to claim 6, characterized in that, m is set to 4.

8. The method according to claim 6 or 7, characterized in that, the FEC is based on low density parity check (LDPC).

9. The method according to claim 6 or 7, characterized in that, the FEC is based on low density parity check (LDPC), and the FEC codeword length is 17,280 bits.

10. The method according to claim 2 or 3 or 6 or 7, characterized in that, the downstream signal includes one or more physical layer (PHY) frames, and the length of the PHY frame includes 6,220,800 bits.

11. The method according to any one of claims 1 to 3, characterized in that, the ONU is in a Hunt state when performing the search.

12. The method according to claim 11, characterized in that, the ONU is out of sync when in the Hunt state.

13. The method according to any one of claims 1 to 3, characterized in that, the all possible alignments include one or more of bit alignment and byte alignment.

14. The method according to any one of claims 1 to 3, characterized in that, searching for the PSync pattern includes: fault-tolerant pattern matching.

15. The method according to any one of claims 1 to 3, characterized in that, searching for the PSync pattern includes: verifying a superframe counter (SFC) hybrid error control (HEC).

16. The method according to any one of claims 1 to 3, characterized in that, The PSync pattern is found when a PSync pattern with the maximum number (K) of bit errors is detected.

17. An optical network unit (ONU) in a passive optical network (PON), characterized in that it comprises: one or more processors for causing the ONU to perform the following operations: receive an encoded downstream (DS) signal from an optical line terminal (OLT); search for a physical synchronization sequence (PSync) pattern in all possible alignments in the downstream signal for all possible OLT bit interleaving patterns; and once the PSync pattern is found, transition to a pre-synchronization state.

18. The ONU according to claim 17, characterized in that the all possible OLT bit interleaving patterns include a non-interleaving pattern and an m-fold bit interleaving pattern, wherein, in the m-fold bit interleaving pattern, m adjacent forward error correction (FEC) codewords are interleaved bit by bit.

19. The ONU according to claim 18, characterized in that m is set to 4.

20. The ONU according to claim 18 or 19, wherein during the search, the ONU is configured to: switch between a non-deinterleaving mode and an m-fold bit deinterleaving mode once every N consecutive failures to find the PSync pattern, where N is at least the length of a physical layer (PHY) frame, characterized in that the m-fold bit deinterleaving mode includes deinterleaving the m adjacent FEC codewords bit by bit.

21. The ONU according to claim 20, characterized in that the downstream signal includes one or more physical layer (PHY) frames, and the length of the PHY frame includes 6,220,800 bits.

22. The ONU according to any one of claims 17 to 19, characterized in that the ONU is in a hunt state when performing the search.

23. The ONU according to claim 22, characterized in that the ONU is out of sync when in the hunt state.

24. The ONU according to any one of claims 17 to 19, characterized in that the all possible alignments include one or more of bit alignment and byte alignment.

25. The ONU according to any one of claims 17 to 19, characterized in that searching for the PSync pattern includes: error-tolerant pattern matching.

26. The ONU according to any one of claims 17 to 19, characterized in that searching for the PSync pattern includes: verifying a superframe counter (SFC) hybrid error control (HEC).

27. The ONU according to any one of claims 17 to 19, characterized in that the PSync pattern is found when a PSync pattern with the maximum number (K) of bit errors is detected.

28. A passive optical network (PON), characterized in that it comprises: an optical line terminal (OLT) for transmitting an encoded downstream (DS) signal; and an optical network unit (ONU) in communication with the OLT, wherein the ONU is configured to perform the method according to any one of claims 1 to 17.

29. An optical network unit (ONU) device in a passive optical network (PON), characterized in that, it comprises: a processing device, configured to cause the ONU device to perform the following operations: receive an encoded downstream (DS) signal from an optical line terminal (OLT); search for a physical synchronization sequence (PSync) pattern among all possible alignments in the downstream signal for all possible OLT bit interleaving patterns; and once the PSync pattern is found, transition to a pre-synchronization state.

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