Graphics processor instruction processing method and device based on risc-v instruction set
By decoding and splicing extended data processing on the RISC-V instruction set graphics processor, the problem of poor instruction processing performance was solved, and the number of registers and the length of immediate values were expanded, thereby improving the performance of the graphics processor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INTERNATIONAL INNOVATION CENTER OF TSINGHUA UNIVERSITY SHANGHAI
- Filing Date
- 2023-03-09
- Publication Date
- 2026-07-10
AI Technical Summary
Because the RISC-V instruction set-based graphics processors are limited by instruction length, and have a limited number of general-purpose registers and immediate values, their instruction processing performance is poor, especially when dealing with support vector data types.
By decoding the current instruction, determining whether it is a register extension instruction, reading and concatenating the extension data in the target temporary register, and generating the target decoding result, the number of registers and the length of immediate values are expanded.
It improves the instruction processing performance of graphics processors designed with the RISC-V instruction set, enhances the processing efficiency of vector data, and is compatible with mainstream RISC-V instructions without increasing the instruction length or decoding overhead.
Smart Images
Figure CN116342368B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more specifically, to a method and apparatus for processing graphics processor instructions based on the RISC-V instruction set. Background Technology
[0002] Currently, for graphics processors designed using the RISC-V instruction set, the number of general-purpose registers and immediate values available is limited due to the instruction length limitations in the RISC-V standard.
[0003] In practice, it has been found that graphics processing units (GPUs) need to support vector data types during programming. For example, OpenCL programming requires support for vectors with lengths ranging from 2 to 16. In this case, if the number of general-purpose registers and immediate values is limited, it can lead to poor instruction processing performance in the GPU.
[0004] There is currently no effective solution to the above problems. Summary of the Invention
[0005] This invention provides a method and apparatus for processing graphics processor instructions based on the RISC-V instruction set, so as to at least improve the instruction processing performance of graphics processors designed with the RISC-V instruction set.
[0006] According to one aspect of the present invention, a graphics processor instruction processing method based on the RISC-V instruction set is provided. The method includes: decoding a current instruction to obtain an initial decoding result; determining whether the current instruction is a register extension instruction based on the initial decoding result; if the current instruction is not a register extension instruction, determining an instruction processing category based on the valid bit information of a target register; wherein the instruction processing category includes a RISC-V standard decoding category or a concatenation decoding category; for the concatenation decoding category, reading target extended data from the target register; wherein the target extended data is the extended data corresponding to the previous register extension instruction; and concatenating the target extended data and the initial decoding result to generate a target decoding result.
[0007] As an optional implementation, the method further includes: if the current instruction is the register extension instruction, determining the extension data corresponding to the current instruction based on the initial decoding result; storing the extension data corresponding to the current instruction in the target temporary register, and updating the valid bit information of the target temporary register to 1.
[0008] As an optional implementation, the target extended data includes at least one of the following: destination operand register extended data, source operand register extended data, and immediate operand extended data.
[0009] As an optional implementation, after concatenating the target extended data and the initial decoding result to generate the target decoding result, the method further includes: updating the valid bit information of the target temporary register to 0.
[0010] As an optional implementation, the instruction processing category is determined based on the valid bit information of the target register, including: if the valid bit information of the target register is 1, then the instruction processing category is determined to be the splicing decoding category; if the valid bit information of the target register is 0, then the instruction processing category is determined to be the RISC-V standard decoding category.
[0011] As an optional implementation, the target temporary register stores the target extended data, the number of the target thread bundle during the graphics processor execution process, and the valid bit information; wherein, one thread bundle corresponds to one temporary register.
[0012] As an optional implementation, the method further includes: sending the target decoding result into an instruction buffer so that the instruction buffer buffers the target decoding result.
[0013] As an optional implementation, the method further includes: for the RISC-V standard decoding category, sending the initial decoding result into an instruction buffer so that the instruction buffer buffers the initial decoding result.
[0014] According to another aspect of the present invention, a graphics processor instruction processing apparatus based on the RISC-V instruction set is also provided. The apparatus includes: an initial decoding unit for decoding a current instruction to obtain an initial decoding result; an extension determination unit for determining whether the current instruction is a register extension instruction based on the initial decoding result; a category determination unit for determining an instruction processing category based on valid bit information of a target register if the current instruction is not a register extension instruction; wherein the instruction processing category includes a RISC-V standard decoding category or a concatenation decoding category; an extension reading unit for reading target extension data from the target register for the concatenation decoding category; wherein the target extension data is the extension data corresponding to the previous register extension instruction; and a concatenation processing unit for concatenating the target extension data and the initial decoding result to generate a target decoding result.
[0015] As an optional implementation, the apparatus further includes: an extended storage unit, configured to, if the current instruction is the register extension instruction, determine the extended data corresponding to the current instruction based on the initial decoding result; store the extended data corresponding to the current instruction in the target temporary register; and update the valid bit information of the target temporary register to 1.
[0016] As an optional implementation, the target extended data includes at least one of the following: destination operand register extended data, source operand register extended data, and immediate operand extended data.
[0017] As an optional implementation, the apparatus further includes: a valid bit update unit, used to update the valid bit information of the target register to 0 after concatenating the target extended data and the initial decoding result to generate the target decoding result.
[0018] As an optional implementation, the category determination unit is specifically used to: determine the instruction processing category as the splicing decoding category if the valid bit information of the target register is 1; and determine the instruction processing category as the RISC-V standard decoding category if the valid bit information of the target register is 0.
[0019] As an optional implementation, the target temporary register stores the target extended data, the number of the target thread bundle during the graphics processor execution process, and the valid bit information; wherein, one thread bundle corresponds to one temporary register.
[0020] As an optional implementation, the apparatus further includes: an instruction execution unit, configured to send the target decoding result into an instruction buffer so that the instruction buffer buffers the target decoding result.
[0021] As an optional implementation, the instruction execution unit is further configured to: for the RISC-V standard decoding category, send the initial decoding result into the instruction buffer so that the instruction buffer buffers the initial decoding result.
[0022] According to another aspect of the present invention, a computer-readable storage medium is also provided, wherein the storage medium stores a computer program, wherein the computer program is configured to execute the above-described graphics processor instruction processing method based on the RISC-V instruction set at runtime.
[0023] According to another aspect of the present invention, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the above-described graphics processor instruction processing method based on the RISC-V instruction set through the computer program.
[0024] In this embodiment of the invention, by concatenating and decoding the instructions, the extended data corresponding to the previous register extension instruction is introduced and concatenated with the decoding result of the current instruction, thereby expanding the number of registers and the length of immediate values, which can improve the instruction processing performance of graphics processors designed with the RISC-V instruction set. Attached Figure Description
[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:
[0026] Figure 1 This is a flowchart of an optional graphics processor instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention;
[0027] Figure 2 This is a schematic diagram of an information item of an optional register extension instruction according to an embodiment of the present invention;
[0028] Figure 3 This is a flowchart of another optional graphics processor instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention;
[0029] Figure 4 This is an optional register extension instruction module structure diagram according to an embodiment of the present invention;
[0030] Figure 5 This is a schematic diagram of the structure of an optional graphics processor instruction processing device based on the RISC-V instruction set according to an embodiment of the present invention.
[0031] Figure 6 This is a schematic diagram of the structure of an optional electronic device according to an embodiment of the present invention. Detailed Implementation
[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0034] This invention provides an optional RISC-V instruction set-based graphics processor instruction processing method, such as... Figure 1 As shown, the RISC-V instruction set-based graphics processor instruction processing method includes:
[0035] S101, decode the current instruction to obtain the initial decoding result.
[0036] In this embodiment, the execution entity can be a graphics processor designed using the RISC-V instruction set. The RISC-V instruction set is an open-source instruction set architecture (ISA) based on the Reduced Instruction Set Computing (RISC) principle.
[0037] In the process of executing instructions, the executing entity can first decode the current instruction through the decoding unit to obtain an initial decoding result. This initial decoding result can be used to determine whether the current instruction is a register extension instruction. The current instruction may include multiple information items; the initial decoding result obtained by decoding the current instruction can include the parsing results of each information item, such as the character corresponding to each information item.
[0038] S102, based on the initial decoding result, determine whether the current instruction is a register extension instruction.
[0039] In this embodiment, after obtaining the initial decoding result, the executing entity can determine whether the current instruction is a register extension instruction based on the initial decoding result. The register extension instruction may include specific information items. If the initial decoding result contains specific information items that match the register extension instruction, then the current instruction is a register extension instruction. If the initial decoding result does not contain specific information items that match the register extension instruction, then the current instruction is not a register extension instruction.
[0040] S103, if the current instruction is not the register extension instruction, then determine the instruction processing category based on the valid bit information of the target temporary register; wherein, the instruction processing category includes the RISC-V standard decoding category or the concatenation decoding category.
[0041] In this embodiment, if the current instruction is not a register extension instruction, valid bit information can be obtained from the target register corresponding to the current thread bundle. The valid bit information is used to mark whether the target register already stores the target extension data to be concatenated. For example, if the valid bit information is set to 1, it indicates that the target register already stores the target extension data to be concatenated. If the valid bit information is set to 0, it indicates that the target register does not store the target extension data to be concatenated. Then, the executing entity can determine the matching instruction processing category based on the valid bit information. The instruction processing category can include a RISC-V standard decoding category or a concatenation decoding category. The RISC-V standard decoding category can be a category that performs normal decoding of instructions according to the RISC-V standard, while the concatenation decoding category can be a category that decodes the information items obtained from parsing the current instruction, concatenates the extension data, and then performs decoding.
[0042] S104, for the splicing decoding category, read the target extended data from the target temporary register; wherein, the target extended data is the extended data corresponding to the previous register extension instruction.
[0043] In this embodiment, if the determined instruction processing category is a concatenation / decoding category, the target extended data can be read from the target temporary register. This target extended data may include specific extended information items, and the number of such items is at least one. Furthermore, the target extended data may be the extended data corresponding to the previous register extension instruction.
[0044] S105, the target extended data and the initial decoding result are concatenated to generate the target decoding result.
[0045] In this embodiment, the executing entity can concatenate at least one extended information item indicated by the target extended data with each information item in the initial decoding result to obtain the concatenated information item, which is the target decoding result. Executing the target decoding result is equivalent to executing the current instruction.
[0046] As an optional implementation, the method further includes: if the current instruction is the register extension instruction, determining the extension data corresponding to the current instruction based on the initial decoding result; storing the extension data corresponding to the current instruction in the target temporary register, and updating the valid bit information of the target temporary register to 1.
[0047] In this embodiment, if the current instruction is a register extension instruction, the character information corresponding to each specific extension information item can be determined based on the specific extension information items in the initial decoding result, thus obtaining the extension data corresponding to the current instruction. Then, the extension data corresponding to the current instruction can be stored in a target register for concatenation decoding of the next non-register extension instruction of the same type. Furthermore, after storing the extension data corresponding to the current instruction in the target register, the valid bit information of the target register can be updated to 1 to indicate that the target register stores extension data for concatenation. After updating the valid bit information of the target register to 1, it is determined that the processing of the current instruction is complete, and the next instruction can be read to repeat the above steps.
[0048] As an optional implementation, the target extended data includes at least one of the following: destination operand register extended data, source operand register extended data, and immediate operand extended data.
[0049] In this embodiment, the target extended data may include extended data corresponding to the destination operand register, extended data corresponding to the source operand register, and extended data corresponding to the immediate operand.
[0050] As an optional implementation, after concatenating the target extended data and the initial decoding result to generate the target decoding result, the method further includes: updating the valid bit information of the target temporary register to 0.
[0051] In this embodiment, after concatenating the target extended data and the initial decoding result to generate the target decoding result, the valid bit information of the target temporary register can be updated to 0 to indicate that there is no extended data for concatenation in the target temporary register at this time.
[0052] As an optional implementation, the instruction processing category is determined based on the valid bit information of the target register, including: if the valid bit information of the target register is 1, then the instruction processing category is determined to be the splicing decoding category; if the valid bit information of the target register is 0, then the instruction processing category is determined to be the RISC-V standard decoding category.
[0053] In this embodiment, if the valid bit information of the target register is 1, the instruction processing category can be determined to be the concatenation decoding category. If the valid bit information of the target register is 0, the instruction processing category can be determined to be the RISC-V standard decoding category.
[0054] As an optional implementation, the target temporary register stores the target extended data, the number of the target thread bundle during the graphics processor execution process, and the valid bit information; wherein, one thread bundle corresponds to one temporary register.
[0055] In this embodiment, the hardware unit can provide a temporary register for each thread bundle during the execution of the graphics processor; that is, one temporary register corresponds to one thread bundle. For the target temporary register, its corresponding temporary register is the target temporary register. Furthermore, the target temporary register can store the aforementioned target extended data, the number of the target thread bundle during the execution of the graphics processor, and the aforementioned valid bit information.
[0056] As an optional implementation, the method further includes: sending the target decoding result into an instruction buffer so that the instruction buffer buffers the target decoding result.
[0057] In this embodiment, after obtaining the target decoding result, the executing entity can directly send the concatenated information items from the target decoding result into the instruction buffer, so that the instruction buffer can control the subsequent execution results. Specifically, the instruction buffer can buffer the target decoding result for subsequent instruction execution units to execute, or allow subsequent instruction issuing units to send the decoded instructions to the corresponding instruction execution units for execution. Afterwards, the decoding unit can determine that the decoding process for the current instruction is complete (the current instruction still needs to undergo subsequent issuance, execution, write-back, and other processing steps), and the decoding unit reads the next instruction and repeats the above decoding process.
[0058] As an optional implementation, the method further includes: for the RISC-V standard decoding category, sending the initial decoding result into an instruction buffer so that the instruction buffer buffers the initial decoding result.
[0059] In this embodiment, for the RISC-V standard decoding category, each information item (the original information item without splicing) in the initial decoding result can be directly sent to the instruction buffer mentioned above so that the instruction buffer can control the subsequent execution result.
[0060] In this embodiment, the target extended data (extended instructions) is fully compatible with mainstream RISC-V instructions, and can easily expand the number of registers and the length of immediate values. Compared with other instruction sets that support more registers, this embodiment does not bring additional instruction length space or decoding overhead in scenarios where no more than 32 registers are needed. The compiler can also prioritize allocating registers to lower-numbered registers to reduce instruction length.
[0061] Furthermore, the compiler can treat register extension instructions and their following instructions as a whole as 64-bit macro instructions. When allocating registers using the graph coloring algorithm, the compiler directly allocates them according to the 256 physical registers. After allocation, the macro instructions can be directly expanded to obtain RISC-V instructions with register extension instructions, without modifying the existing compiler functional framework. More registers can reduce the number of stack calls in function calls, thereby reducing the execution overhead caused by pushing, function jumps and returns, and popping.
[0062] Please see Figure 2 , Figure 2 This is a schematic diagram of an information item of an optional register extension instruction according to an embodiment of the present invention, such as... Figure 2 As shown, register extension instructions include the information entries ext_rd, ext_rs3, ext_rs2, ext_rs1, and ext_imm, which respectively refer to the extension of the destination operand register, the extension of source operand register 3, the extension of source operand register 2, the extension of source operand register 1, and the extension of the immediate operand register. Furthermore, register extension instructions can include register-to-register extension instructions and register-to-immediate extension instructions. For register-to-register extension instructions, it defines the extension of three source operand registers and one destination operand register. Figure 2 Above); For register-immediate extension instructions, it defines an extension portion consisting of two source operand registers, one immediate operand, and one destination operand register. Figure 2 (See below). The register extensions are all 3 bits, and the immediate extensions are 12 bits. The extensions (register extensions and immediate extensions) can be appended to the high-order bits of the corresponding operand in the next instruction, thus expanding the number of register labels from 32 to 256 and increasing the immediate extensions to 4096 times their original size.
[0063] Please see Figure 3 , Figure 3 This is a flowchart of another optional graphics processor instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention, such as... Figure 3 As shown, the following steps can be performed:
[0064] S301 decodes the current instruction.
[0065] S302, is it a register extension instruction? If yes, proceed to step S303; otherwise, proceed to step S304.
[0066] S303: Store the extended information in the current instruction into the temporary register corresponding to the current thread bundle, and set the valid bit to 1.
[0067] S304. Check if the valid bit in the temporary register corresponding to the current thread bundle is 1. If yes, proceed to step S306. If no, proceed to step S305.
[0068] S305 retrieves register and immediate value numbers normally according to the RISC-V standard.
[0069] S306 concatenates the extended information in the temporary register with the normally decoded register / immediate value, and then sets the valid bits to 0.
[0070] S307, fetch the next instruction and process it.
[0071] In this embodiment, the decoding unit first decodes the current instruction and determines whether it is a register extension instruction based on the decoding result.
[0072] Furthermore, if it is a register extension instruction, the extended parts ext_rd, ext_rs3, ext_rs2, ext_rs1, and ext_imm obtained from the decoding of the current instruction are stored in the temporary register corresponding to the current thread block, and the valid bit in the temporary register is set to 1. Then, the processing of this instruction ends, and the next instruction is fetched for processing, repeating the process. This corresponds to... Figure 3 The execution order of S301, S302, S303, S307, and S301.
[0073] Furthermore, if it is not a register extension instruction, the system checks if the valid bits in the current thread's temporary register are 1. If not, it decodes the current instruction normally according to the RISC-V standard, then terminates the processing of this instruction and fetches the next instruction to repeat the process. This corresponds to... Figure 3 The execution order of S301, S302, S304, S305, S307, and S301.
[0074] Furthermore, if it is not a register extension instruction, and the valid bits in the temporary register of the current thread bundle are...
[0075] If the value is 1, then the information from ext_rd, ext_rs3, ext_rs2, ext_rs1, and ext_imm in the temporary register is concatenated to the high bits of the register operand number and the immediate operand obtained through normal decoding. Then, the valid bits in the temporary register are set to 0. This achieves register and immediate extension for this instruction using the previous register extension instruction. (This corresponds to...) Figure 3 The execution order of S301, S302, S304, S306, S307, and S301.
[0076] Please see Figure 4 , Figure 4This is an optional register extension instruction module structure diagram according to an embodiment of the present invention, such as... Figure 4 As shown, the hardware unit can provide a temporary register for each warp during the execution of the graphics processor. This temporary register stores the warp number (warp_id), the valid bits of the current temporary register, and the extended parts ext_rd, ext_rs3, ext_rs2, ext_rs1, and ext_imm.
[0077] Furthermore, during decoding, the system first checks if the current instruction is a register extension instruction. If so, the decoded extension is written into the temporary register of the thread bundle to which the current instruction belongs, and the valid bit is set to 1. The instruction is then executed successfully, and the decoding unit fetches the next instruction and repeats the above process. This situation corresponds to... Figure 4 The branch ① in the text.
[0078] Furthermore, if the current instruction is not a register extension instruction, the corresponding thread bundle's temporary register is selected and checked for a valid bit (1) based on the thread bundle number to which the current instruction belongs. If the bit is not 1, the instruction is directly loaded into the instruction buffer; if the bit is 1, the concatenated instruction is loaded into the instruction buffer, and the valid bit in the temporary register is cleared. The instruction buffer controls the subsequent execution result, and the decoding unit fetches the next instruction and repeats the above process. This situation corresponds to... Figure 4 The branch in ②.
[0079] In this embodiment of the invention, by concatenating and decoding the instructions, the extended data corresponding to the previous register extension instruction is introduced and concatenated with the decoding result of the current instruction, thereby expanding the number of registers and the length of immediate values, which can improve the instruction processing performance of graphics processors designed with the RISC-V instruction set.
[0080] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.
[0081] Furthermore, embodiments of the present invention provide an optional graphics processor instruction processing device based on the RISC-V instruction set, such as... Figure 5 As shown, the RISC-V instruction set-based graphics processor instruction processing device includes:
[0082] The initial decoding unit 501 is used to decode the current instruction to obtain the initial decoding result;
[0083] The extended judgment unit 502 is used to determine whether the current instruction is a register extension instruction based on the initial decoding result;
[0084] The category determination unit 503 is used to determine the instruction processing category based on the valid bit information of the target temporary register if the current instruction is not the register extension instruction; wherein the instruction processing category includes the RISC-V standard decoding category or the concatenation decoding category;
[0085] The extended read unit 504 is used to read target extended data from the target temporary register for the concatenation decoding category; wherein the target extended data is the extended data corresponding to the previous register extension instruction;
[0086] The splicing processing unit 505 is used to splice the target extended data and the initial decoding result to generate the target decoding result.
[0087] As an optional implementation, the apparatus further includes: an extended storage unit, configured to, if the current instruction is the register extension instruction, determine the extended data corresponding to the current instruction based on the initial decoding result; store the extended data corresponding to the current instruction in the target temporary register; and update the valid bit information of the target temporary register to 1.
[0088] As an optional implementation, the target extended data includes at least one of the following: destination operand register extended data, source operand register extended data, and immediate operand extended data.
[0089] As an optional implementation, the apparatus further includes: a valid bit update unit, used to update the valid bit information of the target register to 0 after concatenating the target extended data and the initial decoding result to generate the target decoding result.
[0090] As an optional implementation, the category determination unit 503 is specifically used to: determine the instruction processing category as the splicing decoding category if the valid bit information of the target register is 1; and determine the instruction processing category as the RISC-V standard decoding category if the valid bit information of the target register is 0.
[0091] As an optional implementation, the target temporary register stores the target extended data, the number of the target thread bundle during the graphics processor execution process, and the valid bit information; wherein, one thread bundle corresponds to one temporary register.
[0092] As an optional implementation, the apparatus further includes: an instruction execution unit, configured to send the target decoding result into an instruction buffer so that the instruction buffer buffers the target decoding result.
[0093] As an optional implementation, the instruction execution unit is further configured to: for the RISC-V standard decoding category, send the initial decoding result into the instruction buffer so that the instruction buffer buffers the initial decoding result.
[0094] In this embodiment of the invention, by concatenating and decoding the instructions, the extended data corresponding to the previous register extension instruction is introduced and concatenated with the decoding result of the current instruction, thereby expanding the number of registers and the length of immediate values, which can improve the instruction processing performance of graphics processors designed with the RISC-V instruction set.
[0095] Furthermore, according to another aspect of the present invention, an electronic device for implementing the above-described RISC-V instruction set-based graphics processor instruction processing method is also provided, such as... Figure 6 As shown, the electronic device includes a memory 602 and a processor 604. The memory 602 stores a computer program, and the processor 604 is configured to execute the steps of any of the above method embodiments via the computer program.
[0096] Optionally, in this embodiment, the electronic device may be located in at least one of a plurality of network devices in a computer network.
[0097] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:
[0098] S1, decode the current instruction to obtain the initial decoding result;
[0099] S2, based on the initial decoding result, determine whether the current instruction is a register extension instruction;
[0100] S3, if the current instruction is not the register extension instruction, then determine the instruction processing category based on the valid bit information of the target temporary register; wherein, the instruction processing category includes the RISC-V standard decoding category or the concatenation decoding category;
[0101] S4, for the concatenation decoding category, read the target extended data from the target temporary register; wherein, the target extended data is the extended data corresponding to the previous register extension instruction;
[0102] S5, the target extended data and the initial decoding result are concatenated to generate the target decoding result.
[0103] Alternatively, as those skilled in the art will understand, Figure 6 The structure shown is for illustrative purposes only. The electronic device can also be a smartphone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile internet device (MID), a PAD, and other terminal devices. Figure 6 This does not limit the structure of the aforementioned electronic device. For example, the electronic device may also include components that are more... Figure 6 The more or fewer components shown (such as network interfaces, etc.), or having the same Figure 6 The different configurations shown.
[0104] The memory 602 can be used to store software programs and modules, such as the program instructions / modules corresponding to the RISC-V instruction set-based graphics processor instruction processing method in this embodiment of the invention. The processor 604 executes various functional applications and data processing by running the software programs and modules stored in the memory 602, thereby implementing the aforementioned RISC-V instruction set-based graphics processor instruction processing method. The memory 602 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 602 may further include memory remotely located relative to the processor 604, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. Specifically, the memory 602 may be used, but is not limited to, to store information such as operation instructions. As an example, such as... Figure 6 As shown, the memory 602 may include, but is not limited to, the various modules in the above-described device.
[0105] Optionally, the transmission device 606 described above is used to receive or send data via a network. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 606 includes a Network Interface Controller (NIC), which can be connected to other network devices and routers via a network cable to communicate with the Internet or a local area network. In another example, the transmission device 606 is a radio frequency (RF) module, used for wireless communication with the Internet.
[0106] In addition, the aforementioned electronic device also includes a display 608 and a connection bus 610.
[0107] According to another aspect of the present invention, a storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.
[0108] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:
[0109] S1, decode the current instruction to obtain the initial decoding result;
[0110] S2, based on the initial decoding result, determine whether the current instruction is a register extension instruction;
[0111] S3, if the current instruction is not the register extension instruction, then determine the instruction processing category based on the valid bit information of the target temporary register; wherein, the instruction processing category includes the RISC-V standard decoding category or the concatenation decoding category;
[0112] S4, for the concatenation decoding category, read the target extended data from the target temporary register; wherein, the target extended data is the extended data corresponding to the previous register extension instruction;
[0113] S5, the target extended data and the initial decoding result are concatenated to generate the target decoding result.
[0114] Optionally, in this embodiment, those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.
[0115] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0116] If the integrated units in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in the aforementioned computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause one or more computer devices (which may be personal computers, servers, or network devices, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention.
[0117] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0118] In the several embodiments provided in this application, it should be understood that the disclosed client can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or the indirect coupling or communication connection of units or modules may be electrical or other forms.
[0119] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0120] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0121] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for processing graphics processor instructions based on the RISC-V instruction set, characterized in that, The method includes: Decode the current instruction to obtain the initial decoding result; Based on the initial decoding result, determine whether the current instruction is a register extension instruction; If the current instruction is not the register extension instruction, the instruction processing category is determined based on the valid bit information of the target temporary register; wherein, the instruction processing category includes the RISC-V standard decoding category or the concatenation decoding category; wherein, the target temporary register corresponds to the thread bundle in the execution process of the graphics processor, one thread bundle corresponds to one temporary register, and the target temporary register stores the target extended data, the number of the target thread bundle in the execution process of the graphics processor, and the valid bit information; For the concatenation decoding category, target extended data is read from the target temporary register; wherein, the target extended data is the extended data corresponding to the previous register extension instruction; The target extended data and the initial decoding result are concatenated to generate the target decoding result; If the current instruction is the register extension instruction, then based on the initial decoding result, the extended data corresponding to the current instruction is determined; The extended data corresponding to the current instruction is stored in the target register, and the valid bit information of the target register is updated to 1.
2. The method according to claim 1, characterized in that, The target extended data includes at least one of the following: destination operand register extended data, source operand register extended data, and immediate operand extended data.
3. The method according to claim 1, characterized in that, After concatenating the target extended data and the initial decoding result to generate the target decoding result, the method further includes: Update the valid bit information of the target temporary register to 0.
4. The method according to claim 1, characterized in that, Based on the valid bit information of the target register, determine the instruction processing category, including: If the valid bit information of the target register is 1, then the instruction processing category is determined to be the concatenation decoding category; If the valid bit information of the target register is 0, then the instruction processing category is determined to be the RISC-V standard decoding category.
5. The method according to claim 1, characterized in that, The method further includes: The target decoding result is sent to the instruction buffer so that the instruction buffer buffers the target decoding result.
6. The method according to claim 1, characterized in that, The method further includes: For the RISC-V standard decoding category, the initial decoding result is sent to the instruction buffer so that the instruction buffer buffers the initial decoding result.
7. A graphics processor instruction processing device based on the RISC-V instruction set, characterized in that, The device includes: The initial decoding unit is used to decode the current instruction and obtain the initial decoding result; An extended judgment unit is used to determine whether the current instruction is a register extension instruction based on the initial decoding result; A category determination unit is used to determine the instruction processing category based on the valid bit information of the target temporary register if the current instruction is not the register extension instruction; wherein the instruction processing category includes a RISC-V standard decoding category or a concatenation decoding category; wherein the target temporary register corresponds to a thread bundle in the execution process of the graphics processor, with one thread bundle corresponding to one temporary register, and the target temporary register stores the target extension data, the number of the target thread bundle in the execution process of the graphics processor, and the valid bit information; An extended read unit is used to read target extended data from the target register for the concatenation decoding category; wherein the target extended data is the extended data corresponding to the previous register extension instruction; The splicing processing unit is used to splice the target extended data and the initial decoding result to generate the target decoding result; An extended storage unit is used to determine the extended data corresponding to the current instruction based on the initial decoding result if the current instruction is the register extension instruction; store the extended data corresponding to the current instruction in the target temporary register; and update the valid bit information of the target temporary register to 1.