Display device

Abstract

According to one aspect of the disclosure, a display device includes a substrate in which a plurality of sub-pixels having different areas are defined, a light emitting element disposed on each of the plurality of sub-pixels and including an anode and a cathode, a first anode reset line connected to some of the plurality of sub-pixels and outputting a first anode reset voltage to the anode, and a second anode reset line connected to the remaining sub-pixels of the plurality of sub-pixels and outputting a second anode reset voltage to the anode. Accordingly, according to the disclosure, different anode reset voltages are applied according to the areas of the plurality of sub-pixels, so that a voltage deviation of the anode and a color variation according to the areas of the plurality of sub-pixels can be reduced.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device for reducing color variation. Background Technology

[0002] As display devices used for computer monitors, televisions, or cellular phones, there are organic light-emitting display devices (OLEDs) that are self-emissive and liquid crystal display devices (LCDs) that require a separate light source.

[0003] The applications of display devices have diversified to personal digital assistants, computer monitors, and televisions, and research is underway on display devices with larger display areas and reduced size and weight.

[0004] Among various display devices, organic light-emitting displays (OLEDs) are self-emissive, thus requiring no separate light source, unlike liquid crystal displays (LCDs). Therefore, OLEDs can be manufactured with lighter weight and thinner profiles. Furthermore, because OLEDs are driven by low voltage, they offer advantages not only in terms of power consumption but also in color reproduction, response speed, viewing angle, and contrast. Consequently, OLEDs are being researched as the next generation of displays. Summary of the Invention

[0005] One objective of this disclosure is to provide a display device in which leakage current between sub-pixels of different sizes is reduced.

[0006] Another objective of this disclosure is to provide a display device in which the deviation of anode voltage between sub-pixels of different sizes is reduced.

[0007] Another objective of this disclosure is to provide a display device in which color variations depending on the area of ​​the subpixels are reduced.

[0008] Another objective of this disclosure is to provide a display device that reduces color variations when displaying an image with low grayscale levels.

[0009] The objectives of this disclosure are not limited to those described above, and other objectives not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels with different areas; a light-emitting element disposed on each of the plurality of sub-pixels and including an anode and a cathode; a first anode reset line connected to some of the plurality of sub-pixels and outputting a first anode reset voltage to the anode; and a second anode reset line connected to the remaining sub-pixels of the plurality of sub-pixels and outputting a second anode reset voltage to the anode. Therefore, according to this disclosure, by applying different anode reset voltages according to the areas of the plurality of sub-pixels, voltage deviation and color variation of the anode based on the areas of the plurality of sub-pixels can be reduced.

[0011] Further details of exemplary implementations are included in the detailed description and accompanying drawings.

[0012] According to this disclosure, leakage current caused by area differences between multiple sub-pixels can be reduced.

[0013] According to this disclosure, the voltage deviation of the anode caused by the area of ​​multiple sub-pixels is compensated.

[0014] According to this disclosure, color variations that vary depending on the area of ​​the sub-pixels can be reduced.

[0015] According to this disclosure, when displaying an image with a low grayscale level, the image quality degradation due to leakage current can be reduced.

[0016] The effects of this disclosure are not limited to the examples above, and many more different effects are included in this specification. Attached Figure Description

[0017] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 This is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2 This is a schematic enlarged plan view of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 3 This is a circuit diagram of the first sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 4 This is a circuit diagram of the third sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 5 This is a timing diagram of the driving of sub-pixels of a display device according to an exemplary embodiment of the present disclosure; and

[0023] Figure 6 This is a view used to explain the voltage change of the fourth node of a display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0024] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0025] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may also include the plural.

[0026] Even if not explicitly stated, the components will be interpreted as including the normal error range.

[0027] When using terms such as “above,” “over,” “below,” and “adjacent” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used in conjunction with the terms “immediately adjacent” or “directly.”

[0028] When one element or layer is placed "above" another element or layer, the element or layer can be placed directly on the other element or layer, or another element or layer can be inserted between them.

[0029] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be a second component in the technical concept of this disclosure.

[0030] Throughout the specification, the same reference numerals generally denote the same elements.

[0031] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0032] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be technically interlocked and operated in various ways, and these embodiments may be implemented independently or in association with each other.

[0033] In the following, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 This is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 1 For ease of description, only the substrate 110 and a plurality of sub-pixels SP are shown among the various components of the display device 100.

[0035] The substrate 110 is a component for supporting various components included in the display device 100, and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. Furthermore, the substrate 110 may be configured to include polymers or plastics, or may be formed of a flexible material.

[0036] The substrate 110 includes a display area AA and a non-display area NA.

[0037] The display area AA is an area with multiple sub-pixels SP for displaying images. In each of the multiple sub-pixels SP of the display area AA, a light-emitting element and a driving circuit for driving the light-emitting element can be provided. The light-emitting element can vary depending on the type of the display device 100. For example, when the display device 100 is an organic light-emitting display device, the light-emitting element can be an organic light-emitting element comprising an anode, an organic layer, and a cathode. Alternatively, micro light-emitting elements (LEDs) or quantum dot light-emitting elements (QLEDs) comprising quantum dots (QDs) can also be used as the light-emitting element.

[0038] The non-display area NA is an area where no image is displayed and where various wiring and driving ICs for driving the sub-pixels SP disposed in the display area AA are provided. For example, various ICs such as gating driver ICs and data driver ICs, as well as driving circuits, can be provided in the non-display area NA. At the same time, the non-display area NA may be located on the rear surface of the substrate 110 (i.e., the surface on which no sub-pixels SP are disposed) or may be omitted, and is not limited to what is shown in the figure.

[0039] Multiple subpixels SP are defined in the display area AA of the substrate 110. Each of the multiple subpixels SP is a separate unit that emits light, and a light-emitting element and driving circuit are formed in each of the multiple subpixels SP. For example, the multiple subpixels SP may include red subpixels SP, green subpixels SP, blue subpixels SP and / or white subpixels SP, but is not limited thereto. In the following description, for ease of description, it will be described by assuming that the multiple subpixels SP include a first subpixel SP1, a second subpixel SP2 and a third subpixel SP3.

[0040] Figure 2 This is a schematic enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 3 This is a circuit diagram of the first sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 4 This is a circuit diagram of the third sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 3 and Figure 4 The image shows the first sub-pixel SP1 and the third sub-pixel SP3, which are set in the nth row among multiple sub-pixels SP.

[0041] Reference Figure 2 The multiple sub-pixels SP include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can emit different colors of light. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel. However, the implementation is not limited to this. For example, the multiple sub-pixels SP may also include two or more sub-pixels that emit different colors.

[0042] The sizes of multiple subpixels SP can vary. By considering the lifetime or color balance of the light-emitting elements EL included in each of the first subpixel SP1, second subpixel SP2, and third subpixel SP3, the first subpixel SP1, second subpixel SP2, and third subpixel SP3 can be designed to have different sizes. For example, the size of the first subpixel SP1 can be equal to or similar to the size of the second subpixel SP2. The size of the third subpixel SP3 among the multiple subpixels SP can be the largest.

[0043] At this time, based on the size of each of the multiple sub-pixels SP, the multiple sub-pixels SP can be connected to different anode reset lines ARL. Specifically, the first sub-pixel SP1 and the second sub-pixel SP2, which have the same size, are connected to the first anode reset line ARL1. The third sub-pixel SP3, which has the largest size, can be connected to the second anode reset line ARL2. In the display device 100 according to an exemplary embodiment of this disclosure, the multiple sub-pixels SP are connected to different anode reset lines ARL based on their sizes. By doing so, when the light-emitting element EL emits light, the voltage deviation of the fourth node N4 can be reduced, and leakage current and color change can be reduced.

[0044] Specifically, refer to Figure 3 The first sub-pixel SP1 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor DT, a storage capacitor CST, and a light-emitting element EL. Furthermore, the first sub-pixel SP1 is connected to multiple scan lines, data lines, light-emitting control signal lines, initialization lines, a first anode reset line ARL1, high-potential power lines, and low-potential power lines.

[0045] The first sub-pixel SP1 includes multiple transistors. These transistors can be formed from different types of transistors. For example, one of the transistors can be a transistor with an oxide semiconductor as the active layer. Oxide semiconductor materials have low cutoff current, making them suitable for switching transistors that maintain short on-times and long off-times.

[0046] As another example, one of the multiple transistors could be a transistor with low-temperature polycrystalline silicon (LTPS) as its active layer. Polycrystalline silicon has high mobility, resulting in low power consumption and excellent reliability, making it suitable for driving transistors (DT).

[0047] Furthermore, multiple transistors can be either N-type or P-type transistors. In an N-type transistor, the charge carriers are electrons, allowing electrons to flow from the source electrode to the drain electrode, and current to flow from the drain electrode to the source electrode. In a P-type transistor, the charge carriers are holes, allowing holes to flow from the source electrode to the drain electrode, and current to flow from the source electrode to the drain electrode. For example, one of the multiple transistors can be an N-type transistor, and another of the multiple transistors can be a P-type transistor.

[0048] For example, the first transistor T1 can be an N-type transistor with an oxide semiconductor as its active layer. Furthermore, the driving transistor DT, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type transistors with low-temperature polysilicon as their active layer. However, the materials of the active layers forming the multiple transistors and the types of multiple transistors are illustrative and not limited thereto.

[0049] The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the driving transistor DT is connected to the second node N2, the source electrode is connected to the first node N1, and the drain electrode is connected to the third node N3. The driving current flows through the driving transistor DT to the light-emitting element EL.

[0050] The first transistor T1 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first transistor T1 is connected to the first scan line of the nth row, and the source and drain electrodes are connected between the second node N2 and the third node N3. The first transistor T1 is turned on by the first scan signal SCAN1(n) to electrically connect the second node N2 and the third node N3.

[0051] The second transistor T2 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second transistor T2 is connected to the second scan line of the nth row, and the source and drain electrodes are connected between the data line and the first node N1. The second transistor T2 is turned on by the second scan signal SCAN2(n) to provide a data voltage Vdata from the data line to the first node N1.

[0052] The third transistor T3 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third transistor T3 is connected to the light-emitting control signal line in the nth row, and the source and drain electrodes are connected between the high-potential power supply line and the first node N1. The third transistor T3 is turned on by the light-emitting control signal EM(n) to transmit the high-potential power supply voltage VDD to the first node N1.

[0053] The fourth transistor T4 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fourth transistor T4 is connected to the light-emitting control signal line in the nth row, and the source and drain electrodes are connected to the third node N3 and the fourth node N4. The fourth transistor T4 is turned on by the light-emitting control signal EM(n) to transfer drive current from the driving transistor DT to the light-emitting element EL.

[0054] The fifth transistor T5 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fifth transistor T5 is connected to the third scan line of the nth row, and the source and drain electrodes are connected between the initialization line and the third node N3. When the fifth transistor T5 is turned on by the third scan signal SCAN3(n), the fifth transistor T5 can transmit the initialization voltage Vini(n) to the third node N3.

[0055] The sixth transistor T6 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the sixth transistor T6 is connected to the third scan line of row (n+1), and the source and drain electrodes are connected between the first anode reset line ARL1 and the fourth node N4. The sixth transistor T6 is turned on by the third scan line SCAN3(n+1) to transmit the first anode reset voltage VAR1 of the first anode reset line ARL1 to the fourth node N4.

[0056] The storage capacitor Cst comprises multiple capacitor electrodes. Some of these electrodes are connected to a high-potential power supply line, while others are connected to a second node N2. The voltage at the gate electrode of the driving transistor DT can be stored in the storage capacitor Cst.

[0057] The light-emitting element EL includes an anode and a cathode. The anode of the light-emitting element EL is connected to the fourth node N4, and the cathode is connected to a low-potential power line supplied with a low-potential power supply voltage VSS. The light-emitting element EL can emit light through a drive current from the driving transistor DT.

[0058] Reference Figure 4 Except for the sixth transistor T6 being connected to the second anode reset line ARL2, the third sub-pixel SP3 has the same configuration as the first sub-pixel SP1. Specifically, the third sub-pixel SP3 includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the driving transistor DT, the storage capacitor Cst, and the light-emitting element EL. Furthermore, the third sub-pixel SP3 is connected to multiple scan lines, data lines, light-emitting control signal lines, initialization lines, the second anode reset line ARL2, high-potential power lines, and low-potential power lines.

[0059] The sixth transistor T6 of the third sub-pixel SP3 is turned on by the third scan signal SCAN3(n+1) to transmit the second anode reset voltage VAR2 of the second anode reset line ARL2 to the fourth node N4.

[0060] At the same time, even Figure 3 and Figure 4Not shown, the second sub-pixel SP2 can also have the same configuration as the first sub-pixel SP1. The second sub-pixel SP2 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor DT, a storage capacitor Cst, and a light-emitting element EL. The second sub-pixel SP2 is connected to multiple scan lines, data lines, light-emitting control signal lines, initialization lines, a first anode reset line ARL1, high-potential power lines, and low-potential power lines.

[0061] In the following text, reference will be made to Figure 5 This invention describes a method for driving a sub-pixel SP according to an exemplary embodiment of the present disclosure.

[0062] Figure 5 This is a timing diagram of the driving of sub-pixels of a display device according to an exemplary embodiment of the present disclosure. Figure 6 This is a view used to explain the voltage change of the fourth node of a display device according to an exemplary embodiment of the present disclosure.

[0063] Reference Figure 5 At the first time t1, a low-level third scan signal SCAN3(n) is output from the third scan line in the nth row. Therefore, the fifth transistor T5 is turned on, causing the initialization voltage Vini(n) to be transmitted to the third node N3 of each of the multiple sub-pixels SP. Thus, the voltage of the third node N3 can be initialized to the initialization voltage Vini(n) at the first time t1.

[0064] Next, at the second time t2, a low-level third scan signal SCAN3(n+1) is output from the third scan line in row n+1. In this case, the sixth transistor T6 is turned on, causing the first anode reset voltage VAR1 to be applied to the fourth node N4 of the first sub-pixel SP1 and the second sub-pixel SP2, and the second anode reset voltage VAR2 to be applied to the fourth node N4 of the third sub-pixel SP3. Therefore, the fourth node N4 of each of the multiple sub-pixels SP can be initialized to either the first anode reset voltage VAR1 or the second anode reset voltage VAR2.

[0065] Next, at the third time t3, a high-level first scan signal SCAN1(n) is output from the first scan line in the nth row. The first transistor T1 is turned on by the high-level first scan signal SCAN1(n) and can be electrically connected to the second node N2 and the third node N3. The turn-on of the first transistor T1 allows the driving transistor DT to be in a diode-connected state to function as a diode.

[0066] Next, at the fourth time t4, a low-level second scan signal SCAN2(n) is output from the second scan line in the nth row. The second transistor T2 is turned on by the second scan signal SCAN2(n) and can transmit the data voltage Vdata to the first node N1.

[0067] At this time, the voltage at the gate electrode of the driving transistor DT, which is now in a diode-connected state via the first transistor T1, can be changed to the difference between the data voltage Vdata and the threshold voltage Vth. Therefore, the voltage obtained by subtracting the voltage at the gate electrode of the driving transistor DT from the high-potential power supply voltage VDD can be stored in the storage capacitor Cst connected between the second node N2, which serves as the gate electrode of the driving transistor DT, and the high-potential power supply line. In other words, the voltage obtained by subtracting the data voltage Vdata from the high-potential power supply voltage VDD and adding the threshold voltage Vth can be stored in the storage capacitor Cst. Therefore, the threshold voltage Vth of the driving transistor DT is sampled, and the data voltage Vdata can be stored in the storage capacitor Cst.

[0068] Next, at time t5, a low-level third scan signal SCAN3(n) is output from the third scan line in row n, and at time t6, a low-level third scan signal SCAN3(n+1) is sequentially output from the third scan line in row n+1. At time t5, the initialization voltage Vini(n) is applied to the third node N3, and at time t6, either the first anode reset voltage VAR1 or the second anode reset voltage VAR2 is applied to the fourth node N4 to perform on-bias stress.

[0069] On-bias stress is the process of initializing a transistor to a specific state and applying it to mitigate transistor hysteresis. Transistors exhibit hysteresis, meaning their characteristics change in the current frame depending on their operating state in the previous frame. For example, even if the same data voltage Vdata is provided to the driving transistor DT, different levels of drive current may be generated depending on the operating state in the previous frame. Therefore, on-bias stress is applied to multiple transistors to initialize their characteristics to a predetermined state. For instance, applying the same on-bias stress to each of multiple sub-pixels SP initializes a specific transistor in each of the multiple sub-pixels SP to the same state, resulting in light with the same brightness in all sub-pixels SP provided with the same data voltage Vdata in the subsequent frame.

[0070] Finally, at time t7, a low-level light emission control signal EM(n) is output to the light emission control signal line in the nth row, enabling the light-emitting element EL to emit light. The third transistor T3 and the fourth transistor T4 are turned on by the light emission control signal EM(n) to transfer the drive current from the drive transistor DT to the light-emitting element EL. Therefore, the light-emitting element EL can emit light with a specific brightness based on the drive current.

[0071] Simultaneously, a parasitic capacitor, Colled, can be formed parasitically between the anode and cathode in the light-emitting element (EL). The capacitance of the Colled capacitor may vary depending on the area of ​​each of the multiple sub-pixels (SPs). A larger dielectric constant or area generally results in a higher capacitance. In this case, as the area of ​​the sub-pixel SP increases, the dimensions of the anode and cathode of the EL also increase, and the capacitance of the Colled capacitor may increase. For example, the capacitance of the Colled capacitor in the third sub-pixel SP3, which has the largest area, may be higher than that in the first sub-pixel SP1 and the second sub-pixel SP2.

[0072] However, because the capacitance of the parasitic capacitor Colled varies depending on the area of ​​each of the multiple sub-pixels SP, it can cause a deviation in the voltage of the anode of the light-emitting element EL (the voltage of the fourth node N4). If the voltage of the fourth node N4 of a particular sub-pixel SP is relatively high, leakage current is transferred to another sub-pixel SP, causing that sub-pixel SP to emit light. Specifically, when displaying an image with a low grayscale level close to black, some sub-pixel SPs emit light through leakage current, making it difficult to represent images with low grayscale levels. Therefore, due to the capacitance difference of the parasitic capacitor Colled and the voltage deviation of the fourth node N4, a color change in the light emitted from the sub-pixel SP may occur.

[0073] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, multiple sub-pixels SP are connected to different anode reset lines ARL, taking into account the area of ​​the multiple sub-pixels SP. By doing so, voltage deviations at the fourth node N4 can be compensated, and color changes due to leakage current can be reduced.

[0074] Specifically, the voltage change ΔN4 at the fourth node N4 can be determined by Equation 1. N3 voltage and N4 voltage It is the voltage between the third node N3 and the fourth node N4, N3 cap It is the capacitor at the third node N3, and N4 cap It is the capacitor at the fourth node, N4. N3 cap and N4 capThis refers to the capacitance of the capacitor formed between the third node N3 and the adjacent structure, and the capacitance of the capacitor formed between the fourth node N4 and the adjacent structure.

[0075] [Equation 1]

[0076]

[0077] When the fourth transistor T4 turns on, connecting the third node N3 and the fourth node N4, the voltage of the third node N3 is distributed, and the voltage of the fourth node N4 may rise. At this time, the voltage change ΔN4 of the fourth node N4 (i.e., the amount of voltage rise of the fourth node N4) can vary depending on the capacitance of the fourth node N4.

[0078] At this point, most of the capacitance of the fourth node N4 can be formed by the parasitic capacitor Colled. That is, the capacitance of the fourth node N4 is similar to the capacitance of the parasitic capacitor Colled. However, when the areas of multiple sub-pixels SP are different, the capacitance of the parasitic capacitor Colled can be different, and the voltage change ΔN4 of the fourth node N4 can also be different.

[0079] Combined with reference Figure 6 At the seventh moment t7 when the fourth transistor T4 is turned on, the third node N3 and the fourth node N4 are connected. The voltage of the third node N3 is distributed, and the voltage of the fourth node N4 can rise. The initial voltage Vini(n) of the third node N3 can be higher than the first anode reset voltage VAR1 and the second anode reset voltage VAR2. Therefore, the voltage of the fourth node N4 can vary within a range between the first anode reset voltage VAR1 and the initial voltage Vini(n) of the third node N3, or between the second anode reset voltage VAR2 and the initial voltage Vini(n) of the third node N3.

[0080] At this point, in the third sub-pixel SP3, which has the largest area, the parasitic capacitor Coled of the light-emitting element EL has the highest capacitance, allowing the voltage change ΔN4 of the fourth node N4 to be minimized. Furthermore, when the first sub-pixel SP1 and the second sub-pixel SP2 have smaller areas, the capacitance of the parasitic capacitor Coled is relatively small, allowing the voltage change ΔN4 of the fourth node N4 to be larger.

[0081] Therefore, when the third sub-pixel SP3 has the smallest voltage change ΔN4 at the fourth node N4 (i.e., the smallest voltage rise at the fourth node N4), a second anode reset voltage VAR2 with a relatively high level is applied to the fourth node N4. Conversely, when the first sub-pixel SP1 and the second sub-pixel SP2 have larger voltage changes ΔN4 and voltage rises at the fourth node N4, a first anode reset voltage VAR1 with a lower level is applied to the fourth node N4.

[0082] Although the voltage change ΔN4 of the fourth node N4 in the third sub-pixel SP3 is lower than the voltage change ΔN4 of the fourth node N4 in the first sub-pixel SP1 and the second sub-pixel SP2, the initial voltage of the fourth node N4 in the third sub-pixel SP3 is a second anode reset voltage VAR2 with a relatively high level. Therefore, immediately after turning on the fourth transistor T4, the voltage deviation of the fourth node N4 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be compensated. To compensate for the difference between the voltage change ΔN4 of the fourth node N4 in the third sub-pixel SP3 and the voltage change ΔN4 of the fourth node N4 in the first sub-pixel SP1 and the second sub-pixel SP2, the first anode reset voltage VAR1 and the second anode reset voltage VAR2 can be set. For example, when the voltage change ΔN4 of the fourth node N4 in the third sub-pixel SP3 is A and the voltage change ΔN4 of the fourth node N4 in the first sub-pixel SP1 and the second sub-pixel SP2 is B, the second anode reset voltage VAR2 can be set to a value obtained by adding the difference between A and B to the first anode reset voltage VAR1. In other words, the voltage of the fourth node N4 of the third sub-pixel SP3 is initialized to the second anode reset voltage VAR2, and the voltage of the fourth node N4 of the first sub-pixel SP1 and the second sub-pixel SP2 is initialized to the first anode reset voltage VAR1. By doing so, the deviation ΔN4 caused by the voltage change of the fourth node N4 based on the difference in the parasitic capacitor Coled can be compensated, and the voltage deviation among the fourth nodes N4 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be reduced.

[0083] Therefore, when the fourth node N4 of multiple sub-pixels SP is initialized with different anode reset voltages, causing the fourth transistor T4 to conduct to connect the third node N3 and the fourth node N4, the difference in voltage change ΔN4 of the fourth node is compensated. Furthermore, this can reduce leakage current and color variations.

[0084] If the same anode reset voltage is applied to the fourth node N4 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, a voltage deviation in the fourth node N4 may occur between the third sub-pixel SP3, which has a relatively small voltage change ΔN4, and the first and second sub-pixels SP1 and SP2, which have relatively large voltage changes ΔN4. Immediately after the fourth transistor T4 turns on at time t7, the voltage of the fourth node N4 of the third sub-pixel SP3, which rises due to the voltage of the third node N3, may be lower than the voltage of the fourth node N4 of the first and second sub-pixels SP1 and SP2. Therefore, when the light-emitting element EL begins to emit light, a voltage deviation in the fourth node N4 occurs from time t7, potentially causing leakage current and color changes.

[0085] Therefore, in the display device 100 according to the exemplary embodiment of this disclosure, the anode reset voltage applied to the fourth node N4 can be set differently considering the size of each of the plurality of sub-pixels SP and the capacitance of the parasitic capacitor Colled. Specifically, when the fourth transistor T4 is turned on, connecting the third node N3 and the fourth node N4, the voltage of the third node N3 is distributed and the voltage of the fourth node N4 can vary. At this time, the voltage change ΔN4, which is the amount of voltage rise of the fourth node N4, decreases as the capacitance of the fourth node N4 increases, and can be inversely proportional to the capacitance of the fourth node N4. At this time, the parasitic capacitor Colled of the light-emitting element EL occupies most of the capacitance of the fourth node N4, so that the capacitance of the fourth node N4 can vary according to the parasitic capacitor Colled. Furthermore, as the size of the light-emitting element EL, which is the area of ​​the sub-pixel SP, increases, the capacitance of the parasitic capacitor Colled increases. In this case, the parasitic capacitor Colled of the third sub-pixel SP3, which has the largest area, has the highest capacitance, so that the voltage change ΔN4 of the fourth node N4 of the third sub-pixel SP3 can be minimized. Therefore, the fourth node N4 of the third sub-pixel SP3, which has the largest size, is initialized to a second anode reset voltage VAR2 with a relatively high level. The fourth node N4 of the first sub-pixel SP1 and the second sub-pixel SP2, which have relatively smaller sizes, is initialized to a first anode reset voltage VAR1 with a relatively low level. Therefore, when the third node N3 and the fourth node N4 are connected, the voltage of the fourth node N4 of the third sub-pixel SP3 rises from the second anode reset voltage VAR2, and the voltage of the fourth node N4 of the first sub-pixel SP1 and the second sub-pixel SP2 rises from the first anode reset voltage VAR1. In this case, the voltage change ΔN4 of the fourth node N4 of the third sub-pixel SP3 is less than the voltage change ΔN4 of the fourth node N4 of the first sub-pixel SP1 and the second sub-pixel SP2. Therefore, the voltage deviation of the fourth node N4 among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be reduced. In summary, in the third sub-pixel SP3 with a lower voltage rise of the fourth node N4, the fourth node N4 is initialized to a second anode reset voltage VAR2 with a relatively high level. In the first sub-pixel SP1 and the second sub-pixel SP2, which have a higher voltage rise of the fourth node N4, the fourth node N4 is initialized to a first anode reset voltage VAR1 with a relatively low level, thereby compensating for the deviation of the voltage change ΔN4 of the fourth node N4. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the anode reset voltage of the fourth node N4 applied to each of the plurality of sub-pixels SP can be configured differently, taking into account the size of the plurality of sub-pixels SP and the parasitic capacitor Coled. Therefore, color changes caused by voltage deviation of the fourth node N4 can be reduced.

[0086] Exemplary embodiments of this disclosure can also be described as follows:

[0087] According to one aspect of this disclosure, a display device is provided. The display device includes: a substrate defining a plurality of sub-pixels with different areas; a light-emitting element disposed on each of the plurality of sub-pixels and including an anode and a cathode; a first anode reset line connected to some of the plurality of sub-pixels and outputting a first anode reset voltage to the anode; and a second anode reset line connected to the remaining sub-pixels of the plurality of sub-pixels and outputting a second anode reset voltage to the anode.

[0088] The multiple sub-pixels may include: a first sub-pixel connected to a first anode reset line; a second sub-pixel connected to the first anode reset line; and a third sub-pixel connected to a second anode reset line. The area of ​​the third sub-pixel may be larger than the area of ​​the first sub-pixel and the area of ​​the second sub-pixel.

[0089] The second anode reset voltage can be higher than the first anode reset voltage.

[0090] Each of the plurality of sub-pixels may include: a driving transistor, wherein a gate electrode is connected to a second node and a source electrode and a drain electrode are connected between a first node and a third node; a first transistor, wherein a source electrode and a drain electrode are connected between a second node and a third node; a second transistor, wherein a source electrode and a drain electrode are connected between a first node and a data line; a third transistor, wherein a source electrode and a drain electrode are connected between a high-potential power line and a first node; a fourth transistor, wherein a source electrode and a drain electrode are connected between a third node and a fourth node; a fifth transistor, wherein a source electrode and a drain electrode are connected between an initialization line and a third node; and a sixth transistor, wherein a drain electrode is connected to a fourth node and an anode may be connected to a fourth node.

[0091] The source electrode of the sixth transistor of the first sub-pixel and the second sub-pixel can be connected to the first anode reset line, and the source electrode of the sixth transistor of the third sub-pixel can be connected to the second anode reset line. When the sixth transistor is turned on, the first anode reset voltage or the second anode reset voltage can be transmitted to the fourth node.

[0092] When the fourth transistor is turned on, the voltage of the fourth node can rise through the voltage of the third node.

[0093] When the fourth transistor of the first sub-pixel and the second sub-pixel is turned on, the voltage of the fourth node can vary between the voltage of the third node and the first anode reset voltage. And when the fourth transistor of the third sub-pixel is turned on, the voltage of the fourth node can vary between the voltage of the third node and the second anode reset voltage.

[0094] When the fourth transistor is turned on, the smaller the area of ​​each of the multiple sub-pixels, the greater the voltage change of the fourth node.

[0095] When the fourth transistor is turned on, the voltage change of the fourth node of the third sub-pixel can be less than the voltage change of the fourth node of the first sub-pixel.

[0096] When the fourth transistor is turned on, the voltage change of the fourth node of the third sub-pixel can be less than the voltage change of the fourth node of the second sub-pixel.

[0097] Each of the multiple sub-pixels may also include a parasitic capacitor located between the anode and cathode, and the larger the area of ​​the multiple sub-pixels, the higher the capacitance of the parasitic capacitor.

[0098] When the fourth transistor is turned on, the higher the capacitance of the parasitic capacitor, the smaller the voltage change at the fourth node.

[0099] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0100] Cross-reference to related applications

[0101] This application claims priority to Korean Patent Application No. 10-2021-0186104, filed on December 23, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Claims

1. A display device, the display device comprising: A substrate, wherein a plurality of sub-pixels with different areas are defined; A light-emitting element, wherein the light-emitting element is disposed on each of the plurality of sub-pixels, and includes an anode and a cathode; A first anode reset line is connected to at least one of the plurality of sub-pixels and outputs a first anode reset voltage to the anode. as well as The second anode reset line is connected to at least one of the remaining sub-pixels among the plurality of sub-pixels, and outputs a second anode reset voltage to the anode. Wherein, the area of ​​at least one sub-pixel among the plurality of sub-pixels is smaller than the area of ​​at least one other sub-pixel among the remaining sub-pixels, and The second anode reset voltage is higher than the first anode reset voltage.

2. The display device according to claim 1, wherein, The plurality of sub-pixels includes: The first sub-pixel is connected to the first anode reset line; The second sub-pixel is connected to the first anode reset line; and The third sub-pixel is connected to the second anode reset line, and The area of ​​the third sub-pixel is greater than the area of ​​the first sub-pixel and the area of ​​the second sub-pixel.

3. The display device according to claim 2, wherein, The first sub-pixel and the second sub-pixel are either red or green sub-pixels, and the third sub-pixel is a blue sub-pixel.

4. The display device according to claim 2, wherein, Each of the plurality of sub-pixels includes: A driving transistor in which the gate electrode is connected to a second node, and the source electrode and drain electrode are connected between a first node and a third node; A first transistor, wherein the source electrode and the drain electrode are connected between the second node and the third node; The second transistor has its source and drain electrodes connected between the first node and the data line. A third transistor, wherein the source electrode and the drain electrode are connected between a high-potential power line and the first node; A fourth transistor, wherein the source electrode and the drain electrode are connected between the third node and the fourth node; A fifth transistor, wherein the source and drain electrodes are connected between the initialization line and the third node; and A sixth transistor, in which the drain electrode is connected to the fourth node, and The anode is connected to the fourth node.

5. The display device according to claim 4, wherein, The source electrode of the sixth transistor of the first sub-pixel and the second sub-pixel is connected to the first anode reset line, and the source electrode of the sixth transistor of the third sub-pixel is connected to the second anode reset line. When the sixth transistor is turned on, the first anode reset voltage or the second anode reset voltage is transmitted to the fourth node.

6. The display device according to claim 5, wherein, When the fourth transistor is turned on, the voltage of the fourth node rises through the voltage of the third node.

7. The display device according to claim 5, wherein, When the fourth transistor of the first sub-pixel and the second sub-pixel is turned on, the voltage of the fourth node varies within the range between the voltage of the third node and the first anode reset voltage, and When the fourth transistor of the third sub-pixel is turned on, the voltage of the fourth node varies within the range between the voltage of the third node and the second anode reset voltage.

8. The display device according to claim 7, wherein, When the fourth transistor is turned on, the smaller the area of ​​each of the plurality of sub-pixels, the greater the voltage change of the fourth node.

9. The display device according to claim 7, wherein, When the fourth transistor is turned on, the voltage change of the fourth node of the third sub-pixel is less than the voltage change of the fourth node of the first sub-pixel.

10. The display device according to claim 9, wherein, The second anode reset voltage is set to a value obtained by adding the difference between the voltage change of the fourth node of the third sub-pixel and the voltage change of the fourth node of the first sub-pixel to the first anode reset voltage.

11. The display device according to claim 7, wherein, When the fourth transistor is turned on, the voltage change of the fourth node of the third sub-pixel is less than the voltage change of the fourth node of the second sub-pixel.

12. The display device according to claim 4, wherein, Each of the plurality of sub-pixels also includes a parasitic capacitor located between the anode and the cathode, and The larger the area of ​​the plurality of sub-pixels, the higher the capacitance of the parasitic capacitor.

13. The display device according to claim 12, wherein, When the fourth transistor is turned on, the higher the capacitance of the parasitic capacitor, the smaller the voltage change of the fourth node.

14. The display device according to claim 1, wherein, Subpixels that emit light of the same color among the plurality of subpixels are connected to the same anode reset line.

15. The display device according to claim 1, wherein, The plurality of sub-pixels includes: A first sub-pixel, the first sub-pixel being connected to the first anode reset line; and The second sub-pixel is connected to the second anode reset line, and The area of ​​the second sub-pixel is larger than the area of ​​the first sub-pixel.

16. The display device according to claim 15, wherein, The first anode reset voltage is lower than the second anode reset voltage.

17. The display device according to claim 1, wherein, The first anode reset voltage is different from the second anode reset voltage.

Images