Electroluminescent display device

Abstract

An electroluminescent display device is provided. The electroluminescent display device includes a pixel including a driving element having a gate electrode connected to a data line and a source electrode connected to a reference voltage line, and a pixel driving circuit that applies a sensing data voltage to the gate electrode of the driving element through the data line in a plurality of vertical blanking periods, detects a source electrode voltage of the driving element shifted from a sensing reference voltage based on the sensing data voltage through the reference voltage line to obtain a detection voltage, calculates an offset voltage based on the detection voltage, and reduces a level of the sensing data voltage based on the offset voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0181004, filed on December 16, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to electroluminescent display devices. Background Technology

[0004] In an active-matrix electroluminescent display device, multiple pixels, each including a light-emitting device and a driving element, are arranged in a matrix, and the brightness of the image realized by the pixels is adjusted based on the gray levels of the image data. The driving element controls the pixel current flowing in the light-emitting device based on the voltage applied between its gate electrode and source electrode (hereinafter referred to as the gate-source voltage). The amount of light emitted by the light-emitting device and the brightness of the screen are determined based on the pixel current.

[0005] Because the threshold voltage of the driving element determines the driving characteristics of a pixel, the threshold voltage of the driving element in all pixels should be equal. However, due to various reasons such as process variations and degradation characteristic variations, the threshold voltage between pixels may differ. Such threshold voltage differences lead to brightness variations between pixels, thus limiting the achievement of the desired image.

[0006] Conventional techniques are known for sensing and compensating for threshold voltage differences between driving elements, but it is difficult to apply these conventional techniques to real-time driving of display input images (i.e., display driving). Summary of the Invention

[0007] In order to overcome the above-mentioned problems in the related technologies, this disclosure provides an electroluminescent display device for sensing and compensating the threshold voltage of the driving element in real-time driving.

[0008] To achieve these objectives and other advantages and aspects of this disclosure, as realized and broadly described herein, in one or more aspects, an electroluminescent display device may include: a pixel, the pixel including a driving element having a gate electrode connected to a data line and a source electrode connected to a reference voltage line; and a pixel driving circuit for applying a sensed data voltage to the gate electrode of the driving element via the data line during a plurality of vertical blanking periods, detecting a source electrode voltage of the driving element shifted from a sensed reference voltage based on the sensed data voltage via the reference voltage line to obtain a detection voltage, calculating an offset voltage based on the detection voltage, and reducing the level of the sensed data voltage based on the offset voltage. The pixel driving circuit may apply an nth (where n is a natural number 2 or greater) sensed data voltage to the gate electrode of the driving element during a vertical blanking period of the nth frame, and may apply an (n-1)th sensed data voltage to the gate electrode of the driving element during a vertical blanking period of the (n-1)th frame preceding the nth frame. The nth sensed data voltage may be lower than the (n-1)th sensed data voltage.

[0009] In one or more aspects of this disclosure, an electroluminescent display device may include: a pixel, the pixel including a driving element, the driving element including a gate electrode connected to a data line and a source electrode connected to a reference voltage line; and a pixel driving circuit, the pixel driving circuit being configured to apply an nth (where n is a natural number 2 or greater) sensed data voltage to the gate electrode of the driving element via the data line, store the source electrode voltage of the driving element shifted from a sensed reference voltage based on the nth sensed data voltage as an nth offset voltage, and calculate an nth detection voltage reduced by the nth offset voltage based on the nth sensed data voltage. The pixel driving circuit may apply the (n-1)th sensed data voltage to the gate electrode of the driving element during a vertical blanking period of the (n-1)th frame preceding the nth frame. The nth sensed data voltage may be lower than the (n-1)th sensed data voltage. Attached Figure Description

[0010] This invention includes accompanying drawings to provide a further understanding of the present disclosure. These drawings are included in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. In the drawings:

[0011] Figure 1 This is a schematic diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure;

[0012] Figure 2 Is showing the connection to Figure 1 A diagram showing the configuration of the pixel array and the data driver for the power circuitry;

[0013] Figure 3This is a diagram showing the connection configuration between the pixel driving circuit and the pixel for sensing the threshold voltage of the driving element included in the pixel;

[0014] Figure 4 This shows the use of sensing drive. Figure 3 A diagram showing the driving waveform implemented using conventional techniques in a comparative example of pixel driving circuits;

[0015] Figure 5A and Figure 5B This is shown in the sensor drive Figure 3 A diagram illustrating the technical implementation for sensing the threshold voltage of the driving element in an embodiment of the pixel driving circuit.

[0016] Figure 6 and Figure 7 This is a diagram illustrating an application example of the technical implementation of this disclosure based on the threshold voltage level of the driving element;

[0017] Figure 8 This is a diagram illustrating other connection configurations between the pixel driving circuitry and the pixel for sensing the threshold voltage of the driving elements included in the pixel;

[0018] Figure 9 This demonstrates the display driver during the vertically active time period of multiple frames. Figure 8 A diagram of the driving waveform of the pixel driving circuit;

[0019] Figure 10A and Figure 10B This is shown as the first sensing drive during the vertical effective time period of the first frame. Figure 8 The graph shows the node voltage changes and driving waveforms of the pixel driving circuit.

[0020] Figure 11A and Figure 11B This is shown as the second sensing drive during the vertical effective time period of the second frame. Figure 8 The graph shows the node voltage changes and driving waveforms of the pixel driving circuit.

[0021] Figure 12 This shows the (n-1)th sensing drive in the vertical effective time period of the (n-1)th frame. Figure 8 A diagram of the driving waveform of the pixel driving circuit; and

[0022] Figure 13 This shows the nth sensing drive during the vertical effective time period of the nth frame. Figure 8 The diagram shows the driving waveform of the pixel driving circuit. Detailed Implementation

[0023] In the following description, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the implementation and scope of the present disclosure to those skilled in the art.

[0024] The advantages and features of this disclosure, and its implementation methods, will become clearer through the embodiments described below in conjunction with the accompanying drawings. Furthermore, this disclosure is limited only by the scope of the claims.

[0025] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings for describing various embodiments of this disclosure are merely exemplary, and the disclosure is not limited thereto. The same reference numerals always refer to the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms "comprising," "having," "including," etc., imply that additional parts may be added, unless the term "only" is used. As used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0026] Elements in various embodiments of this disclosure are to be interpreted as including error ranges, even if not explicitly indicated.

[0027] When describing positional relationships, for example, when describing the positional relationship between two parts as “above,” “over,” “below,” and “adjacent,” one or more other parts may be located between the two parts, unless “exactly” or “directly” is used.

[0028] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0029] The same reference numerals always refer to the same elements.

[0030] In this specification, the pixel circuitry disposed on the substrate of the display panel can be implemented using a thin-film transistor (TFT) with an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure, but is not limited thereto, and can also be implemented using a TFT with a p-type MOSFET structure. The TFT can be a three-electrode element including a gate, a source, and a drain. The source can be the electrode that supplies charge carriers to the transistor. In a TFT, charge carriers can flow from the source. The drain can be the electrode that allows charge carriers to flow out of the TFT. That is, in a MOSFET, charge carriers flow from the source to the drain. In an n-type TFT (NMOS), because the charge carriers are electrons, the source voltage can be lower than the drain voltage, thus allowing electrons to flow from the source to the drain. In an n-type TFT, because electrons flow from the source to the drain, current can flow from the drain to the source. On the other hand, in a p-type TFT (PMOS), because the charge carriers are holes, the source voltage is higher than the drain voltage, causing holes to flow from the source to the drain. In a p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It's important to note that the source and drain of a MOSFET are not fixed; they switch between each other. For example, the source and drain of a MOSFET can switch between each other.

[0031] Furthermore, in this disclosure, the semiconductor layer of the TFT can be implemented using at least one of oxide elements, amorphous silicon elements, and polycrystalline silicon elements.

[0032] In the following description, detailed descriptions of relevant known functions or configurations will be omitted where they would unnecessarily obscure the focus of this disclosure. Hereinafter, embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure. Figure 2 Is showing the connection to Figure 1 A diagram showing the configuration of the pixel array and the data driver for the power circuit.

[0034] Reference Figure 1 and Figure 2 An electroluminescent display device according to an embodiment of the present disclosure may include a display panel 10, a gate driving circuit 15, a timing controller 20, a data driving circuit 25, and a power circuit 30.

[0035] Display panel 10 may include multiple pixel lines PNL1 to PNL4, and each of pixel lines PNL1 to PNL4 may include multiple pixels PXL and multiple signal lines. The term "pixel line" as described herein may not be a physical signal line, and may refer to a set of signal lines and pixels PXL adjacent to each other in the extension direction of the gate line. Signal lines may be connected to pixels PXL. Signal lines may include: multiple data lines 140 for providing display data voltage Vdata and sensing data voltage Svdata to pixels PXL; multiple reference voltage lines 150 for providing pixel reference voltage VPRER and sensing reference voltage VPRES to pixels PXL and reading offset voltage VSIO from pixels PXL; multiple gate lines 160 for providing gate signal SCAN to pixels PXL; and multiple high-level power lines PWL for providing high-level pixel voltages to pixels PXL.

[0036] The pixels PXL of the display panel 10 can be arranged in a matrix to configure a pixel array. Each pixel PXL included in the pixel array can be connected to one of the data lines 140, one of the reference voltage lines 150, one of the high-level power lines PWL, and one of the gate lines 160. Each pixel PXL can also receive a low-level pixel voltage from the power circuit 30.

[0037] The timing controller 20 can generate a gate timing control signal GDC for controlling the operation timing of the gate drive circuit 15 and a data timing control signal DDC for controlling the operation timing of the data drive circuit 25 by referring to timing signals input from the host system (e.g., vertical synchronization signal Vsync, horizontal synchronization signal Hsync, dot clock signal DCLK, and data enable signal DE).

[0038] The data timing control signal DDC may include, but is not limited to, the source start pulse, the source sampling clock, and the source output enable signal. The gate timing control signal GDC may include, but is not limited to, the gate start signal and the gate shift clock.

[0039] The timing controller 20 can control the operating timing of the gate drive circuit 15 and the data drive circuit 25 to sense the driving characteristics of pixel PXL during the vertical blanking period of each frame. In this case, the timing controller 20 can sense the driving characteristics of the same pixel multiple times consecutively using multiple vertical blanking periods, thereby allowing the sensing and compensation of the threshold voltage of the driving element included in each pixel PXL in real-time driving where the input image is displayed. The real-time sensing method according to this embodiment can be a method in which the sensing data voltage SVdata to be applied to the same pixel is repeatedly and continuously reduced based on previous sensing results for the same pixel, thus sensing the threshold voltage of the driving element included in the same pixel. According to this real-time sensing method, the accuracy of sensing can be improved, power consumption can be reduced, and a separate power-off period for sensing the threshold voltage of the driving element can be eliminated, thereby reducing the power-off time. In addition, the threshold voltage of the driving element can be sensed and compensated in real-time driving without waiting for the power-off time, thus improving the display quality.

[0040] Here, the vertical blanking period can be a period arranged between adjacent vertical active periods where the display data voltage Vdata corresponding to the image data DATA is not provided to the pixel. The vertical active period can be the period during which the image data DATA used for input video is converted into the display data voltage Vdata and provided to the pixel PXL.

[0041] The timing controller 20 can control the sensing drive timing and display drive timing of pixel lines PNL1 to PNL4 of the display panel 10 based on a predetermined sequence, thus enabling display driving and sensing driving. The display drive timing can correspond to the vertical active period, while the sensing drive timing can correspond to the vertical blanking period.

[0042] The timing controller 20 can generate timing control signals GDC and DDC for display driving and timing control signals GDC and DDC for sensing driving, respectively.

[0043] Whenever a sensing data voltage SVdata lower than the previous data voltage is repeatedly applied to the sensing target pixel PXL based on the previous sensing result, the sensing driver can obtain a new sensing result from the corresponding pixel PXL, and can detect the sensing data voltage SVdata when the change in the new sensing result is 0V, as the driving characteristic of the corresponding pixel PXL (i.e., the threshold voltage of the driving element). The sensing driver may also include an operation to update the compensation value for compensating for changes in the driving characteristic of the corresponding pixel PXL. The timing controller 20 can compensate the input image data DATA to be provided to the corresponding pixel PXL based on the compensation value, thereby preventing image quality degradation caused by changes in the threshold voltage of the driving element.

[0044] The display driver can represent the correction of the digital image data DATA to be input to the corresponding pixel PXL based on the updated compensation value, and apply the display data voltage Vdata corresponding to the corrected image data to the corresponding pixel PXL to display the input image.

[0045] The gate driving circuit 15 can be embedded in the display panel 10. The gate driving circuit 15 can be located in a non-display area (border area) outside the display area where the pixel array is located.

[0046] The gate driving circuit 15 may include multiple gate stages connected to gate lines 160 of the pixel array. The gate stages may generate a gate signal SCAN for controlling the switching elements of pixel PXL and may provide the gate signal to gate line 160. In display driving, the gate signal SCAN may be used to select a pixel line to which display data voltage Vdata is to be provided. In sensing driving, the gate signal SCAN may be used to select a pixel line to which sensing data voltage SVdata is to be provided.

[0047] The data driving circuit 25 may include a data voltage generation circuit DAC and a sensing circuit 22.

[0048] The data voltage generation circuit DAC can be connected to each data line 140 via each data channel DCH. The data voltage generation circuit DAC can be implemented as a digital-to-analog converter (DAC) that converts digital signals into analog signals. The data voltage generation circuit DAC can generate the sensing data voltage SVdata required for sensing drive and the display data voltage Vdata required for display drive, and provide the sensing data voltage SVdata and display data voltage Vdata to the pixel PXL via the data line 140.

[0049] Sensing circuit 22 can be connected to reference voltage line 150 via each sensing channel SCH. Sensing circuit 22 may include a reference voltage circuit, a sampling circuit, and an analog-to-digital converter (see...). Figure 3 It may include a reference voltage circuit, a sampling circuit, an offset storage circuit, a calculation circuit, and an analog-to-digital converter (see...). Figure 8 ).

[0050] In the display driver, the sensing circuit 22 can provide a display reference voltage VPRER to the pixel PXL via the reference voltage line 150. In the sensing driver, the sensing circuit 22 can provide a sensing reference voltage VPRES to the pixel PXL via the reference voltage line 150.

[0051] In the sensing drive, the sensing circuit 22 can detect the source electrode voltage of the driving element shifted from the sensing reference voltage to different levels as the detection voltage during multiple vertical blanking periods based on the sensing data voltage SVdata with different levels via the reference voltage line 150 (see...). Figure 3 ).

[0052] In the sensing drive, the sensing circuit 22 can detect and store the source electrode voltage of the driving element shifted from the sensing reference voltage to different levels as an offset voltage through the reference voltage line 150 during multiple vertical blanking periods based on the sensing data voltage SVdata with different levels (see...). Figure 8 ).

[0053] The power circuit 30 can generate high-level pixel voltages and low-level pixel voltages to be supplied to pixel PXL. Furthermore, the power circuit 30 can generate a display reference voltage VPRER, a sensing reference voltage VPRES, and a ground voltage GND to be supplied to the sensing circuit 22. To meet the driving characteristics of pixel PXL and the sensing range of the sensing circuit 22, the display reference voltage VPRER can be higher than the sensing reference voltage VPRES. The sensing reference voltage VPRES can have the same voltage level as the ground voltage GND, but is not limited to this.

[0054] <First Example Implementation>

[0055] Figure 3 This is an example diagram showing a connection configuration between a pixel driving circuit and a pixel for sensing the threshold voltage of a driving element included in the pixel.

[0056] Reference Figure 3 The pixel PXL may include a light-emitting device EL, a driving thin-film transistor (TFT) DT, multiple switching TFTs ST1 and ST2, and a storage capacitor Cst. The driving TFT DT and the switching TFTs ST1 and ST2 can all be implemented as NMOS transistors, but are not limited thereto.

[0057] The light-emitting device (EL) can emit light using the pixel current supplied from the driving TFT DT. The EL can be implemented using an organic light-emitting diode (OLED) including an organic light-emitting layer, or an inorganic light-emitting diode including an inorganic light-emitting layer. The anode electrode of the EL can be connected to the source node N2, and the cathode electrode can be connected to the input terminal of the low-level pixel voltage EVSS.

[0058] The driving TFT DT can be a driving element that generates pixel current based on its gate-source voltage. The gate electrode of the driving TFT DT can be connected to the gate node N1, the first electrode can be connected to the input terminal of the high-level pixel voltage EVDD through the high-level power line PWL, and the second electrode can be connected to the source node N2.

[0059] Switching TFTs ST1 and ST2 can be switching elements that set the gate-source voltage of the driving TFT DT and connect the first electrode of the driving TFT DT to the data line 140 or connect the second electrode of the driving TFT DT to the reference voltage line 150.

[0060] The first switch TFT ST1 can be connected between data line 140 and gate node N1, and can be turned on based on the gate signal SCAN from gate line 160. The first switch TFT ST1 can be turned on in display driving or sensing driving. When the first switch TFT ST1 is turned on, the display data voltage Vdata or the sensing data voltage SVdata can be applied to the gate node N1. The gate electrode of the first switch TFT ST1 can be connected to gate line 160, its first electrode can be connected to data line 140, and its second electrode can be connected to gate node N1.

[0061] The second switching TFT ST2 can be connected between the reference voltage line 150 and the source node N2, and can be turned on based on the gate signal SCAN from the gate line 160. The second switching TFT ST2 can be turned on in display driving or sensing driving, and can apply the display reference voltage VPRER or the sensing reference voltage VPRES to the source node N2. The second switching TFT ST2 can be turned on in sensing driving and can connect the source node N2 to the reference voltage line 150, so the voltage of the source node N2, reflecting the driving characteristics of the driving TFT DT, can be charged into the reference voltage line 150. The gate electrode of the second switching TFT ST2 can be connected to the gate line 160, its first electrode can be connected to the reference voltage line 150, and its second electrode can be connected to the source node N2.

[0062] The storage capacitor Cst can be connected between the gate node N1 and the source node N2, and can maintain the gate-source voltage of the driving TFT DT in display driving or sensing driving.

[0063] Pixel PXL allows the light-emitting device EL to emit light with a first pixel current based on the voltage difference between the display data voltage Vdata and the display reference voltage VPRER in the display driver, thus enabling the display of the input image. Furthermore, pixel PXL allows the source node N2 and the reference voltage line 150 to be charged with a second pixel current based on the voltage difference between the sensing data voltage SVdata and the sensing reference voltage VPRES in the display driver. In the sensing driver, the light-emitting device EL does not emit light.

[0064] The pixel PXL can be connected to the pixel drive circuit PNL-DRV for sensing drive.

[0065] The pixel driving circuit PNL-DRV may include a reference voltage circuit INT, a sampling circuit SH, an analog-to-digital converter ADC, a timing controller 20, and a data voltage generation circuit DAC. In addition, it may also include the gate driving circuit (not shown) described above.

[0066] The reference voltage circuit INT may include: a first reference voltage switch RPRE for providing a display reference voltage VPRER to the reference voltage line 150; and a second reference voltage switch SPRE for providing a sensed reference voltage VPRES to the reference voltage line 150. The first reference voltage switch RPRE can be turned on in the display driver and can remain off in the sense driver. The second reference voltage switch SPRE can be turned on in the sense driver and can remain off in the display driver.

[0067] The sampling circuit SH samples the voltage (detection voltage) of the reference voltage line 150, which reflects the source node voltage of pixel PXL, during sensing drive. The sampling circuit SH can be configured with a sampling switch SAM, a sampling capacitor CSAM, and a hold switch HOLD. The sampling switch SAM can be connected between the reference voltage line 150 and node NA, the sampling capacitor CSAM can be connected to node NA at one electrode, and the hold switch HOLD can be connected between node NA and the analog-to-digital converter (ADC).

[0068] The analog-to-digital converter (ADC) can convert the output of the sampling circuit SH into a digital detection voltage VSIO and provide the digital detection voltage VSIO to the timing controller 20.

[0069] The timing controller 20 can perform the digital operations required for sensing drive based on the digital detection voltage VSIO. Specifically, the timing controller 20 can calculate a digital offset voltage based on the digital detection voltage VSIO. The timing controller 20 can pre-store the digital level of the sensing reference voltage VPRES and the digital level of the sensing data voltage SVdata provided during the current vertical blanking period. The timing controller 20 can calculate the difference between the detection voltage VSIO and the sensing reference voltage VPRES as the digital offset voltage. When the digital offset voltage is greater than 0V, the timing controller 20 can reduce the digital offset voltage by the digital level of the sensing data voltage SVdata to be provided in the subsequent vertical blanking period, and can provide the reduced sensing data voltage SVdata to the data voltage generation circuit DAC. Therefore, the data voltage generation circuit DAC can generate a sensing data voltage SVdata with reduced offset voltage in the sensing drive performed in the subsequent vertical blanking period, and can provide the generated sensing data voltage SVdata to the pixel PXL.

[0070] Furthermore, when the digital offset voltage is 0V (i.e., when the detection voltage VSIO is equal to the sensing reference voltage VPRES), the timing controller 20 can determine the level of the sensing data voltage SVdata provided during the current vertical blanking period as the threshold voltage level of the driving element, and can stop the sensing operation of the corresponding pixel PXL.

[0071] In sensor driving, the operation of the pixel driving circuit PNL-DRV will be briefly described below.

[0072] During the vertical blanking period of the (n-1)th frame, the reference voltage circuit INT outputs the sensed reference voltage VPRES to the reference voltage line 150, the data voltage generation circuit DAC outputs the (n-1)th sensed data voltage SVdata to the data line 140, and the sampling circuit SH samples the (n-1)th sensed voltage VSIO through the reference voltage line 150. Then, the timing controller 20 can calculate the (n-1)th offset voltage by subtracting the sensed reference voltage VPRES from the (n-1)th sensed voltage VSIO, and can calculate the nth sensed data voltage SVdata that reduces the (n-1)th offset voltage from the (n-1)th sensed data voltage SVdata.

[0073] Subsequently, during the vertical blanking period of the nth frame, the reference voltage circuit INT outputs the sensed reference voltage VPRES to the reference voltage line 150, the data voltage generation circuit DAC outputs the nth sensed data voltage SVdata to the data line 140, and the sampling circuit SH samples the nth sensed voltage VSIO through the reference voltage line 150. Then, the timing controller 20 subtracts the sensed reference voltage VPRES from the nth sensed voltage VSIO to calculate the nth offset voltage. For example, when the nth offset voltage is 0V, the timing controller 20 can detect the nth sensed data voltage as the threshold voltage of the driving element.

[0074] Figure 4 This shows the use of sensing drive. Figure 3 The diagram shows the driving waveform implemented using conventional techniques in a comparative example of pixel driving circuits.

[0075] Reference Figure 4 In conventional implementations, the driving element DT can operate based on a source follower scheme until the gate-source voltage difference ΔV of the driving element DT reaches the threshold voltage Vth of the driving element DT. To this end, a sensed data voltage SVdata can be provided to the gate electrode of the driving element DT, and a sensed reference voltage VPRES can be provided to the source electrode of the driving element DT. Based on the pixel current flowing in the driving element DT, the source node voltage Vs can be increased towards the gate node voltage Vg, and this source follower operation can be continuously performed until the gate-source voltage difference ΔV of the driving element DT reaches the threshold voltage Vth of the driving element DT (i.e., until the driving element DT is turned off).

[0076] According to conventional techniques, the gate node voltage Vg can be fixed by a sensing data voltage SVdata with a fixed level. However, in this state, because the source node voltage Vs gradually increases towards the gate node voltage Vg, the sensing time XY required until the gate-source voltage difference ΔV of the driving element DT reaches the threshold voltage Vth of the driving element DT can be relatively long. Since the sensing time XY is much longer than the vertical blanking period BLK, conventional techniques may be difficult to implement in real-time driving of the input image (i.e., display driving).

[0077] Figure 5A and Figure 5B This is shown in the application of sensing drive Figure 3 The figure shows a technical implementation of a pixel driving circuit for sensing the threshold voltage of the driving element.

[0078] The technical implementation of this embodiment can be based on... Figure 3 The pixel PXL and pixel driving circuit PNL-DRV. (Refer to...) Figure 5ABy using multiple vertical blanking periods (BLK), the pixel driving circuit PNL-DRV can repeat the sensing drive as shown in Figure 5 until the threshold voltage Vth of the corresponding pixel PXL is detected. Each time the sensing drive is repeated, the pixel driving circuit PNL-DRV can accumulate offset voltages V1 to Vn and reduce the level of the sensing data voltage SVdata by the accumulated offset voltage. Each time the sensing drive is repeated, the pixel driving circuit PNL-DRV can provide the corresponding pixel PXL with a sensing data voltage SVdata that has been reduced from the previous offset voltage, thus allowing for repeated acquisition of new sensing results VSIO. As the sensing drive is repeated, the new sensing result VSIO decreases; therefore, the pixel driving circuit PNL-DRV can detect the sensing data voltage SVdata when the change in the new sensing result VSIO is 0V, using this as the driving characteristic of the corresponding pixel PXL (i.e., the threshold voltage of the driving element).

[0079] According to the technical implementation of this embodiment, the nth sensing data voltage SVdata(Fn) applied to the gate electrode of the driving element during the vertical blanking period BLK of the nth frame Fn can be lower than the (n-1)th sensing data voltage SVdata(Fn-1) applied to the gate electrode of the driving element during the vertical blanking period BLK of the (n-1)th frame Fn-1 before the nth frame.

[0080] Furthermore, the (n-1)th detection voltage VSIO detected by the reference voltage line 150 during the vertical blanking period BLK of the (n-1)th frame Fn-1 can be increased by the (n-1)th offset voltage Vn-1 from the sensing reference voltage VPRES, and the nth detection voltage VSIO detected by the reference voltage line 150 during the vertical blanking period BLK of the nth frame Fn can be increased by the sensing reference voltage VPRES by the nth offset voltage Vn-1, which is lower than the (n-1)th offset voltage Vn-1. Therefore, the nth sensing data voltage SVdata(Fn) can be the (n-1)th offset voltage Vn-1, which is lower than the (n-1)th sensing data voltage SVdata(Fn-1).

[0081] The nth sensed data voltage SVdata(Fn) can have The voltage level. Here, "VF1" can be the first sense data voltage SVdata(F1) applied to the gate electrode of the driving element DT during the vertical blanking period BLK of the first frame F1, and It can be the cumulative offset voltage obtained by summing the offset voltages V1 to Vn-1 from the vertical blanking period BLK of the first frame F1 to the vertical blanking period BLK of the (n-1)th frame Fn-1.

[0082] The moment when the new sensing result VSIO changes to 0V can be the moment when the level of the new offset voltage is 0V. For example, when the nth offset voltage Vn is 0V, the nth sensing data voltage SVdata(Fn) can be detected as the threshold voltage Vth of the driving element. In this case, the threshold voltage Vth detection value can be "VF1-(V1+V2+Vn-1)".

[0083] Figure 6 and Figure 7 This is a diagram illustrating an application example of the technical implementation of this disclosure based on the threshold voltage level of the driving element.

[0084] Reference Figure 6 The threshold voltage Vth of the driving element can vary in the negative direction as in cases 1 and 2, or in the positive direction as in cases 3 and 4. The threshold voltage levels in cases 1 to 4 may be different. In the technical implementation of this disclosure, as... Figure 6 As shown, a sensing result can be obtained by providing a sensing data voltage to the gate electrode of the driving element while reducing the sensing data voltage, and in this case, the sensing data voltage when the sensing result does not change can be detected as the threshold voltage Vth of the driving element.

[0085] The output range of the data voltage generation circuit DAC can be 0V or a positive voltage greater than that. The data voltage generation circuit DAC may not output a negative voltage. In cases 3 and 4 where the threshold voltage Vth of the driving element is positive, the technical implementation of this disclosure can be fully applied because the sensed data voltage detected as the threshold voltage Vth of the driving element is detected at different levels within a positive voltage range greater than 0V. On the other hand, in cases 1 and 2 where the threshold voltage Vth of the driving element is negative, the technical implementation of this disclosure can be fully applied because the sensed data voltage detected as the threshold voltage Vth of the driving element saturates to the same 0V. When the technical implementation of this disclosure is fully applied to cases 1 and 2, an accurate threshold voltage may not be detected.

[0086] To address this issue, when the threshold voltage Vth of the driving element is 0V or less, as in cases 1 and 2, the pixel driving circuit PNL-DRV can obtain a specific sensing data voltage when the sensing result remains unchanged. This specific sensing data voltage is then converted into an estimated sensing data voltage lower than the specific sensing data voltage using a predetermined lookup table (LUT), and the estimated sensing data voltage is detected as the threshold voltage Vth of the driving element. In the lookup table (LUT), the level of the estimated sensing data voltage can be based on the moment when the specific sensing data voltage is 0V (…). Figure 7The N value can be set differently. For example, since the moment when a particular sensed data voltage is 0V is earlier in case 1 than in case 2, the estimated sensed data voltage for case 1 can be set to be lower than the estimated sensed data voltage for case 2.

[0087] In one or more examples, the value of n can vary from 1 to N (see...). Figure 6 ), where N can be a natural number. As the value of n decreases, the estimated sensed data voltage can be set to a relatively low value. In one or more examples, when n is a first value, the estimated sensed data voltage can be set to a first voltage value. When n is a second value, the estimated sensed data voltage can be set to a second voltage value. In this sense, when the first value can be lower than the second value, the first voltage value is lower than the second voltage value.

[0088] <Second Example Implementation>

[0089] Figure 8 This is an example of a diagram showing another connection configuration between a pixel driving circuit and a pixel for sensing the threshold voltage of a driving element included in the pixel. Figure 8 The pixel PXL configuration can be used with... Figure 3 The described pixel PXL configurations are essentially the same. However, Figure 8 The pixel driving circuit PNL-DRV can have the same characteristics as... Figure 3 Different configurations are available.

[0090] Reference Figure 8 The pixel PXL can be connected to the pixel drive circuit PNL-DRV for sensing drive.

[0091] By using multiple vertical blanking periods Figure 8 The pixel driving circuit PNL-DRV can repeatedly sense and drive until the threshold voltage of the corresponding pixel PXL is detected. Each time sensing and driving is repeated, the pixel driving circuit PNL-DRV can accumulate and store the offset voltage through analog calculations, and can also reduce the level of the sensed data voltage by accumulating the offset voltage through analog calculations. Each time sensing and driving is repeated, the pixel driving circuit PNL-DRV can provide the corresponding pixel PXL with a sensed data voltage that has decreased from the previous offset voltage, thus repeatedly obtaining a new sensed result VSIO. The new sensed result VSIO can decrease with repeated sensing and driving; therefore, the pixel driving circuit PNL-DRV can detect the sensed data voltage when the change in the new sensed result VSIO is 0V as the driving characteristic of the corresponding pixel PXL (i.e., the threshold voltage of the driving element). Figure 3 The pixel driving circuit PNL-DRV can accumulate offset voltage through digital calculations, and can also reduce the accumulated offset voltage by digitally calculating the level of the sensed data voltage. Figure 8 The pixel driving circuit PNL-DRV may differ in its analog calculations performed using additional analog circuitry included in the data driving circuit 25. Because... Figure 8 The pixel drive circuit PNL-DRV reduces the level of the sensed data voltage through analog operations, thus preventing side effects such as digital noise caused by digital operations.

[0092] The sensing operation of the pixel driving circuit PNL-DRV, which includes analog calculations, will be briefly described below. During the vertical blanking period of the nth frame (where n is a natural number of 2 or greater), the pixel driving circuit PNL-DRV can apply the nth sensing data voltage to the gate electrode of the driving element DT via data line 140, store the source voltage of the driving element DT shifted from the sensing reference voltage VPRES based on the nth sensing data voltage as the nth offset voltage, and calculate the nth detection voltage, which is lower than the nth offset voltage, based on the nth sensing data voltage. Here, the nth sensing data voltage may be lower than the (n-1)th sensing data voltage applied to the gate electrode of the driving element DT during the vertical blanking period of the (n-1)th frame preceding the nth frame.

[0093] The (n-1)th sensed data voltage based on analog calculations can have The level, and the nth sensed data voltage can have Level. Here, "VF1" can be the initial sense data voltage applied to the gate electrode of the driving element DT during the vertical blanking period of the first frame. The first cumulative offset voltage can be obtained by summing the offset voltages from the vertical blanking period of the first frame to the vertical blanking period of the (n-1)th frame, and The second cumulative offset voltage can be obtained by summing the offset voltages from the vertical blanking period of the first frame to the vertical blanking period of the (n-2)th frame before the (n-1)th frame. In this case, the first cumulative offset voltage can be higher than the second cumulative offset voltage.

[0094] The pixel driving circuit PNL-DRV can calculate the nth sensed data voltage as the (n-1)th detection voltage VSIO during the vertical blanking period of the (n-1)th frame. The pixel driving circuit PNL-DRV can compare the nth detection voltage and the (n-1)th detection voltage through digital operations, and when the nth detection voltage is equal to the (n-1)th detection voltage, the pixel driving circuit PNL-DRV can detect the nth detection voltage as the threshold voltage of the driving element.

[0095] Therefore, the pixel driving circuit PNL-DRV may include a reference voltage circuit INT, a sampling circuit SH, an analog-to-digital converter ADC, a timing controller 20, a data voltage generation circuit DAC, an offset storage circuit XX1, and an analog processing circuit XX2. The pixel driving circuit PNL-DRV may also include the aforementioned gate driving circuit (not shown).

[0096] The reference voltage circuit INT may include: a first reference voltage switch RPRE for providing a display reference voltage VPRER to the reference voltage line 150; and a second reference voltage switch SPRE for providing a sensed reference voltage VPRES to the reference voltage line 150. The first reference voltage switch RPRE can be turned on in the display driver and can remain off in the sense driver. The second reference voltage switch SPRE can be turned on in the sense driver and can remain off in the display driver.

[0097] The sampling circuit SH samples the voltage (detection voltage) of the reference voltage line 150, which reflects the source node voltage of pixel PXL, during sensing drive. The sampling circuit SH can be configured with a sampling switch SAM, a sampling capacitor CSAM, and a hold switch HOLD. The sampling switch SAM can be connected between node NA and node G connected to the reference voltage line 150, the sampling capacitor CSAM can be connected to node NA at one of its electrodes, and the hold switch HOLD can be connected between node NA and the analog-to-digital converter (ADC).

[0098] The analog-to-digital converter (ADC) can convert the output of the sampling circuit SH into a digital detection voltage VSIO, and can provide the digital detection voltage VSIO to the timing controller 20.

[0099] The timing controller 20 can perform the digital calculations required for sensing drive based on the digitally detected voltage VSIO. Specifically, the timing controller 20 can compare the current detected voltage (e.g., the nth detected voltage) with a previous detected voltage (e.g., the (n-1)th detected voltage), and can repeat the sensing drive until the current detected voltage equals the previous detected voltage. That is, the timing controller 20 can compare the nth detected voltage with the (n-1)th detected voltage, and when the nth detected voltage equals the (n-1)th detected voltage, the timing controller 20 can detect the nth detected voltage as the threshold voltage of the driving element and can terminate the sensing drive.

[0100] The data voltage generation circuit DAC can generate the initial sensing data voltage VFl during the vertical blanking period of each frame in the execution of sensing drive, and can provide the initial sensing data voltage VFl to the offset storage circuit XXl.

[0101] The offset storage circuit XX1 may include an odd-numbered capacitor CO and an even-numbered capacitor CE. The offset storage circuit XX1 can detect the accumulated offset voltage up to the corresponding time whenever the sensing drive is repeated during the vertical blanking period of each frame, and can alternately store the accumulated offset voltage in the odd-numbered capacitor CO and the even-numbered capacitor CE.

[0102] The offset storage circuit XX1 may include an odd capacitor CO connected between node A and node B, an even capacitor CE connected between node C and node D, a first odd switch SWO-1 connected between node NE and node B, a first even switch SWE-1 connected between node NE and node D, a second odd switch SWO-2 connected between node A and node ND which is subjected to the initial sensing data voltage, a second even switch SWE-2 connected between node NC and node A, a third odd switch SWO-3 connected between node NC and node C, a third even switch SWE-3 connected between node ND and node C, a fourth odd switch SWO-4 connected between node D and ground voltage source GND, a fourth even switch SWE-4 connected between node B and ground voltage source, and a first initialization switch INIT1 connected between node NC and ground voltage source GND.

[0103] The analog operation circuit XX2 can output the nth sensed data voltage obtained by subtracting the first accumulated offset voltage from the initial sensed data voltage VFl to the data line 140, detect and store the nth offset voltage, and subtract the nth offset voltage from the nth sensed data voltage to calculate the nth detection voltage.

[0104] The analog computing circuit XX2 may include a first subtractor DIF1 and a second subtractor DIF2. The first subtractor DIF1 may include a first non-inverting input terminal (+) connected to node NC, a first inverting input terminal (-) connected to node ND, and a first output terminal connected to node E. The second subtractor DIF2 may include a second non-inverting input terminal (+) connected to node E, a second inverting input terminal (-) connected to node NB, and a second output terminal connected to data line 140 via node F.

[0105] In addition, the analog operation circuit XX2 may include a second initialization switch INIT2 connected between node NB and ground voltage source GND, a first switch SW1 connected between node NB and node H, a capacitor C connected to node H, a second switch SW2 connected between node H and node NA, a third switch SW2 connected between node F and node G connected to reference voltage line 150, and a fourth switch SW4 connected between node NE and node F.

[0106] Figure 9This illustrates the display driver used in the vertically active time period of multiple frames. Figure 8 The diagram shows the driving waveform of the pixel driving circuit.

[0107] For display driver Figure 8 The pixel driving circuit PNL-DRV, switch RPRE, and first initialization switches INIT1 and INIT2 can be turned on based on the scan signal SCAN during the vertical active period ACT. With the first initialization switch INIT1 and the second initialization switch INIT2 turned on, the display data voltage generated by the data voltage generation circuit DAC can be applied to the gate node N1 of the driving element DT via the analog operation circuit XX2. At this time, the display reference voltage VPRER can be applied to the source node N2 of the driving element DT via switch RPRE. Then, a pixel current proportional to the voltage difference between the display data voltage and the display reference voltage VPRER can flow into the driving element DT, and based on this pixel current, the light-emitting device EL can emit light, thereby enabling the image to be realized with a brightness corresponding to the gray level of the display data voltage.

[0108] In addition, all switches SPRE, SAM, HOLD, SW1, SW2, SW3, SW4, SWO-1, SWO-2, SWO-3, SWO-4 and SWE-1, SWE-2, SWE-3, SWE-4 can be turned off in the display driver.

[0109] Figure 10A and Figure 10B This illustrates the first sensing drive used in the vertical effective time period BLK of the first frame F1. Figure 8 The graph shows the node voltage changes and driving waveforms of the pixel driving circuit PNL-DRV.

[0110] Reference Figure 10A and Figure 10B The first sensing drive can be executed through the first time period P1 to the fifth time period P5.

[0111] In the first time period Pl, the first initialization switch INIT1, the third odd switch SWO-3, and the fourth odd switch SWO-4 of the offset storage circuit XXl can be turned on, so the even capacitor CE can be reset.

[0112] During the second time period P2, a pixel current I, proportional to the "starting sensing data voltage VF1 - sensing reference voltage VPRES", can flow into the driving element DT of pixel PXL. Based on the pixel current I, the voltage of node G connected to the source node of the driving element DT can be increased by a first offset voltage V1.

[0113] In the third time period P3, node G can be connected to capacitor C of analog operation circuit XX2, and the first offset voltage V1, which is the voltage of node G, can be stored in capacitor C. Therefore, the voltage of node H connected to capacitor C can be the first offset voltage V1.

[0114] In the fourth time period P4, the subtraction operation between the initial sensing data voltage VFl and the first offset voltage Vl can be performed by the second subtractor DIF2 of the analog operation circuit XX2, and the voltage at node F connected to the output terminal of the second subtractor DIF2 can be "VF1-V1". Furthermore, "VF1-V1", as the voltage at node F, can be provided to node B of the offset storage circuit XX1 through the fourth switch SW4 and the first odd-numbered switch SWO-1. At this time, the initial sensing data voltage VF1 has already been provided to node A of the offset storage circuit XX1. Therefore, the first offset voltage V1 can be stored in the odd-numbered capacitor CO between node A and node B. Additionally, "VF1-V1", as the voltage at node F, can be provided to node G through the third switch SW3.

[0115] In the fifth time period P5, the voltage “VF1-V1” of node G can be sampled by the sampling circuit SH and can be output to the timing controller 20 as the first detection voltage VSIO.

[0116] Figure 11A and Figure 11B This illustrates the second sensing drive used in the vertical effective time period of the second frame. Figure 8 The graph shows the node voltage changes and driving waveforms of the pixel driving circuit.

[0117] Reference Figure 11A and Figure 11B The second sensing drive can be executed through the first time period P1 to the fifth time period P5.

[0118] During the first time period P1, as the first to fourth even switches SWE-1 to SWE-4 of the offset storage circuit XX1 are turned on, "VF1" can be applied to node C, and "VF1-V1" can be applied to node D. Therefore, the first offset voltage V1 can be stored in the even capacitors CE of the offset storage circuit XX1 connected to nodes C and D. At this time, the odd capacitors CO of the offset storage circuit XX1 can hold the first offset voltage V1 stored in the vertical blanking period of the first frame.

[0119] During the second time period P2, the pixel current 2, which is proportional to "(VF1-V1)-VPRES", can flow into the driving element DT of pixel PXL. Based on the pixel current 2, the voltage of node G connected to the source node of the driving element DT can be increased by a second offset voltage V2. Here, the pixel current 2 can be lower than the aforementioned pixel current 1, therefore, the second offset voltage V2 can be lower than the aforementioned first offset voltage V1.

[0120] In the third time period P3, node G can be connected to capacitor C of analog circuit XX2, and the second offset voltage V2, which is the voltage of node G, can be stored in capacitor C. Therefore, the voltage of node H connected to capacitor C can be the second offset voltage V2.

[0121] In the fourth time period P4, the subtraction operation between "VF1-V1" and the first offset voltage V1 can be performed by the second subtractor DIF2 of the analog operation circuit XX2, and the voltage at node F connected to the output terminal of the second subtractor DIF2 can be "VF1-V1-V2". Furthermore, "VF1-V1-V2", as the voltage at node F, can be provided to node D of the offset storage circuit XX1 via the fourth switch SW4 and the first even-numbered switch SWE-1. At this time, the initial sensing data voltage VF1 has already been provided to node C of the offset storage circuit XX1. Therefore, the accumulated offset voltage "V1+V2", obtained by summing the first offset voltage V1 and the second offset voltage V2, can be stored in the even-numbered capacitor CE between node C and node D. Additionally, "VF1-V1-V2", as the voltage at node F, can be provided to node G via the third switch SW3.

[0122] In the fifth time period P5, the voltage “VF1-V1-V2” of node G can be sampled by the sampling circuit SH and can be output to the timing controller 20 as the second detection voltage VSIO.

[0123] Figure 12 This shows the (n-1)th sensing drive in the vertical effective time period of the (n-1)th frame. Figure 8 The diagram shows the driving waveform of the pixel driving circuit.

[0124] Reference Figure 12The (n-1)th sensing drive can be executed through the first time period P1 to the fifth time period P5. Through the (n-1)th sensing drive, the (n-1)th offset voltage Vn-1 can be stored in capacitor C, and based on the second subtractor DIF2 of the analog operation circuit XX2, the voltage at node F can be “VF1-V1-V2-…-Vn-1”. The accumulated offset voltage “V1+V2+…+Vn-1” can be stored in the odd-numbered capacitor CO of the offset storage circuit XX1. Furthermore, the voltage at node G, “VF1-V1-V2-…-Vn-1”, can be sampled by the sampling circuit SH and output as the (n-1)th detection voltage VSIO to the timing controller 20.

[0125] Figure 13 This shows the nth sensing drive during the vertical effective time period of the nth frame. Figure 8 The diagram shows the driving waveform of the pixel driving circuit.

[0126] Reference Figure 13 The nth sensing drive can be executed through the first time period P1 to the fifth time period P5. Through the nth sensing drive, the nth offset voltage Vn can be stored in capacitor C, and based on the second subtractor DIF2 of the analog operation circuit XX2, the voltage at node F can be “VF1-V1-V2-…-Vn-1”. The accumulated offset voltage “V1+V2+…+Vn-1+Vn” can be stored in the odd-numbered capacitor CO of the offset storage circuit XX1. Furthermore, the voltage at node G, “VF1-V1-V2-…-Vn-1-Vn”, can be sampled by the sampling circuit SH and output as the nth detection voltage VSIO to the timing controller 20.

[0127] In this embodiment, the same pixel can be sensed multiple times consecutively by using multiple vertical blanking periods, thus enabling the sensing and compensation of the threshold voltage of the driving element included in each pixel in the real-time drive of displaying the input image.

[0128] In this embodiment, the sensing data voltage to be applied to the same pixel can be repeatedly and continuously reduced based on previous sensing results for the same pixel. Therefore, the threshold voltage of the driving element included in the same pixel can be sensed. According to this embodiment, the sensing accuracy can be improved, power consumption can be reduced, and a separate power-off period for sensing the threshold voltage of the driving element can be eliminated, thereby reducing power-off time. Furthermore, the threshold voltage of the driving element can be sensed and compensated in real-time driving without waiting for power-off time, thus improving display quality.

[0129] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0130] Although this disclosure has been specifically shown and described with reference to exemplary embodiments, those skilled in the art will understand that various changes may be made to its form and details without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. An electroluminescent display device, comprising: A pixel, the pixel including a driving element having a gate electrode connected to a data line and a source electrode connected to a reference voltage line; as well as A pixel driving circuit is configured to apply a sensing data voltage to the gate electrode of the driving element via the data line during multiple vertical blanking periods, detect the source electrode voltage of the driving element shifted from a sensing reference voltage based on the sensing data voltage via the reference voltage line to obtain a detection voltage, calculate an offset voltage based on the detection voltage, and reduce the level of the sensing data voltage based on the offset voltage. in: The pixel driving circuit is configured to apply the nth sensing data voltage to the gate electrode of the driving element during the vertical blanking period of the nth frame. The pixel driving circuit is configured to apply the (n-1)th sensing data voltage to the gate electrode of the driving element during the vertical blanking period of the (n-1)th frame preceding the nth frame. The nth sensed data voltage is lower than the (n-1)th sensed data voltage, and Where n is a natural number of 2 or greater.

2. The electroluminescent display device according to claim 1, wherein: The pixel driving circuit is configured to detect the (n-1)th detection voltage through the reference voltage line during the vertical blanking period of the (n-1)th frame, and to increase the (n-1)th detection voltage from the sensing reference voltage by the (n-1)th offset voltage; The pixel driving circuit is configured to detect the nth detection voltage through the reference voltage line during the vertical blanking period of the nth frame, and to increase the nth detection voltage from the sensing reference voltage by the nth offset voltage; The nth offset voltage is lower than the (n-1)th offset voltage; and The nth sensed data voltage is lower than the (n-1)th sensed data voltage by the (n-1)th offset voltage.

3. The electroluminescent display device according to claim 2, wherein, When the nth offset voltage is 0V, the pixel driving circuit detects the nth sensed data voltage as the threshold voltage of the driving element.

4. The electroluminescent display device according to claim 2, wherein, The voltage level of the nth sensed data voltage is and "VF1" is the first sensed data voltage applied to the gate electrode of the driving element during the vertical blanking period of the first frame, and The cumulative offset voltage is obtained by summing the offset voltages from the vertical blanking period of the first frame to the vertical blanking period of the (n-1)th frame.

5. The electroluminescent display device according to claim 1, wherein, When the threshold voltage of the driving element is higher than 0V, the pixel driving circuit detects the nth sensing data voltage as the threshold voltage of the driving element.

6. The electroluminescent display device according to claim 1, wherein, When the threshold voltage of the driving element is lower than or equal to 0V, The pixel driving circuit detects the estimated sensing data voltage, which differs from the nth sensing data voltage, as the threshold voltage of the driving element, and The estimated sensing data voltage is set differently based on the moment when the nth sensing data voltage is 0V.

7. The electroluminescent display device according to claim 6, wherein: When n is a first value, the estimated sensing data voltage is set to a first voltage value; When n is a second value, the estimated sensing data voltage is set to the second voltage value; and When the first value is lower than the second value, the first voltage value is lower than the second voltage value.

8. The electroluminescent display device according to claim 4, wherein, The pixel driving circuit includes: A reference voltage circuit is used to output the sensed reference voltage to the reference voltage line during the vertical blanking period of the (n-1)th frame; A sampling circuit is used to sample the (n-1)th detection voltage through the reference voltage line during the vertical blanking period of the (n-1)th frame; A timing controller, configured to subtract the sensing reference voltage from the (n-1)th detected voltage to calculate the (n-1)th offset voltage, and to calculate the nth sensed data voltage that is lower than the (n-1)th sensed data voltage by the (n-1)th offset voltage; and A digital-to-analog converter (DAC) is configured to output the (n-1)th sensed data voltage to the data line during the vertical blanking period of the (n-1)th frame, and to output the nth sensed data voltage to the data line during the vertical blanking period of the nth frame.

9. The electroluminescent display device according to claim 8, wherein, During the vertical blanking period of the nth frame. The reference voltage circuit is configured to output the sensed reference voltage to the reference voltage line. The sampling circuit is configured to sample the nth detected voltage input through the reference voltage line, and The timing controller is configured to subtract the sensing reference voltage from the nth detected voltage to calculate the nth offset voltage, and when the nth offset voltage is 0V, the timing controller detects the nth sensed data voltage as the threshold voltage of the driving element.

10. An electroluminescent display device, comprising: A pixel, the pixel including a driving element, the driving element including a gate electrode connected to a data line and a source electrode connected to a reference voltage line; as well as A pixel driving circuit is configured to apply an nth sensed data voltage to the gate electrode of the driving element via the data line, store the source electrode voltage of the driving element shifted from a sensed reference voltage based on the nth sensed data voltage as an nth offset voltage, and calculate an nth detection voltage that is reduced by the nth offset voltage based on the nth sensed data voltage, where n is a natural number of 2 or greater. in: The pixel driving circuit is configured to apply the (n-1)th sensing data voltage to the gate electrode of the driving element during the vertical blanking period of the (n-1)th frame preceding the nth frame; and The voltage of the nth sensing data is lower than the voltage of the (n-1)th sensing data.

11. The electroluminescent display device according to claim 10, wherein, The nth sensed data voltage is at a level Calculated at the location, The (n-1)th sensed data voltage is at a level Calculated at the location, "VF1" is the initial sensing data voltage applied to the gate electrode of the driving element during the vertical blanking period of the first frame. The first cumulative offset voltage is obtained by summing the offset voltages from the vertical blanking period of the first frame to the vertical blanking period of the (n-1)th frame, and The second cumulative offset voltage is obtained by summing the offset voltages from the vertical blanking period of the first frame to the vertical blanking period of the (n-2)th frame before the (n-1)th frame, and The first cumulative offset voltage is higher than the second cumulative offset voltage.

12. The electroluminescent display device according to claim 11, wherein, The pixel driving circuit is configured to calculate the nth sensed data voltage as the (n-1)th detection voltage during the vertical blanking period of the (n-1)th frame, and When the nth detection voltage is equal to the (n-1)th detection voltage, the pixel driving circuit detects the nth detection voltage as the threshold voltage of the driving element.

13. The electroluminescent display device according to claim 12, wherein, The pixel driving circuit includes: A reference voltage circuit is used to output the sensed reference voltage to the reference voltage line during the vertical blanking period of the nth frame; An analog computing circuit is configured to output the nth sensing data voltage obtained by subtracting the first accumulated offset voltage from the initial sensing data voltage to the data line during the vertical blanking period of the nth frame, detect and store the nth offset voltage, and subtract the nth offset voltage from the nth sensing data voltage to calculate the nth detection voltage. An offset storage circuit is used to provide the initial sensing data voltage and the first accumulated offset voltage to the analog processing circuit during the vertical blanking period of the nth frame. A digital-to-analog converter, the digital-to-analog converter being used to provide the initial sensing data voltage to the offset storage circuit during the vertical blanking period of the nth frame; A sampling circuit, wherein the sampling circuit is configured to sample the nth detection voltage during the vertical blanking period of the nth frame; and A timing controller is used to determine whether the nth detection voltage is equal to the (n-1)th detection voltage.

14. The electroluminescent display device according to claim 13, wherein, The offset storage circuit includes: An odd number of capacitors connected between node A and node B; An even number of capacitors connected between node C and node D; The first odd-numbered switch connecting node NE and node B; The first even-numbered switch connected between node NE and node D; A second odd-numbered switch is connected between node A and node ND, wherein the second odd-numbered switch is configured to receive the initial sensing data voltage; The second even-numbered switch connected between node NC and node A; The third odd-numbered switch connected between node NC and node C; The third even-numbered switch is connected between node ND and node C; The fourth odd-numbered switch is connected between node D and the node used as a ground voltage source; A fourth even-numbered switch connected between node B and the node used as a ground voltage source; and A first initialization switch is connected between node NC and the node used as a ground voltage source.

15. The electroluminescent display device according to claim 14, wherein, The analog computing circuit includes: The first subtractor includes a first non-inverting input terminal connected to node NC, a first inverting input terminal connected to node ND, and a first output terminal connected to node E. The second subtractor includes a second non-inverting input terminal connected to node E, a second inverting input terminal connected to node NB, and a second output terminal connected to the data line via node F; A second initialization switch is connected between node NB and the node used as a ground voltage source; The first switch connecting node NB and node H; The capacitor connected to node H; A second switch connecting node H and node NA; A third switch connected between node F and node G connected to the reference voltage line; and The fourth switch is connected between node NE and node F.

16. The electroluminescent display device according to claim 15, wherein, The sampling circuit includes: A sampling switch connected between node G and node NA; The sampling capacitor connected to node NA; and A holding capacitor connected to node NA.

17. The electroluminescent display device according to claim 10, wherein, When the threshold voltage of the driving element is higher than 0V, the pixel driving circuit detects the nth sensing data voltage as the threshold voltage of the driving element.

18. The electroluminescent display device according to claim 10, wherein, When the threshold voltage of the driving element is lower than or equal to 0V, The pixel driving circuit detects the estimated sensing data voltage, which differs from the nth sensing data voltage, as the threshold voltage of the driving element, and The estimated sensing data voltage is set differently based on the moment when the nth sensing data voltage is 0V.

19. The electroluminescent display device according to claim 18, wherein: When n is a first value, the estimated sensing data voltage is set to a first voltage value; When n is a second value, the estimated sensing data voltage is set to the second voltage value; and When the first value is lower than the second value, the first voltage value is lower than the second voltage value.

Images