A dual binary data transmission device with controllable inter-code interference

Abstract

The present invention discloses a duobinary data transmission device with controllable intersymbol interference (ISI). The present invention includes a transmitter and a receiver, wherein the transmitter includes: a precoding module for eliminating the correlation between the preceding and following symbols of multiple parallel low-speed source signals through precoding; a feedforward equalizer (FFE) for compensating for channel loss; a parallel-to-serial conversion module for synthesizing the multiple parallel low-speed source signals into a smaller number of multiple serial high-speed signals; a high-speed synthesizer for synthesizing the multiple serial high-speed signals into a single data stream; a transmitting driver circuit for outputting the data stream in the form of duobinary data; and a clock unit for providing a clock signal based on an externally input clock source. The present invention uses precoding to introduce controllable ISI during transmission, which reduces the requirements for signal bandwidth and subsequent equalizer performance.

Description

Technical Field

[0001] The present invention belongs to the field of high-speed serial interface technology in integrated circuit design and data transmission technology, and in particular relates to a dual binary data transmission device with controllable inter-code crosstalk. Background Art

[0002] In recent years, with the rapid development of high-performance computing, data transmission rates have also significantly increased. Serializer / Deserializer (SerDes) has become a mainstream technology for high-speed serial data communications due to its low cost, high speed, and strong anti-interference capabilities. However, as signal rates increase, channel attenuation and inter-symbol crosstalk (ISI) can occur during high-speed channel transmission in backplane transmission systems used in data centers, high-performance computers, and other applications, making channel integrity a pressing issue. Due to channel non-idealities, traditional non-return-to-zero (NRZ) modulation significantly impacts channel attenuation in high-speed serial port applications above 56 Gb / s. Therefore, the industry has proposed duo-binary (DB) as an alternative to PAM4 and NRZ. Some solutions use feedforward equalization (FFE) at the transmitter to equalize the 56 Gb / s NRZ signal to DB at the channel output. The receiver then directly decodes the signal without using adaptive equalization. This approach limits the overall equalizer performance. Other solutions use DB encoding directly at the transmitter, but this places high demands on the subsequent equalizer performance. Summary of the Invention

[0003] The technical problem to be solved by the present invention: In response to the above-mentioned problems of the prior art, a dual-binary data transmission device with controllable inter-code interference is provided. The present invention uses precoding to introduce controllable inter-code interference during the transmission process, and has low requirements on signal bandwidth and subsequent equalizer performance.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A duobinary data transmission device with controllable inter-symbol interference includes a transmitter, wherein the transmitter includes:

[0006] A precoding module is used to eliminate the correlation between the front and back symbols of multiple parallel low-speed source signals through precoding;

[0007] Feedforward equalizer (FFE), used to compensate for channel loss;

[0008] A parallel-to-serial conversion module is used to synthesize multiple parallel low-speed source signals into a smaller number of multiple serial high-speed signals;

[0009] High-speed synthesizer, used to synthesize multiple serial high-speed signals into one data stream;

[0010] A transmitting driving circuit, configured to output the data stream in the form of duobinary data;

[0011] and a clock unit for providing a clock signal based on an externally input clock source;

[0012] The precoding module, feedforward equalizer FFE, parallel-to-serial conversion module, high-speed synthesizer and transmit drive circuit are connected in sequence, and the input end of the precoding module is used to be connected to the signal generation module, the output of the transmit drive circuit is used to output the duobinary data obtained after encoding, and the output end of the clock unit is respectively connected to the clock signal input end of the precoding module, feedforward equalizer FFE, parallel-to-serial conversion module, and high-speed synthesizer.

[0013] Optionally, the parallel-to-serial conversion module is a 64:4 parallel-to-serial conversion module, which is used to synthesize 64 parallel low-speed source signals into 4 serial high-speed signals; the high-speed synthesizer is a 4:1 high-speed synthesizer, which is used to synthesize 4 serial high-speed signals into one data stream.

[0014] Optionally, the function expression of the input and output of the feedforward equalizer FFE is:

[0015]

[0016] In the above formula, y(n) is the output signal, x(ni) is the input signal of the i-th tap, C i is the i-th tap coefficient, and N is the number of taps.

[0017] Optionally, the feedforward equalizer FFE is a 4-tap feedforward equalizer, which includes: four tail current sources, a load resistor R L And 4 groups of symmetrical structure NMOS tubes M1~M8, differential output signal TX_OUT of the pre-coding module P [n], TX_OUT N [n] respectively through a load resistor R L Connected to the power supply VDD, and connected to the drain of NMOS tubes M1 to M8. The source of NMOS tubes M1 to M8 is connected to a tail current source in groups. Each group of NMOS tubes is connected to a tail current source. The tail current source is used to change the transconductance of the corresponding group of NMOS tubes by changing the current to achieve the update of the tap coefficient. The gates of the four groups of NMOS tubes are respectively connected to the four differential data signals DATA output by the precoding module. P [n-2~n+1] and DATA N One of [n-2 to n+1] is connected, and the drains of the four groups of NMOS tubes are superimposed and pass through another load resistor R L Output FFE_OUT P [n],FFE_OUTN [n] Two differential signals.

[0018] Optionally, the clock unit includes a phase-locked loop (PPL) and four groups of dividers. The input end of the phase-locked loop (PPL) is connected to an external clock source, and the output end generates a 14G clock signal. The 875M clock signal is generated through four dividers and is respectively connected to the precoding module, the feedforward equalizer (FFE), and the parallel-serial conversion module. The output end of the phase-locked loop (PPL) is connected to the clock signal input end of the high-speed synthesizer to provide a 14G clock signal for the high-speed synthesizer.

[0019] Optionally, a receiver is further included, wherein the receiver includes:

[0020] Receiver driver circuit for input matching and electrostatic discharge;

[0021] Continuous Time Linear Equalizer (CTLE), used to implement duobinary signal modulation and provide equalization processing in combination with channels;

[0022] Variable gain amplifier (VGA) is used to adjust the signal dynamic range, adjust the output signal amplitude to a range suitable for the subsequent decision feedback equalizer, and stabilize the output signal power;

[0023] Decision Feedback Equalizer (DFE) for equalizing duobinary signals to eliminate residual intersymbol interference (ISI) after post-processing.

[0024] Slicer, used to judge the DFE output signal and input it into the adaptive equalization algorithm as an ideal signal to achieve adaptive update of the decision feedback equalizer tap coefficients;

[0025] and a clock recovery circuit for generating a clock signal;

[0026] The input end of the receiving drive circuit is connected to the input signal source, and the output end outputs the decoded signal Dn to the corresponding signal receiving module through the continuous time linear equalizer CTLE, the variable gain amplifier VGA, the decision feedback scale DFE and the slicer in sequence. The output end of the clock recovery circuit is respectively connected to the clock signal input ends of the decision feedback scale DFE and the slicer.

[0027] Optionally, the continuous time linear equalizer CTLE is a continuous time linear equalizer CTLE with a complementary symmetrical structure, and the continuous time linear equalizer CTLE with a complementary symmetrical structure includes a PMOS transistor M p1 ~M p4 、NMOS tube M n1 ~M n4 , adjustable degradation resistance R S , degeneration capacitance C Sand used to generate the bias voltage V BP and bias voltage V Bn Bias voltage generating circuit, PMOS tube M p3 、PMOS tube M p1 、NMOS tube M n1 、NMOS tube M n3 The source and drain are connected end to end and connected in series between the power supply VDD and the ground GND. p4 、PMOS tube M p2 、NMOS tube M n2 、NMOS tube M n4 The source and drain are connected end to end and connected in series between the power supply VDD and the ground GND. p3 and PMOS tube M p4 The gates of both are connected to a bias voltage V BP A set of adjustable degradation resistors R is connected in parallel between the drain and S and the degeneration capacitance C S , PMOS tube M p1 、NMOS tube M n1 The gates of both are connected to the input differential signal V IN and V IP The signal V IP , PMOS tube M p2 、NMOS tube M n2 The gates of both are connected to the input differential signal V IN and V IP The signal V IN , NMOS tube M n3 and NMOS tube M n4 The gates of both are connected to a bias voltage V Bn Another set of adjustable degradation resistors R is connected in parallel between the drain and S and the degeneration capacitance C S , the adjustable degradation resistor R S It includes multiple resistance branches connected in parallel and with different resistance values. Each resistance branch includes a switch tube and resistors with the same resistance value connected in series on both sides of the switch tube.

[0028] Optionally, the bias voltage generating circuit includes a resistor R, NMOS tubes M5 to M8 and M 12 、PMOS tube M9~M 11 and the current source I bias , PMOS tube M 10 The PMOS tube M9 is connected in series with the power supply VDD at one end, and the other end is connected to the ground through the resistor R, NMOS tube M7 and NMOS tube M5 in series through the source and drain to form a path. The current source I biasThe input terminal is connected to the power supply VDD, and the output terminal is connected to the output bias voltage V Bn And respectively with NMOS tube M5 ~ M6 and M 12 The gate of NMOS tube M is connected to 12 The source and drain of the PMOS tube are grounded. 11 The source and drain are connected to the power supply VDD, the gate and the PMOS tube M 10 The gate is connected to the output bias voltage V BP The gates of NMOS tubes M7 and M8 and PMOS tube M9 are connected to the power supply V CM Connected, PMOS tube M 11 The gate is also connected to the drain of the PMOS tube M9.

[0029] Optionally, the system further includes a first adaptive circuit for updating a bias voltage of a continuous time linear equalizer CTLE to implement adaptive channel shaping. The function expression for updating the bias voltage of the continuous time linear equalizer CTLE by the first adaptive circuit is:

[0030] dlev(n+1)=dlev(n)+ CTLE e(n)·d(),

[0031] In the above formula, dlev(n+1) is the bias voltage at time n+1, dlev(n) is the bias voltage at time n, μ CTLE is the iteration factor, d(n) is the ideal signal replaced by the decision feedback device DFE at time n, and e(n) is the error signal of the output result of the continuous time linear equalizer CTLE at time n.

[0032] Optionally, a second adaptive circuit is further included for updating the tap coefficients of the decision feedback equalizer DFE, and the function expression of the second adaptive circuit for updating the tap coefficients of the decision feedback equalizer DFE is:

[0033]

[0034] In the above formula, w(n+1) is the tap coefficient at time n+1, w(n) is the tap coefficient at time n, μ DFE is the iteration factor, is the gradient of the mean square error function, E(n) is the error signal between d(n) at time n and the output of the continuous time linear equalizer CTLE, d(n-1) is the substitute ideal signal after the judgment of the feedback scale DFE at time n-1, and d(n) is the substitute ideal signal after the judgment of the feedback scale DFE at time n.

[0035] Optionally, the judgment feedback scale DFE is a two-tap half-rate judgment feedback scale DFE, which includes a combiner MUX, a buffer, and two half-rate data paths. An adder and two cascaded master-slave D flip-flops are arranged in series on each half-rate data path, and each half-rate data path also has a first multiplier for multiplying the tap coefficient C2 and the output of the second master-slave D flip-flop after delay as the second input of the adder, and a second multiplier for multiplying the tap coefficient C1 by the output of the second master-slave D flip-flop after delay. The output of the first master-slave D flip-flop after the delay is multiplied to serve as the third input of the adder of another half-rate data path. The first input of the adder is the original input signal of the two-tap half-rate judgment feedback scale DFE. The adder sums the three inputs and serves as the input of the first master-slave D flip-flop. The odd signal Odd and the even signal Even are obtained respectively through the second master-slave D flip-flops of the two half-rate data paths. The odd signal Odd and the even signal Even are synthesized in a 2:1 ratio by the combiner MUX and then buffered and output through the buffer.

[0036] Compared with the prior art, the present invention mainly has the following advantages:

[0037] 1. The present invention designs a 56Gbp transceiver system (including at least a transmitter) based on duobinary data (DB) coding technology for channels with an attenuation greater than 35dB at the Nyquist frequency, which can achieve reliable transmission of duobinary data.

[0038] 2. The present invention includes a precoding module to eliminate the correlation between the front and back symbols of multiple parallel low-speed source signals through precoding. Moreover, on the basis of the precoding module, controllable inter-symbol crosstalk is introduced in combination with the adjustment of the equalizer, so that the channel and the equalizer can work together, so that part of the channel loss becomes part of the generation of the dual binary data signal, effectively reducing the requirements for signal bandwidth and subsequent equalizer performance, and can solve the problems of complex traditional blind adaptive algorithms and low equalization strength. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of the structure of the device in an embodiment of the present invention.

[0040] Figure 2 Schematic diagram of the circuit principle of the feedforward equalizer FFE in an embodiment of the present invention.

[0041] Figure 3 FIG. 4 is a schematic diagram of the circuit principle of a continuous time linear equalizer CTLE according to an embodiment of the present invention.

[0042] Figure 4 Schematic diagram of the circuit principle of the bias voltage generating circuit in an embodiment of the present invention.

[0043] Figure 5 1 is the amplitude-frequency characteristic curve of CTLE under different Rs in the embodiment of the present invention.

[0044] Figure 6 Schematic diagram of the circuit principle of the adjustable degradation resistor Rs in an embodiment of the present invention.

[0045] Figure 7 Schematic diagram of the principle of the adaptive regulation circuit in an embodiment of the present invention.

[0046] Figure 8 Schematic diagram of the principle of a two-tap half-rate judgment feedback scale DFE in an embodiment of the present invention.

[0047] Figure 9 Schematic diagram of channel return loss (S11) in an embodiment of the present invention.

[0048] Figure 10 Schematic diagram of channel insertion loss (S21) in an embodiment of the present invention.

[0049] Figure 11 This is the eye diagram output after the signal passes through the channel in the embodiment of the present invention.

[0050] Figure 12 is the adjustable degradation resistor R in the embodiment of the present invention S The convergence curve.

[0051] Figure 13 is a convergence curve of the DFE tap coefficients in an embodiment of the present invention.

[0052] Figure 14 1 is a signal waveform before equalization by a continuous time linear equalizer (CTLE) in an embodiment of the present invention.

[0053] Figure 15 1 is a signal waveform after being equalized by a continuous time linear equalizer (CTLE) in an embodiment of the present invention.

[0054] Figure 16 1 is an eye diagram of a signal before and after equalization by a continuous time linear equalizer (CTLE) in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] Duobinary data (DB) is essentially a three-level modulation scheme. The scheme was first proposed by Lender in 1963 and has been rapidly developed in the following decades. It still attracts widespread attention today, especially in the field of optics. In order to convert an NRZ signal into a DB signal, the current NRZ symbol ("+1" or "-1") needs to be delayed and added to the previous symbol, following the function H(z) = 1 + z -1, the generated DB signal has three levels ("-1", "0" and "+1"), and the signal must pass through the intermediate "0" level signal to jump from "+1" to "-1", and vice versa. Therefore, the fastest rising and falling edges in the signal are eliminated, and the signal bandwidth is reduced to half of the NRZ signal. In order to reduce power consumption and meet the requirements of high-loss channels, this embodiment proposes a 56Gb / s dual binary encoding technology. Figure 1 As shown, the duobinary data transmission device with controllable inter-symbol interference in this embodiment includes a transmitter, and the transmitter includes:

[0056] A precoding module is used to eliminate the correlation between the front and back symbols of multiple parallel low-speed source signals through precoding;

[0057] Feedforward equalizer (FFE), used to compensate for channel loss;

[0058] A parallel-to-serial conversion module is used to synthesize multiple parallel low-speed source signals into a smaller number of multiple serial high-speed signals;

[0059] High-speed synthesizer, used to synthesize multiple serial high-speed signals into one data stream;

[0060] A transmitting driving circuit, configured to output the data stream in the form of duobinary data;

[0061] and a clock unit for providing a clock signal based on an externally input clock source;

[0062] The precoding module, the feedforward equalizer FFE, the parallel-to-serial conversion module, the high-speed synthesizer and the transmit drive circuit are connected in sequence, and the input end of the precoding module is used to be connected to the signal generation module, the output of the transmit drive circuit is used to output the duobinary data obtained after encoding, and the output end of the clock unit is respectively connected to the clock signal input ends of the precoding module, the feedforward equalizer FFE, the parallel-to-serial conversion module and the high-speed synthesizer.

[0063] Figure 1 The signal generating module is the signal source of the transmitter, which can be integrated into the transmitter or independent of the transmitter. In this embodiment, it is only illustrated as being integrated into the transmitter.

[0064] In this embodiment, the parallel-to-serial conversion module is a 64:4 parallel-to-serial conversion module, which is used to synthesize 64 parallel low-speed source signals into 4 serial high-speed signals; the high-speed synthesizer is a 4:1 high-speed synthesizer, which is used to synthesize 4 serial high-speed signals (14Gb / s high-speed serial signals) into one data stream (56Gb / s Pre_DB signal).

[0065] In this embodiment, the function expression of the input and output of the feedforward equalizer FFE is:

[0066]

[0067] In the above formula, y(n) is the output signal, x(ni) is the input signal of the i-th tap, C i is the i-th tap coefficient, and N is the number of taps.

[0068] A feedforward equalizer (FFE) is a linear equalizer that functions similarly to an FIR filter and corrects a signal by adding the waveform's own components. FFEs have the advantages of simple structure and noise-free amplification; however, they attenuate low-frequency components and have limited ability to eliminate severe intersymbol interference. The functional expressions for the input and output of a feedforward equalizer are:

[0069]

[0070] In the above formula, C i Is the tap coefficient of FFE. After a series of delays, the input signal x(n) is multiplied by the tap coefficient C. i (), and finally sum to get the output y().

[0071] like Figure 2 As shown, the feedforward equalizer FFE in this embodiment is a 4-tap feedforward equalizer, which is implemented using a voltage mode logic circuit CML. The 4-tap feedforward equalizer includes: four tail current sources, a load resistor R L And 4 groups of symmetrical structure NMOS tubes M1~M8, differential output signal TX_OUT of the pre-coding module P [n], TX_OUT N [n] respectively through a load resistor R L Connected to the power supply VDD, and connected to the drain of NMOS tubes M1 to M8. The source of NMOS tubes M1 to M8 is connected to a tail current source in groups. Each group of NMOS tubes is connected to a tail current source. The tail current source is used to change the transconductance of the corresponding group of NMOS tubes by changing the current to achieve the update of the tap coefficient. The gates of the four groups of NMOS tubes are respectively connected to the four differential data signals DATA output by the precoding module. P [n-2~n+1] and DATA N One of [n-2 to n+1] is connected, and the drains of the four groups of NMOS tubes are superimposed and pass through another load resistor R L Output FFE_OUT P [n],FFE_OUT N [n] Two differential signals.

[0072] In this embodiment, the clock unit includes a phase-locked loop (PPL) and four sets of two-way dividers. The input end of the phase-locked loop (PPL) is connected to an external clock source, and the output end generates a 14G clock signal. The 875M clock signal generated by the four two-way dividers is connected to the precoding module, the feedforward equalizer (FFE), and the parallel-to-serial conversion module respectively. The output end of the phase-locked loop (PPL) is connected to the clock signal input end of the high-speed synthesizer to provide a 14G clock signal for the high-speed synthesizer. The input signal of the four-tap feedforward equalizer at the current time t is V i (t), the output signal is V o (t), the output signal can be expressed as:

[0073] V o ()=[g3V i (+T)+g2V i ()+g1V i (-T)+g0V i (-2T)]R L ,

[0074] In the above formula, g0~g3 are the transconductance values ​​of MOS tubes, V i (+T) is the input signal at time t+T, V i (-T) is the input signal at time tT, V i (-2T) is the input signal at time t-2T, R L is the load resistance; R L Substituting into the above formula, we have:

[0075] V o ()=C3V i (+T)+C2V i ()+C1V i (-T)+C0V i (-2T),

[0076] In the above formula, C0~C3 are the tap coefficients of the 4-tap feedforward equalizer respectively. By controlling the current of the four tail current sources to change the value of the transistor transconductance, the tap coefficients C0~C3 of the 4-tap feedforward equalizer can be changed.

[0077] See also Figure 1 This embodiment further includes a receiver, which includes:

[0078] Receiver driver circuit for input matching and electrostatic discharge;

[0079] Continuous Time Linear Equalizer (CTLE), used to implement duobinary signal modulation and provide equalization processing in combination with channels;

[0080] Variable gain amplifier (VGA) is used to adjust the signal dynamic range, adjust the output signal amplitude to a range suitable for the subsequent decision feedback equalizer, and stabilize the output signal power;

[0081] Decision Feedback Equalizer (DFE) for equalizing duobinary signals to eliminate residual intersymbol interference (ISI) after post-processing.

[0082] Slicer, used to judge the DFE output signal and input it into the adaptive equalization algorithm as an ideal signal to achieve adaptive update of the decision feedback equalizer tap coefficients;

[0083] and a clock recovery circuit for generating a clock signal;

[0084] The input end of the receiving drive circuit is connected to the input signal source, and the output end outputs the decoded signal Dn to the corresponding signal receiving module through the continuous time linear equalizer CTLE, the variable gain amplifier VGA, the decision feedback scale DFE and the slicer in sequence. The output end of the clock recovery circuit is respectively connected to the clock signal input ends of the decision feedback scale DFE and the slicer.

[0085] The continuous-time linear equalizer (CTLE) is a commonly used analog equalization method at the receiver end. Because the channel has a low-pass characteristic and the CTLE is a high-pass filter, it equalizes the signal by attenuating low frequencies and amplifying high frequencies. This characteristic, which is inversely proportional to the channel characteristics, can be used to compensate for channel bandwidth and offset channel attenuation. Because traditional CTLEs adjust the gain range by adjusting the degeneration resistor Rs and capacitor Cs, CTLEs with a source-degenerated CML structure composed solely of NMOS cannot provide a large transconductance gm, resulting in insufficient equalization strength in high-loss channels less than -35dB. To address this issue, the CTLE in this embodiment uses a complementary symmetrical structure.

[0086] like Figure 3 As shown, the continuous time linear equalizer CTLE with complementary symmetric structure includes a PMOS tube M p1 ~M p4 、NMOS tube M n1 ~M n4 , adjustable degradation resistance R S , degeneration capacitance C S and used to generate the bias voltage V BP and bias voltage V Bn Bias voltage generating circuit, PMOS tube M p3 、PMOS tube M p1 、NMOS tube M n1、NMOS tube M n3 The source and drain are connected end to end and connected in series between the power supply VDD and the ground GND. p4 、PMOS tube M p2 、NMOS tube M n2 、NMOS tube M n4 The source and drain are connected end to end and connected in series between the power supply VDD and the ground GND. p3 and PMOS tube M p4 The gates of both are connected to a bias voltage V BP A set of adjustable degradation resistors R is connected in parallel between the drain and S and the degeneration capacitance C S , PMOS tube M p1 、NMOS tube M n1 The gates of both are connected to the input differential signal V IN and V IP The signal V IP , PMOS tube M p2 、NMOS tube M n2 The gates of both are connected to the input differential signal V IN and V IP The signal V IN , NMOS tube M n3 and NMOS tube M n4 The gates of both are connected to a bias voltage V Bn Another set of adjustable degradation resistors R is connected in parallel between the drain and S and the degeneration capacitance C S .

[0087] PMOS tube M p1 ~M p4 、NMOS tube M n1 ~M n4 , adjustable degradation resistance R S , degeneration capacitance C S The PMOS and NMOS differential transistor pairs increase the transconductance and improve the gain of the equalizer. Figure 3 As shown, the left complementary g m The circuit consists of a PMOS and NMOS differential transistor pair to increase the total g m In order to make the CTLE have good linearity, the transconductance values ​​of PMOS and NMOS should be kept close during design. The right side is the CTLE bias voltage generation circuit, which provides a suitable bias voltage for the complementary symmetrical structure of the CTLE circuit. mn1 is the transconductance of NMOS, g mp1 is the transconductance of PMOS. mn1 =g mp1 =g mWhen , the CTLE output function of the complementary symmetric structure is expressed as:

[0088]

[0089] In the above formula, g m Indicates the transconductance of the MOS tube, R S and C S Represent the adjustable degeneration resistance and degeneration capacitance respectively, C L and R L Represents load resistance and load capacitance respectively, L S Indicates the magnitude of the inductive peaking inductance.

[0090] like Figure 4 As shown, the bias voltage generating circuit includes a resistor R, NMOS tubes M5 to M8 and M 12 、PMOS tube M9~M 11 and the current source I bias , PMOS tube M 10 The PMOS tube M9 is connected in series with the power supply VDD at one end, and the other end is connected to the ground through the resistor R, NMOS tube M7 and NMOS tube M5 in series through the source and drain to form a path. The current source I bias The input terminal is connected to the power supply VDD, and the output terminal is connected to the output bias voltage V Bn And respectively with NMOS tube M5 ~ M6 and M 12 The gate of NMOS tube M is connected to 12 The source and drain of the PMOS tube are grounded. 11 The source and drain are connected to the power supply VDD, the gate and the PMOS tube M 10 The gate is connected to the output bias voltage V BP The gates of NMOS tubes M7 and M8 and PMOS tube M9 are connected to the power supply V CM Connected, PMOS tube M 11 The gate is also connected to the drain of the PMOS tube M9.

[0091] In this embodiment, the complementary topology of the continuous-time linear equalizer (CTLE) with a complementary symmetric structure requires a higher power supply voltage, but because the current flowing through the NMOS and PMOS transistors is the same, power consumption can be reduced by 50%. This solution requires a 20% higher power supply voltage than the NMOS-only solution to keep both devices in saturation. The combination of lower current and higher power supply voltage can save approximately 40% of power. The output of the resistor array can be adaptively controlled to achieve adjustable equalization strength, and the capacitor array can be manually controlled. However, at high-speed data rates of 56 Gbps, the value of the degeneration capacitor Cs does not change if the data frequency at the receiving end does not change. Figure 5 The amplitude-frequency characteristic curves of CTLE under different resistance values ​​are shown.

[0092] In this embodiment, the adjustable degradation resistor R S It includes multiple resistor branches connected in parallel with different resistance values, each of which includes a switch tube and resistors with the same resistance value connected in series on both sides of the switch tube. Figure 6 As shown, (a) is the PMOS tube M p3 and PMOS tube M p4 The gates of both are connected to a bias voltage V BP , the adjustable degradation resistor R in parallel between the drain S , switch tube R S <0> ~R S <3> The resistors with the same resistance on both sides are 50, 100, 200, and 400 ohms, corresponding to the four resistance values ​​of 100, 200, 400, and 800 ohms. (b) is the NMOS tube M n3 and NMOS tube M n4 Another set of adjustable degeneration resistors R is connected in parallel between the drains of the two S , switch tube! R S <0> ~R S <3> The resistors with the same resistance on both sides are 50, 100, 200, and 400 ohms, corresponding to the four resistance values ​​of 100, 200, 400, and 800 ohms. S <0> ~R S <3> and switch tube R S <0> ~R S <3> The control levels are opposite.

[0093] like Figure 1 As shown, this embodiment further includes a first adaptive circuit for updating the bias voltage of the continuous time linear equalizer CTLE to implement adaptive channel shaping. The function expression for the first adaptive circuit to update the bias voltage of the continuous time linear equalizer CTLE is:

[0094] dlev(n+1)=dlev(n)+ CTLE e(n)·d(),

[0095] In the above formula, dlev(n+1) is the bias voltage at time n+1, dlev(n) is the bias voltage at time n, μ CTLEis the iteration factor, d(n) is the substituted ideal signal after the decision of the decision feedback equalizer (DFE) at time n, and e(n) is the error signal of the output result of the continuous-time linear equalizer (CTLE) at time n. In this embodiment, when the signal reaches the receiving end through the channel, the output results of "2," "1," and "0" are determined by the decision feedback equalizer (DFE), and the error signal e(n) is calculated. This processing method does not require obtaining the exact value of the receiving end data; it only needs to ensure that the processed data meets the decision result. It can be expressed as:

[0096]

[0097] Where x(n) represents the output result of the continuous time linear equalizer CTLE.

[0098] like Figure 1 As shown, this embodiment further includes a second adaptive circuit for updating the tap coefficients of the decision feedback equalizer DFE. The function expression for the second adaptive circuit to update the tap coefficients of the decision feedback equalizer DFE is:

[0099]

[0100] In the above formula, w(n+1) is the tap coefficient at time n+1, w(n) is the tap coefficient at time n, μ DFE is the iteration factor, is the gradient of the mean square error function, E(n) is the error signal between d(n) at time n and the output of the continuous time linear equalizer CTLE, d(n-1) is the substitute ideal signal after the judgment of the feedback scale DFE at time n-1, and d(n) is the substitute ideal signal after the judgment of the feedback scale DFE at time n.

[0101] The output y(n) of the judgment feedback device DFE at time n can be expressed as:

[0102] y(n)=x(n)-d(n-1)w(n-1),

[0103] In the above formula, x(n) is the input signal of the judgment feedback scale DFE at time n, d(n-1) is the substitute ideal signal after the judgment of the judgment feedback scale DFE at time n-1, and w(n-1) is the tap coefficient of the judgment feedback scale DFE at time n-1.

[0104] Therefore, the error signal E(n) between d(n) at time n and the output of the decision feedback equalizer DFE can be expressed as:

[0105] E(n)=d()-y(n)=d()-x(n)+d(-1)(-1),

[0106] The gradient of the mean square error function can be expressed as:

[0107]

[0108] According to the steepest descent method, the weight coefficient vector of the "next moment" should be equal to the proportional term of the weight vector of the "current moment" plus the negative mean square error gradient, then:

[0109]

[0110] Therefore, the formula for updating the tap coefficient can be written as:

[0111]

[0112] The mean square error is a quadratic function of the weight coefficient vector. The weight coefficient vector is a concave parabola with a unique minimum value. The Wiener optimal solution of the decision feedback equalizer DFE can be obtained using the steepest descent method.

[0113] like Figure 7 As shown, the decision feedback equalizer DFE in this embodiment is a two-tap (including tap coefficients w1 and w2), so the first adaptive circuit is as follows Figure 7 As shown in (a) in FIG, the second adaptive circuit is as follows Figure 7 As shown in (b) in .

[0114] like Figure 7 As shown in (a), the first adaptive circuit calculates μ through two multipliers. CTLE e(n)d(n), and then μ CTLE e(n)d(n) is summed with the bias voltage at time n through an adder to obtain the bias voltage at time n+1.

[0115] The output y(n) of the judgment feedback device DFE at time n can be expressed as:

[0116] y(n)=(n)-(n-1)w1(n-1)-(n-2)w2(n-2),

[0117] In the above formula, x(n) is the signal of the decision feedback scale DFE at time n, d(n-1) and d(n-2) are the substitute ideal signals after the decision feedback scale DFE is made at time n-1 and n-2, respectively, w1(-1) is the tap coefficient of the decision feedback scale DFE at time n-1, and w2(-2) is the tap coefficient of the decision feedback scale DFE at time n-2.

[0118] like Figure 7As shown in (b), the second adaptive circuit first calculates the error signal E(n) between d(n) at time n and the output of the decision feedback equalizer DFE through a subtractor, and then adds it to the iteration factor (μ) through a multiplier. DFE1 and μ DFE2 ), and then multiplied by a multiplier with the ideal signal d(n-1) determined by the decision feedback device DFE at time n-1. Finally, the tap coefficient at time n+1 is obtained by adding it to the tap coefficient at time n through an adder, which can be expressed as:

[0119] w1(n+1)=1()-2 DFE1 E(n)d(n-1),

[0120] w2(n+1)=2()-2 DFE2 E(n)d(n-1),

[0121] In the above formula, w1(n+1) and w2(n+1) represent the two tap coefficients at the next moment, w1(n) and w2(n) are the two tap coefficients at the current moment, μ DFE is the iteration factor corresponding to the two-tap system, E(n) is the error signal between d(n) and the output of the decision feedback equalizer DFE at time n, and d(n-1) is the ideal signal after the decision of the decision feedback equalizer DFE at time n-1. Unlike FFE and CTLE, the decision feedback equalizer DFE is a nonlinear equalizer that can effectively eliminate post-scaling and has strong noise and crosstalk resistance. Figure 8 As shown, in this embodiment, the judgment feedback scale DFE is a two-tap half-rate judgment feedback scale DFE, which includes a combiner MUX, a buffer, and two half-rate data paths (the operating frequency is half of the data rate). Each half-rate data path is connected in series with an adder and two cascaded master-slave D flip-flops. Each half-rate data path also has a first multiplier for multiplying the tap coefficient C2 with the output of the second delayed master-slave D flip-flop as the second input of the adder, and a second multiplier for multiplying the tap coefficient C 1 and the output of the first master-slave D flip-flop after delay are multiplied to serve as the third input of the adder of another half-rate data path. The first input of the adder is the original input signal of the two-tap half-rate judgment feedback scale DFE. The adder sums the three inputs and serves as the input of the first master-slave D flip-flop. The odd signal Odd and the even signal Even are obtained respectively through the second master-slave D flip-flops of the two half-rate data paths. The odd signal Odd and the even signal Even are synthesized in a 2:1 ratio by the combiner MUX and then buffered and output through the buffer. clk is the clock signal of the master-slave D flip-flops.

[0122] In order to verify the performance of the equalizer, the present embodiment respectively establishes the model in MATLAB and Cadence to carry out simulation and verification. The present invention is designed based on TSMC 28nm technology and is constructed under the Cadence IC software platform as follows: Figure 1 The actual -35dB channel parameters are imported for verification. The channel return loss (S11) and insertion loss (S21) in the channel parameters are as follows: Figure 9 and Figure 10 The transmitter's PRBS generator generates a 56Gb / s NRZ signal, which enters the precoding module before passing through the channel module. It is pre-emphasized by the transmitter's FFE and sampled and output by the DAC. The eye diagram after the signal passes through the channel is shown in Figure 1. Figure 11 As shown in Figure 1, (a) is the eye diagram output by Matlab, and (b) is the eye diagram output by Cadence. The signal at the receiver generates a DB signal through adaptive CTLE. Figure 12 and Figure 13 As shown in the figure, the bias voltage dlev of the traditional continuous time linear equalizer CTLE controls the adjustable degeneration resistor R S , adjustable degradation resistance R S It is stable at about 300 ohms. The tap coefficient of the feedback scale DFE is judged to converge within 0.35us. The signal waveform before and after the continuous time linear equalizer CTLE of this embodiment is as follows Figure 14 and Figure 15 As shown, Figure 14 is the signal waveform before equalization, Figure 15 The eye diagram after processing by the continuous time linear equalizer CTLE in this embodiment is as follows: Figure 16 As shown in the figure, (a) is the eye diagram output by Matlab, and (b) is the eye diagram output by Cadence. A clear duobinary signal is visible, indicating that channel shaping is complete. After performing a PRBS7 test on the signal receiving module, the system bit error rate is 4e-12.

[0123] In summary, the dual-binary data transmission device with controllable inter-symbol interference in this embodiment uses a 4-tap FFE for pre-emphasis at the transmitter, and the receiver equalization consists of a complementary symmetrical continuous time linear equalizer (CTLE) and a decision feedback equalizer (DFE). The gain is changed by adjusting the CTLE degeneration resistor, and can be combined with partial channel loss to generate a DB signal, which then enters the DFE to further eliminate inter-symbol interference (ISI). In terms of adaptive equalization, the CTLE control signal and DFE tap coefficients are adjusted to deal with residual inter-symbol interference (ISI). Controllable inter-symbol interference is introduced during transmission using precoding, which reduces the requirements for signal bandwidth and subsequent equalizer performance.

[0124] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A duobinary data transmission device with controllable inter-symbol interference, comprising a transmitter and a receiver, characterized in that: The transmitter comprises: A precoding module is used to eliminate the correlation between the front and back symbols of multiple parallel low-speed source signals through precoding; Feedforward equalizer (FFE), used to compensate for channel loss; A parallel-to-serial conversion module is used to synthesize multiple parallel low-speed source signals into a smaller number of multiple serial high-speed signals; High-speed synthesizer, used to synthesize multiple serial high-speed signals into one data stream; A transmitting driving circuit, configured to output the data stream in the form of duobinary data; and a clock unit for providing a clock signal based on an externally input clock source; The precoding module, feedforward equalizer FFE, parallel-to-serial conversion module, high-speed synthesizer and transmit drive circuit are connected in sequence, and the input end of the precoding module is used to be connected to the signal generation module, the output of the transmit drive circuit is used to output the duobinary data obtained after encoding, and the output end of the clock unit is respectively connected to the clock signal input ends of the precoding module, feedforward equalizer FFE, parallel-to-serial conversion module, and high-speed synthesizer; In the receiver, the input end of the receiving drive circuit is connected to the input signal source, and the output end sequentially outputs the decoded signal Dn to the corresponding signal receiving module through the continuous time linear equalizer CTLE, the variable gain amplifier VGA, the decision feedback equalizer DFE and the slicer; the continuous time linear equalizer CTLE is a continuous time linear equalizer CTLE with a complementary symmetrical structure, and the continuous time linear equalizer CTLE with a complementary symmetrical structure includes a PMOS transistor M p1 ~M p4 、NMOS tube M n1 ~M n4 , adjustable degradation resistance R S , degraded capacitance C S and used to generate the bias voltage V BP and bias voltage V Bn Bias voltage generating circuit, PMOS tube M p3 、PMOS tube M p1 、NMOS tube M n1 、NMOS tube M n3 The source and drain are connected end to end and connected in series between the power supply VDD and the ground GND. p4 、PMOS tube M p2 、NMOS tube M n2 、NMOS tube M n4 The source and drain are connected end to end and connected in series between the power supply VDD and the ground GND. p3 and PMOS tube M p4 The gates of both are connected to a bias voltage V BP A set of adjustable degradation resistors R is connected in parallel between the drain and S and the degeneration capacitance C S , PMOS tube M p1 、NMOS tube M n1 The gates of both are connected to the input differential signal V IN and V IP The signal V IP , PMOS tube M p2 、NMOS tube M n2 The gates of both are connected to the input differential signal V IN and V IP The signal V IN , NMOS tube M n3 and NMOS tube M n4 The gates of both are connected to a bias voltage V Bn Another set of adjustable degradation resistors R is connected in parallel between the drain and S and the degeneration capacitance C S , the adjustable degradation resistor R S It includes multiple resistance branches connected in parallel and with different resistance values. Each resistance branch includes a switch tube and resistors with the same resistance value connected in series on both sides of the switch tube.

2. The duobinary data transmission device with controllable inter-symbol interference according to claim 1, wherein: The function expression of the input and output of the feedforward equalizer FFE is: In the above formula, y ( n ) is the output signal, x ( ni ) is the i The input signal of the tap is C i For the i tap coefficients, N is the number of taps.

3. The duobinary data transmission device with controllable inter-symbol interference according to claim 2, wherein: The feedforward equalizer FFE is a 4-tap feedforward equalizer, which includes: four tail current sources, a load resistor R L And 4 groups of symmetrical structure NMOS tubes M1~M8, differential output signal TX_OUT of the pre-coding module P [n], TX_OUT N [n] respectively through a load resistor R L Connected to the power supply VDD, and connected to the drain of NMOS tubes M1~M8. The source of NMOS tubes M1~M8 is connected to a tail current source in groups. Each group of NMOS tubes is connected to a tail current source. The tail current source is used to change the transconductance of the corresponding group of NMOS tubes by changing the current to achieve the update of the tap coefficient. The gates of the four groups of NMOS tubes are respectively connected to the four differential data signals DATA output by the precoding module. P [n-2~n+1] and DATA N One of [n-2~n+1] is connected, and the drains of the four groups of NMOS tubes are superimposed and pass through another load resistor R L Output FFE_OUT P [n], FFE_OUT N [n] Two differential signals.

4. The duobinary data transmission device with controllable inter-symbol interference according to claim 1, wherein: The clock unit includes a phase-locked loop (PPL) and four groups of dividers. The input end of the phase-locked loop (PPL) is connected to an external clock source, and the output end generates a 14G clock signal. The 875M clock signal is generated through the four dividers and is respectively connected to the precoding module, the feedforward equalizer (FFE), and the parallel-to-serial conversion module. The output end of the phase-locked loop (PPL) is connected to the clock signal input end of the high-speed synthesizer to provide a 14G clock signal for the high-speed synthesizer.

5. The duobinary data transmission device with controllable inter-symbol interference according to claim 1, wherein: The receiver comprises: Receiver driver circuit for input matching and electrostatic discharge; Continuous Time Linear Equalizer (CTLE), used to implement duobinary signal modulation and provide equalization processing in combination with channels; Variable gain amplifier (VGA) is used to adjust the signal dynamic range, adjust the output signal amplitude to a range suitable for the subsequent decision feedback equalizer, and stabilize the output signal power; Decision feedback equalizer (DFE), used to perform equalization processing on the duobinary signal to eliminate the residual intersymbol interference after post-processing; The slicer is used to judge the output signal of the decision feedback equalizer (DFE) and input it into the adaptive equalization algorithm as an ideal signal to achieve adaptive update of the tap coefficients of the decision feedback equalizer; And a clock recovery circuit is used to generate a clock signal, the output end of the clock recovery circuit is connected to the clock signal input ends of the decision feedback equalizer DFE and the slicer respectively.

6. The duobinary data transmission device with controllable inter-symbol interference according to claim 1, wherein: The bias voltage generating circuit includes a resistor R, NMOS tubes M5 to M8 and M 12 、PMOS tube M9~M 11 and the current source I bias , PMOS tube M 10 The PMOS tube M9 is connected in series with the power supply VDD at one end, and the other end is connected to the ground through the resistor R, NMOS tube M7 and NMOS tube M5 in series through the source and drain to form a path. The current source I bias The input terminal is connected to the power supply VDD, and the output terminal is connected to the output bias voltage V Bn And respectively with NMOS tube M5 ~ M6 and M 12 The gate of NMOS tube M is connected to 12 The source and drain of the PMOS tube are grounded. 11 The source and drain are connected to the power supply VDD, the gate and the PMOS tube M 10 The gate is connected to the output bias voltage V BP The gates of NMOS tubes M7 and M8 and PMOS tube M9 are connected to the power supply V CM Connected, PMOS tube M 11 The gate is also connected to the drain of the PMOS tube M9.

7. The duobinary data transmission device with controllable inter-symbol interference according to claim 5, characterized in that: The system further includes a first adaptive circuit for updating a bias voltage of a continuous time linear equalizer CTLE to implement adaptive channel shaping. The first adaptive circuit updates the bias voltage of the continuous time linear equalizer CTLE using a function expression as follows: ， In the above formula, is the bias voltage at time n+1, is the bias voltage at time n, is the iteration factor, is the ideal signal replaced by the feedback equalizer DFE decision at time n, is the error signal of the output result of the continuous time linear equalizer CTLE at time n.

8. The duobinary data transmission device with controllable inter-symbol interference according to claim 7, characterized in that: The system further includes a second adaptive circuit for updating the tap coefficients of the decision feedback equalizer DFE. The function expression of the second adaptive circuit for updating the tap coefficients of the decision feedback equalizer DFE is: ， In the above formula, is the tap coefficient at time n+1, is the tap coefficient at time n, is the iteration factor, is the gradient of the mean square error function, For time n , the error signal between the output results of the continuous time linear equalizer CTLE, for The ideal signal after the moment judgment feedback equalizer DFE decision is replaced, for The ideal signal is replaced by the feedback equalizer DFE decision.

9. The duobinary data transmission device with controllable inter-symbol interference according to claim 5, wherein: The decision feedback equalizer (DFE) is a two-tap half-rate decision feedback equalizer (DFE), comprising a combiner (MUX), a buffer (buffer), and two half-rate data paths. An adder and two cascaded master-slave D flip-flops are arranged in series on each half-rate data path. Each half-rate data path also includes a first multiplier for multiplying a tap coefficient C2 by the delayed output of the second master-slave D flip-flop to serve as a second input to the adder, and a second multiplier for multiplying a tap coefficient C1 by the delayed output of the first master-slave D flip-flop to serve as a third input to the adder of another half-rate data path. The first input of the adder is the original input signal of the two-tap half-rate decision feedback equalizer (DFE). The adder sums the three inputs and serves as the input of the first master-slave D flip-flop. The sum passes through the second master-slave D flip-flops of the two half-rate data paths. The trigger obtains the odd signal Odd and the even signal Even respectively, and the odd signal Odd and the even signal Even are combined by the combiner MUX in a 2:1 ratio and then output through the buffer buffer.

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