Display device having an emission layer

Abstract

A display device is provided, comprising a signal line and a pixel connected to the signal line. The first pixel includes a first transistor, the first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a first drain region facing the first source region, wherein the first channel region is positioned between the first source region and the first drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region, wherein the third channel region is positioned between the third source region and the third drain region. A shielding portion overlaps a boundary between the third source region and the third channel region, and does not overlap a boundary between the third drain region and the third channel region.

Description

[0001] This application is a divisional application of a patent application filed on October 9, 2017, with application number 201710929549.2 and titled “Display device with emission layer”. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device including an emission layer. Background Art

[0003] A display device for displaying an image includes a plurality of pixels. For example, a pixel of an organic light emitting diode (OLED) display may include an organic light emitting diode having a cathode, an anode, and an organic emissive layer interposed therebetween. A plurality of transistors for driving the organic light emitting diode and at least one capacitor may also be included.

[0004] In an OLED display, electrons injected from the cathode combine with holes injected from the anode in the organic emission layer to form excitons. When the excitons return to a relaxed state within the organic emission layer, energy is emitted as light.

[0005] The plurality of transistors includes at least one switching transistor and a driving transistor. The at least one switching element can receive a data signal based on a scan signal and transmit a voltage to the driving transistor. The driving transistor is directly or indirectly connected to the organic light-emitting diode to control the amount of current transmitted to the organic light-emitting diode, thereby emitting light of a desired brightness through each pixel.

[0006] The capacitor is connected to the driving gate electrode of the driving transistor so as to maintain the voltage of the driving gate electrode. Summary of the Invention

[0007] The display device includes a plurality of signal lines and a plurality of pixels connected to the plurality of signal lines. A first pixel of the plurality of pixels includes a first transistor, the first transistor including a first gate electrode, a first channel region at least partially overlapping the first gate electrode in a plan view, a first source region, and a first drain region facing the first source region, wherein the first channel region is positioned between the first source region and the first drain region. A third transistor includes a third gate electrode, a third channel region at least partially overlapping the third gate electrode in a plan view, a third drain region connected to the first gate electrode, and a third source region facing the third drain region, wherein the third channel region is positioned between the third source region and the third drain region. In a plan view, the shielding portion at least partially overlaps a boundary between the third source region and the third channel region, and does not overlap a boundary between the third drain region and the third channel region.

[0008] The display device includes a plurality of signal lines and a plurality of pixels connected to the plurality of signal lines. A first pixel included in the plurality of pixels includes a first transistor, the first transistor including a first gate electrode, a first channel region at least partially overlapping the first gate electrode in a plan view, and a first source region and a first drain region facing each other, with the first channel region being positioned between the first source region and the first drain region. A third transistor includes a third gate electrode, a third channel region at least partially overlapping the third gate electrode in a plan view, a third drain region connected to the first gate electrode, and a third source region facing the third drain region, with the third channel region being positioned between the third drain region and the third source region. A shielding portion at least partially overlaps a boundary between the third source region and the third channel region and a boundary between the third drain region and the third channel region. The shielding portion is configured to transmit an initialization voltage.

[0009] An organic light emitting diode (OLED) display device includes a display substrate. A plurality of pixels are disposed on the display substrate. Each of the plurality of pixels includes a transistor. A plurality of signal lines are disposed on the display substrate and connected to the plurality of pixels. The plurality of signal lines at least partially cover each transistor in the plurality of pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure and its many additional aspects will be more readily obtained as the disclosure may be better appreciated by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is an equivalent circuit diagram showing one pixel of a display device according to an exemplary embodiment of the present invention;

[0012] Figure 2 is a timing diagram illustrating driving signals of a display device according to an exemplary embodiment;

[0013] Figure 3 is a top plan view showing a plurality of pixels of a display device according to an exemplary embodiment of the present invention;

[0014] Figures 4 to 6 It shows Figure 3 a top plan view of one pixel among the plurality of pixels shown in ;

[0015] Figure 7 The diagram is taken along line VII-VII'. Figure 4 A cross-sectional view of the display device shown in ;

[0016] Figure 8 The diagram is taken along line VIII-VIII'. Figure 4 A cross-sectional view of the display device shown in ;

[0017] Figure 9 is a top plan view showing a plurality of pixels of a display device according to an exemplary embodiment of the present invention;

[0018] Figure 10 is a top plan view showing one pixel of a display device according to an exemplary embodiment of the present invention;

[0019] Figure 11 The figure shows a section taken along line XI-XI'. Figure 10 A cross-sectional view of the display device shown in ;

[0020] Figure 12 is a top plan view showing one pixel of a display device according to an exemplary embodiment of the present invention;

[0021] Figure 13 The figure shows a view taken along line XIII-XIII'. Figure 12 A cross-sectional view of the display device shown in ;

[0022] Figure 14 The figure shows a section taken along line XIV-XIV'. Figure 12 A cross-sectional view of the display device shown in ;

[0023] Figure 15 is a top plan view illustrating one pixel of a display device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.

[0025] Throughout the specification and drawings, the same reference numerals may be used to designate the same or similar constituent elements.

[0026] Furthermore, the size and thickness of each configuration (such as layer, film, plate, region, etc.) shown in the drawings may be exaggerated for better understanding and ease of description, but the present invention is not limited thereto.

[0027] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0028] The following will refer to Figure 1 A display device according to an exemplary embodiment of the present invention is described.

[0029] Figure 1is an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment of the present invention.

[0030] Reference Figure 1 According to an exemplary embodiment of the present invention, a display device includes a plurality of pixels PX that display an image in response to an image signal and a plurality of signal lines 151, 152, 153, 154, 171, and 172. One pixel PX may include a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to the plurality of signal lines 151, 152, 153, 154, 171, and 172, a capacitor Cst, and at least one light emitting diode (LED) ED. According to an exemplary embodiment of the present invention, an example in which one pixel PX includes one light emitting diode (LED) ED is mainly described.

[0031] The signal lines 151 , 152 , 153 , 154 , 171 , and 172 may include a plurality of scan lines 151 , 152 , and 154 , a plurality of control lines 153 , a plurality of data lines 171 , and a plurality of driving voltage lines 172 .

[0032] The plurality of scan lines 151, 152, and 154 may transmit scan signals GWn, GIn, and GI(n+1), respectively. The scan signals GWn, GIn, and GI(n+1) may transmit gate-on voltages and gate-off voltages for turning on / off transistors T2, T3, T4, and T7 included in the pixel PX.

[0033] The scan lines 151, 152, and 154 connected to one pixel PX may include a first scan line 151 that transmits a scan signal GWn, a second scan line 152 that transmits a scan signal GIn having a gate-on voltage at a different time than the first scan line 151, and a third scan line 154 that transmits a scan signal GI(n+1). According to an exemplary embodiment of the present invention, an example in which the second scan line 152 transmits the gate-on voltage at an earlier time than the first scan line 151 will be mainly described. For example, when the scan signal GWn is the nth scan signal Sn (where n is a positive integer) among the scan signals applied during one frame, the scan signal GIn may be a previous scan signal such as the (n-1)th scan signal S(n-1), and the scan signal GI(n+1) may be the nth scan signal Sn. However, the present invention is not limited thereto, and the scan signal GI(n+1) may be a scan signal other than the nth scan signal Sn.

[0034] The control line 153 may transmit a control signal. For example, the control line 153 may transmit a light emission control signal for controlling the light emission of the light emitting diode (LED) ED included in the pixel PX. The control signal transmitted by the control line 153 may transmit a gate-on voltage and a gate-off voltage, and may have a waveform different from that of the scan signal transmitted by the scan lines 151, 152, and 154.

[0035] The data line 171 may transmit a data signal Dm, and the driving voltage line 172 may transmit a driving voltage ELVDD. The data signal Dm may have different voltage levels in response to an image signal input to the display device, and the driving voltage ELVDD may have a substantially constant level.

[0036] The display device may further include a driver that transmits signals to a plurality of signal lines 151, 152, 153, 154, 171, and 172. For example, the driver may include a scan driver that transmits scan signals to the plurality of scan lines 151, 152, and 154, and a data driver that transmits data signals to the data line 171. At least one driver may be formed directly on the display panel of the display device together with the plurality of transistors T1 to T7 included in the pixel PX. Alternatively, at least one driver may be attached to the display panel in the form of at least one driver circuit chip. Alternatively, at least one driver may be attached to a printed circuit film connected to the display panel to transmit signals to the display panel. The driver or printed circuit film may be arranged around a display area of ​​the display panel where the plurality of pixels PX are arranged.

[0037] The transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 may include a first transistor T1 (also referred to as a driving transistor T1 ), a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 .

[0038] The first scan line 151 can transmit the scan signal GWn to the second transistor T2 and the third transistor T3, the second scan line 152 can transmit the scan signal GIn to the fourth transistor T4, the third scan line 154 can transmit the scan signal GI(n+1) to the seventh transistor T7, and the control line 153 can transmit the light emitting control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0039] A gate electrode G1 of the first transistor T1 is connected to one terminal Cst1 of the capacitor Cst via a driving gate node GN. A source electrode S1 of the first transistor T1 is connected to a driving voltage line 172 via a fifth transistor T5. A drain electrode D1 of the first transistor T1 is electrically connected to an anode of a light emitting diode (LED) ED via a sixth transistor T6. The first transistor T1 receives a data signal Dm transmitted via a data line 171 in response to a switching operation of the second transistor T2 to supply a driving current Id to the light emitting diode (LED) ED.

[0040] A gate electrode G2 of the second transistor T2 is connected to the first scan line 151, a source electrode S2 of the second transistor T2 is connected to the data line 171, and a drain electrode D2 of the second transistor T2 is connected to the source electrode S1 of the first transistor T1 and is connected to the driving voltage line 172 via the fifth transistor T5. The second transistor T2 is turned on in response to a scan signal GWn transmitted through the first scan line 151, so that a data signal Dm transmitted from the data line 171 can be transmitted to the source electrode S1 of the first transistor T1.

[0041] The gate electrode G3 of the third transistor T3 is connected to the first scan line 151, and the source electrode S3 of the third transistor T3 is connected to the drain electrode D1 of the first transistor T1 and connected to the anode of the light emitting diode (LED) ED via the sixth transistor T6. The drain electrode D3 of the third transistor T3 is connected to the drain electrode D4 of the fourth transistor T4, one terminal Cst1 of the capacitor Cst, and the gate electrode G1 of the first transistor T1. The third transistor T3 is turned on in response to the scan signal GWn transmitted through the first scan line 151 to diode-connect the first transistor T1 by connecting the gate electrode G1 and the drain electrode D1 of the first transistor T1 to each other.

[0042] A gate electrode G4 of the fourth transistor T4 is connected to the second scan line 152, a source electrode S4 of the fourth transistor T4 is connected to a terminal of an initialization voltage Vint, and a drain electrode D4 of the fourth transistor T4 is connected to one terminal Cst1 of the capacitor Cst and the gate electrode G1 of the first transistor T1 via the drain electrode D3 of the third transistor T3. The fourth transistor T4 is turned on in response to a previous scan signal GIn transmitted through the previous scan line 152 to transmit the initialization voltage Vint to the gate electrode G1 of the first transistor T1, thereby performing an initialization operation to initialize the voltage of the gate electrode G1 of the first transistor T1.

[0043] The gate electrode G5 of the fifth transistor T5 is connected to the control line 153 , the source electrode S5 of the fifth transistor T5 is connected to the driving voltage line 172 , and the drain electrode D5 of the fifth transistor T5 is connected to the source electrode S1 of the first transistor T1 and the drain electrode D2 of the second transistor T2 .

[0044] A gate electrode G6 of the sixth transistor T6 is connected to the control line 153, a source electrode S6 of the sixth transistor T6 is connected to the drain electrode D1 of the first transistor T1 and the source electrode S3 of the third transistor T3, and a drain electrode D6 of the sixth transistor T6 is electrically connected to the anode of the light emitting diode (LED) ED. The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the light emission control signal EM transmitted through the control line 153, so that the driving voltage ELVDD is compensated by the diode-connected driving transistor T1 and can be transmitted to the light emitting diode (LED) ED after being compensated by the diode-connected driving transistor T1.

[0045] The gate electrode G7 of the seventh transistor T7 is connected to the third scan line 154, the source electrode S7 of the seventh transistor T7 is connected to the drain electrode D6 of the sixth transistor T6 and the anode of the light emitting diode (LED), and the drain electrode D7 of the seventh transistor T7 is connected to the terminal of the initialization voltage Vint and the source electrode S4 of the fourth transistor T4. Alternatively, the gate electrode G7 of the seventh transistor T7 may be connected to a separate control line.

[0046] Transistors T1, T2, T3, T4, T5, T6 and T7 can all be P-channel transistors such as PMOS, however, the present invention is not limited thereto, and at least one of the transistors T1, T2, T3, T4, T5, T6 and T7 can be an N-channel transistor.

[0047] As described above, one terminal Cst1 of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other terminal Cst2 of the capacitor Cst is connected to the driving voltage line 172. The cathode of the light emitting diode (LED) ED may be connected to the common voltage ELVSS terminal transmitting the common voltage ELVSS to receive the common voltage ELVSS.

[0048] The structure of the pixel PX according to the exemplary embodiment of the present invention is not limited to Figure 1 , and the number of transistors and the number of capacitors included in one pixel PX and their connection relationship may be variously modified.

[0049] Next, we will refer to Figure 2 as well as Figure 1 A driving method of a display device according to an exemplary embodiment of the present invention is described. In this specification, an example in which transistors T1, T2, T3, T4, T5, T6, and T7 are P-channel transistors is described, and an operation of one frame will be described.

[0050] Reference Figure 2, in one frame, low-level scan signals . . . , S(n-2), S(n-1), Sn, . . . may be sequentially applied to the plurality of first scan lines 151 connected to the plurality of pixels PX.

[0051] During the initialization period, a low-level scan signal GIn is supplied through the second scan line 152. For example, the scan signal GIn may be the (n-1)th scan signal S(n-1). Then, the fourth transistor T4 is turned on in response to the low-level scan signal GIn, and the initialization voltage Vint is connected to the gate electrode G1 of the first transistor T1 through the fourth transistor T4, and the driving transistor T1 is initialized by the initialization voltage Vint.

[0052] Subsequently, if a low-level scan signal GWn is supplied via the first scan line 151 during the data programming and compensation period, the second transistor T2 and the third transistor T3 are turned on in response to the low-level scan signal GWn. For example, the scan signal GWn may be the nth scan signal Sn. In this case, the first transistor T1 is diode-connected by the turned-on third transistor T3 and is biased in the forward direction. Therefore, a compensation voltage (Dm+Vth, where Vth is a negative value) obtained by reducing the threshold voltage Vth of the first transistor T1 from the data signal Dm supplied from the data line 171 is applied to the gate electrode G1 of the first transistor T1. For example, the gate voltage applied to the gate electrode G1 of the first transistor T1 may become the compensation voltage (Dm+Vth).

[0053] The driving voltage ELVDD and the compensation voltage (Dm+Vth) may be applied to both terminals of the capacitor Cst, respectively, and the capacitor Cst may be charged with an amount corresponding to a voltage difference between the two terminals.

[0054] Next, during the light-emitting period, the light-emitting control signal EM supplied from the control line 153 changes from a high level to a low level. In one frame, the time when the light-emitting control signal EM changes from a high level to a low level may be after the scan signal GWn is applied to all the first scan lines 151. Therefore, during the light-emitting period, the fifth transistor T5 and the sixth transistor T6 are turned on by the light-emitting control signal EM of the low level. Therefore, in response to the voltage difference between the gate voltage of the gate electrode G1 of the first transistor T1 and the driving voltage ELVDD, a driving current Id is generated, and the driving current Id is supplied to the light-emitting diode ED through the sixth transistor T6, so that the current LED flows to the light-emitting diode ED. During the light-emitting period, the gate-source voltage Vgs of the first transistor T1 is maintained at "(Dm+Vth)-ELVDD" by the capacitor Cst, and in response to the current-voltage relationship of the first transistor T1, the driving current Id may be proportional to the square of the value obtained by subtracting the threshold voltage from the gate-source voltage "(Dm-ELVDD)". 2" is proportional. Therefore, regardless of the threshold voltage Vth of the first transistor T1, the driving current Id can be determined.

[0055] During the initialization period, the seventh transistor T7 receives a low-level scan signal GI(n+1) through the third scan line 154 and is turned on. The scan signal GI(n+1) may be the nth scan signal Sn. In this case, the seventh transistor T7 may be turned on simultaneously with the second transistor T2 and the third transistor T3. Due to the turned-on seventh transistor T7, a portion of the drive current Id may flow through the seventh transistor T7 as a bypass current Ibp.

[0056] Next, we will refer to Figures 3 to 8 as well as Figure 1 and Figure 2 An example of a detailed structure of a display device according to an exemplary embodiment of the present invention is described.

[0057] For easy understanding, a planar structure of a display device according to an exemplary embodiment of the present invention is first described, and then a cross-sectional structure is described in detail.

[0058] Figure 3 is a top plan view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention, Figure 4 yes Figure 3 A top plan view of the area indicated by "A" in FIG. Figure 5 yes Figure 3 A top plan view of the area indicated by "B" in FIG. Figure 6 yes Figure 3 A top plan view of the area indicated by "C" in FIG.

[0059] According to an exemplary embodiment of the present invention, a plurality of pixels PX included in a display device may respectively display predetermined colors. For example, the plurality of pixels may include a red pixel R representing red, a green pixel G representing green, and a blue pixel B representing blue. Figure 3 There are shown red, green, and blue pixels R, G, and B that are adjacent to each other. Alternatively, at least one of the red, green, and blue pixels R, G, and B may represent a different color.

[0060] According to an exemplary embodiment of the present invention, the display device may include a first conductive layer including a first scan line 151 transmitting a scan signal GWn, a second scan line 152 transmitting a scan signal GIn, a third scan line 154 transmitting a scan signal GI(n+1), and a control line 153 transmitting a light emission control signal EM. In a cross-sectional view, the first conductive layer is provided on one surface of a substrate 110 and may include the same material and be provided on the same layer.

[0061] The substrate 110 may include an inorganic insulating material or an organic insulating material such as glass, plastic, etc., and may be flexible.

[0062] In a plan view, the plurality of scan lines 151, 152, and 154 and the control line 153 may be arranged in the same direction (eg, Figure 3 The first scan line 151 extends in a horizontal direction (in a plan view). In a plan view, the first scan line 151 can be disposed between the second scan line 152 and the control line 153. When the entire display device is viewed, the third scan line 154, which is a scan line substantially similar to the second scan line 152, can transmit a scan signal GI(n+1) adjacent to the scan signal GIn transmitted by the second scan line 152. As described above, when the first scan line 151 transmits the nth scan signal Sn, the third scan line 154 can also transmit the nth scan signal Sn.

[0063] According to an exemplary embodiment of the present invention, the display device may further include a second conductive layer including a storage line 156 and an initialization voltage line 159. In a cross-sectional view, the second conductive layer is disposed on a different layer from the first conductive layer. For example, the second conductive layer may be disposed on the first conductive layer, may include the same material, and may be disposed in the same layer.

[0064] In a plan view, the storage line 156 and the initialization voltage line 159 may be mainly arranged in the same direction (eg, Figure 3 The horizontal direction in the figure extends.

[0065] In a plan view, the storage line 156 may be disposed between the first scan line 151 and the control line 153 and may include an extension portion 157 disposed in each pixel R, G, and B. The extension portion 157 is connected to the driving voltage line 172 through the contact hole 68 to receive the driving voltage ELVDD. The extension portion 157 may have an opening 51.

[0066] The initialization voltage line 159 may transmit the initialization voltage Vint and may be disposed between the third scan line 154 and the control line 153 in a plan view, but the location is not limited thereto.

[0067] According to an exemplary embodiment of the present invention, the display device may further include a third conductive layer, the third conductive layer including a data line 171 for transmitting a data signal Dm and a driving voltage line 172 for transmitting a driving voltage ELVDD. In a cross-sectional view, the third conductive layer is disposed at a different layer from the first and second conductive layers. For example, in a cross-sectional view, the third conductive layer may be disposed on the second conductive layer, may include the same material, and may be disposed in the same layer.

[0068] In a plan view, the data line 171 and the driving voltage line 172 may be mainly along the same direction (eg, Figure 3 The line 152 extends in a vertical direction (in a vertical direction) and may cross the plurality of scan lines 151, 152, and 154, the control line 153, the initialization voltage line 159, and the storage line 156.

[0069] Each of the pixels R, G, and B may include a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to scan lines 151, 152, and 154, a control line 153, a data line 171, and a driving voltage line 172, a capacitor Cst, and a light emitting diode (LED) ED.

[0070] Each channel of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 for one pixel PX may be formed in one active pattern 130, and the active pattern 130 may be bent in various shapes. The active pattern 130 may include a semiconductor material such as polysilicon or an oxide semiconductor.

[0071] In a cross-sectional view, the active pattern 130 may be disposed between the substrate 110 and the first conductive layer.

[0072] Active pattern 130 includes channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g, as well as a conductive region, forming each channel of transistors T1, T2, T3, T4, T5, T6, and T7. For example, the third transistor T3 and the fourth transistor T4 may have a dual-gate structure. In this case, the third transistor T3 includes two channel regions 131c_1 and 131c_2, and the fourth transistor T4 also includes two channel regions 131d_1 and 131d_2.

[0073] The conductive regions of the active pattern 130 are disposed at both sides of each of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g and have a higher carrier concentration than the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g. In the active pattern 130, most of the remaining portions except the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g may be conductive regions. A pair of conductive regions at both sides of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f and 131g of each of the transistors T1, T2, T3, T4, T5, T6 and T7, which serve as the source and drain regions of the corresponding transistors T1, T2, T3, T4, T5, T6 and T7, may serve as source and drain electrodes.

[0074] The first transistor T1 includes a channel region 131a, a source region 136a and a drain region 137a disposed at respective sides of the channel region 131a as conductive regions of the active pattern 130, and a driving gate electrode 155a overlapping the channel region 131a in a plan view.

[0075] The channel region 131a of the first transistor T1 may be bent at least once. For example, the channel region 131a may have a meandering shape or a zigzag shape. Figures 3 to 6 An example is shown in which the channel regions 131 a have U-shapes alternately arranged upward and downward.

[0076] In a plan view, the source region 136 a and the drain region 137 a are connected to respective sides of the channel region 131 a .

[0077] The driving gate electrode 155a may be included in the first conductive layer and may be connected to the connector 174 through the contact hole 61. In a plan view, the contact hole 61 may be provided inside the opening 51. In a cross-sectional view, the connector 174 may be included in the third conductive layer. The connector 174 may extend in a direction that is mainly parallel to the direction in which the data line 171 extends. The connector 174 and the driving gate electrode 155a are connected to the Figure 1 corresponds to the driving gate node GN shown in the circuit diagram.

[0078] The second transistor T2 includes a channel region 131b, a source region 136b and a drain region 137b, which are conductive regions of the active pattern 130 and are disposed on respective sides of the channel region 131b, and a gate electrode 155b that overlaps the channel region 131b in a plan view. The gate electrode 155b is a portion of the first scan line 151. In a plan view, the source region 136b is disposed upward based on the first scan line 151, connected to the channel region 131b, and connected to the data line 171 through the contact hole 62. In a plan view, the drain region 137b is disposed downward based on the first scan line 151, connected to the channel region 131b, and connected to the source region 136a of the first transistor T1.

[0079] The third transistor T3 may be formed of two parts to prevent leakage current. For example, the third transistor T3 may include an upper third transistor T3_1 and a lower third transistor T3_2 that are adjacent to and connected to each other.

[0080] The upper third transistor T3_1 includes a channel region 131c_1 that overlaps with the first scan line 151 in a plan view, a source region 136c_1 and a drain region 137c_1 that are disposed on respective sides of the channel region 131c_1 and serve as conductive regions of the active pattern 130, and a gate electrode 155c_1 that overlaps with the channel region 131c_1. The gate electrode 155c_1 may be a portion of a protrusion from the first scan line 151. In a plan view, the drain region 137c_1 is disposed upwardly based on the first scan line 151 and is connected to the connection member 174 through the contact hole 63.

[0081] The lower third transistor T3_2 includes a channel region 131c_2 that overlaps with the first scan line 151 in plan view, a source region 136c_2 and a drain region 137c_2 that serve as conductive regions of the active pattern 130 and are disposed on respective sides of the channel region 131c_2, and a gate electrode 155c_2 that overlaps with the channel region 131c_2. The gate electrode 155c_2 is part of the first scan line 151. The source region 136c_2 of the lower third transistor T3_2 is connected to the drain region 137a of the first transistor T1, and the drain region 137c_2 is connected to the source region 136c_1 of the upper third transistor T3_1.

[0082] The fourth transistor T4 may also be formed of two parts to prevent leakage current. For example, the fourth transistor T4 may include a left fourth transistor T4_1 and a right fourth transistor T4_2 that are adjacent to and connected to each other.

[0083] The left fourth transistor T4_1 includes a channel region 131d_1 that overlaps with the second scan line 152 in a plan view, a source region 136d_1 and a drain region 137d_1 disposed on respective sides of the channel region 131d_1 as a conductive region of the active pattern 130, and a gate electrode 155d_1 that overlaps with the channel region 131d_1. The gate electrode 155d_1 is part of the second scan line 152. In a plan view, the drain region 137d_1 is disposed downwardly from the second scan line 152, is connected to the drain region 137c_1 of the upper third transistor T3_1, and is also connected to the connector 174 through the contact hole 63.

[0084] The right fourth transistor T4_2 includes a channel region 131d_2 that overlaps with the second scan line 152 in plan view, a source region 136d_2 and a drain region 137d_2 that are provided on respective sides of the channel region 131d_2 as conductive regions of the active pattern 130, and a gate electrode 155d_2 that overlaps with the channel region 131d_2. The gate electrode 155d_2 is part of the second scan line 152. The drain region 137d_2 is connected to the source region 136d_1 of the left fourth transistor T4_1, and the source region 136d_2 is connected to the connector 175 through the contact hole 65.

[0085] In the cross-sectional view, the connector 175 may be included in the second conductive layer or the third conductive layer. When the connector 175 is included in the third conductive layer, the connector 175 is electrically connected to the initialization voltage line 159 through the contact hole 64. When the connector 175 is included in the second conductive layer, the connector 175 is provided on the same layer as the initialization voltage line 159 in the cross-sectional view and may be connected to the initialization voltage line 159.

[0086] In a plan view, a boundary between the channel region 131d_1 and the source region 136d_1, a boundary between the channel region 131d_1 and the drain region 137d_1, and the channel region 131d_1 of the left fourth transistor T4_1 connected to the connection 174 that transmits the voltage of the driving gate electrode 155a may all be covered by the driving voltage line 172. In a plan view, the channel region 131d_1, the boundary between the channel region 131d_1 and the source region 136d_1, and the boundary between the channel region 131d_1 and the drain region 137d_1 overlap with the driving voltage line 172 and may be disposed in a planar area of ​​the driving voltage line 172. In a plan view, the width of each of the channel region 131d_1, the source region 136d_1, and the drain region 137d_1 of the left fourth transistor T4_1 in the horizontal direction is smaller than the width of the driving voltage line 172 in the horizontal direction, and the channel region 131d_1, the source region 136d_1, and the drain region 137d_1 can all be set within the region of the driving voltage line 172.

[0087] Therefore, although external light (such as Figure 8Although external light (as shown in FIG) is incident on the display device, the external light is blocked by the driving voltage line 172, thereby preventing the external light from entering the channel region 131d_1 of the left fourth transistor T4_1. Therefore, the left fourth transistor T4_1, which is directly connected to the driving gate node GN, prevents leakage current that would otherwise be caused by light, thereby suppressing changes in the voltage of the capacitor Cst. Therefore, display malfunctions such as changes in image brightness and color coordinates can be prevented.

[0088] An upper third transistor T3_1 is provided as one transistor, serving as a connection 174 directly connected to a voltage transmission driver gate electrode 155a. In a plan view, a boundary between a channel region 131c_1 and a source region 136c_1, and / or a boundary between the channel region 131c_1 and the drain region 137c_1 of the upper third transistor T3_1 is covered by a shielding portion 176. For example, in a plan view, at least one of a boundary between the channel region 131c_1 and the source region 136c_1 and a boundary between the channel region 131c_1 and the drain region 137c_1 overlaps with the shielding portion 176, thereby being disposed within the region of the shielding portion 176.

[0089] For example, as shown above, in a plan view, the shielding portion 176 overlaps the boundary between the channel region 131c_1 and the source region 136c_1 of the upper third transistor T3_1. The shielding portion 176 may not overlap the boundary between the channel region 131c_1 and the drain region 137c_1 of the upper third transistor T3_1, and thus, these elements may be spaced apart from the connector 174 in a plan view.

[0090] In a plan view, a width W1 of a distance from a boundary between the channel region 131c_1 and the source region 136c_1 of the upper third transistor T3_1 to one edge of the left or right side of the shielding portion 176 may be about 3 micrometers or more, however, the width W1 is not limited thereto.

[0091] The shielding portion 176 may be included in the second conductive layer or the third conductive layer. When the shielding portion 176 is included in the third conductive layer, the shielding portion 176 may be provided on the same layer as the connector 175 and may be electrically and physically connected to the connector 175. The shielding portion 176 may be spaced apart from the connector 174 connected to the driving gate electrode 155a by a predetermined distance.

[0092] Alternatively, the shielding portion 176 may further include a portion overlapping a boundary between the channel region 131 c_1 and the drain region 137 c_1 of the upper third transistor T3_1 in a plan view. For example, as described above, when the shielding portion 176 is provided on a different layer from the connector 174 in a cross-sectional view, the shielding portion 176 may include a portion overlapping a boundary between the channel region 131 c_1 and the source region 136 c_1 of the upper third transistor T3_1 and a boundary between the channel region 131 c_1 and the drain region 137 c_1 in a plan view.

[0093] According to an exemplary embodiment of the present invention, although external light is incident on the display device, the external light is blocked by the shielding portion 176, so that the external light can be prevented from being incident through the boundary portion between the channel region 131c_1 and the source region 136c_1 and / or the drain region 137c_1 of the upper third transistor T3_1. Therefore, leakage current caused by light is prevented by the upper third transistor T3_1 directly connected to the driving gate node GN, so that a change in the voltage of the capacitor Cst can be suppressed, and thus display malfunctions such as changes in brightness and color coordinates of an image can be prevented.

[0094] The fifth transistor T5 includes a channel region 131e, a source region 136e and a drain region 137e, which are conductive regions of the active pattern 130 and are disposed on respective sides of the channel region 131e, and a gate electrode 155e overlapping the channel region 131e. The gate electrode 155e is part of the control line 153. In a plan view, the source region 136e is disposed downwardly from the control line 153, connected to the channel region 131e, and connected to the driving voltage line 172 through the contact hole 67. In a plan view, the drain region 137e is disposed upwardly from the control line 153, connected to the channel region 131e, and connected to the source region 136a of the first transistor T1.

[0095] The sixth transistor T6 includes a channel region 131f, a source region 136f and a drain region 137f, which are conductive regions of the active pattern 130 and are located on respective sides of the channel region 131f, and a gate electrode 155f overlapping the channel region 131f. The gate electrode 155f is part of the control line 153. In a plan view, the source region 136f is positioned upward based on the control line 153, connected to the channel region 131f, and connected to the drain region 137a of the first transistor T1. In a plan view, the drain region 137f is positioned downward based on the control line 153, connected to the channel region 131f, and connected to the connector 179 through the contact hole 69. In a cross-sectional view, the connector 179 may be included in the third conductive layer.

[0096] The seventh transistor T7 includes a channel region 131g, a source region 136g and a drain region 137g, which are conductive regions of the active pattern 130 and are located on respective sides of the channel region 131g, and a gate electrode 155g overlapping the channel region 131g. The gate electrode 155g is a portion of the third scan line 154. In a plan view, the source region 136g is positioned upward based on the third scan line 154, connected to the channel region 131g, and connected to the drain region 137f of the sixth transistor T6. In a plan view, the drain region 137g is positioned downward based on the third scan line 154 and is connected to the connector 175 through the contact hole 65, thereby receiving the initialization voltage Vint.

[0097] The capacitor Cst may include a driving gate electrode 155a and an extension portion 157 of the storage line 156 overlapping each other in a plan view as two terminals. The capacitor Cst may maintain a voltage difference corresponding to a voltage difference between the extension portion 157 of the storage line 156 receiving the driving voltage ELVDD and the driving gate electrode 155a. In a plan view, the extension portion 157 of the storage line 156 may have an area wider than that of the driving gate electrode 155a and may cover the entire area of ​​the corresponding driving gate electrode 155a.

[0098] The second conductive layer may further include a shielding pattern 158 overlapping the data line 171. The shielding pattern 158 is connected to the driving voltage line 172 through the contact hole 66, thereby receiving the driving voltage ELVDD. The shielding pattern 158 shields the driving gate node GN from the data line 171, thereby blocking the voltage change of the driving gate node GN caused by the change of the data signal Dm. According to some exemplary embodiments of the present invention, the shielding pattern 158 may be omitted.

[0099] According to an exemplary embodiment of the present invention, the display device may further include a fourth conductive layer including a plurality of pixel electrodes 191a, 191b, and 191c and a pixel conductive pattern 192. In a cross-sectional view, the fourth conductive layer is disposed on a different layer from the first conductive layer, the second conductive layer, and the third conductive layer. For example, in a cross-sectional view, the fourth conductive layer may be disposed on the third conductive layer and may include the same material and be disposed on the same layer.

[0100] The plurality of pixel electrodes 191a, 191b, and 191c may be arranged in a pentile matrix structure. For example, the pixel electrodes 191a of the red pixel R and the pixel electrodes 191c of the blue pixel B may be arranged alternately in the horizontal direction, the pixel electrodes 191a of the red pixel R and the pixel electrodes 191b of the green pixel G may be arranged alternately in a first diagonal direction, and the pixel electrodes 191c of the blue pixel B and the pixel electrodes 191b of the green pixel G may be arranged alternately in a second diagonal direction, which may be different from the first diagonal direction. However, the arrangement of the pixel electrodes 191a, 191b, and 191c is not limited thereto.

[0101] The pixel electrode 191 a of the red pixel R may be smaller than the pixel electrode 191 c of the blue pixel B, and the pixel electrode 191 b of the green pixel G may be smaller than the pixel electrode 191 a of the red pixel R.

[0102] Each of the pixel electrodes 191 a , 191 b , and 191 c is connected to the connection member 179 through the contact hole 89 , thereby receiving a voltage.

[0103] The pixel conductive pattern 192 may be bent along the edges of adjacent pixel electrodes 191a, 191b, and 191c and may include straight portions (192a, 192b, and 192c) and oblique portions 193 that are alternately arranged. The straight portions (192a, 192b, and 192c) may extend primarily parallel to the scan lines 151, 152, and 154, and the oblique portions 193 may extend obliquely along the extending directions of the straight portions (192a, 192b, and 192c). The straight portion 192a may be adjacent to the pixel electrode 191a of the red pixel R, the straight portion 192b may be adjacent to the pixel electrode 191b of the green pixel G, and the straight portion 192c may be adjacent to the pixel electrode 191c of the blue pixel B.

[0104] The pixel conductive pattern 192 may transmit an initialization voltage Vint.

[0105] Reference Figures 3 to 6 In a plan view, the channel region 131c_1 of the upper third transistor T3_1, the boundary between the channel region 131c_1 and the source region 136c_1, and the boundary between the channel region 131c_1 and the drain region 137c_1 are all covered by the fourth conductive layer.

[0106] In a plan view, the channel region 131c_1, the boundary between the channel region 131c_1 and the source region 136c_1, and the boundary between the channel region 131c_1 and the drain region 137c_1 of the third upper transistor T3_1 of the red pixel R all overlap with the pixel electrode 191a, and are thus disposed in the planar area of ​​the pixel electrode 191a. In a plan view, the channel region 131c_1, the boundary between the channel region 131c_1 and the source region 136c_1, and the boundary between the channel region 131c_1 and the drain region 137c_1 of the third upper transistor T3_1 of the green pixel G all overlap with the pixel conductive pattern 192 (for example, overlap with the straight portion 192b of the pixel conductive pattern 192), and are thus disposed in the planar area of ​​the pixel conductive pattern 192. In a plan view, the channel region 131c_1 of the upper third transistor T3_1 of the blue pixel B, the boundary between the channel region 131c_1 and the source region 136c_1, and the boundary between the channel region 131c_1 and the drain region 137c_1 all overlap with the pixel electrode 191c and are thus disposed in a planar region of the pixel electrode 191c.

[0107] Therefore, although external light is incident on the display device, the external light is blocked by the fourth conductive layer including pixel electrodes 191a, 191b, and 191c and pixel conductive pattern 192, thereby preventing the external light from being incident on the channel region 131c_1 of the upper third transistor T3_1. For example, although the boundary between the channel region 131c_1 and the drain region 137c_1 of the upper third transistor T3_1 is not covered by shielding portion 176, the boundary between the channel region 131c_1 and the drain region 137c_1, along with the channel region 131c_1, is covered by the fourth conductive layer, thereby preventing external light from being incident on the channel region 131c_1 of the upper third transistor T3_1. Therefore, by blocking leakage current caused by light through the upper third transistor T3_1, which is directly connected to the driving gate node GN, a change in the voltage of the capacitor Cst can be suppressed.

[0108] Next, we will refer to Figures 3 to 8 A cross-sectional structure of a display device according to an exemplary embodiment of the present invention is described in detail.

[0109] The buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 blocks impurities from the substrate 110 from contaminating an upper layer above the buffer layer 120. For example, the buffer layer 120 may block impurities from the substrate 110 from penetrating into the active pattern 130, thereby increasing desired characteristics of the active pattern 130 and reducing stress applied to the active pattern 130. The buffer layer 120 may include a material such as silicon nitride (SiN x ) or silicon oxide (SiO x ) of an inorganic insulating material or an organic insulating material. At least a portion of the buffer layer 120 may be omitted.

[0110] The active pattern 130 is disposed on the buffer layer 120 , and the first insulating layer 141 is disposed on the active pattern 130 .

[0111] The above-mentioned first conductive layer may be provided on the first insulating layer 141. The first conductive layer may include a metal such as copper (Cu), aluminum (Al), molybdenum (Mo), or an alloy thereof.

[0112] The second insulating layer 142 may be disposed on the first conductive layer and the first insulating layer 141 .

[0113] The above-mentioned second conductive layer may be provided on the second insulating layer 142. The second conductive layer may include a metal such as copper (Cu), aluminum (Al), molybdenum (Mo), or an alloy thereof.

[0114] The third insulating layer 160 may be disposed on the second conductive layer and the second insulating layer 142 .

[0115] At least one of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may include silicon nitride (SiN x ), silicon oxide (SiO x ) of inorganic insulating materials and / or organic insulating materials.

[0116] The first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may include a contact hole 61 disposed on the driving gate electrode 155a, a contact hole 62 disposed on the source region 136b of the second transistor T2, a contact hole 63 disposed on the drain region 137c_1 of the upper third transistor T3_1 or the drain region 137d_1 of the left fourth transistor T4_1, a contact hole 64 disposed on the initialization voltage line 159, a contact hole 65 disposed on the source region 136d_2 of the right fourth transistor T4_2 or the drain region 137g of the seventh transistor T7, a contact hole 66 disposed on the shield pattern 158, a contact hole 67 disposed on the source region 136e of the fifth transistor T5, a contact hole 68 disposed on the extension portion 157 of the storage line 156, and a contact hole 69 disposed on the drain region 137f of the sixth transistor T6. The contact hole 61 may be formed through the opening 51 of the extension portion 157 of the storage line 156.

[0117] The third conductive layer may be disposed on the third insulating layer 160. The third conductive layer may include a metal such as copper (Cu), aluminum (Al), molybdenum (Mo), or an alloy thereof.

[0118] The extension portion 157 of the storage line 156 overlaps the driving gate electrode 155 a with the second insulating layer 142 interposed therebetween, thereby forming a capacitor Cst.

[0119] Passivation layer 180 is disposed on the third conductive layer and third insulating layer 160. Passivation layer 180 may include an organic insulating material such as polyacrylate resin and polyimide resin, and its upper surface may be substantially flat. Passivation layer 180 may include contact hole 89 disposed on connector 179.

[0120] The fourth conductive layer may be disposed on the passivation layer 180 .

[0121] A pixel defining layer (PDL) 350 may be disposed on the passivation layer 180 and the fourth conductive layer. The pixel defining layer 350 has openings 351 formed on the pixel electrodes 191a, 191b, and 191c.

[0122] The emission layer 370 is disposed on the pixel electrodes 191a, 191b, and 191c. The emission layer 370 may be disposed in the opening 351. The emission layer 370 may include an organic light emitting material or an inorganic light emitting material.

[0123] The common electrode 270 is disposed on the emission layer. The common electrode 270 may also be formed on the pixel defining layer 350 so as to extend across a plurality of pixels.

[0124] The pixel electrodes 191a, 191b, and 191c, the emission layer 370, and the common electrode 270 together form a light emitting diode (LED) ED.

[0125] An encapsulation layer protecting a light emitting diode (LED) ED may be disposed on the common electrode 270. The encapsulation layer may include inorganic layers and organic layers alternately stacked.

[0126] Next, we will refer to Figures 9 to 15 The above drawings describe a display device according to an exemplary embodiment of the present invention. Elements not specifically described below may be assumed to be similar or identical to corresponding elements already described.

[0127] First, refer to Figure 9 , the display device can be connected with Figures 1 to 8 176 is substantially the same as the display device according to the above exemplary embodiment shown in , however, in this example, the shielding portion 176 is spaced apart from the connection member 175. In a cross-sectional view, the shielding portion 176 may be provided at the same layer as the connection member 175, or may be provided at different layers.

[0128] Next, refer to Figure 10 and Figure 11The display device according to the exemplary embodiment of the present invention is substantially the same as the display device according to the above exemplary embodiment. However, in the cross-sectional view, the connector 175 is included in the second conductive layer. Therefore, the connector 175 is provided at the same layer as the initialization voltage line 159 and can be physically and electrically connected to the initialization voltage line 159. The shielding portion 176 may also be included in the second conductive layer and can be connected to the connector 175.

[0129] Next, refer to Figures 12 to 14 , a display device according to an exemplary embodiment of the present invention and Figure 10 and Figure 11 176 is substantially the same as the display device according to the above exemplary embodiment shown in , however, the shielding portion 176 is spaced apart from the connector 175. In a cross-sectional view, the shielding portion 176 may be provided at a different layer from the connector 175. For example, the shielding portion 176 may be included in the second conductive layer.

[0130] Next, refer to Figure 15 The display device according to the exemplary embodiment of the present invention is substantially the same as the display device according to the above exemplary embodiment, however, the second conductive layer including the storage line 156, the initialization voltage line 159, the shield pattern 158, etc. may be omitted. In addition, the second insulating layer 142 may be omitted.

[0131] The driving voltage line 172 may include an extension portion 173 overlapping the driving gate electrode 155a. In a plan view, the extension portion 173 and the driving gate electrode 155a overlap each other, and an insulating layer (e.g., the third insulating layer 160) is interposed between the extension portion 173 and the driving gate electrode 155a to form a capacitor Cst. Therefore, space utilization can be increased, and a capacitor Cst with sufficient capacitance can be formed.

[0132] The passivation layer 180 may include a contact hole 88 disposed on the connection member 175. The pixel conductive pattern 192 may transmit the initialization voltage Vint and may be electrically connected to the connection member 175 through the contact hole 88, thereby transmitting the initialization voltage Vint to the connection member 175.

[0133] While the invention has been described with reference to exemplary embodiments, it will be understood that the invention is not limited to the disclosed embodiments, but on the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.

Claims

1. A display device, comprising: a plurality of signal lines, including a first scan line; a plurality of pixels connected to the plurality of signal lines; as well as Conductive pattern, Each of the plurality of pixels includes a pixel electrode and a plurality of transistors. Wherein, the plurality of transistors include: a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first source region and a first drain region opposing each other with respect to the first channel region; a second transistor including a second gate electrode of the first scan line, a second channel region overlapping the second gate electrode, a second drain region electrically connected to the first gate electrode, and a second source region opposite to the second drain region with respect to the second channel region; and a third transistor including a third gate electrode of the first scan line, a third channel region overlapping the third gate electrode, a third drain region extending from the second source region, and a third source region opposite to the third drain region relative to the third channel region, The pixel electrode or the conductive pattern overlaps with at least a portion of the second source region and the second drain region and at least a portion of the third source region and the third drain region. The plurality of pixels include a first color pixel, a second color pixel, and a third color pixel. The pixel electrodes of the first color pixels and the pixel electrodes of the second color pixels are alternately arranged in a horizontal direction. The pixel electrodes of the first color pixels and the pixel electrodes of the third color pixels are alternately arranged in a first diagonal direction relative to the horizontal direction. wherein the pixel electrodes of the second color pixels and the pixel electrodes of the third color pixels are alternately arranged in a second diagonal direction relative to the horizontal direction, and The third source region of the third transistor is directly connected to the first drain region of the first transistor.

2. The display device according to claim 1, wherein The plurality of pixels include a first pixel and a second pixel, and In the first pixel, the pixel electrode overlaps at least a portion of the second source region and the second drain region and at least a portion of the third source region and the third drain region.

3. The display device according to claim 2, wherein: The conductive pattern and the pixel electrode are arranged in the same layer.

4. The display device according to claim 3, wherein In the second pixel, the conductive pattern overlaps at least a portion of the second source region and the second drain region and at least a portion of the third source region and the third drain region.

5. The display device according to claim 1, wherein The plurality of signal lines at least partially overlap the plurality of transistors. The display device according to claim 5 , wherein: The plurality of signal lines at least partially overlap channel regions of the plurality of transistors.

7. The display device according to claim 1, further comprising: a second scan line among the plurality of signal lines; as well as A fourth transistor includes a fourth gate electrode of the second scan line, a fourth channel region overlapping the fourth gate electrode, a fourth drain region electrically connected to the first gate electrode and extending from the second drain region, and a fourth source region opposite to the fourth drain region relative to the fourth channel region.

8. The display device according to claim 7, further comprising: a driving voltage line for transmitting a driving voltage, The driving voltage line overlaps with a boundary between the fourth source region and the fourth channel region and a boundary between the fourth drain region and the fourth channel region.

9. The display device according to claim 1, wherein The conductive pattern includes straight portions and oblique portions that are alternately arranged.

10. A display device, comprising: a plurality of signal lines, including a first scan line; a plurality of pixels connected to the plurality of signal lines; as well as Conductive pattern, Each of the plurality of pixels includes a pixel electrode and a plurality of transistors. Wherein, the plurality of transistors include: a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first source region and a first drain region opposing each other with respect to the first channel region; a second transistor including a second gate electrode of the first scan line, a second channel region overlapping the second gate electrode, a second drain region electrically connected to the first gate electrode, and a second source region opposite to the second drain region with respect to the second channel region; and a third transistor including a third gate electrode of the first scan line, a third channel region overlapping the third gate electrode, a third drain region extending from the second source region, and a third source region opposite to the third drain region relative to the third channel region, The pixel electrode or the conductive pattern overlaps with at least a portion of the second source region and the second drain region and at least a portion of the third source region and the third drain region, and The plurality of pixels include a first color pixel, a second color pixel, and a third color pixel. The pixel electrodes of the first color pixels and the pixel electrodes of the second color pixels are alternately arranged in a horizontal direction, The pixel electrodes of the first color pixels and the pixel electrodes of the third color pixels are alternately arranged in a first diagonal direction relative to the horizontal direction, and The pixel electrodes of the second color pixels and the pixel electrodes of the third color pixels are alternately arranged in a second diagonal direction relative to the horizontal direction, Wherein, the display device further includes: A shield portion overlaps at least a portion of the second source region and the second drain region and at least a portion of the third source region and the third drain region.

11. The display device according to claim 10, further comprising: a first connection member connected to the first gate electrode and provided in a conductive layer different from that of the first gate electrode; Wherein, the second drain region is electrically connected to the first gate electrode via the first connecting member.

12. The display device according to claim 11, wherein The shielding portion is located in the same conductive layer as the first connecting member and is separated from the first connecting member.

13. A display device, comprising: a plurality of signal lines, including a first scan line; a plurality of pixels connected to the plurality of signal lines; as well as Shielding part, Each of the plurality of pixels includes a pixel electrode and a plurality of transistors. Wherein, the plurality of transistors include: a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first source region and a first drain region opposing each other with respect to the first channel region; a second transistor including a second gate electrode of the first scan line, a second channel region overlapping the second gate electrode, a second drain region electrically connected to the first gate electrode, and a second source region opposite to the second drain region with respect to the second channel region; and a third transistor including a third gate electrode of the first scan line, a third channel region overlapping the third gate electrode, a third drain region extending from the second source region, and a third source region opposite to the third drain region relative to the third channel region, wherein the shielding portion overlaps at least a portion of the second source region and the second drain region and at least a portion of the third source region and the third drain region, and The plurality of pixels include a first color pixel, a second color pixel, and a third color pixel. The pixel electrodes of the first color pixels and the pixel electrodes of the second color pixels are alternately arranged in a horizontal direction, The pixel electrodes of the first color pixels and the pixel electrodes of the third color pixels are alternately arranged in a first diagonal direction relative to the horizontal direction, and The pixel electrodes of the second color pixels and the pixel electrodes of the third color pixels are alternately arranged in a second diagonal direction with respect to the horizontal direction.

14. The display device according to claim 13, wherein: In a first pixel among the plurality of pixels, the pixel electrode overlaps at least a portion of the second source region and the second drain region and at least a portion of the third source region and the third drain region. 15 . The display device according to claim 14 , further comprising a conductive pattern provided in the same layer as the pixel electrode.

16. The display device according to claim 15, wherein In a second pixel among the plurality of pixels, the conductive pattern overlaps at least a portion of the second source region and the second drain region and at least a portion of the third source region and the third drain region.

17. The display device according to claim 13, further comprising: a first connection member connected to the first gate electrode and provided in a conductive layer different from that of the first gate electrode; Wherein, the second drain region is electrically connected to the first gate electrode via the first connecting member.

18. The display device according to claim 17, wherein: In the plan view, the shielding portion is spaced apart from the first connecting member.

19. The display device according to claim 13, further comprising: a second scan line among the plurality of signal lines; as well as A fourth transistor includes a fourth gate electrode of the second scan line, a fourth channel region overlapping the fourth gate electrode, a fourth drain region electrically connected to the first gate electrode and extending from the second drain region, and a fourth source region opposite to the fourth drain region relative to the fourth channel region.

20. The display device according to claim 19, further comprising: a driving voltage line for transmitting a driving voltage, The driving voltage line overlaps with a boundary between the fourth source region and the fourth channel region and a boundary between the fourth drain region and the fourth channel region.

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