A coherent synchronization method for coherent pulse radar

Abstract

The present invention discloses a coherent synchronization method for a coherent pulse radar. The method comprises the following steps: using a temperature-controlled crystal oscillator (OCR) of a frequency source as the synchronization clock for the radar system, ensuring timing synchronization between the various data acquisition units; employing a level-triggered operation mode, with the master controller generating a trigger level using the synchronization clock and transmitting it to the data acquisition unit, which then samples the pulse signal using the synchronization clock, ensuring coherent operation of pulse transmission and data acquisition; transmitting the trigger level using LVPECL differential level transmission; optimizing the synchronization clock using the FPGA's built-in phase-locked loop (PLL); using the FPGA's built-in FDCE source language to constrain the transmission paths of the pulse trigger level and the synchronization clock within the FPGA; and pre-setting power-on self-test program logic to eliminate sampling instability caused by differences in the locking time between the PLLs, thereby ensuring coherent operation of the entire system. The present invention improves the stability and anti-interference performance of the coherent pulse radar's coherence function.

Description

Technical Field

[0001] The present invention relates to the technical field of coherent radar synchronization, in particular to a coherent synchronization method of a coherent pulse radar. Background Art

[0002] During operation, radars are affected by strong reflections from objects, clouds, and waves. To detect and identify various target parameters amidst strong background clutter, moving target indication (MTI), moving target detection (MTD), and pulse Doppler (PD) techniques are typically used. Regardless of the technology employed, highly stable coherent radar operation is required. However, in practical applications, various factors can interfere with the radar, such as interference from other equipment, long installation distances between data acquisition units, long electrical transmission links, and complex electromagnetic environments. These factors can prevent the radar from operating coherently as designed, leading to operational instability, pulse loss, or asynchrony. Therefore, the stability of the radar's coherent operation and its anti-interference performance must be considered in radar design. Summary of the Invention

[0003] The object of the present invention is to provide a coherent synchronization method for a coherent pulse radar, which can improve the error accuracy of the synchronization of the whole machine operation of the coherent pulse radar, ensure the synchronization of the whole machine, ensure the stability of high-speed transmission signals, improve the signal transmission quality in complex electromagnetic environments, enhance the electromagnetic environment adaptability of the whole machine operation and the coherent working stability in complex environments.

[0004] The technical solution for achieving the purpose of the present invention is: a coherent synchronization method for a coherent pulse radar, comprising the following steps:

[0005] Step 1: Use the crystal oscillator of the frequency source as the synchronous clock of the radar system to ensure the working timing synchronization between the data acquisition extensions;

[0006] Step 2: The whole machine uses the level trigger working mode. The master uses the synchronous clock to generate the trigger level and transmit it to the data acquisition extension. The data acquisition extension uses the synchronous clock to sample the pulse signal to ensure that the pulse emission and data acquisition work in a coherent manner.

[0007] Step 3: Use LVPECL differential level transmission to transmit the trigger level, ensuring the pulse signal transmission rate and reducing the interference introduced in the transmission path;

[0008] Step 4: Use the FPGA's built-in phase-locked loop to optimize the synchronous clock and eliminate distortion, distortion, and spurious signals during clock transmission.

[0009] Step 5. Use the FPGA's built-in FDCE source language to constrain the transmission path of the pulse trigger level and the synchronous clock in the FPGA to ensure that the delay of the trigger signal remains unchanged after each recompilation;

[0010] Step 6: Preset the power-on self-test program logic to eliminate the sampling instability caused by the locking time difference between the phase-locked loops. Perform a self-test every time the whole machine is powered on. If it is determined that the whole machine is out of synchronization, perform a phase shift operation on the clock output by the FPGA phase-locked loop to make the whole machine work in a coherent manner.

[0011] Furthermore, the crystal oscillator of the frequency source described in step 1 is a high-precision constant-temperature crystal oscillator, which is provided by the frequency source of the whole machine. A 120MHz high-precision constant-temperature crystal oscillator is selected, and the single-sideband phase noise is 158dBc / Hz@1KHz. The synchronous clock is sent from the frequency source to the main control and data acquisition extension. The main control and data acquisition extension use the synchronous clock to generate the working pulse of the whole machine. The frequency source and data acquisition extension use the synchronous clock to collect the working pulses sent by the main control and data acquisition extension; the data acquisition extensions use the same clock to ensure that the working timing between each data acquisition extension is synchronized.

[0012] Furthermore, the LVPECL differential level transmission method described in step 3 has a transmission rate of 10 Gbps and has anti-interference performance, so that no distortion or burrs will occur during the transmission of the pulse signal of the entire device.

[0013] Furthermore, the FPGA described in step 4 has its own phase-locked loop. The IP core is called in the ISE programming software to set the input and output frequencies. The external input clock is output after passing through the FPGA phase-locked loop. The input and output frequencies are consistent. By using the FPGA phase-locked loop, signal distortion and glitches caused by transmission are eliminated, and the re-locked synchronous clock is a standard sine signal.

[0014] Furthermore, the FDCE source language described in step 5 is based on Verilog syntax and redefines the external input pulse trigger signal so that the transmission link of the pulse trigger signal in the FPGA is fixed.

[0015] Furthermore, the power-on self-test program described in step 6 is automatically run after the entire machine is powered on.

[0016] Furthermore, the power-on self-test program described in step 6 includes two functional modules: pulse counting and phase shifting.

[0017] Furthermore, the power-on self-test procedure described in step 6 is as follows:

[0018] Step 6.1: The master controller sends a predetermined number of pulses to each data acquisition extension, and the data acquisition extension performs sampling and counting;

[0019] Step 6.2: After the data collection extension finishes sampling, perform comparative counting:

[0020] If the number of pulses received is the same as the agreed number, the whole machine will start to work normally and end the self-test procedure;

[0021] If the number of pulses received is different from the agreed number, the problematic data acquisition extension will shift the sampling clock by 180° and report it to the main control, and then go to step 6.3;

[0022] Step 6.3: The data acquisition extension performs the pulse counting operation again:

[0023] If the number of pulses received is the same as the agreed number, the whole machine will start to work normally and end the self-test procedure;

[0024] If the number of pulses received is still different from the agreed number, a fault will be reported and manual inspection will be required.

[0025] Furthermore, in step 6.1, the pulse sent by the master control is a narrow trigger pulse.

[0026] Furthermore, in step 6.2, the problematic data acquisition extension shifts the sampling clock by 180° and reports it to the main control.

[0027] Compared with the prior art, the present invention has the following significant advantages: (1) The present invention is designed in a coordinated manner from the aspects of hardware and software. In terms of hardware design, the sampling clock uses a high-precision constant temperature crystal oscillator source in the frequency source according to the coherent working requirements of the whole machine to ensure the error accuracy of the whole machine working synchronization; (2) The working trigger level is generated by the sampling clock of the whole machine to ensure the synchronization of the whole machine, and is transmitted to each data acquisition extension through the LVPECL method to ensure the stability of the high-speed transmission signal and improve the signal transmission quality in a complex electromagnetic environment; (3) The software design optimizes the signal quality by using FPGA source language and phase-locked loop IP core, presets the power-on sampling self-test program, and detects and adjusts the signal working status; (4) Through the combination of software and hardware, the pulse radar whole machine can realize the coherent synchronous operation, and effectively improves the working stability and anti-interference performance of the whole machine in a complex electromagnetic environment. The working timing accuracy of the whole machine reaches 8.3ns, ensuring the coherence of the whole machine operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a design principle diagram of a coherent synchronization method of a coherent pulse radar of the present invention.

[0029] Figure 2 This is an example diagram of FPGA source language application in an embodiment of the present invention.

[0030] Figure 3 This is a diagram illustrating the use of an FPGA phase-locked loop in an embodiment of the present invention.

[0031] Figure 4 This is a working logic diagram of the coherent pulse radar power-on self-test in an embodiment of the present invention.

[0032] Figure 5 1 is a timing diagram illustrating the sampling clock and trigger pulse of the coherent pulse radar in an embodiment of the present invention.

[0033] Figure 6 1 is a timing diagram illustrating the phase shifting of the coherent pulse radar clock in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] A coherent synchronization method for a coherent pulse radar comprises the following steps:

[0035] Step 1: Use the crystal oscillator of the frequency source as the synchronous clock of the radar system to ensure the working timing synchronization between the data acquisition extensions;

[0036] Step 2: The whole machine uses the level trigger working mode. The master uses the synchronous clock to generate the trigger level and transmit it to the data acquisition extension. The data acquisition extension uses the synchronous clock to sample the pulse signal to ensure that the pulse emission and data acquisition work in a coherent manner.

[0037] Step 3: Use LVPECL differential level transmission to transmit the trigger level, ensuring the pulse signal transmission rate and reducing the interference introduced in the transmission path;

[0038] Step 4: Use the FPGA's built-in phase-locked loop to optimize the synchronous clock and eliminate distortion, distortion, and spurious signals during clock transmission.

[0039] Step 5. Use the FPGA's built-in FDCE source language to constrain the transmission path of the pulse trigger level and the synchronous clock in the FPGA to ensure that the delay of the trigger signal remains unchanged after each recompilation;

[0040] Step 6: Preset the power-on self-test program logic to eliminate the sampling instability caused by the locking time difference between the phase-locked loops. Perform a self-test every time the whole machine is powered on. If it is determined that the whole machine is out of synchronization, perform a phase shift operation on the clock output by the FPGA phase-locked loop to make the whole machine work in a coherent manner.

[0041] As a specific example, the crystal oscillator of the frequency source described in step 1 is a high-precision constant-temperature crystal oscillator, which is provided by the frequency source of the whole machine. A 120MHz high-precision constant-temperature crystal oscillator is selected, and the single-sideband phase noise is 158dBc / Hz@1KHz. The synchronous clock is sent from the frequency source to the main control and data acquisition extension. The main control and data acquisition extension use the synchronous clock to generate the working pulse of the whole machine. The frequency source and data acquisition extension use the synchronous clock to collect the working pulses sent by the main control and data acquisition extension; the data acquisition extensions use the same clock to ensure that the working timing of each data acquisition extension is synchronized.

[0042] As a specific example, the LVPECL differential level transmission method described in step 3 has a transmission rate of 10 Gbps and has anti-interference performance, so that no distortion or burrs will occur during the transmission of the entire device pulse signal.

[0043] As a specific example, the FPGA described in step 4 has a built-in phase-locked loop. The IP core is called in the ISE programming software to set the input and output frequencies. The external input clock is output after passing through the FPGA phase-locked loop. The input and output frequencies are consistent. By using the FPGA phase-locked loop, signal distortion and glitches caused by transmission are eliminated, and the re-locked synchronous clock is a standard sine signal.

[0044] As a specific example, the FDCE source language described in step 5 is based on Verilog syntax and redefines the external input pulse trigger signal so that the transmission link of the pulse trigger signal in the FPGA is fixed.

[0045] As a specific example, the power-on self-test program described in step 6 runs automatically after the entire machine is powered on.

[0046] As a specific example, the power-on self-test program described in step 6 includes two functional modules: pulse counting and phase shifting.

[0047] As a specific example, the power-on self-test procedure described in step 6 is as follows:

[0048] Step 6.1: The master controller sends a predetermined number of pulses to each data acquisition extension, and the data acquisition extension performs sampling and counting;

[0049] Step 6.2: After the data collection extension finishes sampling, perform comparative counting:

[0050] If the number of pulses received is the same as the agreed number, the whole machine will start to work normally and end the self-test procedure;

[0051] If the number of pulses received is different from the agreed number, the problematic data acquisition extension will shift the sampling clock by 180° and report it to the main control, and then go to step 6.3;

[0052] Step 6.3: The data acquisition extension performs the pulse counting operation again:

[0053] If the number of pulses received is the same as the agreed number, the whole machine will start to work normally and end the self-test procedure;

[0054] If the number of pulses received is still different from the agreed number, a fault will be reported and manual inspection will be required.

[0055] As a specific example, in step 6.1, the pulse sent by the master control is a narrow trigger pulse.

[0056] As a specific example, in step 6.2, the problematic data acquisition extension shifts the sampling clock by 180° and reports it to the main control.

[0057] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0058] Example

[0059] Combine Figure 1 The present invention provides a coherent synchronization method for a coherent pulse radar. The method uses a high-precision oven-controlled crystal oscillator in a frequency source as a synchronization clock for the entire device, which is output to a master control unit and a digital sampling extension. The master control unit uses the synchronization clock to generate a working trigger pulse for the entire device, which is transmitted to each data acquisition extension via an LVPECL level. The frequency source and the digital sampling data acquisition extension use the synchronization clock as a sampling clock to sample the working trigger pulse, thereby responding to the control of the master control to achieve coherent operation of the entire device. The method specifically includes the following steps:

[0060] Step 1: Use the high-precision oven-controlled crystal oscillator of the frequency source as the synchronous clock of the radar system to ensure the working timing synchronization between the data acquisition extensions;

[0061] The high-precision constant-temperature crystal of the frequency source is provided by the frequency source of the whole machine. A 120MHz high-precision constant-temperature crystal oscillator is selected, and the single-sideband phase noise is 158dBc / Hz@1KHz. The synchronous clock is sent by the frequency source to the main control and data acquisition extension. The main control and data acquisition extension use the synchronous clock to generate the working pulse of the whole machine. The frequency source and data acquisition extension use the synchronous clock to collect the working pulses sent by the main control and data acquisition extension; the data acquisition extensions use the same clock to ensure the working timing synchronization between the data acquisition extensions.

[0062] Step 2: The whole machine uses the level trigger working mode. The master uses the synchronous clock to generate the trigger level and transmit it to the data acquisition extension. The data acquisition extension uses the synchronous clock to sample the pulse signal to ensure that the pulse emission and data acquisition work in a coherent manner.

[0063] Step 3: Use LVPECL differential level transmission to transmit the trigger level, ensuring the pulse signal transmission rate and reducing the interference introduced in the transmission path;

[0064] The LVPECL differential level transmission method has a theoretical transmission rate of 10Gbps and has strong anti-interference performance, ensuring that there will be no distortion or burrs during the transmission of the entire machine pulse signal, thereby improving the signal transmission quality.

[0065] Step 4: Use the FPGA's built-in phase-locked loop to optimize the synchronous clock and eliminate distortion, distortion, and spurious signals during clock transmission.

[0066] The FPGA has a built-in phase-locked loop. The IP core is called in the ISE programming software to set the input and output frequencies. The external input clock is output after passing through the FPGA phase-locked loop. The input and output frequencies are consistent. By using the FPGA phase-locked loop, signal distortion and burrs caused by transmission are eliminated. The re-locked synchronous clock is a standard sine signal, ensuring the stability and accuracy of sampling.

[0067] Step 5. Use the FPGA's built-in FDCE source language to constrain the transmission path of the pulse trigger level and the synchronous clock in the FPGA to ensure that the delay of the trigger signal remains unchanged after each recompilation;

[0068] The FDCE source language is based on Verilog syntax and redefines the external input pulse trigger signal to fix the transmission link of the signal in the FPGA, thereby avoiding changes in the transmission link after each compilation, which causes timing deviation.

[0069] Step 6: Preset the power-on self-test program logic to eliminate the sampling instability caused by the locking time difference between the phase-locked loops. Perform a self-test every time the whole machine is powered on. If it is determined that the whole machine is out of synchronization, perform a phase shift operation on the clock output by the FPGA phase-locked loop to make the whole machine work in a coherent manner.

[0070] The power-on self-test program automatically runs after the whole machine is powered on. The power-on self-test program includes two functional modules: pulse counting and phase shifting. The power-on self-test program is specifically as follows:

[0071] Step 6.1: The master controller sends a predetermined number of narrow pulses to each data acquisition extension, and the data acquisition extension starts sampling the pulses; the pulses sent by the master controller are narrow trigger pulses;

[0072] Step 6.2: After sampling is completed, compare the counts. If the counts are the same as the agreed number, the machine will start to work normally.

[0073] Step 6.3: If the number is different from the agreed number, the problematic data acquisition extension will shift the sampling clock by 180 degrees and report it to the main control, and perform the pulse counting operation again;

[0074] Step 6.4: If the number is the same as the agreed number, the whole machine will start to work normally;

[0075] Step 6.5: If the quantity is still different from the agreed quantity, a fault will be reported and manual inspection will be required.

[0076] To eliminate the DC component in the synchronous clock and the effects of spurious signals and distortion during transmission, each data acquisition unit outputs the input synchronous clock through the FPGA phase-locked loop. In this example, the synchronous clock is 120MHz, and the phase-locked loop is set as follows: Figure 2 As shown, the input is 120MHz and the output is 120MHz. After the PLL is re-locked, the output clock is a standard sine wave.

[0077] Figure 3 This is FPGA source code written in Verilog hardware description language. TIMER_IN is the external input trigger pulse, CLK_120M is the system synchronization clock after passing through the phase-locked loop (PLL), and TIMER is the trigger pulse after passing through the FPGA. All other parameters are left as default. After applying FDCE source language constraints, the relative relationship between TIMER and CLK_120M is determined and remains unchanged after recompiling. This setting improves program stability and eliminates system errors caused by program compilation.

[0078] Figure 4 This is the relationship between the synchronous sampling clock and the trigger pulse after each power-on. Because the synchronous clock used by each data acquisition extension passes through its own FPGA phase-locked loop, the phase difference of each synchronous clock is inconsistent after each power-on, resulting in a change in the relative relationship between the sampling clock and the trigger pulse after power is re-applied. The figure lists the relative relationship diagram of clk1-clk6 and the trigger pulse. In actual conditions, the relative relationship may be at any position after power is re-applied, but after power is re-applied, the relationship no longer changes. This is equivalent to a random phase difference of Δφ between the synchronous clocks of each data acquisition extension at each power-on, but this value no longer changes after the phase-locked loop stabilizes, so it does not affect the coherent performance of the entire machine during operation.

[0079] In actual use, when Figure 4 In the clk3 clock state, the rising edge of the sampling clock is aligned with the rising edge of the trigger pulse. Since the trigger mode adopts rising edge triggering (the same applies to falling edge), when the two edges are aligned, the sampling clock may miss samples or skip clock cycles, causing pulse signal delay and unstable pulse repetition frequency cycle.

[0080] To solve the above problem, a self-test is performed every time the system is restarted. The working process is as follows: Figure 5 As shown in the figure, the master sends 1000 narrow trigger pulses, and the data acquisition extension counts the pulses. If the received pulses are also 1000, the whole device starts working normally. If the data acquisition extension counts pulses less than 1000, the synchronous clock and pulse trigger signal in the data acquisition extension may be in Figure 4 clk3 state, the clock is phase shifted 180 degrees, such as Figure 6As shown, the phase-shifted clock ~clk allows for stable sampling of the pulse trigger signal. At this point, the radar performs another self-test. If it passes, the entire system boots up normally. If it still fails, a fault is reported and awaits manual troubleshooting. This design effectively improves the stability of the entire system's coherent operation and controls the overall synchronization error to 8.3ns, or within one sampling clock cycle. This effectively enhances the radar's target recognition capability and increases its operational reliability.

[0081] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A coherent synchronization method for a coherent pulse radar, characterized in that: The following steps are involved: Step 1: Use the crystal oscillator of the frequency source as the synchronous clock of the radar system to ensure the working timing synchronization between the data acquisition extensions; Step 2: The whole machine uses the level trigger working mode. The master uses the synchronous clock to generate the trigger level and transmit it to the data acquisition extension. The data acquisition extension uses the synchronous clock to sample the pulse signal to ensure that the pulse emission and data acquisition work in a coherent manner. Step 3: Use LVPECL differential level transmission to transmit the trigger level, ensuring the pulse signal transmission rate and reducing the interference introduced in the transmission path; Step 4: Use the FPGA's built-in phase-locked loop to optimize the synchronous clock and eliminate distortion, distortion, and spurious signals during clock transmission. Step 5. Use the FPGA's built-in FDCE source language to constrain the transmission path of the pulse trigger level and the synchronous clock in the FPGA to ensure that the delay of the trigger signal remains unchanged after each recompilation; Step 6: Preset the power-on self-test program logic to eliminate the sampling instability caused by the locking time difference between the phase-locked loops. Perform a self-test every time the whole machine is powered on. If it is determined that the whole machine is out of synchronization, perform a phase shift operation on the clock output by the FPGA phase-locked loop to make the whole machine work in a coherent manner.

2. The coherent synchronization method of the coherent pulse radar according to claim 1, characterized in that: The crystal oscillator of the frequency source described in step 1 is a high-precision oven-controlled crystal oscillator, provided by the frequency source of the whole machine. A 120MHz high-precision oven-controlled crystal oscillator is selected, and the single-sideband phase noise is 158dBc / Hz@1KHz. The synchronous clock is sent by the frequency source to the main control and data acquisition extension. The main control and data acquisition extension use the synchronous clock to generate the working pulse of the whole machine. The frequency source and data acquisition extension use the synchronous clock to collect the working pulses emitted by the main control and data acquisition extension; The data collection extensions use the same clock to ensure that the working timing of each data collection extension is synchronized.

3. The coherent synchronization method of the coherent pulse radar according to claim 1, characterized in that: The LVPECL differential level transmission method described in step 3 has a transmission rate of 10 Gbps and has anti-interference performance, so that the entire device pulse signal transmission process will not be distorted or burred.

4. The coherent synchronization method of a coherent pulse radar according to claim 1, characterized in that: The FPGA described in step 4 has a built-in phase-locked loop. Call the IP core in the ISE programming software, set the input and output frequencies, and output the external input clock after passing through the FPGA phase-locked loop. The input and output frequencies are consistent. By using the FPGA phase-locked loop, signal distortion and glitches caused by transmission are eliminated. The re-locked synchronous clock is a standard sine signal.

5. The coherent synchronization method of a coherent pulse radar according to claim 1, characterized in that: The FDCE source language described in step 5 is based on Verilog syntax and redefines the external input pulse trigger signal so that the transmission link of the pulse trigger signal in the FPGA is fixed.

6. The coherent synchronization method of a coherent pulse radar according to claim 1, characterized in that: The power-on self-test program described in step 6 runs automatically after the entire machine is powered on.

7. The coherent synchronization method of a coherent pulse radar according to claim 6, characterized in that: The power-on self-test program described in step 6 includes two functional modules: pulse counting and phase shifting.

8. The coherent synchronization method of a coherent pulse radar according to claim 7, characterized in that: The power-on self-test procedure described in step 6 is as follows: Step 6.1: The master controller sends a predetermined number of pulses to each data acquisition extension, and the data acquisition extension performs sampling and counting; Step 6.2: After the data collection extension finishes sampling, perform comparative counting: If the number of pulses received is the same as the agreed number, the whole machine will start to work normally and end the self-test procedure; If the number of pulses received is different from the agreed number, the problematic data acquisition extension will shift the sampling clock by 180° and report it to the main control, and then go to step 6.3; Step 6.3: The data acquisition extension performs the pulse counting operation again: If the number of pulses received is the same as the agreed number, the whole machine will start to work normally and end the self-test procedure; If the number of pulses received is still different from the agreed number, a fault will be reported and manual inspection will be required.

9. The coherent synchronization method of a coherent pulse radar according to claim 8, characterized in that: In step 6.1, the pulse sent by the master is a narrow trigger pulse.

10. The coherent synchronization method of a coherent pulse radar according to claim 8, characterized in that: In step 6.2, the problematic data acquisition extension shifts the sampling clock by 180° and reports it to the main control.

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