Display device, data driving circuit, and display driving method

Abstract

This disclosure relates to display devices, data driving circuits, and display driving methods. According to one embodiment, the display device includes: a display panel having a plurality of sub-pixel circuits disposed therein, each of the plurality of sub-pixel circuits including a light-emitting element, a driving transistor, and a sensing transistor; a gate driving circuit configured to provide a plurality of scan signals to the display panel via a plurality of gate lines; a data driving circuit configured to provide a plurality of data voltages to the display panel via a plurality of data lines and to provide a constant current to the plurality of sub-pixel circuits during a resistance sensing period; and a timing controller configured to control the gate driving circuit and the data driving circuit, and to provide compensated image data to the display panel by using the resistance of the sensing transistor detected during the resistance sensing period.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0188245, filed on December 27, 2021, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0003] This disclosure relates to display devices, data driving circuits, and display driving methods capable of accurately determining and compensating for the characteristic values ​​of driving transistors. Background Technology

[0004] With the development of the information society, the demand for various types of image display devices is increasing. In this regard, a range of display devices, such as liquid crystal displays and organic light-emitting diode displays, have recently been widely used.

[0005] Among these display devices, organic light-emitting displays use organic light-emitting diodes, thus offering advantages in terms of contrast, luminous efficiency, brightness, and viewing angle, as well as various other benefits.

[0006] In this display device, pixels, each having its own subpixel, are arranged in a matrix pattern on a display panel that displays an image. By controlling the voltage supplied to the light-emitting elements, the light-emitting elements constituting each subpixel emit light, thereby controlling the brightness of each subpixel and displaying the image.

[0007] Each sub-pixel defined on the display panel of a display device has a light-emitting element and a driving transistor for driving that light-emitting element. The characteristic values ​​of the driving transistor (e.g., threshold voltage or mobility) can vary depending on the driving time, or may deviate due to the driving time difference between sub-pixels. Brightness deviations between sub-pixels (brightness non-uniformity) may lead to a reduction in image quality.

[0008] To address brightness discrepancies between subpixels, techniques exist that use sensing transistors to sense characteristic values ​​(e.g., threshold voltage or mobility) of driving transistors and to compensate for these characteristic values.

[0009] However, since the voltage of the sensing transistor may vary due to the drive current during the sensing period of the characteristic value of the driving transistor, it may introduce errors into the sensing results of the characteristic value of the driving transistor. Summary of the Invention

[0010] Therefore, the inventors of this disclosure have invented a display device, a data driving circuit, and a display driving method capable of detecting the resistance of a sensing transistor.

[0011] Embodiments of this disclosure can provide a display device, a data driving circuit, and a display driving method capable of accurately determining the characteristic value of a driving transistor by detecting the resistance of the sensing transistor before sensing the characteristic value of the driving transistor.

[0012] Embodiments of this disclosure can provide a display device, a data driving circuit, and a display driving method capable of detecting the resistance of a sensing transistor by sensing changes in a characteristic value based on changes in data voltage and driving voltage while providing a constant current to the driving transistor.

[0013] Embodiments of this disclosure can provide a display device, a data driving circuit, and a display driving method capable of accurately compensating for characteristic value deviations of a driving transistor by precisely determining the characteristic value of the driving transistor using the resistance of the sensing transistor.

[0014] One embodiment of this disclosure provides a display device comprising: a display panel having a plurality of sub-pixel circuits therein, each of the plurality of sub-pixel circuits including a light-emitting element, a driving transistor, and a sensing transistor; a gate driving circuit configured to provide a plurality of scan signals to the display panel via a plurality of gate lines; a data driving circuit configured to provide a plurality of data voltages to the display panel via a plurality of data lines and to provide a constant current to the plurality of sub-pixel circuits during a resistance sensing period; and a timing controller configured to control the gate driving circuit and the data driving circuit, and to provide compensated image data to the display panel by using the resistance of the sensing transistor detected during the resistance sensing period.

[0015] One embodiment of this disclosure provides a data driving circuit for providing multiple data voltages to a display panel, wherein multiple sub-pixel circuits are disposed in the display panel, each of the multiple sub-pixel circuits including a light-emitting element, a driving transistor, and a sensing transistor. The data driving circuit includes: an analog-to-digital converter configured to convert a sensed voltage detected from a reference voltage line into a digital value; a sampling switch configured to control the connection between the reference voltage line and the analog-to-digital converter; a constant current source configured to provide a constant current to the multiple sub-pixel circuits during a resistance sensing period; and a constant current switch configured to control the connection between the constant current source and the reference voltage line.

[0016] One embodiment of this disclosure provides a display driving method for a display panel having a plurality of sub-pixel circuits, each of the plurality of sub-pixel circuits including a light-emitting element, a driving transistor, and a sensing transistor. The display driving method includes: setting a resistance sensing period for detecting the resistance of the sensing transistor; providing a constant current to the plurality of sub-pixel circuits through a constant current source during the resistance sensing period; detecting a change in the sensed voltage on a reference voltage line while changing a data voltage; calculating the resistance of the sensing transistor; determining a characteristic value of the driving transistor using the resistance of the sensing transistor; and providing compensated image data reflecting the characteristic value of the driving transistor.

[0017] According to one embodiment of this disclosure, a display device, a data driving circuit, and a display driving method capable of detecting the resistance of a sensing transistor can be provided.

[0018] Additionally, according to one embodiment of this disclosure, a display device, data driving circuit, and display driving method can be provided that are capable of accurately determining the characteristic value of a driving transistor by detecting the resistance of the sensing transistor before sensing the characteristic value of the driving transistor.

[0019] Additionally, according to one embodiment of this disclosure, a display device, a data driving circuit, and a display driving method can be provided that can detect the resistance of a sensing transistor by sensing changes in a characteristic value based on changes in data voltage and driving voltage while providing a constant current to the driving transistor.

[0020] Additionally, according to one embodiment of this disclosure, a display device, data driving circuit, and display driving method can be provided that can accurately compensate for characteristic value deviations of the driving transistor by precisely determining the characteristic value of the driving transistor using the resistance of the sensing transistor. Attached Figure Description

[0021] In the attached diagram:

[0022] Figure 1 A schematic diagram of a display device according to one embodiment of the present disclosure is shown;

[0023] Figure 2 A system diagram of a display device according to one embodiment of the present disclosure is shown;

[0024] Figure 3 A circuit diagram of a sub-pixel circuit of a display device according to one embodiment of the present disclosure is shown;

[0025] Figure 4 An example circuit structure for sensing the characteristic values ​​of a driving transistor is shown;

[0026] Figure 5The signal timing diagram for external compensation of the threshold voltage used to drive the transistor is shown;

[0027] Figure 6 The signal timing diagram for external compensation of the mobility of the driving transistor is shown;

[0028] Figure 7 The signal timing diagram for internal compensation of the threshold voltage and mobility used to drive the transistor is shown;

[0029] Figure 8 A conceptual diagram is shown illustrating the error in the sensed voltage due to the voltage deviation of the sensed transistor during the process of sensing the characteristic value of the drive transistor.

[0030] Figure 9 An exemplary circuit structure is shown for detecting the resistance of a sensing transistor in a display device according to one embodiment of the present disclosure.

[0031] Figure 10 An exemplary signal waveform diagram is shown in a display device according to one embodiment of the present disclosure when a first level data voltage and a second level data voltage that are different from each other are provided during a resistance sensing period;

[0032] Figure 11 An exemplary circuit structure is shown in a display device according to one embodiment of the present disclosure, in which the resistance of a sensing transistor is used to compensate for characteristic value deviations of a driving transistor.

[0033] Figure 12 A signal timing diagram is shown in a display device according to one embodiment of the present disclosure, showing the use of the resistance of a sensing transistor to compensate for the mobility of a driving transistor.

[0034] Figure 13 A flowchart of a display driving method according to one embodiment of the present disclosure is shown. Detailed Implementation

[0035] In the following description, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and in the drawings, the same reference numerals and symbols may be used to refer to the same or similar components even if shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0036] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0037] When it is mentioned that the first element is "connected or coupled to" the second element, or "in contact or overlaps" with the second element, it should be interpreted as meaning that the first element can not only be "directly connected or coupled to" the second element or "directly contact or overlap" with the second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled," "in contact or overlap" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact or overlap," etc.

[0038] When time-related terms such as “after,” “follow,” “next,” “before,” etc., are used to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe non-continuous or non-sequential handling or operation, unless the terms “directly” or “immediately after” are used together.

[0039] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical values ​​or corresponding information (e.g., levels, ranges, etc.) of an element or feature include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0040] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 This is a view schematically illustrating the configuration of a display device according to one embodiment of the present disclosure;

[0042] Reference Figure 1 The display device 100 according to embodiments of the present disclosure may include: a display panel 110, in which a plurality of gate lines GL and data lines DL are connected and a plurality of sub-pixels SP are arranged in a matrix; a gate driving circuit 120 that drives the plurality of gate lines GL; a data driving circuit 130 that provides data voltage through the plurality of data lines DL; a timing controller 140 that controls the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0043] The display panel 110 displays images based on scan signals transmitted from the gate drive circuit 120 via multiple gate lines GL and data voltages transmitted from the data drive circuit 130 via multiple data lines DL.

[0044] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates and can operate in any known mode, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or edge field switching (FFS) mode. In the case of an organic light-emitting display, the display panel 110 may be implemented as a top-emitting scheme, a bottom-emitting scheme, or a dual-emitting scheme.

[0045] In the display panel 110, multiple pixels can be arranged in a matrix, and each pixel can include sub-pixels SP with different colors, such as white sub-pixels, red sub-pixels, green sub-pixels and blue sub-pixels, and each sub-pixel SP can be defined by multiple data lines DL and multiple gate lines GL.

[0046] A sub-pixel SP may include, for example: a thin-film transistor (TFT) formed at the intersection between a data line DL and a gate line GL; a light-emitting element (e.g., an organic light-emitting diode) charged with a data voltage; and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0047] For example, when a display device 100 with a resolution of 2160×3840 includes four sub-pixels SP representing white (W), red (R), green (G), and blue (B), 3840 data lines DL can be connected to 2160 gate lines GL and the four sub-pixels WRGB, thus providing 3840×4=15360 data lines DL. Each sub-pixel SP is positioned at the intersection between the gate line GL and the data line DL.

[0048] The gate drive circuit 120 can be controlled by the controller 140 to sequentially output scan signals to multiple gate lines GL disposed in the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0049] In a display device 100 with a resolution of 2160×3840, sequentially outputting scan signals from the first gate line to the 2160th gate line to 2160 gate lines GL can be referred to as 2160-phase driving. Sequentially outputting scan signals to each of the four gate lines GL (for example, after sequentially outputting scan signals to the first to fourth gate lines, sequentially outputting scan signals to the fifth to eighth gate lines) is referred to as 4-phase driving. In other words, sequentially outputting scan signals to every N gate lines GL can be referred to as N-phase driving.

[0050] The gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs). Depending on the driving scheme, the gate driving circuit 120 may be located only on one side of the display panel 110, or on each of two opposite sides of the display panel 110. The gate driving circuit 120 may be implemented as an in-panel gate (GIP) embedded in the bezel area of ​​the display panel 110.

[0051] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, according to the timing when a scan signal is provided through the gate line GL, the data voltage is output to each data line DL, and each sub-pixel SP connected to the data line DL displays a light-emitting signal with a brightness corresponding to the data voltage.

[0052] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may be connected to the bonding pads of the display panel 110 in a tape auto-bonding (TAB) type or chip-on-glass (COG) type, or may be directly disposed on the display panel 110.

[0053] In some cases, each source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Furthermore, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) type, and in this case, each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL of the display panel 110 via the circuit film.

[0054] The timing controller 140 provides various control signals to the gate drive circuit 120 and the data drive circuit 130, and controls the operation of the gate drive circuit 120 and the data drive circuit 130. In other words, the timing controller 140 can control the gate drive circuit 120 to output a scan signal according to the timing implemented in each frame, and on the other hand, transmit the image data DATA received from the outside to the data drive circuit 130.

[0055] In this configuration, the timing controller 140 receives several timing signals from the external host system 200, including, for example, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, the master clock MCLK, and the image data DATA.

[0056] The host system 200 can be any of the following: a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0057] Therefore, the timing controller 140 can generate control signals based on various timing signals received from the host system 200, and transmit the control signals to the gate drive circuit 120 and the data drive circuit 130.

[0058] For example, timing controller 140 outputs several gate control signals (including, for example, a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE) to control gate drive circuit 120. The gate start pulse GSP controls the timing of the start of operation of one or more gate driver integrated circuits (GDICs) constituting gate drive circuit 120. The gate clock GCLK is a clock signal typically input to one or more gate driver integrated circuits (GDICs) and controls the shift timing of the scan signal. The gate output enable signal GOE specifies timing information regarding one or more gate driver integrated circuits (GDICs).

[0059] The timing controller 140 outputs various data control signals (including, for example, a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE) to control the data drive circuit 130. The source start pulse SSP controls the timing of data sampling for one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source sampling clock SCLK is a clock signal that controls the timing of the sampled data in the source driver integrated circuits (SDICs). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0060] The display device 100 may also include a power management circuit 150, which provides various voltages or currents to, for example, the display panel 110, the gate driving circuit 120, and the data driving circuit 130, or controls the various voltages or currents to be provided.

[0061] The power management circuit 150 adjusts the DC input voltage Vin provided from the host system 200 to generate the power required to drive the display panel 100, the gate drive circuit 120, and the data drive circuit 130.

[0062] Subpixels SP are positioned at the intersection between gate line GL and data line DL, and light-emitting elements can be disposed in each subpixel SP. For example, an organic light-emitting display can include a light-emitting element (e.g., an organic light-emitting diode) in each subpixel SP, and an image can be displayed by controlling the current flowing to the light-emitting element according to the data voltage.

[0063] The display device 100 can be one of various types of devices, such as a liquid crystal display, an organic light-emitting display, or a plasma display panel.

[0064] Figure 2 A system diagram of a display device according to one embodiment of the present disclosure is shown.

[0065] Reference Figure 2 In one embodiment of the display device 100 according to the present disclosure, the source driver integrated circuit SDIC included in the data driver circuit 130 is implemented as a chip-on-film (COF) type of various types (e.g., TAB, COG, or COF), and the gate driver circuit 120 is implemented as a gate-in-panel (GIP) type of various types (e.g., TAB, COG, COF, or GIP).

[0066] When the gate drive circuit 120 is implemented in a GIP (Gate In-Place) manner, a plurality of gate drive integrated circuits (GDICs) included in the gate drive circuit 120 can be directly formed in the bezel area of ​​the display panel 110. In this case, the gate drive integrated circuits (GDICs) can receive various signals (e.g., clock signals, gate high signals, gate low signals, etc.) required to generate scan signals through gate drive related signal lines disposed in the bezel area.

[0067] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 can each be mounted on the source film SF, and one side of the source film SF can be electrically connected to the display panel 110. Lines for electrically connecting the source driver integrated circuits (SDICs) and the display panel 110 can be provided on the source film SF.

[0068] The display device 100 may include: at least one source printed circuit board (SPCB) for circuit connection between multiple source driver integrated circuits (SDICs) and other devices; and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0069] The other side of the source film SF, on which the source driver integrated circuit SDIC is mounted, can be connected to at least one source printed circuit board SPCB. In other words, one side of the source film SF, on which the source driver integrated circuit SDIC is mounted, can be electrically connected to the display panel 110, while the other side can be electrically connected to the source printed circuit board SPCB.

[0070] The timing controller 140 and the power management circuit 150 can be mounted on a control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gate drive circuit 120. The power management circuit 150 can provide power supply voltage or current to the display panel 110, the data drive circuit 130, and the gate drive circuit 120, and control the provided voltage or current.

[0071] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be circuitally connected via at least one connecting member. The connecting member may include, for example, a flexible printed circuit board (FPC) or a flexible flat cable (FFC). At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0072] The display device 100 may also include a setup board 170 electrically connected to a control printed circuit board (CPCB). In this case, the setup board 170 may also be referred to as a power board. A main power management circuit (M-PMC) 160 for managing the total power of the display device 100 may be provided on the setup board 170. The main power management circuit 160 may interact with the power management circuit 150.

[0073] In the display device 100 configured in this way, a power supply voltage is generated in the setup board 170 and transmitted to the power management circuit 150 in the control printed circuit board CPCB. The power management circuit 150 transmits the power supply voltage required for display driving or feature value sensing to the source printed circuit board SPCB via a flexible printed circuit FPC or a flexible flat cable FFC. The power supply voltage transmitted to the source printed circuit board SPCB is provided to emit light or sense specific sub-pixels SP in the display panel 110 through the source driver integrated circuit SDIC.

[0074] Each of the sub-pixels SP arranged in the display panel 110 of the display device 100 may include a light-emitting element and a circuit element (e.g., a driving transistor) for driving an organic light-emitting diode.

[0075] The type and number of circuit elements constituting each sub-pixel SP can vary depending on the functions and design schemes to be provided.

[0076] Figure 3 A circuit diagram of a sub-pixel circuit of a display device according to one embodiment of the present disclosure is shown.

[0077] Reference Figure 3 In a display device 100 according to one embodiment of the present disclosure, the sub-pixel circuit may include one or more transistors and capacitors, and may have light-emitting elements disposed therein.

[0078] For example, a subpixel circuit may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light-emitting element ED.

[0079] The driving transistor DRT includes a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT can be the gate node. When the switching transistor SWT is turned on, the data voltage Vdata is supplied to this gate node from the data driving circuit 130 through the data line DL.

[0080] The second node N2 of the driving transistor DRT can be electrically connected to the anode electrode of the light-emitting element ED, and can be either the source node or the drain node.

[0081] The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL that provides the driving voltage EVDD to it, and can be a drain node or a source node.

[0082] In this case, during the display driving period, the driving voltage EVDD required to display the image can be supplied to the driving voltage line DVL. For example, the driving voltage EVDD required to display the image can be 27V.

[0083] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and the gate line GL is connected to the gate node. Therefore, the switching transistor SWT is operated according to the first scan signal SCAN1 provided through the gate line GL. When turned on, the switching transistor SWT transmits the data voltage Vdata provided through the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0084] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and the gate line GL is connected to the gate node. The sensing transistor SENT is operated according to the second scan signal SCAN2 provided through the gate line GL. When the sensing transistor SENT is turned on, the reference voltage Vref provided through the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0085] In other words, when the switching transistor SWT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the voltage of the second node N2 of the driving transistor DRT are controlled, thereby providing current for driving the light-emitting element ED.

[0086] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a common gate line GL, or they can be connected to different gate lines GL. An example is shown in which the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL. In this case, the switching transistor SWT and the sensing transistor SENT can be independently controlled by a first scan signal SCAN1 and a second scan signal SCAN2 transmitted through different gate lines GL.

[0087] In contrast, if the switching transistor SWT and the sensing transistor SENT are connected to a gate line GL, the switching transistor SWT and the sensing transistor SENT can be simultaneously controlled by a first scan signal SCAN1 or a second scan signal SCAN2 transmitted through a gate line GL, and the aperture ratio of the sub-pixel SP can be increased.

[0088] The transistors disposed in the sub-pixel circuits can be N-type transistors or P-type transistors, and in the example shown, the transistors are N-type transistors.

[0089] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and holds the data voltage Vdata during one frame.

[0090] Depending on the type of driving transistor DRT, the storage capacitor Cst can also be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode of the light-emitting element ED can be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage EVSS can be provided to the cathode of the light-emitting element ED.

[0091] The base voltage EVSS can be ground voltage or a voltage higher or lower than ground voltage. The base voltage EVSS can vary depending on the drive state. For example, the base voltage EVSS during display drive and the base voltage EVSS during sensing drive can be set to be different from each other.

[0092] The switching transistor SWT and the sensing transistor SENT can be referred to as the scanning transistors controlled by the scanning signals SCAN1 and SCAN2.

[0093] The structure of a subpixel SP may also include one or more transistors, or in some cases, one or more capacitors.

[0094] In this case, in order to effectively sense the characteristic value (e.g., threshold voltage or mobility) of the driving transistor DRT, the display device 100 can use a method for measuring the current flowing from the voltage charged to the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT, which is called current sensing.

[0095] In other words, by measuring the current flowing through the voltage from charging to the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT, the characteristic value or the change in characteristic value of the driving transistor DRT in the sub-pixel SP can be calculated.

[0096] In this case, the reference voltage line RVL is used not only to transmit the reference voltage Vref, but also as a sensing line for sensing the characteristic values ​​of the driving transistor DRT in the sub-pixel. Therefore, the reference voltage line RVL can also be referred to as a sensing line or sensing channel.

[0097] More specifically, the characteristic value or change of characteristic value of the driving transistor DRT can correspond to the difference between the gate node voltage and the source node voltage of the driving transistor DRT.

[0098] Compensation for the characteristic values ​​of the driving transistor DRT can be performed through external compensation or internal compensation. External compensation involves using an external compensation circuit to sense and compensate for the characteristic values ​​of the driving transistor DRT. Internal compensation involves sensing and compensating for the characteristic values ​​of the driving transistor DRT inside the sub-pixel SP without using additional external configuration.

[0099] In this case, external compensation can be performed before the display device 100 leaves the factory, and internal compensation can be performed after the display device 100 leaves the factory. However, even after the display device 100 leaves the factory, internal compensation and external compensation can be performed together.

[0100] Figure 4 An example circuit structure for sensing the characteristic values ​​of a driving transistor is shown.

[0101] Reference Figure 4 The display device 100 may include components for compensating for eigenvalue deviations of the driving transistor DRT.

[0102] For example, during the sensing period of the display device 100, the characteristic value or change in characteristic value of the driving transistor DRT can be provided as the voltage (e.g., Vdata-Vth) of the second node N2 of the driving transistor DRT. When the sensing transistor SENT is in the ON state, the voltage of the second node N2 of the driving transistor DRT can correspond to the voltage of the reference voltage line RVL. The line capacitor Cline on the reference voltage line RVL can be charged by the voltage of the second node N2 of the driving transistor DRT. Due to the sensing voltage Vsen that charges the line capacitor Cline, the reference voltage line RVL can have a voltage corresponding to the voltage of the second node N2 of the driving transistor DRT.

[0103] The display device 100 may include: an analog-to-digital converter (ADC) that measures the voltage of a reference voltage line RVL corresponding to the voltage of the second node N2 of the driving transistor DRT and converts the voltage into a digital value; and switching circuits SAM and SPRE for sensing characteristic values.

[0104] The switching circuits SAM and SPRE used to control the sensing drive may include: a sensing reference switch SPRE, which controls the connection between each reference voltage line RVL and the sensing reference voltage supply node Npres that provides the reference voltage Vref to it; and a sampling switch SAM, which controls the connection between each reference voltage line RVL and the analog-to-digital converter (ADC). The sensing reference switch SPRE is the switch used to control the sensing drive, and the reference voltage Vref supplied to the reference voltage line RVL by the sensing reference switch SPRE becomes the sensing reference voltage VpreS.

[0105] The switching circuit for sensing the characteristic values ​​of the driving transistor DRT may include a display reference switch RPRE for controlling the display drive. The display reference switch RPRE controls the connection between each reference voltage line RVL and the display reference voltage supply node Nprer that provides the reference voltage Vref to it. The display reference switch RPRE is a switch for driving the display, and the reference voltage Vref provided by the display reference switch RPRE to the reference voltage line RVL corresponds to the display reference voltage VpreR.

[0106] In this configuration, the sensing reference switch SPRE and the display reference switch RPRE can be provided separately or integrated into one unit. The sensing reference voltage VpreS and the display reference voltage VpreR can have the same voltage value or different voltage values.

[0107] The timing controller 140 of the display device 100 may include: a memory MEM for storing data transmitted from the analog-to-digital converter (ADC) or pre-stored reference values; and a compensation circuit COMP for comparing the reference values ​​stored in the memory MEM with the received data and compensating for deviations in the characteristic values. In this case, the compensation value calculated by the compensation circuit COMP can be stored in the memory MEM.

[0108] Therefore, the timing controller 140 can compensate the image data DATA to be provided to the data driving circuit 130 using the compensation value calculated by the compensation circuit COMP, and can output the compensated image data DATA_comp to the data driving circuit 130. The data driving circuit 130 can then convert the compensated image data DATA_comp into an analog signal type data voltage Vdata using a digital-to-analog converter (DAC), and output the converted data voltage Vdata to the data line DL via the output buffer BUF. Thus, deviations in the characteristic values ​​of the driving transistor DRT in the corresponding sub-pixel SP (e.g., threshold voltage deviation or mobility deviation) can be compensated.

[0109] As described above, a period for sensing the characteristic values ​​(threshold voltage and mobility) of the driving transistor DRT can be performed after the power-on signal is generated and before the display driving begins. For example, if the power-on signal is provided to the display device 100, the timing controller 140 loads the parameters required to drive the display panel 110 and then drives the display. In this case, the parameters required to drive the display panel 110 may include information about the sensing and compensation of characteristic values ​​previously performed on the display panel 110. During the parameter loading process, the sensing of the characteristic values ​​of the driving transistor DRT can be performed. As described above, the process of sensing characteristic values ​​during the parameter loading process after the power-on signal is generated and before the sub-pixel emits light is called the power-on sensing process.

[0110] Alternatively, the sensing period for the characteristic value of the driving transistor DRT can be performed after a power-off signal is generated in the display device 100. For example, when a power-off signal is generated in the display device 100, the timing controller 140 can cut off the data voltage supplied to the display panel 110 and sense the driving characteristic value of the driving transistor DRT for a predetermined time. Thus, the process of performing characteristic value detection in a state where the data voltage is cut off when a power-off signal is generated, thereby terminating the emission of sub-pixels, is called the disconnect sensing process.

[0111] The sensing period for the characteristic values ​​of the driving transistor DRT can be performed in real time while driving the display. This sensing process is called real-time (RT) sensing. During real-time sensing, sensing processing can be performed on one or more sub-pixel SPs of one or more sub-pixel SP lines during each blank period of the display driving period.

[0112] In other words, during the display driving period when an image is displayed on the display panel 110, there is a blank period in a frame or between the nth and (n+1)th frames during which no data voltage is provided to the sub-pixel SP, during which mobility sensing of one or more sub-pixel SPs can be performed.

[0113] In this way, when performing sensing processing during a blank period, the sub-pixel (SP) line on which sensing processing is performed can be randomly selected. Therefore, after performing sensing processing in the blank period, anomalies that may occur during the display driving period can be mitigated. After performing sensing processing during the blank period, a compensated data voltage can be provided to the sub-pixel SP that has already performed sensing processing during the display driving period. Therefore, anomalies in the sub-pixel SP lines that have completed sensing processing during the display driving period after the sensing processing in the blank period can also be mitigated.

[0114] The data driver circuit 130 may include a data voltage output circuit 136, which includes a latch circuit, a digital-to-analog converter (DAC), and an output buffer (BUF). In some cases, the data driver circuit 130 may also include an analog-to-digital converter (ADC) and various switches (SAM, SPRE, and RPRE). Alternatively, the ADC and the switches (SAM, SPRE, and RPRE) may be located outside the data driver circuit 130.

[0115] The compensation circuit COMP can exist inside or outside the timing controller 140. The memory MEM can be located outside the timing controller 140, or it can be implemented inside the timing controller 140 as a register.

[0116] Figure 5 The signal timing diagram for external compensation of the threshold voltage used to drive the transistor is shown.

[0117] Reference Figure 5 The threshold voltage Vth of the driving transistor DRT in the display device 100 can be sensed during the initialization phase, the tracking phase, and the sampling phase.

[0118] In this case, since the switching transistor SWT and the sensing transistor SENT are simultaneously turned on and off to sense the threshold voltage Vth of the driving transistor DRT, the first scan signal SCAN1 and the second scan signal SCAN2 can be provided together through a single gate line GL, or the first scan signal SCAN1 and the second scan signal SCAN2 can be provided simultaneously through different gate lines GL.

[0119] The initialization phase (INITIAL) is the period during which the second node N2 of the driving transistor DRT is charged with the reference voltage Vref to sense the threshold voltage Vth of the driving transistor DRT, and a first scan signal SCAN1 and a second scan signal SCAN2 with a high level can be provided through the gate line GL.

[0120] The tracking phase is the period after the second node N2 of the driving transistor DRT has finished charging, during which the charge is transferred to the storage capacitor Cst.

[0121] The sampling phase is the period after the storage capacitor Cst of the driving transistor DRT is charged, during which the current flowing from the charge to the storage capacitor Cst is detected.

[0122] If both the first scan signal SCAN1 and the second scan signal SCAN2 are provided at the turn-on level during the initialization phase INITIAL, then the switching transistor SWT is turned on. Therefore, the first node N1 of the driving transistor DRT is initialized to the sensing data voltage Vdata_sen used to sense the threshold voltage Vth.

[0123] The sensing transistor SENT is also turned on by the first scan signal SCAN1 and the second scan signal SCAN2, and a reference voltage Vref is provided through the reference voltage line RVL, so that the second node N2 of the driving transistor DRT is initialized to the reference voltage Vref.

[0124] During the tracking phase, the voltage of the second node N2 of the driving transistor DRT, which reflects the threshold voltage Vth of the driving transistor DRT, is tracked. For this purpose, during the tracking phase, the switching transistor SWT and the sensing transistor SENT can remain on, and the reference voltage Vref provided through the reference voltage line RVL is turned off.

[0125] Therefore, the second node N2 of the driving transistor DRT can float, and the voltage of the second node N2 of the driving transistor DRT begins to rise from the reference voltage Vref. In this case, due to the turn-on of the sensing transistor SENT, the increase in the voltage of the second node N2 of the driving transistor DRT leads to an increase in the voltage of the reference voltage line RVL.

[0126] During this process, the voltage at the second node N2 of the driving transistor DRT increases and then saturates. The saturation voltage at which the second node N2 of the driving transistor DRT reaches saturation can be represented by the difference (Vdata_sen - Vth) between the sensing data voltage Vdata_sen used to sense the threshold voltage Vth and the threshold voltage Vth of the driving transistor DRT.

[0127] During the sampling phase, the high-level first scan signal SCAN1 and second scan signal SCAN2 to the gate line GL are maintained, and the charge charged in the storage capacitor Cst of the driving transistor DRT is sensed by the feature value sensing circuit included in the data driving circuit 130.

[0128] Figure 6 The signal timing diagram for external compensation of the mobility of the driving transistor is shown.

[0129] Reference Figure 6Similar to sensing a threshold voltage Vth, sensing the mobility of the drive transistor DRT in the display device 100 can be performed during the initialization phase, the tracking phase, and the sampling phase.

[0130] During the initialization phase (INITIAL), the switching transistor SWT can be turned on by the first scan signal SCAN1 at an on level, causing the first node N1 of the driving transistor DRT to be initialized to the sensing data voltage Vdata_sen for mobility sensing. Furthermore, the sensing transistor SENT is turned on by the second scan signal SCAN2 at an on level, and in this state, the second node N2 of the driving transistor DRT is initialized to the reference voltage Vref.

[0131] The TRACKING stage is used to track the mobility of the driving transistor DRT. The mobility of the driving transistor DRT can indicate its current driving capability, and the voltage of the second node N2 of the driving transistor DRT, which is used to calculate the mobility of the driving transistor DRT, is tracked through the TRACKING stage.

[0132] During the TRACKING phase, the switching transistor SWT is turned off by the first scan signal SCAN1 at the cutoff level, and the switch providing the reference voltage Vref is also turned off. Therefore, both the first node N1 and the second node N2 of the driving transistor DRT float, and the voltages of both the first node N1 and the second node N2 of the driving transistor DRT increase.

[0133] Specifically, since the voltage of the second node N2 of the driving transistor DRT is initialized to the reference voltage Vref, it begins to increase from the reference voltage Vref. In this case, due to the turn-on of the sensing transistor SENT, the increase in the voltage of the second node N2 of the driving transistor DRT leads to an increase in the voltage of the reference voltage line RVL.

[0134] During the sampling phase, at a predetermined time Δt after the voltage of the second node N2 begins to increase, the eigenvalue sensing circuit detects the voltage of the second node N2 of the driving transistor DRT.

[0135] Here, the case where the sensing data voltage Vdata_sen is provided via the data line DL during the sampling phase has been shown. However, if the data voltage Vdata is continuously provided during the sampling phase, the voltage of the second node N2 of the driving transistor DRT can be changed. Therefore, for stable voltage detection, the black-grayscale data voltage Vdata can be provided via the data line DL during the sampling phase.

[0136] In this case, the sensing voltage indicated by the eigenvalue sensing circuit is the reference voltage Vref plus a predetermined voltage ΔV, and the mobility of the driving transistor DRT can be calculated based on the sensing voltage Vref+ΔV thus detected, the known reference voltage Vref, and the time increment Δt of the voltage of the second node N2.

[0137] In other words, the mobility of the driving transistor DRT is proportional to the voltage change ΔV / Δt per unit time of the reference voltage line RVL through the tracking phase and the sampling phase. Therefore, the mobility of the driving transistor DRT will be proportional to the slope of the voltage waveform of the reference voltage line RVL.

[0138] Figure 7 The signal timing diagram showing the internal compensation for the threshold voltage and mobility of the driving transistor is shown.

[0139] Reference Figure 7 The internal compensation process for the characteristic values ​​of the driving transistor DRT in the display device 100 may include: an initialization phase (INITIAL), a threshold voltage sensing phase (VthSENSING), a mobility compensation phase (u COMPENSATION), and an emission phase (EMISSION).

[0140] During the initialization phase (INITIAL), the sensing transistor SENT is first turned on by the second scan signal SCAN2 with a high level, and the voltage of the second node N2 (i.e., the source node voltage of the driving transistor DRT) is initialized to the reference voltage Vref.

[0141] Subsequently, the switching transistor SWT is turned on by the first scan signal SCAN1 with a high level, and the driving transistor DRT is turned on by the data voltage Vdata provided to the first node N1 (i.e., the gate node of the driving transistor DRT). Then, when the data voltage Vdata drops to the level of the offset voltage Vos, the voltage of the first node N1 becomes the level of the offset voltage Vos.

[0142] During the threshold voltage sensing phase VthSENSING, when the sensing transistor SENT is turned off by the second scan signal SCAN2 provided at a low level, the voltage of the second node N2 of the driving transistor DRT rises to the voltage difference between the offset voltage Vos of the driving transistor DRT and the threshold voltage Vth, and finally charges the storage capacitor Cst to the level of the threshold voltage Vth.

[0143] During the mobility compensation phase u COMPENSATION, the first node N1 rises to the level of the data voltage Vdata by providing the grayscale to be displayed (i.e., the corresponding data voltage Vdata) to the display panel 110. Therefore, according to the mobility characteristics of the driving transistor DRT, the second node N2 is gradually charged, and thus, the difference voltage obtained by subtracting the voltage change ΔV based on the offset voltage Vos and the mobility from the sum of the data voltage Vdata and the threshold voltage Vth is stored in the storage capacitor Cst.

[0144] During the emission phase, the switching transistor SWT is turned off by the first scan signal SCAN1, which is provided with a low level. Therefore, the threshold voltage Vth of the driving transistor DRT and the current compensated by the voltage level stored in the storage capacitor Cst are supplied to the light-emitting element ED.

[0145] Internal or external compensation can be performed after the power-on signal is generated and before the display driving operation begins. For example, when a power-on signal is provided to the display device 100, the timing controller 140 loads the parameters required to drive the display panel 110 and then performs the display driving operation.

[0146] At this point, since the sensing process of the threshold voltage of the driving transistor DRT may take a relatively long time to saturate the voltage at the second node N2 of the driving transistor DRT, the sensing and compensation process of the threshold voltage Vth is mainly performed during the disconnection sensing process. On the other hand, since the sensing process of the mobility of the driving transistor DRT takes a relatively short time compared to the sensing process of the threshold voltage Vth, the sensing and compensation process of the mobility can be performed in real-time sensing processing.

[0147] As described above, the threshold voltage or mobility of the driving transistor DRT constituting the sub-pixel SP can vary depending on the driving time, or can deviate due to the driving time difference of each sub-pixel SP. Therefore, since the brightness of the sub-pixel SP can vary according to the characteristic value of the driving transistor DRT, the characteristic value of the driving transistor DRT can be called the characteristic value of the sub-pixel SP.

[0148] Meanwhile, multiple pixels can be arranged in a specific layout on the display panel 110, and each pixel can be formed by multiple sub-pixels SP that emit different colors.

[0149] However, when sensing the characteristic value of the driving transistor DRT, the voltage of the sensing transistor SENT may change due to variations in the drive current. Because of the voltage deviation of the sensing transistor SENT, the sensed voltage Vsen may have an error relative to the characteristic value of the driving transistor DRT.

[0150] Figure 8 A conceptual diagram is shown illustrating the error in the sensed voltage due to voltage deviation of the sensed transistor during the process of sensing the characteristic value of the drive transistor.

[0151] Reference Figure 8 During the sensing period of the display device 100, the change in the characteristic value of the driving transistor DRT can be reflected as the source node voltage Vs of the driving transistor DRT. In this case, when the sensing transistor SENT is turned on, the source node voltage Vs of the driving transistor DRT can correspond to the voltage of the reference voltage line RVL.

[0152] Additionally, the line capacitor Cline of the reference voltage line RVL can be charged by the source node voltage Vs of the driving transistor DRT, and the sensed voltage Vsen is charged into the line capacitor Cline. The reference voltage line RVL can have a voltage corresponding to the source node voltage Vs of the driving transistor DRT.

[0153] However, during the process of sensing the characteristic value of the driving transistor DRT, the voltage of the sensing transistor SENT and the sensing voltage Vsen charged to the line capacitor Cline can be changed due to the fluctuation of the driving current Id flowing through the driving transistor DRT and the sensing transistor SENT.

[0154] For example, since the sensing transistor SENT is located between the source node of the driving transistor DRT and the reference voltage line RVL, the source node voltage Vs of the driving transistor DRT will be the sum of the sensing voltage Vsen formed in the reference voltage line RVL and the voltage formed in the sensing transistor SENT.

[0155] At this point, the voltage formed in the sensing transistor SENT will be the value obtained by multiplying the resistance Rsent between the source and drain nodes of the sensing transistor SENT by the drive current Id flowing through the sensing transistor SENT. Therefore, the source node voltage Vs of the driving transistor DRT can be expressed as follows.

[0156] Vs=Vsen+Id×Rsent

[0157] At this time, when the voltage Id×Rsent between the source and drain nodes of the sensing transistor SENT changes during the process of sensing the characteristic value of the driving transistor DRT, the sensing voltage Vsen detected by the reference voltage line RVL also changes, making it difficult to accurately measure the characteristic value of the driving transistor DRT.

[0158] Therefore, this disclosure uses a constant current source to detect the resistance Rsent of the sensing transistor SENT before sensing the characteristic value of the driving transistor DRT, and then uses the resistance Rsent of the sensing transistor SENT to accurately measure the characteristic value of the driving transistor DRT.

[0159] Figure 9 An exemplary circuit structure for detecting the resistance of a sensing transistor in a display device, according to one embodiment of the present disclosure, is shown.

[0160] Reference Figure 9 In one embodiment of the present disclosure, the sub-pixel circuit in the display device 100 may include one or more transistors and capacitors, and may have light-emitting elements disposed therein.

[0161] For example, a subpixel circuit may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light-emitting element ED.

[0162] The driving transistor DRT has a gate node corresponding to the first node, a source node corresponding to the second node, and a drain node corresponding to the third node. When the switching transistor SWT is turned on, the data voltage Vdata is supplied to the gate node of the driving transistor DRT through the data line DL.

[0163] The source node of the driving transistor DRT can be electrically connected to the anode electrode of the light-emitting element ED.

[0164] The drain node of the driving transistor DRT can be electrically connected to the driving voltage line DVL, and the driving voltage EVDD is applied to the driving voltage line DVL.

[0165] In this case, during the display driving period, the driving voltage EVDD required to display the image can be supplied to the driving voltage line DVL. For example, the driving voltage EVDD required to display the image can be 27V.

[0166] The switching transistor SWT is electrically connected between the gate node of the driving transistor DRT and the data line DL, and operates according to the first scan signal SCAN1 provided through the gate line GL. When turned on, the switching transistor SWT transmits the data voltage Vdata provided through the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0167] The sensing transistor SENT is electrically connected between the source node of the driving transistor DRT and the reference voltage line RVL, and operates according to the second scan signal SCAN2 provided via the gate line GL. When the sensing transistor SENT is turned on, the reference voltage Vref provided via the reference voltage line RVL is transmitted to the source node of the driving transistor DRT.

[0168] In other words, when the switching transistor SWT and the sensing transistor SENT are controlled, the gate node voltage Vg and the source node voltage Vs of the driving transistor DRT are controlled, thereby providing current for driving the light-emitting element ED.

[0169] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a common gate line GL, or they can be connected to different gate lines GL. An example is shown in which the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL. In this case, the switching transistor SWT and the sensing transistor SENT can be independently controlled by a first scan signal SCAN1 and a second scan signal SCAN2 transmitted through different gate lines GL.

[0170] In contrast, if the switching transistor SWT and the sensing transistor SENT are connected to a gate line GL, the switching transistor SWT and the sensing transistor SENT can be simultaneously controlled by a first scan signal SCAN1 or a second scan signal SCAN2 transmitted through a gate line GL, and the aperture ratio of the sub-pixel SP can be increased.

[0171] The transistors disposed in the sub-pixel circuits can be N-type transistors or P-type transistors, and in the example shown, the transistors are N-type transistors.

[0172] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and holds the data voltage Vdata during one frame.

[0173] Depending on the type of driving transistor DRT, the storage capacitor Cst can also be connected between the gate node and the drain node of the driving transistor DRT. The anode electrode of the light-emitting element ED can be electrically connected to the source node of the driving transistor DRT, and the base voltage EVSS can be provided to the cathode electrode of the light-emitting element ED.

[0174] The base voltage EVSS can be ground voltage or a voltage higher or lower than ground voltage. The base voltage EVSS can vary depending on the drive state. For example, the base voltage EVSS during display drive and the base voltage EVSS during sensing drive can be set to be different from each other.

[0175] The structure of a subpixel SP may also include one or more transistors, or in some cases, one or more capacitors.

[0176] In this case, in order to effectively sense the characteristic value (e.g., threshold voltage or mobility) of the driving transistor DRT, the display device 100 can use a method for measuring the current flowing from the voltage charged to the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT, which is called current sensing.

[0177] In other words, by measuring the current flowing through the voltage from charging to the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT, the characteristic value or the change in characteristic value of the driving transistor DRT in the sub-pixel SP can be calculated.

[0178] In this case, the reference voltage line RVL is used not only to transmit the reference voltage Vref, but also as a sensing line for sensing the characteristic values ​​of the driving transistor DRT in the sub-pixel. Therefore, the reference voltage line RVL can also be referred to as a sensing line or sensing channel.

[0179] More specifically, the characteristic value or change of characteristic value of the driving transistor DRT can correspond to the difference between the gate node voltage and the source node voltage of the driving transistor DRT.

[0180] In this structure, the display device 100 according to one embodiment of the present disclosure detects the resistance Rsent of the sensing transistor SENT in advance before sensing the characteristic value of the driving transistor DRT, so as to accurately sense the characteristic value of the driving transistor DRT.

[0181] For the purposes described above, a constant current source Isource is arranged in the display device 100 of this disclosure, and the display device 100 can detect the resistance Rsent of the sensing transistor SENT by using a constant current Is flowing through the sub-pixel circuit before sensing the characteristic value of the driving transistor DRT.

[0182] The constant current source Isource can be set in the data drive circuit 130, and the reference voltage line RVL can be electrically connected to the constant current source Isource through the operation of the constant current switch SWI.

[0183] In other words, the display device 100 of this disclosure can provide a resistance sensing period for detecting the resistance Rsent of the sensing transistor SENT before sensing the characteristic value of the driving transistor DRT. During the resistance sensing period, with a constant current Is flowing to the sub-pixel circuit through a constant current source Isource, the resistance Rsent of the sensing transistor SENT can be calculated by detecting the change in the sensing voltage Vsen formed on the reference voltage line RVL while changing the data voltage Vdata supplied to the sub-pixel circuit.

[0184] The detailed method for calculating the resistance Rsent of the sensing transistor SENT is as follows.

[0185] First, the current Ids flowing from the drain node to the source node of the driving transistor DRT can be determined by the mobility u, gate-source voltage Vgs, threshold voltage Vth, and drain-source voltage Vds of the driving transistor DRT, as shown in the following formula.

[0186]

[0187] Using the above, the resistance Rdrt between the drain node and the source node of the driving transistor DRT can be calculated as follows.

[0188]

[0189] During this period, a constant current Is is supplied to the sub-pixel circuit via a constant current source Isource, such that the current flowing through the sensing transistor SENT and the driving transistor DRT is the same as the constant current Is. For the above purposes, preferably, the driving voltage EVDD supplied during the resistance sensing period is maintained at a value lower than the turn-on level of the light-emitting element ED to prevent current from flowing through the light-emitting element ED during the resistance sensing period.

[0190] Therefore, the voltage formed between the drain node of the driving transistor DRT, which provides the driving voltage EVDD, and the reference voltage line RVL is the sum of the drain-source voltage of the driving transistor DRT and the drain-source voltage of the sensing transistor SENT.

[0191]

[0192] The formula above can be expressed as follows.

[0193]

[0194] Meanwhile, when a first-level data voltage Vdata1 and a second-level data voltage Vdata2, which are different from each other, are provided during the resistance sensing period, the gate-source voltage Vgs and drain-source voltage Vds of the driving transistor DRT, as well as the sensing voltage Vsen formed on the reference voltage line RVL, will be changed.

[0195] Figure 10 An exemplary signal waveform diagram is shown in a display device according to one embodiment of the present disclosure when a first level data voltage and a second level data voltage that are different from each other are provided during a resistance sensing period.

[0196] Reference Figure 10 Even when providing different first-level data voltages Vdata1 and second-level data voltages Vdata2 during the resistance sensing period ( Figure 10 In case (a), the constant current Is flowing through the sub-pixel circuit is supplied by a constant current source Isource in a display device 100 according to an embodiment of the present disclosure. Figure 10 (b) remains constant.

[0197] Meanwhile, the formulas would be as follows if different first-level data voltages Vdata1 and second-level data voltages Vdata2 were provided during the resistance sensing period.

[0198]

[0199]

[0200] At this point, when the data voltages Vdata1 and Vdata2 are set to a level higher than the reference level of the drive voltage EVDD, the gate-source voltages Vgs1 and Vgs2 of the drive transistor DRT become greater than the drain-source voltages Vds1 and Vds2. In this case, since the drain-source voltage Vds can be ignored, the above formula has a linear relationship. For example, when the gate-source voltages Vgs1 and Vgs2 of the drive transistor DRT are greater than 5 times the drain-source voltages Vds1 and Vds2, the drain-source voltage Vds can be ignored.

[0201] In addition, the gate-source voltages Vgs1 and Vgs2 of the driving transistor DRT can be calculated as follows.

[0202] Vgs1=Vdata1-(IsRsent+Vsen1) (Formula 7)

[0203] Vgs2=Vdata2-(IsRsent+Vsen2) (Formula 8)

[0204] Here, the threshold voltage Vth of the driving transistor DRT can be measured during the threshold voltage sensing process, or the threshold voltage Vth of the driving transistor DRT can be used as a predetermined value during the manufacturing process of the display device 100.

[0205] Therefore, the resistance Rsent between the drain and source nodes of the sensing transistor SENT can be calculated by providing different first-level data voltages Vdata1 and second-level data voltages Vdata2 during the resistance sensing period, and by using the changes in the gate-source voltages Vgs1 and Vgs2 of the driving transistor DRT and the sensing voltages Vsen1 and Vsen2 of the reference voltage line RVL for each case.

[0206] When calculating the resistance Rsent of the sensing transistor SENT, the mobility u and resistance Rdrt of the driving transistor DRT can also be calculated.

[0207] The mobility u of the driving transistor DRT can be determined by subtracting the drain-source voltage of the sensing transistor SENT from the sensing voltage Vsen detected during the mobility sensing process. The mobility u of the driving transistor DRT can also be calculated by applying the resistance Rsent of the sensing transistor SENT to the above formula.

[0208] In addition, when the mobility u of the driving transistor DRT is determined, the resistance Rdrt of the driving transistor DRT can be calculated using the above formula 2.

[0209] Therefore, since the display device 100 of this disclosure can accurately calculate the characteristic value of the driving transistor DRT by using the resistance Rsent of the sensing transistor SENT, the resistance Rsent of the sensing transistor SENT can be used to compensate for the deviation of the characteristic value of the driving transistor DRT.

[0210] Figure 11 An exemplary circuit structure is shown in a display device according to one embodiment of the present disclosure, in which the resistance of a sensing transistor is used to compensate for the characteristic value deviation of a driving transistor.

[0211] Reference Figure 11 According to one embodiment of the present disclosure, the display device 100 may include components for compensating for characteristic value deviations of the driving transistor DRT.

[0212] For example, during the sensing period of the display device 100, the characteristic value or change of the characteristic value of the driving transistor DRT can be provided as the voltage of the second node N2 of the driving transistor DRT. When the sensing transistor SENT is in the ON state, the voltage of the second node N2 of the driving transistor DRT can correspond to the voltage of the reference voltage line RVL.

[0213] The line capacitor Cline on the reference voltage line RVL can be charged by the voltage of the second node N2 of the driving transistor DRT. Due to the sensed voltage Vsen for charging the line capacitor Cline, the reference voltage line RVL can have a voltage corresponding to the voltage of the second node N2 of the driving transistor DRT.

[0214] In this structure, the characteristic value of the driving transistor DRT can be sensed more accurately by pre-detecting the resistance Rsent of the sensing transistor SENT before sensing the characteristic value of the driving transistor DRT.

[0215] For the purposes described above, the display device 100 may include: an analog-to-digital converter (ADC) that measures the voltage of a reference voltage line RVL and converts the voltage into a digital value; and a switching circuit SAM and a switching circuit SPRE that are used to sense characteristic values.

[0216] Additionally, the display device 100 of this disclosure may include: a constant current source Isource, which provides a constant current Is to the sub-pixel circuit to calculate the resistance Rsent of the sensing transistor SENT; and a constant current switch SWI, which controls the provision of the constant current Is.

[0217] The switching circuits SAM and SPRE used to control the sense drive may include a sense reference switch SPRE, which controls the connection between each reference voltage line RVL and the sense reference voltage supply node Npres that provides the reference voltage Vref to it; and a sampling switch SAM, which controls the connection between each reference voltage line RVL and the analog-to-digital converter ADC. The sense reference switch SPRE is the switch used to control the sense drive, and the reference voltage Vref supplied by the sense reference switch SPRE to the reference voltage line RVL becomes the sense reference voltage VpreS.

[0218] The switching circuit for sensing characteristic values ​​of the driving transistor DRT may include a display reference switch RPRE for controlling the display drive. The display reference switch RPRE controls the connection between each reference voltage line RVL and the display reference voltage supply node Nprer that provides the reference voltage Vref to it. The display reference switch RPRE is the switch for driving the display, and the reference voltage Vref provided by the display reference switch RPRE to the reference voltage line RVL corresponds to the display reference voltage VpreR.

[0219] Additionally, the switching circuit of the display device 100 may include a constant current switch SWI for controlling the supply of a constant current Is to the sub-pixel circuit. The constant current switch SWI can control the connection between the constant current source Isource and the reference voltage line RVL.

[0220] The constant current switch SWI provides a constant current Is to the sub-pixel circuit by turning it on before the start of the sensing period for sensing the characteristic value of the driving transistor DRT. Therefore, a resistance sensing period can be performed to detect the resistance Rsent of the sensing transistor SENT. The resistance Rsent of the sensing transistor SENT can be detected by detecting the level of the sensing voltage Vsen, which is varied by providing a data voltage Vdata at multiple levels during the resistance sensing period.

[0221] In this case, the sensing reference switch SPRE, the display reference switch RPRE, and the constant current switch SWI can be provided individually or integrated into one.

[0222] The timing controller 140 of the display device 100 may include: a memory MEM for storing data transmitted from the analog-to-digital converter (ADC) or pre-stored reference values; and a compensation circuit COMP for comparing the reference values ​​stored in the memory MEM with the received data and compensating for deviations in the characteristic values. In this case, the compensation value calculated by the compensation circuit COMP can be stored in the memory MEM.

[0223] Therefore, the timing controller 140 can compensate the image data DATA to be provided to the data drive circuit 130 by using the compensation value calculated by the compensation circuit COMP, and can provide the compensated image data DATA_comp to the data drive circuit 130.

[0224] Therefore, the data driving circuit 130 can convert the compensated image data DATA_comp into an analog signal type data voltage Vdata via a digital-to-analog converter (DAC), and provide the converted data voltage Vdata to the data line DL via an output buffer (BUF). Thus, deviations in the characteristic values ​​of the driving transistor DRT in the corresponding sub-pixel SP (e.g., threshold voltage deviation or mobility deviation) can be compensated.

[0225] As described above, the display device 100 of this disclosure can more accurately sense the characteristic value of the driving transistor DRT by pre-detecting the resistance Rsent of the sensing transistor SENT before sensing the characteristic value of the driving transistor DRT. Therefore, the timing controller 140 can provide compensated image data DATA_comp that can accurately compensate for the characteristic value deviation of the driving transistor DRT.

[0226] The data driving circuit 130 may include a data voltage output circuit 136, which includes a latch circuit, a digital-to-analog converter (DAC), and an output buffer (BUF). In some cases, the ADC and various switches (SAM, SPRE, RPRE, SWI) may be located outside the data driving circuit 130.

[0227] The compensation circuit COMP can exist inside or outside the timing controller 140. The memory MEM can be located outside the timing controller 140, or it can be implemented inside the timing controller 140 as a register.

[0228] Figure 12 A signal timing diagram is shown in a display device according to one embodiment of the present disclosure, which uses the resistance of a sensing transistor to compensate for the mobility of a driving transistor.

[0229] Reference Figure 12 According to one embodiment of the present disclosure, the display device 100 may include a resistance sensing period R SENSING for detecting the resistance Rsent of the sensing transistor SENT and a characteristic value determination period of the driving transistor DRT.

[0230] During the resistance sensing period R SENSING, the switching transistor SWT is turned on by the first scan signal SCAN1 at the on level, while a constant current Is is provided to the sub-pixel circuit, and the sensing transistor SENT is turned on by the second scan signal SCAN2 at the on level.

[0231] In this state, the resistance Rsent between the drain and source nodes of the sensing transistor SENT can be calculated by providing data voltages Vdata1 and Vdata2 with different levels during the resistance sensing period R SENSING, and detecting the changes in the sensing voltages Vsen1 and Vsen2 on the reference voltage line RVL for each case.

[0232] In this case, it can be determined that the levels of data voltages Vdata1 and Vdata2 are higher than the driving voltage EVDD by a certain level or more. Therefore, since the gate-source voltages Vgs1 and Vgs2 of the driving transistor DRT are greater than the drain-source voltages Vds1 and Vds2, the resistance Rsent of the sensing transistor SENT can be easily calculated using a linear relationship.

[0233] In addition, in order to prevent current from flowing in the light-emitting element ED during the resistance sensing period R SENSING, it is preferable to keep the level of the driving voltage EVDD provided during the resistance sensing period R SENSING below the on-level of the light-emitting element ED.

[0234] The mobility sensing process of the driving transistor DRT can be performed in the initialization phase, the tracking phase, and the sampling phase.

[0235] During the initialization phase (INITIAL), the switching transistor SWT can be turned on by the first scan signal SCAN1 at an on level, causing the first node N1 of the driving transistor DRT to be initialized to the sensing data voltage Vdata_sen for mobility sensing. Furthermore, the sensing transistor SENT is turned on by the second scan signal SCAN2 at an on level, and in this state, the second node N2 of the driving transistor DRT is initialized to the reference voltage Vref.

[0236] The TRACKING stage is used to track the mobility of the driving transistor DRT. The mobility of the driving transistor DRT can indicate its current driving capability, and the voltage of the second node N2 of the driving transistor DRT, which is used to calculate the mobility of the driving transistor DRT, is tracked through the TRACKING stage.

[0237] During the TRACKING phase, the switching transistor SWT is turned off by the first scan signal SCAN1 at the cutoff level, and the switch providing the reference voltage Vref is also turned off. Therefore, both the first node N1 and the second node N2 of the driving transistor DRT float, and the voltages of both the first node N1 and the second node N2 of the driving transistor DRT increase.

[0238] Specifically, since the voltage of the second node N2 of the driving transistor DRT is initialized to the reference voltage Vref, it begins to increase from the reference voltage Vref. In this case, due to the turn-on of the sensing transistor SENT, the increase in the voltage of the second node N2 of the driving transistor DRT leads to an increase in the voltage of the reference voltage line RVL.

[0239] During the sampling phase, at a predetermined time Δt after the voltage of the second node N2 begins to increase, the eigenvalue sensing circuit detects the voltage of the second node N2 of the driving transistor DRT.

[0240] In this case, the sensing voltage indicated by the eigenvalue sensing circuit is the reference voltage Vref plus a predetermined voltage ΔV, and the mobility of the driving transistor DRT can be calculated based on the sensing voltage Vref+ΔV thus detected, the known reference voltage Vref, and the time increment Δt of the voltage of the second node N2.

[0241] In other words, the mobility of the driving transistor DRT is proportional to the voltage change ΔV / Δt per unit time of the reference voltage line RVL through the tracking phase and the sampling phase. Therefore, the mobility of the driving transistor DRT will be proportional to the slope of the voltage waveform of the reference voltage line RVL.

[0242] At this point, the mobility of the driving transistor DRT can be determined more accurately by applying the resistance Rsent of the sensing transistor SENT detected during the resistance sensing period R SENSING.

[0243] The above text has explained how to determine the mobility of the driving transistor DRT by using the resistance Rsent of the sensing transistor SENT. However, the threshold voltage of the driving transistor DRT can be calculated by using the resistance Rsent of the sensing transistor SENT.

[0244] Figure 13 A flowchart of a display driving method according to one embodiment of the present disclosure is shown.

[0245] Reference Figure 13 A display driving method according to one embodiment of the present disclosure may include: step S100, setting a resistance sensing period R SENSING for detecting the resistance Rsent of the sensing transistor SENT; step S200, providing a constant current Is to the sub-pixel circuit through a constant current source Isource during the resistance sensing period R SENSING; step S300, detecting a change in the sensing voltage Vsen on the reference voltage line RVL while changing the data voltage Vdata; step S400, calculating the resistance Rsent of the sensing transistor SENT; step S500, determining the characteristic value of the driving transistor DRT; and step S600, providing compensated image data DATA_comp by reflecting the characteristic value of the driving transistor DRT.

[0246] Step S100, which sets the resistance sensing period RSENSING for sensing the sensing transistor SENT, is a process of setting the resistance sensing period RSENSING for sensing the sensing transistor SENT before sensing the characteristic value of the driving transistor DRT.

[0247] Step S200, which involves providing a constant current Is to the sub-pixel circuit via a constant current source Isource during the resistance sensing period R SENSING, is a process of allowing a constant current Is to flow through the sub-pixel circuit via the constant current source Isource during the resistance sensing period R SENSING. The display device 100 of this disclosure may include a constant current source Isource disposed in the data driving circuit 130 and uses the constant current Is flowing through the sub-pixel circuit to detect the resistance Rsent of the sensing transistor SENT during the resistance sensing period R SENSING.

[0248] Step S300, which detects the change of the sensing voltage Vsen on the reference voltage line RVL while changing the data voltage Vdata, is a process in which a constant current Is flows through the constant current source Isource through the sub-pixel circuit during the resistance sensing period R SENSING, and the change of the sensing voltage Vsen on the reference voltage line RVL is detected while the data voltage Vdata supplied to the sub-pixel circuit is changed.

[0249] When different first-level data voltages Vdata1 and second-level data voltages Vdata2 are provided during the resistance sensing period R SENSING, the gate-source voltages Vgs1 and Vgs2 of the driving transistor DRT and the sensed voltages Vsen1 and Vsen2 on the reference voltage line RVL change in each case. During the resistance sensing period R SENSING, the resistance Rsent of the sensing transistor SENT is calculated based on the change in the sensed voltage Vsen according to the data voltage Vdata.

[0250] At this point, it is determined that the levels of the data voltages Vdata1 and Vdata2 provided during the resistance sensing period R SENSING are higher than the drive voltage EVDD by a certain level or more, so that the resistance Rsent of the sensing transistor SENT can be easily calculated.

[0251] In addition, it is preferable to keep the driving voltage EVDD level lower than the turn-on level of the light-emitting element ED so that current does not flow through the light-emitting element ED during the resistance sensing period R SENSING.

[0252] The step S400 of calculating the resistance Rsent of the sensing transistor SENT is a process of calculating the resistance Rsent of the sensing transistor SENT by using the change of the sensing voltage Vsen based on the change of the data voltage Vdata during the resistance sensing period R SENSING.

[0253] At this point, the resistance Rsent of the sensing transistor SENT can be calculated using the following formula.

[0254]

[0255] At this point, EVDD is the driving voltage, Vsen is the sensing voltage detected by the reference voltage line RVL, Vgs is the gate-source voltage of the driving transistor DRT, Vth is the threshold voltage of the driving transistor DRT, Vds is the drain-source voltage of the driving transistor DRT, u is the mobility of the driving transistor DRT, Is is the constant current flowing through the sub-pixel circuit, and Rsent is the resistance of the sensing transistor SENT.

[0256] Step S500, which determines the characteristic value of the driving transistor DRT, is a process of determining the characteristic value of the driving transistor DRT using the resistance Rsent of the sensing transistor SENT.

[0257] In this case, the characteristic value of the driving transistor DRT can be determined by using the formula for calculating the resistance Rsent of the sensing transistor SENT, or by applying the resistance Rsent of the sensing transistor SENT to the sensing voltage Vsen detected by the reference voltage line RVL during the characteristic value sensing process.

[0258] Step S600, which provides compensated image data DATA_comp by reflecting the characteristic value of the driving transistor DRT, is the processing by which the timing controller 140 determines the compensated image data DATA_comp by reflecting the characteristic value of the driving transistor DRT and provides the compensated image data DATA_comp to the data driving circuit 130.

[0259] Through the above process, the display device 100 of this disclosure can use the resistance Rsent of the sensing transistor SENT to accurately determine the characteristic value of the driving transistor DRT and accurately compensate for the characteristic value deviation.

[0260] A brief description of the implementation methods of the present disclosure described above is as follows.

[0261] A display device 100 according to one embodiment of the present disclosure may include: a display panel 110, in which a plurality of sub-pixel circuits are disposed, each of the plurality of sub-pixel circuits including a light-emitting element ED, a driving transistor DRT, and a sensing transistor SENT; a gate driving circuit 120 configured to provide a plurality of scan signals SCAN to the display panel 110 through a plurality of gate lines GL; a data driving circuit 130 configured to provide a plurality of data voltages Vdata to the display panel 110 through a plurality of data lines DL during a resistance sensing period R SENSING, and to provide a constant current Is to the plurality of sub-pixel circuits; and a timing controller 140 configured to control the gate driving circuit 120 and the data driving circuit 130. Compensated image data DATA_comp is provided to the display panel 110 by using the resistance Rsent of the sensing transistor SENT detected during the resistance sensing period R SENSING.

[0262] The subpixel circuit may include: a driving transistor DRT configured to supply current to a light-emitting element ED; a switching transistor SWT electrically connected between the gate node of the driving transistor DRT and a data line DL; a sensing transistor SENT electrically connected between the source node or drain node of the driving transistor DRT and a reference voltage line RVL; and a storage capacitor Cst electrically connected between the gate node of the driving transistor DRT and the source node or drain node of the sensing transistor SENT.

[0263] The data driving circuit 130 may include: an analog-to-digital converter (ADC) configured to convert a sensed voltage Vsen detected from a reference voltage line RVL into a digital value; a sampling switch (SAM) configured to control the connection between the reference voltage line RVL and the ADC; a constant current source (Isource) configured to provide a constant current Is to a plurality of sub-pixel circuits during the resistance sensing period R SENSING; and a constant current switch (SWI) configured to control the connection between the constant current source (Isource) and the reference voltage line RVL.

[0264] During the resistance sensing period R SENSING, the level of the drive voltage EVDD supplied to the drive transistor DRT can be lower than the turn-on level of the light-emitting element ED.

[0265] The level of the data voltage Vdata provided during the resistance sensing period R SENSING can be higher than the level of the drive voltage EVDD.

[0266] The level of the data voltage Vdata can be determined such that the gate-source voltage of the driving transistor DRT is at least 5 times the drain-source voltage of the driving transistor DRT.

[0267] The resistance Rsent of the sensing transistor can be calculated using the first sensing voltage Vsen1 and the second sensing voltage Vsen2 of the reference voltage line RVL, which are detected by the first level data voltage Vdata1 and the second level data voltage Vdata2 provided during the resistance sensing period R SENSING.

[0268] The resistance Rsent of the sensing transistor can be calculated using the following formula.

[0269]

[0270] Where EVDD is the driving voltage, Vsen is the sensing voltage, Vgs is the gate-source voltage of the driving transistor, Vth is the threshold voltage of the driving transistor, Vds is the drain-source voltage of the driving transistor, u is the mobility of the driving transistor, Is is the constant current flowing through the sub-pixel circuit, and Rsent is the resistance of the sensing transistor.

[0271] The timing controller 140 can be configured to calculate the mobility of the drive transistor DRT based on the resistance Rsent of the sensing transistor using the formula described above.

[0272] The timing controller 140 can be configured to determine the compensated image data DATA_comp by reflecting the resistance Rsent of the sensing transistor to the characteristic value of the driving transistor DRT determined in the characteristic value determination period after the resistance sensing period R SENSING.

[0273] According to one embodiment of the present disclosure, a data driving circuit 130 for providing multiple data voltages Vdata to a display panel 110, wherein the display panel 110 is provided with multiple sub-pixel circuits, each of the multiple sub-pixel circuits including a light-emitting element ED, a driving transistor DRT, and a sensing transistor SENT, the data driving circuit 130 may include: an analog-to-digital converter ADC configured to convert a sensed voltage Vsen detected from a reference voltage line RVL into a digital value; a sampling switch SAM configured to control the connection between the reference voltage line RVL and the analog-to-digital converter ADC; a constant current source Isource configured to provide a constant current Is to the multiple sub-pixel circuits during a resistance sensing period R SENSING; and a constant current switch SWI configured to control the connection between the constant current source Isource and the reference voltage line RVL.

[0274] The resistance Rsent of the sensing transistor can be calculated using the first sensing voltage Vsen1 and the second sensing voltage Vsen2 of the reference voltage line RVL, which are detected by the first level data voltage Vdata1 and the second level data voltage Vdata2 provided during the resistance sensing period R SENSING.

[0275] A display driving method for a display panel 110 according to one embodiment of the present disclosure includes a plurality of sub-pixel circuits disposed in the display panel 110, each of the plurality of sub-pixel circuits including a light-emitting element ED, a driving transistor DRT, and a sensing transistor SENT. The display driving method for the display panel 110 may include: setting a resistance sensing period R SENSING for detecting the resistance Rsent of the sensing transistor; providing a constant current Is to the plurality of sub-pixel circuits through a constant current source Isource during the resistance sensing period R SENSING; detecting a change in the sensing voltage Vsen on a reference voltage line RVL while changing the data voltage Vdata; calculating the resistance Rsent of the sensing transistor; determining a characteristic value of the driving transistor DRT using the resistance Rsent of the sensing transistor; and providing compensated image data DATA_comp by reflecting the characteristic value of the driving transistor DRT.

[0276] The resistance sensing period R SENSING can be performed before the characteristic value determination period of the driving transistor DRT.

[0277] The foregoing description has been presented to enable any person skilled in the art to make and use the technical concepts of the invention, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and figures provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the invention should be understood based on the appended claims, and all technical concepts within the scope of their equivalents should be understood to be included within the scope of the invention.

Claims

1. A display device, comprising: A display panel is provided in which a plurality of sub-pixel circuits are provided, each of the plurality of sub-pixel circuits including a light-emitting element, a driving transistor and a sensing transistor; A gate driving circuit is configured to provide multiple scan signals to the display panel through multiple gate lines; A data driving circuit is configured to provide multiple data voltages to the display panel via multiple data lines during the resistance sensing period and to provide a constant current to the multiple sub-pixel circuits for detecting the resistance of the sensing transistors; as well as A timing controller is configured to control the gate drive circuit and the data drive circuit, and to provide compensated image data to the display panel by using the resistance of the sensing transistor detected during the resistance sensing period.

2. The display device according to claim 1, wherein, The sub-pixel circuit includes: The driving transistor is configured to provide current to the light-emitting element; A switching transistor, which is electrically connected between the gate node of the driving transistor and the data line; The sensing transistor is electrically connected between the source or drain node of the driving transistor and the reference voltage line; and A storage capacitor is electrically connected between the gate node of the driving transistor and the source node or drain node of the sensing transistor.

3. The display device according to claim 1, wherein, The data driving circuit includes: An analog-to-digital converter, configured to convert a sensed voltage detected from a reference voltage line into a digital value; A sampling switch configured to control the connection between the reference voltage line and the analog-to-digital converter; A constant current source, configured to provide a constant current to the plurality of sub-pixel circuits during the resistance sensing period; and A constant current switch is configured to control the connection between the constant current source and the reference voltage line.

4. The display device according to claim 1, wherein, During the resistance sensing period, the level of the driving voltage supplied to the driving transistor is lower than the turn-on level of the light-emitting element.

5. The display device according to claim 4, wherein, The level of the data voltage provided during the resistance sensing period is higher than the level of the drive voltage.

6. The display device according to claim 5, wherein, The level of the data voltage is determined such that the gate-source voltage of the driving transistor is at least 5 times the drain-source voltage of the driving transistor.

7. The display device according to claim 1, wherein, The resistance of the sensing transistor is calculated using a first sensing voltage and a second sensing voltage detected by a reference voltage line through a first level data voltage and a second level data voltage provided during the resistance sensing period.

8. The display device according to claim 7, wherein, The resistance of the sensing transistor is calculated using the following formula: Wherein, EVDD is the driving voltage, Vsen is the sensing voltage, Vgs is the gate-source voltage of the driving transistor, Vth is the threshold voltage of the driving transistor, Vds is the drain-source voltage of the driving transistor, u is the mobility of the driving transistor, Is is the constant current flowing through the sub-pixel circuit, and Rsent is the resistance of the sensing transistor.

9. The display device according to claim 8, wherein, The timing controller is configured to calculate the mobility of the driving transistor based on the resistance of the sensing transistor using the formula.

10. The display device according to claim 1, wherein, The timing controller is configured to determine the compensated image data by reflecting the resistance of the sensing transistor onto the characteristic value of the driving transistor determined during a characteristic value determination period following the resistance sensing period.

11. A data driving circuit for providing multiple data voltages to a display panel, wherein a plurality of sub-pixel circuits are disposed in the display panel, each of the plurality of sub-pixel circuits including a light-emitting element, a driving transistor, and a sensing transistor, the data driving circuit comprising: An analog-to-digital converter, configured to convert a sensed voltage detected from a reference voltage line into a digital value; A sampling switch configured to control the connection between the reference voltage line and the analog-to-digital converter; A constant current source is configured to provide a constant current to the plurality of sub-pixel circuits for detecting the resistance of the sensing transistor during the resistance sensing period; as well as A constant current switch is configured to control the connection between the constant current source and the reference voltage line.

12. The data driving circuit according to claim 11, wherein, The resistance of the sensing transistor is calculated using a first sensing voltage and a second sensing voltage of the reference voltage line detected by a first level data voltage and a second level data voltage provided during the resistance sensing period.

13. A display driving method for a display panel, wherein a plurality of sub-pixel circuits are disposed in the display panel, each of the plurality of sub-pixel circuits including a light-emitting element, a driving transistor, and a sensing transistor, the display driving method comprising: Set a resistance sensing period for detecting the resistance of the sensing transistor; During the resistance sensing period, a constant current is supplied to the plurality of sub-pixel circuits via a constant current source; The change in the sensed voltage on the reference voltage line is detected while the data voltage is changed; Calculate the resistance of the sensing transistor; The characteristic value of the driving transistor is determined using the resistance of the sensing transistor; as well as Compensated image data is provided by reflecting the characteristic values ​​of the driving transistor.

14. The display driving method according to claim 13, wherein, The resistance sensing period is executed before the characteristic value determination period of the driving transistor.

15. The display driving method according to claim 13, wherein, During the resistance sensing period, the level of the driving voltage supplied to the driving transistor is lower than the turn-on level of the light-emitting element.

16. The display driving method according to claim 13, wherein, The level of the data voltage provided during the resistance sensing period is higher than the level of the drive voltage.

17. The display driving method according to claim 16, wherein, The level of the data voltage is determined such that the gate-source voltage of the driving transistor is at least 5 times the drain-source voltage of the driving transistor.

18. The display driving method according to claim 13, wherein, The resistance of the sensing transistor is calculated using the following formula: Wherein, EVDD is the driving voltage, Vsen is the sensing voltage, Vgs is the gate-source voltage of the driving transistor, Vth is the threshold voltage of the driving transistor, Vds is the drain-source voltage of the driving transistor, u is the mobility of the driving transistor, Is is the constant current flowing through the sub-pixel circuit, and Rsent is the resistance of the sensing transistor.

19. The display driving method according to claim 18, wherein, The characteristic value of the driving transistor is the mobility of the driving transistor based on the resistance of the sensing transistor using the formula.

20. The display driving method according to claim 13, wherein, The compensated image data is determined by reflecting the resistance of the sensing transistor onto the characteristic value of the driving transistor determined during a characteristic value determination period following the resistance sensing period.

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