Display device

Abstract

A display apparatus includes a circuit substrate, and a pixel array on the circuit substrate and including a plurality of pixels. The pixel array includes light emitting diode (LED) cells constituting the plurality of pixels, each of the LED cells including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, a wavelength converter on the LED cells, an upper semiconductor layer on the LED cells and having a partition structure, a passivation layer on side surfaces of the LED cells, a first electrode along areas of the LED cells to have a lattice shape, a second electrode connected to the second conductive type semiconductor layer, and a reflective layer between the first electrode and the second electrode along the passivation layer on the side surfaces of the LED cells and having a surface inclined toward an outside of the LED cells.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2022-0000823 filed on January 4, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a display device. Background Art

[0004] Semiconductor light emitting diodes (LEDs) can be used not only as light sources for light-emitting devices but also as light sources for various electronic products. Specifically, LEDs can be widely used as light sources for various display devices such as televisions (TVs), mobile phones, personal computers (PCs), laptop PCs, personal digital assistants (PDAs), etc.

[0005] A display device may include a display panel including a liquid crystal display (LCD) panel and a backlight. However, recently, display devices that use LEDs as pixels and thus do not use an additional backlight have been developed. Compared to LCDs, such display devices can be made compact and can achieve high brightness with improved optical efficiency. Summary of the Invention

[0006] According to an embodiment, a display device includes: a circuit substrate including a driving circuit and a first bonding electrode; and a pixel array located on the circuit substrate and including light-emitting diode (LED) units constituting a plurality of pixels and a second bonding electrode bonded to the first bonding electrode. Each of the LED units includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer stacked sequentially. The pixel array also includes: a wavelength converter located on the LED unit; an upper semiconductor layer located on the LED unit and having a partition structure that surrounds the side surface of the wavelength converter and separates the wavelength converters from each other; a passivation layer located on the side surface of the LED unit and having an outer surface inclined to increase thickness in a direction toward the wavelength converter; a first electrode located on the outer surface of the passivation layer and extending to an area between the LED units; a second electrode located on the lower surface of the LED unit and connected to the second conductive type semiconductor layer; a common electrode located on at least one side of the LED unit; and a pad electrode located outside the LED unit.

[0007] According to an embodiment, a display device includes: a circuit substrate including a driving circuit; and a pixel array located on the circuit substrate and including a plurality of pixels. The pixel array includes: light-emitting diode (LED) units constituting a plurality of pixels, each of the LED units including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer stacked sequentially; a wavelength converter located on the LED units; an upper semiconductor layer located on the LED units and having a partition structure that surrounds the side surfaces of the wavelength converters and separates the wavelength converters from each other; a passivation layer located on the side surfaces of the LED units and extending to a portion of the lower surface of the LED units; a first electrode having a grid shape along the area of ​​the LED units; a second electrode connected to the second conductive type semiconductor layer; and a reflective layer located between the first and second electrodes along the passivation layer located on the side surfaces of the LED units and having a surface inclined toward the outside of the LED units.

[0008] According to an embodiment, a display device includes: a circuit substrate including a driving circuit and a first bonding electrode; and a pixel array located on the circuit substrate and including light-emitting diode (LED) units constituting a plurality of pixels, each of the LED units including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer stacked sequentially. The pixel array includes: a wavelength converter located on the LED unit; a passivation layer located on a side surface of the LED unit and having an outer surface inclined to increase in thickness toward the wavelength converter; a first electrode having an inclined surface in contact with the passivation layer; a second electrode connected to the second conductive type semiconductor layer; a common electrode located on at least one side of the LED unit; and a second bonding electrode bonded to the first bonding electrode. The first electrode is disposed in an area between adjacent LED units so as not to vertically overlap the LED units and is electrically connected to a portion of the second bonding electrode outside the LED units via the common electrode. Each of the second electrodes is disposed below a lower surface of each of the LED units so as to vertically overlap the LED units and is directly connected to a portion of the second bonding electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become more apparent to those skilled in the art by describing example embodiments in detail with reference to the accompanying drawings, in which:

[0010] Figure 1A and Figure 1B are respectively a schematic perspective view and a schematic plan view of a display apparatus according to an example embodiment.

[0011] Figure 2A and Figure 2B are respectively a schematic cross-sectional view and a partially enlarged view of a display device according to example embodiments.

[0012] Figure 3 is a schematic plan view of electrodes of a display device according to example embodiments.

[0013] Figure 4 is a plan view of a driving circuit implemented in a display device according to example embodiments.

[0014] Figures 5A to 5C is a schematic partially enlarged view of a display device according to example embodiments.

[0015] Figure 6A and Figure 6B are respectively a schematic cross-sectional view and a partially enlarged view of a display device according to example embodiments.

[0016] Figure 7A and Figure 7B are respectively a schematic cross-sectional view and a partially enlarged view of a display device according to example embodiments.

[0017] Figure 8 is a schematic partially enlarged view of a display device according to example embodiments.

[0018] Figures 9A to 9Q are cross-sectional views of stages in a method of manufacturing a display device according to example embodiments.

[0019] Figure 10 is a conceptual diagram of an electronic device including a display device according to example embodiments. DETAILED DESCRIPTION

[0020] In the following description, unless the context indicates otherwise, terms such as "upper", "upper part", "upper surface", "lower", "lower part", "lower surface", "side surface" and the like are used with reference to the accompanying drawings, and these terms may change according to the direction in which the device is set.

[0021] Figure 1A and Figure 1B are respectively a schematic perspective view and a schematic plan view of a display apparatus according to an example embodiment. Figure 1B yes Figure 1A An enlarged plan view of portion "A" of FIG.

[0022] Reference Figure 1A and Figure 1B The display device 10 may include a circuit substrate 200 including a driving circuit and a pixel array 100 disposed on the circuit substrate 200 and including a plurality of pixels PX arranged therein. The display device 10 may include a frame 11 surrounding the circuit substrate 200 and the pixel array 100.

[0023] The circuit substrate 200 may be a driving circuit substrate including a thin film transistor (TFT) unit. In some example embodiments, the circuit substrate 200 may include only a portion of the driving circuit for the display device. In this case, the display device 10 may include a driving device including another portion of the driving circuit. In some example embodiments, for example, the circuit substrate 200 may be a flexible substrate to implement a display device that can have a curved profile.

[0024] The pixel array 100 may be an LED module for display, and may include a connection pad PAD, a connection region CR connecting a plurality of pixels PX and the connection pad PAD to each other, and an edge region ISO.

[0025] Each of the plurality of pixels PX may include first to third subpixels SP1, SP2, and SP3 configured to emit light of different specific wavelengths (e.g., specific colors) to provide a color image. For example, the first to third subpixels SP1, SP2, and SP3 may be configured to emit blue (B) light, green (G) light, and red (R) light, respectively. In each of the pixels PX, the first to third subpixels SP1, SP2, and SP3 may be arranged in, for example, a diamond pentagonal arrangement.

[0026] For example, each of the pixels PX may include a first subpixel SP1 and a second subpixel SP2 in a first column, and a second subpixel SP2 and a third subpixel SP3 in a second column, arranged in a first diagonal direction (e.g., direction D1). The first column and the second column may be arranged in a second diagonal direction (e.g., direction D2) perpendicular to the D1 direction. In each of the pixels PX, the first to third subpixels SP1, SP2, and SP3 may be arranged in a diamond shape. For example, the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the second subpixel SP2 may be arranged in a clockwise order. The pixels PX may be arranged sequentially in the directions D1 and D2.

[0027] exist Figure 1B , each of the pixels PX is illustrated as including four arranged first to third sub-pixels SP1 , SP2 , and SP3 , but the number of sub-pixels constituting each pixel PX may be changed.

[0028] As will be described in detail below, the upper semiconductor layer 111 (see also Figure 2A ) may be disposed between the first to third sub-pixels SP1, SP2, and SP3.

[0029] Reference Figure 1BIn the directions D1 and D2, the first to third sub-pixels SP1, SP2, and SP3 may be arranged at a pitch of a first length L1. The first length L1 may be in a range of about 1.5 μm to about 2.0 μm.

[0030] Each of the first to third sub-pixels SP1, SP2, and SP3 may have a second length L2 in the directions D1 and D2. The second length L2 may be in the range of about 0.7 μm to about 1.3 μm.

[0031] In some example embodiments, the first to third subpixels SP1, SP2, and SP3 may be arranged in a Bayer pattern. In some example embodiments, some subpixels may be configured to emit light having colors other than R, G, and B shown (eg, yellow light).

[0032] exist Figure 1A In the pixel array 100 , the number of the plurality of pixels PX arranged may be any appropriate number, for example, 1024×768.

[0033] The connection pads PAD may be provided on at least one side of the plurality of pixels PX along an edge of the display device 10. The connection pads PAD may be electrically connected to the plurality of pixels PX and the driving circuit of the circuit substrate 200. The connection pads PAD may electrically connect an external device and the display device 10 to each other. The number of connection pads PAD may vary according to example embodiments and may be determined according to, for example, the number of pixels PX, a driving method of the TFT circuit in the circuit substrate 200, and the like.

[0034] The connection region CR may be provided between the plurality of pixels PX and the connection pad PAD. An interconnection structure (eg, a common electrode) electrically connected to the plurality of pixels PX may be provided in the connection region CR.

[0035] The edge area ISO may be an area extending along the edge of the pixel array 100. Figure 2A As described, the edge area ISO may be an area in which the upper semiconductor layer 111 is not disposed.

[0036] The frame 11 may be provided around the pixel array 100 to serve as a guide for defining a space in which the pixel array 100 is provided. The frame 11 may include, for example, at least one of a polymer, a ceramic, a semiconductor, and a metal. The frame 11 may be configured as a black matrix. The frame 11 may be configured as a white matrix or a structure having different colors depending on the purpose of the display device 10. For example, the white matrix may include a reflective material or a light scattering material.

[0037] Although the display device 10 is illustrated as having a rectangular planar structure in FIG. 1, the display device 10 can have a different shape according to example embodiments.

[0038] Figure 2A and Figure 2B are a schematic cross-sectional view and a partial enlarged view of a display device according to example embodiments, respectively. Figure 2A illustrates a cross-sectional view taken along Figure 1A and a cross-sectional view taken along Figure 1B of FIG. 1. Figure 2B is an enlarged view of a portion "B" of Figure 2A

[0039] Figure 3 is a schematic plan view of an electrode of a display device according to example embodiments. Figure 3 illustrates a region corresponding to a portion "A" of Figure 1A

[0040] Referring to Figure 2A and Figure 2B , the display device 10 can include a circuit substrate 200 and a pixel array 100 disposed on the circuit substrate 200.

[0041] The circuit substrate 200 can include a semiconductor substrate 201, a drive circuit including a drive element 220 disposed on the semiconductor substrate 201 and including a TFT unit, a contact plug 230 electrically connected to the drive element 220, a circuit interconnection line 240 on the contact plug 230, and a circuit insulating layer 290 covering the drive circuit. The circuit substrate 200 can include a through electrode 250 (such as a through silicon via (TSV)) connected to the drive circuit, a first substrate interconnection line 261 and a second substrate interconnection line 262 connected to the through electrode 250, a first bonding insulating layer 295 on the circuit insulating layer 290, and a first bonding electrode 298 disposed in the first bonding insulating layer 295 and connected to the circuit interconnection line 240.

[0042] The semiconductor substrate 201 can include an impurity region including a source / drain region 205. The semiconductor substrate 201 can include, for example, a semiconductor such as silicon (Si) or germanium (Ge) or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP.

[0043] ​​The driving circuit may include a circuit for controlling the driving of a pixel or sub-pixel. The source region 205 of the TFT unit may be electrically connected to the electrode of the LED unit 110 through the contact plug 230, the circuit interconnection line 240, and the first bonding electrode 298. The drain region 205 of the TFT unit may be connected to the first substrate interconnection line 261 through the through electrode 250, and the first substrate interconnection line 261 may be electrically connected to the data line. The gate electrode of the TFT unit may be connected to the second substrate interconnection line 262 through the through electrode 250, etc., and the second substrate interconnection line 262 may be electrically connected to the gate line. Figure 4 Such circuit configuration and operation are described in more detail.

[0044] The upper surface of the first bonding electrode 298 and the upper surface of the first bonding insulating layer 295 may constitute the upper surface of the circuit substrate 200. The first bonding electrode 298 may be bonded to the second bonding electrode 198 of the pixel array 100 to provide an electrical connection path. The first bonding electrode 298 may include a conductive material such as copper (Cu). The first bonding insulating layer 295 may be bonded to the second bonding insulating layer 195 of the pixel array 100. The first bonding insulating layer 295 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0045] The pixel array 100 may include an upper semiconductor layer 111, an LED unit 110 on a lower surface of the upper semiconductor layer 111, a first passivation layer 122 covering a side surface of the LED unit 110, a second passivation layer 124 covering a lower surface and a side surface of the first passivation layer 122, a first electrode 130 and a second electrode 150 electrically connected to the LED unit 110, wavelength converters 160B, 160G and 160R on the LED unit 110, color filters 180G and 180R, and a microlens 185. The pixel array 100 may include a contact layer 155 on the lower surface of the LED unit 110, a separation reflective layer 170 surrounding the side surfaces and lower surfaces of the wavelength converters 160B, 160G and 160R, an encapsulation layer 182 and a planarization layer 184 on the wavelength converters 160B, 160G and 160R, a common electrode 145, a first pad electrode 147, an interconnect insulation layer 190, a second bonding insulation layer 195, a second bonding electrode 198, and a second pad electrode 199.

[0046] An upper semiconductor layer 111 may be provided on the LED unit 110. In the pixel PX, the upper semiconductor layer 111 may have a partition structure that surrounds the side surfaces of the wavelength converters 160B, 160G, and 160R and separates the wavelength converters 160B, 160G, and 160R from each other. Due to the partition structure of the upper semiconductor layer 111, light emitted from the LED unit 110 can be emitted through the wavelength converters 160B, 160G, and 160R without interfering with each other.

[0047] The upper semiconductor layer 111 may have a side surface between the wavelength converters 160B, 160G, and 160R that is perpendicular to the lower surface of the LED unit 110 or inclined relative to the lower surface of the LED unit 110. For example, the upper semiconductor layer 111 may have an inclined side surface between the wavelength converters 160B, 160G, and 160R so that the width of the upper portion is narrower than the width of the lower portion.

[0048] The upper semiconductor layer 111 may be provided to extend in the connection region CR to form a continuous layer rather than a separate structure, and may extend on the common electrode 145. The upper semiconductor layer 111 may be provided in the connection pad PAD to have a configuration in which at least a portion is removed, and may not be provided in the edge region ISO.

[0049] The upper semiconductor layer 111 may include a region that is integrated or continuous with the first conductive type semiconductor layer 112 of the LED unit 110. The upper semiconductor layer 111 may be a layer grown during the growth process of the LED unit 110. For example, the upper semiconductor layer 111 may include a material that is the same as the material of the first conductive type semiconductor layer 112 in at least a region adjacent to the first conductive type semiconductor layer 112. The upper semiconductor layer 111 may include an undoped layer and a doped layer. The upper semiconductor layer 111 may include an epitaxial nitride semiconductor layer. The interface between the upper semiconductor layer 111 and the first conductive type semiconductor layer 112 may not be distinguished. However, the upper semiconductor layer 111 and the first conductive type semiconductor layer 112 may be substantially distinguished and identified by the position of the lower surface of the separation reflective layer 170.

[0050] The LED units 110 may constitute each of the plurality of pixels PX and may each constitute a micro-LED. The LED units 110 may be arranged in rows and columns. The LED units 110 (e.g., each of the LED units 110) may generate blue light (e.g., light having a wavelength of 435 nm to 460 nm). Each of the LED units 110 may include a first conductive type semiconductor layer 112, an active layer 114, and a second conductive type semiconductor layer 116 sequentially stacked on the lower surface of the upper semiconductor layer 111.

[0051] The first conductive type semiconductor layer 112 may extend from the upper region of the pixel PX to a portion of the connection region CR and the connection pad PAD along the upper semiconductor layer 111. The first conductive type semiconductor layer 112 may be connected to each other through the upper regions between the first to third sub-pixels SP1, SP2, and SP3 to be provided as one layer (e.g., a single layer), and may also be connected between the pixels PX to be provided as a single layer. The thickness T1 of each of the upper regions of the first conductive type semiconductor layer 112 may be, for example, in the range of about 0.1 μm to about 1.0 μm.

[0052] The active layer 114 and the second conductive type semiconductor layer 116 may be provided only in the pixel PX, and may be provided between the LED units 110 to be separated and spaced apart from each other.

[0053] Although the first conductive type semiconductor layer 112 is provided between the LED units 110 to be connected to each other in the exemplary embodiment, each of the LED units 110 may be individually defined by the side surface of the active layer 114 and the side surface of the second conductive type semiconductor layer 116. Hereinafter, the first conductive type semiconductor layers 112 of the LED units 110 may be described as being connected to each other.

[0054] The first conductive type semiconductor layer 112, the active layer 114, and the second conductive type semiconductor layer 116 may be formed of nitride semiconductors and may be epitaxial layers. x Al y Ga 1-x-y N-type and P-type nitride semiconductor layers composed of N (0≤x<1, 0≤y<1, 0≤x+y<1). For example, the first conductive type semiconductor layer 112 may be an N-type gallium nitride (n-GaN) layer doped with silicon (Si), germanium (Ge) or carbon (C), and the second conductive type semiconductor layer 116 may be a P-type gallium nitride (p-GaN) layer doped with magnesium (Mg) or zinc (Zn). In some example embodiments, in addition to nitride semiconductors, the first conductive type semiconductor layer 112 and the second conductive type semiconductor layer 116 may be formed of a semiconductor based on aluminum indium gallium phosphide (AlInGaP) or a semiconductor based on aluminum indium gallium arsenide (AlInGaAs). Each of the first conductive type semiconductor layer 112 and the second conductive type semiconductor layer 116 may be formed as a single layer, or may include multiple layers with different characteristics (e.g., doping concentration, composition, etc.).

[0055] The active layer 114 can emit light having a predetermined energy through recombination of electrons and holes. The active layer 114 can have a single quantum well (SQW) structure or a multiple quantum well (MQW) structure in which quantum well layers and quantum barrier layers are alternately disposed with each other. The quantum well layers and the quantum barrier layers can be In x Al y Ga 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1) layers. For example, the quantum well layers can be In x Ga 1-x N (0 < x ≤ 1) layers, and the quantum barrier layers can be GaN layers or AlGaN layers.

[0056] Referring to Figure 2B , in each of the LED units 110, an angle θ1 between a lower surface and a side surface thereof can be a right angle or an angle close to a right angle. For example, the angle θ1 can be in a range of about 85 degrees to about 95 degrees. As will be described below with reference to Figure 9C , the LED units 110 can have such a structure by sequentially performing a dry etching process and a wet etching process.

[0057] The first passivation layer 122 and the second passivation layer 124 can cover at least some portions of the lower surface as well as the side surface of the LED unit 110, and can extend to the connection region CR and the connection pad PAD. Herein, the second passivation layer 124 can be referred to as a "passivation layer", and the first passivation layer 122 can be referred to as an "upper passivation layer".

[0058] The first passivation layer 122 can have a substantially uniform thickness, and can extend conformally. Accordingly, the first passivation layer 122 can have an outer side surface on the side surface of the LED unit 110 that is substantially perpendicular to the lower surface of the LED unit 110. The first passivation layer 122 can be disposed to cover the lower surface of the first conductive type semiconductor layer 112 in the connection region CR and the connection pad PAD. In an example embodiment, the first passivation layer 122 can not extend to the edge region ISO.

[0059] The second passivation layer 124 can cover the outer side surface of the first passivation layer 122 on the side surface of the LED unit 110, and can extend along the first passivation layer 122. The second passivation layer 124 can extend along the first passivation layer 122 on a portion of the lower surface of the LED unit 110. The second passivation layer 124 can extend to the connection region CR and the connection pad PAD, and can also extend to the edge region ISO.

[0060] Referring to Figure 2B, the second passivation layer 124 may have a non-uniform thickness. For example, the second passivation layer 124 may have an outer surface that is inclined to increase in thickness in a direction toward the wavelength converters 160B, 160G, and 160R. The outer surface may be a surface facing the outside of the LED unit 110. On one side of the LED unit 110, the second passivation layer 124 may have a fourth thickness T4 on its upper end and a fifth thickness T5 on its lower end that is less than the fourth thickness T4. The thickness of the second passivation layer 124 may be in a range of approximately 20 nm to approximately 500 nm. For example, the fourth thickness T4 may be in a range of approximately 100 nm to approximately 500 nm, and the fifth thickness T5 may be in a range of approximately 20 nm to approximately 40 nm. In some example embodiments, the thickness of the second passivation layer 124 may be determined taking into account the distance between the LED units 110 and the slope of the second passivation layer 124.

[0061] The angle θ2 at which the outer surface of the second passivation layer 124 is inclined in the vertical direction may be in a range of about 10 degrees to about 50 degrees relative to the vertical direction. In some example embodiments, the angle θ2 may be determined in consideration of light extraction efficiency of the LED units 110, the distance between the LED units 110, the thickness of the second passivation layer 124, and the like.

[0062] The first passivation layer 122 and the second passivation layer 124 may include different materials. The first passivation layer 122 and the second passivation layer 124 may include a light-transmitting insulating material. For example, the first passivation layer 122 may include a metal oxide, and the second passivation layer 124 may include a semiconductor oxide. For example, the second passivation layer 124 may include at least one of SiO2, SiN, SiCN, SiOC, SiON, and SiOCN, and, in addition to the semiconductor oxide, the first passivation layer 122 may include hafnium oxide (HfO2) and / or aluminum oxide (Al2O3) in the region in contact with the second passivation layer 124. In example embodiments, the first passivation layer 122 may have a multilayer structure.

[0063] The first electrode 130 may be connected to the first conductive type semiconductor layer 112. The first electrode 130 may be provided on a side surface of the LED unit 110, spaced apart from the LED unit 110 by the first passivation layer 122 and the second passivation layer 124, and may extend toward the outside of the LED unit 110. The first electrode 130 may be provided on the second passivation layer 124 with a substantially uniform thickness to have inclined inner and outer surfaces formed by the inclined outer surface of the second passivation layer 124. The inner and outer surfaces of the first electrode 130 may be inclined toward the outside of the LED unit 110. The first electrode 130 may have an inclination angle that is the same as or similar to the inclination angle of the second passivation layer 124. When the first electrode 130 has an inclined side surface as described above, light emitted from the active layer 114 may be reflected upward with high efficiency.

[0064] In the first electrode 130, a region having such an inclined side surface may be referred to as a reflective region RL or a reflective layer separated from a contact region contacting the first conductive type semiconductor layer 112. The reflective region RL may be located between the contact regions of the first electrode 130 and the second electrode 150 along the second passivation layer 124 or the inclined outer surface of the second passivation layer 124. In some example embodiments, in the first electrode 130, the reflective region RL and other regions may include different materials or may be formed in different processes so that they may have boundaries separated from each other and may be connected to each other.

[0065] The first electrode 130 may extend toward the outside of the LED unit 110 and may be connected in a region between adjacent LED units 110 to be provided as a single layer. The first electrode 130 may have a shape extending from one side surface of one LED unit 110 to the opposite side surface of an adjacent LED unit 110. The first electrode 130 may be provided to have an inverted U-shape or an inverted V-shape between adjacent LED units 110.

[0066] Reference Figure 3 , the first electrode 130 may include lines extending in the direction D1 and the direction D2 along the region between the pixels PX and between the first to third sub-pixels SP1, SP2, and SP3. The lines may extend along the boundary of the LED unit 110 and may have a shape surrounding each of the contact layers 155. The first electrode 130 may have a grid shape or a mesh shape in which the lines are connected to each other. In the first electrode 130, the outermost lines provided on the outermost sides of the lines may be connected to the outermost lines such as Figure 2A The common electrode 145 is shown in FIG.

[0067] The first electrode 130 may be electrically connected to the first conductive type semiconductor layer 112 in the region between the LED cells 110. For example, the region where the first electrode 130 contacts the first conductive type semiconductor layer 112 may overlap with the partition structure of the upper semiconductor layer 111. In example embodiments, the first electrode 130 may be disposed so as not to overlap with the LED cells 110 (specifically, the active layer 114 and the second conductive type semiconductor layer 116) in the vertical direction. In example embodiments, the first electrode 130 may be disposed so as not to overlap with the wavelength converters 160B, 160G, and 160R in the vertical direction. The first electrode 130 may extend to the outermost portion of the pixel PX and may be connected to the first conductive type semiconductor layer 112 in the connection region CR, and may be physically and electrically connected to the common electrode 145. In some example embodiments, the first electrode 130 in the region between the LED cells 110 may be spaced apart from the first conductive type semiconductor layer 112 by the first passivation layer 122 and the second passivation layer 124.

[0068] The first electrode 130 may include a reflective metal, for example, at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au). In some example embodiments, the first electrode 130 may be formed of a single layer or a multilayer structure of a conductive material.

[0069] The contact layer 155 and the second electrode 150 may be sequentially arranged on the lower surface of the second conductive type semiconductor layer 116 and may be connected to the second conductive type semiconductor layer 116. The contact layer 155 may be provided to cover, for example, the entire lower surface of the second conductive type semiconductor layer 116. The second electrode 150 may be provided to overlap with the LED unit 110 below each of the LED units 110 in the vertical direction. The second electrode 150 may be provided below the contact layer 155 to be connected to the contact layer 155. In example embodiments, the length of the second electrode 150 in one direction may be the same as or similar to the length of the LED unit 110. In some example embodiments, the second electrode 150 may be omitted. In this case, the contact layer 155 may be directly connected to the second bonding electrode 198 below.

[0070] The contact layer 155 and the second electrode 150 may include a highly reflective metal, for example, at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au).

[0071] Wavelength converters 160B, 160G, and 160R may be provided on the LED unit 110. Each of the wavelength converters 160R, 160G, and 160B may be a region in which a wavelength conversion material (e.g., quantum dots) dispersed in a cured binder resin is filled in the partition structure of the upper semiconductor layer 111. The second wavelength converter 160G and the third wavelength converter 160R may include quantum dots for converting blue light into green light and red light, respectively, and the first wavelength converter 160B may include only a binder resin without quantum dots to form a transparent resin portion. In an exemplary embodiment, the wavelength converters 160B, 160G, and 160R may have a shape in which the side surfaces are inclined so that the width of the upper portion is greater than the width of the lower portion.

[0072] The separation reflective layer 170 may be provided to surround the side surfaces and lower surface of the wavelength converters 160R, 160G, and 160B in the separation structure of the upper semiconductor layer 111. The separation reflective layer 170 may extend on the upper surface of the upper semiconductor layer 111 between the wavelength converters 160B, 160G, and 160R. Each of the separation reflective layers 170 may include a first separation insulating layer 172, a separation metal layer 174, and a second separation insulating layer 176 sequentially provided from the bottom. The separation metal layer 174 may be provided only on the side surfaces of the wavelength converters 160R, 160G, and 160B and on the upper surface of the upper semiconductor layer 111, and may not be provided below the lower surface of the wavelength converters 160R, 160G, and 160B. The lower surface of the separation reflective layer 170 may be provided at a level higher than the level of the uppermost surface of the first electrode 130. The first and second separation insulating layers 172 and 176 may include an insulating material, for example, at least one of SiO2, SiN, SiCN, SiOC, SiON, and SiOCN. The separation metal layer 174 may include a reflective metal, for example, at least one of silver (Ag), nickel (Ni), and aluminum (Al).

[0073] The encapsulation layer 182 may be provided to cover the upper surfaces of the wavelength converters 160R, 160G, and 160B and the upper surface of the separation reflective layer 170. The encapsulation layer 182 may serve as a protective layer to prevent degradation of the wavelength converters 160R, 160G, and 160B. In some example embodiments, the encapsulation layer 182 may be omitted.

[0074] Color filters 180R and 180G may be disposed on the second wavelength converter 160G and the third wavelength converter 160R in the second subpixel SP2 and the third subpixel SP3, respectively. The color filters 180R and 180G may improve the color purity of light emitted through the second wavelength converter 160G and the third wavelength converter 160R. In some example embodiments, a color filter may also be disposed on the first wavelength converter 160B.

[0075] A planarization layer 184 may be provided to cover upper surfaces of the color filters 180G and 180R and the encapsulation layer 182. The planarization layer 184 may be a transparent layer.

[0076] Microlenses 185 may be provided on planarization layer 184 to correspond to wavelength converters 160R, 160G, and 160B, respectively. Microlenses 185 may collect light incident from wavelength converters 160R, 160G, and 160B. Microlenses 185 may have a diameter in one direction greater than the width of each of LED units 110. Microlenses 185 may be formed of, for example, a transparent photoresist material or a transparent thermosetting resin.

[0077] The common electrode 145 and the first pad electrode 147 may be arranged in the connection region CR and the connection pad PAD, respectively. The common electrode 145 may be provided on the lower surface of the first electrode 130 extending from the pixel PX to connect the first electrode 130 to the second bonding electrode 198. The common electrode 145, together with the first electrode 130, may constitute a common electrode structure on the outer side of the LED unit 110. The common electrode 145 may be provided with a rectangular ring shape or a ring shape to completely surround the pixel PX in a plan view, and may be connected to the end of the first electrode 130. The arrangement of the common electrode 145 may vary according to example embodiments. For example, in some embodiments, the common electrode 145 may have a partial shape of a square ring or a partial shape of a ring to surround a portion of the pixel PX in a plan view. The first pad electrode 147 may be provided below the second pad electrode 199 in the connection pad PAD to connect the second pad electrode 199 and the second bonding electrode 198 to each other. The common electrode 145 and the first pad electrode 147 may include at least one conductive material, for example, silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), or gold (Au).

[0078] The second pad electrode 199 may be provided on the first pad electrode 147 in the connection pad PAD. The second pad electrode 199 may be provided so that at least its upper surface is exposed in an upward direction (e.g., exposed by an opening penetrating the upper semiconductor layer 111 and the first conductive type semiconductor layer 112). The second pad electrode 199 may be connected to an external device (e.g., an external circuit for applying an electrical signal to the circuit substrate 200, etc.) by wire bonding or anisotropic conductive film (AFC) bonding. The second pad electrode 199 may electrically connect the driving circuit of the circuit substrate 200 and the external device. The second pad electrode 199 may include a metal (e.g., gold (Au), silver (Ag), nickel (Ni), etc.).

[0079] The second bonding electrode 198 can connect the second electrode 150, the common electrode 145, and the first pad electrode 147 to the first bonding electrode 298 of the circuit substrate 200. The second bonding electrode 198 can be connected to the second electrode 150 below the second electrode 150 in the pixel PX, can be connected to the common electrode 145 in the connection region CR, and can be connected to the first pad electrode 147 in the connection pad PAD. Among the second bonding electrodes 198, the second bonding electrode 198 connected to the second electrode 150 can have a second thickness T2 or a second height, and the second bonding electrode 198 connected to the common electrode 145 and the first pad electrode 147 can have a third thickness T3 or a third height greater than the second thickness T2. The first electrode 130 can be connected to the second bonding electrode 198 through the common electrode 145, and the second electrode 150 can be directly connected to the second bonding electrode 198.

[0080] The second bonding electrode 198 may be provided to penetrate the interconnection insulating layer 190 and the second bonding insulating layer 195. The second bonding electrode 198 may have a columnar shape (e.g., a cylindrical shape, etc.). According to example embodiments, the second bonding electrode 198 may have a sidewall that is inclined so that the size of its upper surface is smaller than the size of its lower surface. The second bonding electrode 198 may include, for example, copper (Cu). The second bonding electrode 198 may include a barrier metal layer (e.g., a tantalum (Ta) layer) and / or a tantalum nitride (TaN) layer on its upper surface and side surfaces.

[0081] The interconnection insulating layer 190, together with the second bonding insulating layer 195, may be disposed below the LED unit 110 and the upper semiconductor layer 111. The interconnection insulating layer 190 may include silicon oxide or a silicon oxide-based insulating material (e.g., tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluoride silicate glass (FSG), spin-on glass (SOG), Tonen silazane (TOSZ), or a combination thereof).

[0082] The lower surface of the second bonding insulating layer 195 can be provided together with the lower surface of the second bonding electrode 198 to constitute the lower surface of the pixel array 100. The second bonding insulating layer 195 can form a dielectric-to-dielectric bond with the first bonding insulating layer 295. The circuit substrate 200 and the pixel array 100 can be bonded by bonding the first bonding electrode 298 and the second bonding electrode 198 and by bonding the first bonding insulating layer 295 and the second bonding insulating layer 195. The bonding of the first bonding electrode 298 and the second bonding electrode 198 can be, for example, a copper (Cu) to copper (Cu) bond, and the bonding of the first bonding insulating layer 295 and the second bonding insulating layer 195 can be, for example, a dielectric to dielectric bond (such as SiCN to SiCN bond). The circuit substrate 200 and the pixel array 100 can be bonded by a hybrid bond including a copper (Cu) to copper (Cu) bond and a dielectric to dielectric bond, and can be bonded without an adhesive layer.

[0083] The display device 10 according to the present embodiment can optimize the arrangement of the electrode structure including the first electrode 130 , and can bond the circuit substrate 200 and the pixel array 100 using hybrid bonding to implement a miniaturized high-resolution device.

[0084] Figure 4 is a plan view of a driving circuit implemented in a display device according to example embodiments.

[0085] Reference Figure 4 , shows a circuit diagram of a display device 10 in which n×n sub-pixels are arranged. The first to third sub-pixels SP1, SP2, and SP3 can transmit data signals through data lines D1 to Dn, which can be respectively arranged as paths in the vertical direction (e.g., column direction). The first to third sub-pixels SP1, SP2, and SP3 can transmit control signals (e.g., gate signals) through gate lines G1 to Gn, which can be respectively arranged as paths in the horizontal direction (e.g., row direction).

[0086] The plurality of pixels PX including the first to third sub-pixels SP1, SP2, and SP3 may provide an active area DA for display, and the active area DA may be set as a display area for a user. A non-active area NA may be formed along at least one edge of the active area DA. The non-active area NA may extend along a peripheral portion of the panel of the display device 10, may be an area in which no pixels PX exist, and may correspond to the frame 11 of the display device 10 (see FIG. Figure 1A ).

[0087] The first driver circuit 12 and the second driver circuit 13 may be used to control the operation of the pixel PX (eg, the first to third sub-pixels SP1, SP2, and SP3). Some or all of the first driver circuit 12 and the second driver circuit 13 may be on the circuit substrate 200 (see FIG. Figure 1A ). The first driver circuit 12 and the second driver circuit 13 may be formed by an integrated circuit, a thin film transistor panel circuit, or other suitable circuits, and may be provided in the non-active area NA of the display device 10. The first driver circuit 12 and the second driver circuit 13 may include, for example, a microprocessor, a memory such as a storage unit, a processing circuit, and a communication circuit.

[0088] In order to display an image using the pixel PX, the first driver circuit 12 can send a clock signal or other control signal to the second driver circuit 13 (e.g., a gate driver circuit) while supplying image data to the data lines D1 to Dn. The second driver circuit 13 can be implemented using an integrated circuit and / or a thin film transistor circuit. The gate signals for controlling the first to third sub-pixels SP1, SP2, and SP3 arranged in the row direction can be sent via the gate lines G1 to Gn of the display device 10.

[0089] Figures 5A to 5C is a schematic partially enlarged view of a display device according to an example embodiment. Figures 5A to 5C Shown with Figure 2A The area "B" corresponds to the area.

[0090] Reference Figure 5A In the display device 10a, the first reflective electrode 130a may be provided to fill the space between the first passivation layer 122 and the second passivation layer 124 between the LED units 110. Specifically, the first reflective electrode 130a may be provided without Figure 2B Although the first reflective electrode 130a may be formed to a conformal, substantially uniform thickness as in the exemplary embodiment, it may be configured to be relatively thick to fill the spaces between the LED units 110. Furthermore, in this case, the side surface of the first reflective electrode 130a facing the LED units 110 may be an inclined surface. Even in this case, the first reflective electrodes 130a may be arranged in a line extending along the boundaries between the LED units 110, or in a grid or mesh. As described above, the relative thickness and partial shape of the first reflective electrode 130a may vary depending on the exemplary embodiment.

[0091] Reference Figure 5BIn the display device 10b, the first electrode 130b may include an ohmic contact layer 132 and a reflective electrode layer 134. The ohmic contact layer 132 may be provided to be connected to the first conductive type semiconductor layer 112, and the reflective electrode layer 134 may be provided to extend on the side surface of the LED unit.

[0092] In some example embodiments, the ohmic contact layer 132 may be formed between the centers of two adjacent first to third sub-pixels SP1, SP2, and SP3, or four adjacent first to third sub-pixels SP1, SP2, and SP3. For example, the ohmic contact layer 132 may be provided in the center regions of the four first to third sub-pixels SP1, SP2, and SP3 arranged in a diamond shape. In this case, even when it is difficult to provide the first electrode 130b to be directly connected to the first conductive type semiconductor layer 112 in all regions, the ohmic contact layer 132 may be provided in the center regions of the four first to third sub-pixels SP1, SP2, and SP3 arranged in a diamond shape, which are relatively wide regions, to ensure electrical connection.

[0093] The ohmic contact layer 132 and the reflective electrode layer 134 may include the same material or different materials.

[0094] Reference Figure 5C ,and Figure 2B Compared to the second passivation layer 124 of the exemplary embodiment, in the display device 10c, the second passivation layer 124c may have a rounded slope. Therefore, the first electrode 130c may have an inner surface and an outer surface that are curved surfaces that are inclined as a whole.

[0095] As described above, in example embodiments, the shape of the outer surface of the second passivation layer 124c may be changed within a range in which the outer surface of the second passivation layer 124c has an overall inclination. Therefore, the shape of the inclined side surface of the first electrode 130c may also be changed.

[0096] Figure 6A and Figure 6B are respectively a schematic cross-sectional view and a partially enlarged view of a display device according to example embodiments. Figure 6B yes Figure 6A An enlarged view of portion "B" of FIG.

[0097] Reference Figure 6A and Figure 6B In the pixel array 100 of the display device 10d, the first electrode 130d and the second electrode 150d have Figure 2A and Figure 2B Those different shapes in the example embodiments.

[0098] The first electrode 130d may be connected to the first conductive type semiconductor layer 112, and only a portion of the first electrode 130d may extend downward along the side surface of the LED unit 110 or may not extend downward along the side surface of the LED unit 110. The second electrode 150d may extend upward along the side surface of the LED unit 110. Therefore, in this embodiment, instead of the first electrode 130d, the second electrode 150d may include a reflective region RL, may be connected to the reflective region RL, or may be integrated with the reflective region RL. In some example embodiments, in the second electrode 150d, the reflective region RL and other regions may include different materials. Or they may be formed in different processes so that the boundaries between the reflective region RL and other regions can be distinguished from each other.

[0099] In the present exemplary embodiment, the interconnection insulating layer 190 may include a region covering the second passivation layer 124 and the first electrode 130d. The reflective region RL of the second electrode 150d may be spaced apart from the second passivation layer 124 and the first electrode 130d by the region of the interconnection insulating layer 190. The relative lengths of the first electrode 130d and the second electrode 150d on the side surface of the LED unit 110 may vary according to exemplary embodiments.

[0100] Figure 7A and Figure 7B are respectively a schematic cross-sectional view and a partially enlarged view of a display device according to example embodiments. Figure 7B yes Figure 7A An enlarged view of portion "B" of FIG.

[0101] Reference Figure 7A and Figure 7B , the pixel array 100 of the display device 10e may include a reflective layer RLe. The reflective layer RLe may be provided on the side surfaces of the LED units 110 so as to be spaced apart from the first electrode 130e and the second electrode 150. The reflective layer RLe may be provided between the first electrode 130e and the second electrode 150 in a vertical direction or along the side surfaces of the LED units 110. The reflective layer RLe may be provided between the first electrode 130e and the second electrode 150 along the second passivation layer 124 on the side surfaces of the LED units 110. On the side surfaces of each of the LED units 110, the reflective layer RLe may be inclined so that the distance between the upper ends thereof is greater than the distance between the lower ends thereof.

[0102] In this exemplary embodiment, the reflective layer RLe can be in a floating state with no electrical signal applied. Therefore, even when the distance between the LED units 110 is relatively small, defects such as a short circuit between the first electrode 130e and the second electrode 150 can be prevented. The reflective layer RLe can include a reflective metal, for example, at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au).

[0103] Figure 8 is a schematic partially enlarged view of a display device according to an example embodiment. Figure 8 Shown with Figure 7B The corresponding area.

[0104] Reference Figure 8 In the display device 10f, the reflective layer RLf may have Figure 7A and Figure 7B For example, the reflective layer RLf may have a shape that connects adjacent LED units 110. The reflective layer RLf may be separated from the first electrode 130f by a region of the interconnection insulating layer 190 disposed between the first electrodes 130f.

[0105] Figures 9A to 9Q is a cross-sectional view of a stage in a method of manufacturing a display device according to an example embodiment. Figures 9A to 9Q According to Figure 2A and Figure 2B An example of a method of manufacturing a display device according to an example embodiment of the present invention.

[0106] Reference Figure 9A An upper semiconductor layer 111, a first conductive type semiconductor layer 112, an active layer 114, and a second conductive type semiconductor layer 116 may be sequentially formed on the growth substrate GS, and a contact layer 155 may be formed on the upper semiconductor layer 111, the first conductive type semiconductor layer 112, the active layer 114, and the second conductive type semiconductor layer 116.

[0107] The growth substrate GS can be used for nitride single crystal growth and may include, for example, at least one of sapphire, Si, SiC, MgAl2O4, MgO, LiAlO2, LiGaO2, and GaN. In some example embodiments, to improve the cleanliness of the semiconductor layer and light extraction efficiency, the growth substrate GS may have a concavo-convex structure on at least a portion of its upper surface. In this case, the concavo-convex structure may even be formed in the layer being grown.

[0108] The upper semiconductor layer 111, the first conductive type semiconductor layer 112, the active layer 114, and the second conductive type semiconductor layer 116 may be formed by, for example, a metal organic chemical vapor deposition (MOCVD) process, a hydride vapor phase epitaxy (HVPE) process, or a molecular beam epitaxy (MBE) process. The first conductive type semiconductor layer 112 may be an N-type nitride semiconductor layer (e.g., N-type GaN), and the second conductive type semiconductor layer 116 may be a P-type nitride semiconductor layer (e.g., P-type GaN / P-type AlGaN). The active layer 114 may have a multi-quantum well structure (e.g., InGaN / GaN). In some example embodiments, the upper semiconductor layer 111 may include a buffer layer. In this case, the buffer layer may serve to mitigate lattice defects in the first conductive type semiconductor layer 112 and may include an undoped nitride semiconductor (e.g., undoped GaN, undoped AlN, or undoped InGaN).

[0109] A contact layer 155 may be formed on an upper surface of the second conductive type semiconductor layer 116. The contact layer 155 may be a highly reflective ohmic contact layer.

[0110] Reference Figure 9B , the LED unit 110 may be formed by etching a stacked structure of the first conductive type semiconductor layer 112 , the active layer 114 , the second conductive type semiconductor layer 116 , and the contact layer 155 .

[0111] A portion of the stack structure may be removed by a dry etching process in this operation to thereby form individual units of the first to third sub-pixels SP1 , SP2 , and SP3 . In this operation, the stack structure may be etched to have an inclined side surface.

[0112] In the above operation, a damaged region DR may be partially formed on the side surface of the LED unit 110 through a dry etching process. Figure 9C , the damaged region DR can be removed from the LED unit 110. The damaged region DR can be selectively removed by, for example, a wet etching process. In the wet etching process, only the damaged region DR can be selectively removed by controlling the process conditions (e.g., different etching selectivities between crystal planes). Therefore, the angle between the upper surface and the side surface of the LED unit 110 can be a right angle or a nearly right angle, and non-radiative recombination caused by the damaged region DR can be reduced to improve the brightness of the final device.

[0113] Reference Figure 9D , the first passivation layer 122 may be formed, and a portion of the upper semiconductor layer 111 may be removed from the edge area ISO.

[0114] A first passivation layer 122 may be formed on the upper surface of the stacked structure to have a uniform thickness. The first passivation layer 122 may include, for example, at least one of SiO2, SiN, SiCN, SiOC, SiON, SiOCN, HfO2, and Al2O3. In some example embodiments, the first passivation layer 122 may include a metal oxide disposed on the uppermost portion, and the first passivation layer 122 may include, for example, a SiO2 layer, an HfO2 layer, and an Al2O3 layer stacked sequentially. The first passivation layer 122 may be conformally formed to have a substantially uniform thickness.

[0115] In the edge region ISO, the semiconductor layers constituting the upper semiconductor layer 111 and the first conductive type semiconductor layer 112 may be removed to a predetermined depth. The edge region ISO may be a region to be cut in a subsequent process and may be a region used to separate modules. Therefore, in this operation, a portion of the semiconductor layer may be removed to prevent cracks from occurring during the cutting or scribing process.

[0116] Reference Figure 9E , an initial second passivation layer 124P may be formed.

[0117] A preliminary second passivation layer 124P may be formed on the upper surface of the stacked structure. The preliminary second passivation layer 124P may be formed by a plasma enhanced chemical vapor deposition (PECVD) process. In example embodiments, the preliminary second passivation layer 124P may include, for example, SiO2. The thickness of the preliminary second passivation layer 124P may be determined in consideration of the thickness of the second passivation layer 124 to be ultimately formed.

[0118] Reference Figure 9F , the second passivation layer 124 may be formed by removing a portion of the preliminary second passivation layer 124P.

[0119] The initial second passivation layer 124P may be removed from the upper surface to have a predetermined thickness using, for example, an etch-back process. When the first passivation layer 122 includes a metal oxide layer on the uppermost portion, the first passivation layer 122 may serve as an etch stop layer during the etch-back process. The initial second passivation layer 124P may be removed relatively more on the upper surface of the LED unit 110 and relatively less on the side surfaces of the LED unit 110. Thus, a substrate having a thickness of Figure 9F The second passivation layer 124 has an inclined outer surface as shown in FIG. The shape of the second passivation layer 124 can be adjusted by controlling the conditions of this process.

[0120] In a region (eg, where the first electrode 130 is to be formed (see Figure 2A ), the first passivation layer 122 and the second passivation layer 124 may be removed.

[0121] Reference Figure 9G , a first electrode 130 , a common electrode 145 and a first pad electrode 147 may be formed.

[0122] The first electrode 130 may be conformally formed on the first and second passivation layers 122 and 124 and the first conductive type semiconductor layer 112. Thus, the first electrode 130 may have a substantially uniform thickness, and an inner surface contacting an outer surface of the second passivation layer 124 may be an inclined surface. The first electrode 130 may be formed in the pixel PX and the connection region CR.

[0123] A common electrode 145 and a first pad electrode 147 may be formed in the connection region CR and the connection pad PAD, respectively. The common electrode 145 may be formed on the first electrode 130, and the first pad electrode 147 may be formed on the second passivation layer 124. The common electrode 145 and the first pad electrode 147 may be formed together through the same process. The first electrode 130, the common electrode 145, and the first pad electrode 147 may include a conductive material such as a metal.

[0124] Reference Figure 9H , a preliminary interconnection insulating layer 190P may be formed.

[0125] The preliminary interconnection insulating layer 190P may be formed to cover all structures formed in previous operations including the first electrode 130. For example, the preliminary interconnection insulating layer 190P may be a low-k dielectric material (eg, silicon oxide).

[0126] Reference Figure 9I , a portion of the preliminary interconnection insulating layer 190P may be removed to form the interconnection insulating layer 190 .

[0127] For example, a portion of the initial interconnection insulating layer 190P may be removed from the top using a planarization process (e.g., a chemical mechanical polishing (CMP) process or an etch-back process). During the removal of the initial interconnection insulating layer 190P, the first electrode 130 may also be removed from the upper surface of the LED unit 110, and the first electrode 130 may remain only on the side surface of the LED unit 110.

[0128] Reference Figure 9J , a second electrode 150 connected to the contact layer 155 may be formed.

[0129] An interconnection insulating layer 190 may be additionally formed, and a contact hole may be formed to expose the contact layer 155 through the interconnection insulating layer 190 and the second passivation layer 124. By filling the contact hole with a conductive material, a second electrode 150 may be formed to fill the contact hole and extend on the upper surface of the interconnection insulating layer 190.

[0130] Reference Figure 9K, a second bonding insulating layer 195 may be formed on the second electrode 150 , and a second bonding electrode 198 may be formed.

[0131] The second bonding insulating layer 195 may include a material that is the same as or different from that of the interconnection insulating layer 190. In some example embodiments, the thickness of the second bonding insulating layer 195 may be, for example, Figure 2A ) changes within the range of a surface.

[0132] The second bonding electrode 198 may be formed by forming a via hole penetrating the second bonding insulating layer 195 and the interconnection insulating layer 190 and then filling the via hole with a conductive material. The second bonding electrode 198 may be formed to be connected to the second electrode 150, the common electrode 145, and the first pad electrode 147.

[0133] Reference Figure 9L , a structure in which the LED unit 110 and the circuit substrate 200 are combined can be formed by bonding.

[0134] The circuit substrate 200 may be prepared through additional processes. The structure including the LED unit 110 and the circuit substrate 200 may be bonded at the wafer level using a wafer bonding method (e.g., the hybrid bonding method described above). The first bonding electrode 298 may be bonded to the second bonding electrode 198, and the first bonding insulating layer 295 may be bonded to the second bonding insulating layer 195. Thus, the structure including the LED unit 110 and the circuit substrate 200 may be connected without an adhesive layer.

[0135] In the following drawings, for better understanding, the structure including the LED unit 110 is shown as having Figure 9L , which is a mirror image (eg, inverted image) of the structure shown in FIG.

[0136] Reference Figure 9M , the growth substrate GS may be removed from the upper semiconductor layer 111 , and a portion of the upper semiconductor layer 111 may be removed.

[0137] The growth substrate GS may be removed through various processes such as a laser lift-off process, a mechanical polishing process, a mechanical chemical polishing process, or an etching process.

[0138] A portion of the upper semiconductor layer 111 may be removed using a polishing process such as CMP to reduce a predetermined thickness. The upper semiconductor layer 111 may be removed, for example, to a thickness that is substantially equal to that of the wavelength converters 160R, 160G, and 160B (see FIG. Figure 2A ) corresponds to the level of the upper surface and can be removed so as not to remain in the edge area ISO (see Figure 3) in some example embodiments, the second passivation layer 124 of the edge region ISO can also be removed in this operation.

[0139] Referring to Figure 9N The first opening OP1 can be formed in the upper semiconductor layer 111.

[0140] The first opening OP1 can be formed by removing the upper semiconductor layer 111 in regions where the wavelength converters 160R, 160G, and 160B (see Figure 2A ) are to be provided. In this example embodiment, the first opening OP1 can be formed in this operation such that the first-conductivity-type semiconductor layer 112 is not completely separated between the LED units 110. Thus, the first-conductivity-type semiconductor layer 112 can be continuously provided between the upper surface of the first electrode 130 and the bottom surface of the first opening OP1.

[0141] Referring to Figure 9O The partitioned reflective layer 170 and the wavelength converters 160R, 160G, and 160B can be formed in the first opening OP1.

[0142] The partitioned reflective layer 170 can be prepared by forming the first partitioned insulating layer 172 and the partitioned metal layer 174, removing the partitioned metal layer 174 from the bottom surface of the first opening OP1, and then forming the second partitioned insulating layer 176.

[0143] The first wavelength converter 160B can be prepared by forming a transparent resin on the partitioned reflective layer 170, and the second wavelength converter 160G and the third wavelength converter 160R can be prepared by forming a transparent resin mixed with a wavelength conversion material. The wavelength conversion material can convert blue light into green light and red light, respectively, with the second wavelength converter 160G and the third wavelength converter 160R. The transparent resin can include, for example, silicone or epoxy resin. Alternatively, according to some example embodiments, the wavelength converters 160R, 160G, and 160B can be formed of silicon oxide (e.g., Si02) instead of a transparent resin.

[0144] Referring to Figure 9P The color filters 180G and 180R and the microlenses 185 can be formed on the wavelength converters 160B, 160G, and 160R.

[0145] A packaging layer 182 can be formed on the wavelength converters 160B, 160G, and 160R to protect the wavelength converters 160B, 160G, and 160R from environmental factors such as moisture, oxygen, etc. Color filters 180G and 180R can be formed on the second and third wavelength converters 160G and 160R, respectively. In some example embodiments, the color filters 180G and 180R can also be formed on the first wavelength converter 160B.

[0146] A planarization layer 184 can be formed to cover the color filters 180G and 180R, and a microlens 185 can be formed. The microlens 185 can be formed by, for example, forming a lens material layer of an exposure material layer using a jetting process or a spin coating process, directly patterning the lens material layer, and reflowing the patterned lens material layer. Alternatively, the microlens 185 can be formed by forming a lens material layer, forming an additional mask layer including a lens pattern, and performing an etching process such as a dry etching process on the lens material layer using the mask layer to transfer a shape of the lens pattern.

[0147] Referring to Figure 9Q A second opening OP2 can be formed by removing the planarization layer 184, the packaging layer 182, the upper semiconductor layer 111, and the first conductive type semiconductor layer 112 on the first pad electrode 147.

[0148] The second opening OP2 can be formed to expose the first passivation layer 122 on the first pad electrode 147 in the connection pad PAD.

[0149] Referring to Figure 2A After removing the portion of the first passivation layer 122 exposed through the second opening OP2, a second pad electrode 199 can be formed, and the adjacent module can be cut in the edge area ISO to complete the manufacturing of the display apparatus 10.

[0150] Figure 10 is a conceptual diagram of an electronic apparatus including a display apparatus according to an example embodiment.

[0151] Referring to Figure 10 , the electronic apparatus 1000 can be a glasses-type display (e.g., a wearable device). The electronic apparatus 1000 can include a pair of temples 1100, a pair of light coupling lenses 1200, and a temple bar 1300. The electronic apparatus 1000 can include the display apparatus 10 including an image sensor.

[0152] The electronic apparatus 1000 can be a head-mounted, glasses-type, or goggle-type virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device for providing virtual reality or providing a virtual image and an external real landscape.

[0153] The temples 1100 may be spaced apart from each other and may extend in parallel. The display device 10 may be disposed in the temples 1100, and a projection lens may be additionally disposed therein. The temples 1100 may be folded to face the bridge 1300. The optical coupling lenses 1200 may include a light guide plate and an input / output grating. The bridge 1300 may be disposed between the optical coupling lenses 1200 to connect the optical coupling lenses 1200 to each other.

[0154] The display device 10 may be provided on each of the temples 1100, and may generate an image on the optical coupling lens 1200. For example, after light from the display device 10 is incident on the projection lens, the light may be transmitted along the light guide plate of the optical coupling lens 1200 to generate an image. The display device 10 may be the display device according to the above description with reference to FIG. 1 to FIG. Figure 8 A display device according to an exemplary embodiment is described.

[0155] As described above, according to example embodiments, the first electrode may be provided to have an inclined surface, and thus a display device having improved light extraction efficiency may be provided.

[0156] As described above, embodiments relate to a display device including a light emitting diode (LED). Embodiments can provide a display device having improved light extraction efficiency.

[0157] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display device, comprising: a circuit substrate including a driving circuit and a first bonding electrode; as well as A pixel array is located on the circuit substrate, the pixel array including light-emitting diode units constituting a plurality of pixels and a second bonding electrode bonded to the first bonding electrode, wherein: Each of the light emitting diode units includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer sequentially stacked, and The pixel array further includes: a wavelength converter, which is located on the light-emitting diode unit; an upper semiconductor layer located on the light emitting diode unit and having a partition structure that surrounds side surfaces of the wavelength converters and separates the wavelength converters from each other; a passivation layer located on a side surface of the light emitting diode unit and having an outer side surface inclined to increase in thickness in a direction toward the wavelength converter; a first electrode located on an outer surface of the passivation layer and extending to a region between the light emitting diode units; second electrodes, each located on a lower surface of the light emitting diode unit and connected to the second conductive type semiconductor layer; a common electrode located on at least one side of the light emitting diode unit; and A pad electrode is located outside the light emitting diode unit and is electrically connected to the driving circuit.

2. The display device according to claim 1, wherein The passivation layer extends on a lower surface of the light emitting diode unit.

3. The display device according to claim 1, wherein: The pixel array further includes an upper passivation layer located between the passivation layer and the light emitting diode unit, and The upper passivation layer has an outer surface substantially perpendicular to a lower surface of the light emitting diode unit.

4. The display device according to claim 3, wherein The passivation layer includes a semiconductor oxide, and the upper passivation layer includes a metal oxide.

5. The display device according to claim 1, wherein The first electrode is disposed so as not to overlap with the active layer and the second conductive type semiconductor layer of the light emitting diode unit in a direction perpendicular to a lower surface of the light emitting diode unit. The display device according to claim 1 , wherein: The first electrode has a substantially uniform thickness on an outer surface of the passivation layer.

7. The display device according to claim 1, wherein The first electrode is configured to fill a space between the light emitting diode units.

8. The display device according to claim 1, wherein The upper semiconductor layer is connected to the first conductive type semiconductor layer and includes the same material as that of the first conductive type semiconductor layer.

9. The display device according to claim 8, wherein The upper semiconductor layer includes an epitaxial nitride semiconductor layer.

10. The display device according to claim 1, wherein The first electrode includes an ohmic contact layer contacting the first conductive type semiconductor layer and a reflective electrode layer on a lower surface of the ohmic contact layer.

11. A display device comprising: a circuit substrate including a driving circuit; as well as A pixel array is located on the circuit substrate, and the pixel array includes: Light emitting diode units constituting a plurality of pixels, each of the light emitting diode units including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer sequentially stacked; a wavelength converter, which is located on the light-emitting diode unit; an upper semiconductor layer located on the light emitting diode unit and having a partition structure that surrounds side surfaces of the wavelength converters and separates the wavelength converters from each other; a passivation layer located on a side surface of the light emitting diode unit and extending to a portion of a lower surface of the light emitting diode unit; A first electrode having a grid shape along a region of the light emitting diode unit; a second electrode connected to the second conductive type semiconductor layer; and A reflective layer is located between the first electrode and the second electrode along the passivation layer located on the side surface of the light emitting diode unit and has an inclined surface inclined toward the outside of the light emitting diode unit.

12. The display device according to claim 11, wherein The reflective layer is connected to the first electrode.

13. The display device according to claim 11, wherein The reflective layer is connected to the second electrode.

14. The display device according to claim 11, wherein The reflective layer is disposed to be spaced apart from the first electrode and the second electrode.

15. The display device according to claim 11, wherein The inclined surface of the reflective layer is inclined such that a distance between upper ends is greater than a distance between lower ends.

16. The display device according to claim 11, wherein The wavelength converter has inclined side surfaces such that a width of an upper portion is greater than a width of a lower portion.

17. The display device according to claim 11, wherein The pixel array further includes a separation reflective layer covering a side surface of the wavelength converter and including a first separation insulating layer, a separation metal layer, and a second separation insulating layer that are sequentially stacked.

18. The display device according to claim 17, wherein The separated reflective layer extends on the upper surface of the upper semiconductor layer between the wavelength converters.

19. A display device comprising: a circuit substrate including a driving circuit and a first bonding electrode; as well as A pixel array is located on the circuit substrate and includes light-emitting diode units constituting a plurality of pixels, each of the light-emitting diode units including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer stacked sequentially, wherein: The pixel array further includes: a wavelength converter, which is located on the light-emitting diode unit; a passivation layer located on a side surface of the light emitting diode unit and having an outer side surface inclined to increase in thickness in a direction toward the wavelength converter; a first electrode having an inclined surface in contact with the passivation layer; a second electrode connected to the second conductive type semiconductor layer; a common electrode located on at least one side of the light emitting diode unit; and a second bonding electrode bonded to the first bonding electrode, The first electrode is provided in a region between the light emitting diode units adjacent to each other so as not to vertically overlap the light emitting diode units, and is electrically connected to a portion of the second bonding electrode through the common electrode in an outer portion of the light emitting diode units, and Each of the second electrodes is disposed below a lower surface of each of the light emitting diode units to vertically overlap the light emitting diode units and is directly connected to a portion of the second bonding electrode.

20. The display device according to claim 19, wherein: The light emitting diode units are arranged in rows and columns, and The first electrode includes a line extending along a boundary between the light emitting diode units.

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