Display device

Abstract

A display device is disclosed. According to an aspect of the disclosure, a display device includes a display panel in which a plurality of pixels including a plurality of sub-pixels having different colors are disposed, a data driver configured to supply a data voltage to the plurality of pixels through a plurality of data lines, and a gate driver configured to supply a gate signal to the plurality of pixels through a plurality of gate lines, wherein the plurality of sub-pixels are sequentially disposed in the same column, each of the plurality of data lines is divided into a plurality of sub-data lines, and each of the plurality of sub-data lines is disposed on both sides of the plurality of sub-pixels sequentially disposed in the same column.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0194703, filed on December 31, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device capable of being driven at a high driving frequency. Background Technology

[0004] As display devices used as monitors for computers, televisions, or cellular phones, there are organic light-emitting display devices (OLEDs) that are self-emissive and liquid crystal display devices (LCDs) that require a separate light source.

[0005] Among various display devices, organic light-emitting display devices include a display panel having multiple sub-pixels and a driver for driving the display panel. The driver includes a gate driver configured to supply gate signals to the display panel and a data driver configured to supply data voltages. When signals such as gate signals and data voltages are supplied to the sub-pixels of the organic light-emitting display device, selected sub-pixels emit light to display an image.

[0006] As display panel sizes increase, a double-rate driving method is used to drive the display panel by increasing the driving frequency in order to drive it smoothly. As mentioned above, when the driving frequency increases, the time for charging the data voltage of the sub-pixels decreases rapidly, resulting in the problem that the data may not be fully charged into the sub-pixels. Summary of the Invention

[0007] One objective of this disclosure is to provide a display device including a sensing transistor that senses characteristic values ​​of sub-pixels.

[0008] Another objective of this disclosure is to provide a display device that improves data charging rate.

[0009] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] To achieve the above objectives, according to one aspect of this disclosure, a display device includes: a display panel having a plurality of pixels, the plurality of pixels including a plurality of sub-pixels of different colors; a data driver configured to supply data voltage to the plurality of pixels via a plurality of data lines; and a gate driver configured to supply gate signals to the plurality of pixels via a plurality of gate lines, wherein the plurality of sub-pixels are sequentially arranged in the same column, each of the plurality of data lines is divided into a plurality of sub-data lines, and each of the plurality of sub-data lines is disposed on both sides of the plurality of sub-pixels sequentially arranged in the same column.

[0011] Further detailed topics, including exemplary embodiments, are included in the detailed description and accompanying drawings.

[0012] According to this disclosure, the RC delay of the data signal is reduced to improve the charging rate of the data signal.

[0013] According to this disclosure, even in a specific mode, the charging rate of the data signal can be constantly controlled.

[0014] The effects of this disclosure are not limited to those illustrated above, and this specification includes many more effects. Attached Figure Description

[0015] The above and other aspects, features and advantages of this disclosure will become clearer when taken in conjunction with the accompanying drawings and the following detailed description, in which:

[0016] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0017] Figure 2 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 3 This is a block diagram used to explain the placement relationship of sub-pixels in a display device according to exemplary embodiments of the present disclosure;

[0019] Figure 4 It is a waveform of the gate voltage of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 5 This is a view used to explain the driving order in odd-numbered frames of a display device according to exemplary embodiments of the present disclosure;

[0021] Figure 6 This is a view used to explain the driving order in even-numbered frames of a display device according to exemplary embodiments of the present disclosure; and

[0022] Figure 7This is a view used to explain the charging rate of the data voltage of the display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clearer from the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure is not limited to the following exemplary embodiments, but can be implemented in various different forms. Exemplary embodiments are provided only to complete the disclosure and to fully provide those skilled in the art to which this disclosure pertains, and this disclosure will be defined by the appended claims.

[0024] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Similar reference numerals generally refer to similar elements throughout the specification. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0025] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0026] When using terms such as “above,” “over,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “adjacent” or “direct.”

[0027] When a component or layer is referred to as being "on" another component or layer, it can be directly on the other component or layer, or there can be an intervening component or layer.

[0028] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of this disclosure, the first component mentioned below can be the second component.

[0029] Throughout the specification, the same reference numerals denote the same elements.

[0030] Since the dimensions and thicknesses of each component shown in the accompanying drawings are for ease of interpretation, this disclosure is not necessarily limited to the dimensions and thicknesses of each component shown.

[0031] The features of the various embodiments of this disclosure may be partially or completely coupled or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently or in association with each other.

[0032] Various exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0033] The transistors used in the display device of this disclosure can be implemented by one or more of n-channel transistors (NMOS) and p-channel transistors (PMOS). The transistors can be implemented as oxide semiconductor transistors having oxide semiconductor as the active layer or LTPS transistors having low-temperature polycrystalline silicon (LTPS) as the active layer. The transistors can include at least a gate electrode, a source electrode, and a drain electrode. The transistors can be implemented as thin-film transistors on a display panel. In the transistor, charge carriers flow from the source electrode to the drain electrode. In the case of an n-channel transistor (NMOS), since the charge carriers are electrons, the source voltage can be lower than the drain voltage to allow electrons to flow from the source electrode to the drain electrode. Current in the n-channel transistor (NMOS) flows from the drain electrode to the source electrode, and the source electrode can be used as an output terminal. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage to allow holes to flow from the source electrode to the drain electrode. In a p-channel transistor (PMOS), holes flow from the source electrode to the drain electrode, current flows from the source electrode to the drain electrode, and the drain electrode is used as an output terminal. Therefore, the source and drain electrodes can be changed according to the applied voltage; it should be noted that the source and drain electrodes of a transistor are not fixed. In this specification, it is assumed that the transistor is an n-channel transistor (NMOS), but it is not limited to this, allowing the use of p-channel transistors and thus enabling changes to the circuit configuration.

[0034] The gate signal of a transistor used as a switching element switches between a gate on-state voltage and a gate off-state voltage. The gate on-state voltage is set higher than the transistor's threshold voltage Vth, and the gate off-state voltage is set lower than the transistor's threshold voltage Vth. The transistor turns on in response to the gate on-state voltage and turns off in response to the gate off-state voltage. In the case of NMOS, the gate on-state voltage is the gate high voltage VGH, and the gate off-state voltage is the gate low voltage VGL. In the case of PMOS, the gate on-state voltage is the gate low voltage VGL, and the gate off-state voltage is the gate high voltage VGH.

[0035] Various exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Reference Figure 1The display device 100 includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

[0037] Display panel 110 is a panel for displaying images. Display panel 110 may include various circuits, wiring lines, and light-emitting diodes disposed on a substrate. Display panel 110 is divided by multiple intersecting data lines DL and multiple gate lines GL, and includes multiple pixels PX connected to the multiple data lines DL and multiple gate lines GL. Display panel 110 includes a display area defined by the multiple pixels PX and a non-display area forming various signal lines or pads. Display panel 110 can be implemented using display panels 110 used in various display devices such as liquid crystal display devices, organic light-emitting display devices, or electrophoretic display devices. Hereinafter, display panel 110 is described as a panel used in an organic light-emitting display device, but is not limited thereto.

[0038] The timing controller 140 receives timing signals such as vertical synchronization signals, horizontal synchronization signals, data enable signals, or point clocks via a receiver circuit such as an LVDS or TMDS interface connected to a host system. The timing controller 140 generates timing control signals based on the input timing signals to control the data driver 130 and the gate driver 120.

[0039] Data driver 130 supplies data voltage DATA to multiple sub-pixels SP. Data driver 130 includes multiple source driver ICs (integrated circuits). Digital video data and source timing control signals can be supplied to the multiple source driver ICs from timing controller 140. In response to the source timing control signals, the multiple source driver ICs convert digital video data into gamma voltage to generate data voltage DATA and supply data voltage DATA through data lines DL of display panel 110. The multiple source driver ICs can be connected to data lines DL of display panel 110 via chip-on-glass (COG) process or tape-on-board (TAB) process. Furthermore, the source driver ICs are formed on display panel 110 or on a separate PCB substrate for connection to display panel 110.

[0040] Gate driver 120 supplies gate signals to multiple sub-pixels SP. Gate driver 120 may include a level shifter and a shift register. The level shifter shifts the level of a clock signal input from timing controller 140 at the transistor-transistor-logic (TTL) level and then supplies the clock signal to the shift register. The shift register may be formed in a non-display area of ​​display panel 110 using a GIP configuration, but is not limited thereto. The shift register is constructed of multiple stages that shift the gate signal in response to the clock signal and drive signal for output. The multiple stages included in the shift register sequentially output the gate signal through multiple output terminals.

[0041] The display panel 110 may include multiple subpixels SP. The multiple subpixels SP may be subpixels SP used to emit light of different colors. For example, the multiple subpixels SP may be red subpixels, green subpixels, blue subpixels, and white subpixels, but are not limited to these. The multiple subpixels SP can construct a pixel PX. That is, red subpixels, green subpixels, blue subpixels, and white subpixels construct a pixel PX, and the display panel 110 may include multiple pixels PX.

[0042] In the following text, reference will be made to Figure 2 The driving circuitry used to drive a sub-pixel SP will be described in more detail below.

[0043] Figure 2 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 2 The diagram shows a circuit diagram of one of the multiple sub-pixels SP of the display device 100.

[0044] refer to Figure 2 The sub-pixel SP may include a switching transistor SWT, a sensing transistor SET, a driving transistor DT, a storage capacitor SC, and a light-emitting diode 150.

[0045] The light-emitting diode 150 may include an anode, an organic layer, and a cathode. The organic layer may include various organic layers, such as a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer. The anode of the light-emitting diode 150 may be connected to the output terminal of the driving transistor DT, and a low-potential voltage VSS is applied to the cathode. Even when... Figure 2 The present invention describes the light-emitting diode 150 as an organic light-emitting diode 150, but this disclosure is not limited thereto, and inorganic light-emitting diodes (i.e. LEDs) may also be used as light-emitting diode 150.

[0046] refer to Figure 2 The switching transistor SWT is a transistor that transmits the data voltage DATA to the first node N1 corresponding to the gate electrode of the driving transistor DT. The switching transistor SWT may include a drain electrode connected to the data line DL, a gate electrode connected to the gate line GL, and a source electrode connected to the gate electrode of the driving transistor DT. The switching transistor SWT is turned on by a scan signal SCAN applied from the gate line GL to transmit the data voltage DATA supplied from the data line DL to the first node N1 corresponding to the gate electrode of the driving transistor DT.

[0047] refer to Figure 2The driving transistor DT is a transistor configured to supply driving current to the light-emitting diode 150 to drive the light-emitting diode 150. The driving transistor DT may include a gate electrode corresponding to the first node N1, a source electrode corresponding to the second node N2 and the output terminal, and a drain electrode corresponding to the third node N3 and the input terminal. The gate electrode of the driving transistor DT is connected to the switching transistor SWT, the drain electrode is given a high-potential voltage VDD via the high-potential voltage line VDDL, and the source electrode is connected to the anode of the light-emitting diode 150.

[0048] refer to Figure 2 The storage capacitor SC is a capacitor that maintains a voltage corresponding to the data voltage DATA within one frame. One electrode of the storage capacitor SC is connected to the first node N1, and the other electrode is connected to the second node N2.

[0049] Meanwhile, in the case of display device 100, as the driving time of each sub-pixel SP increases, circuit elements such as the driving transistor DT may degrade. Therefore, the unique characteristic values ​​of circuit elements such as the driving transistor DT can be changed. Here, the unique characteristic values ​​of the circuit elements may include the threshold voltage Vth of the driving transistor DT or the mobility α of the driving transistor DT. Changes in the characteristic values ​​of the circuit elements may cause changes in the brightness of the corresponding sub-pixel SP. Therefore, changes in the characteristic values ​​of the circuit elements can be used as the same concept as changes in the brightness of the sub-pixel SP.

[0050] Furthermore, the degree of variation in characteristic values ​​between the circuit elements of each sub-pixel SP can vary depending on the degree of degradation of each circuit element. This difference in the degree of variation in characteristic values ​​between circuit elements can lead to brightness deviations between sub-pixel SPs. Therefore, the characteristic value deviation between circuit elements can be used as the same concept as the brightness deviation between sub-pixel SPs. Variations in the characteristic values ​​of circuit elements (i.e., brightness variations in sub-pixel SPs) and characteristic value deviations between circuit elements (i.e., brightness deviations between sub-pixel SPs) can cause problems such as reduced accuracy in the brightness representation of sub-pixel SPs or screen anomalies.

[0051] Therefore, the sub-pixel SP of the display device 100 according to the exemplary embodiments of the present disclosure provides a sensing function for sensing the characteristic value of the sub-pixel SP and a compensation function for compensating the characteristic value of the sub-pixel SP using the sensing result.

[0052] Therefore, as Figure 2 As shown, in addition to the switching transistor SWT, driving transistor DT, storage capacitor SC, and light-emitting diode 150, the sub-pixel SP may also include a sensing transistor SET that effectively controls the voltage state of the source electrode of the driving transistor DT.

[0053] refer to Figure 2The sensing transistor SET is connected between the source electrode of the driving transistor DT and the reference voltage line RVL, which is configured to supply the reference voltage Vref, and its gate electrode is connected to the gate line GL. Therefore, the sensing transistor SET is turned on by a sensing signal SENSE applied through the gate line GL to apply the reference voltage Vref supplied through the reference voltage line RVL to the source electrode of the driving transistor DT. Furthermore, the sensing transistor SET can be used as one of the voltage sensing paths for the source electrode of the driving transistor DT.

[0054] refer to Figure 2 In a sub-pixel SP, the switching transistor SWT and the sensing transistor SET can share a single gate line GL. That is, the switching transistor SWT and the sensing transistor SET are connected to the same gate line GL to be applied with the same gate signal. However, for ease of description, the voltage applied to the gate electrode of the switching transistor SWT is called the scan signal SCAN, and the voltage applied to the gate electrode of the sensing transistor SET is called the sensing signal SENSE. However, the scan signal SCAN and the sensing signal SENSE applied to a sub-pixel SP are the same signal transmitted from the same gate line GL. Therefore, in Figure 3 In this context, the scan signal SCAN and the sensing signal SENSE are defined as gate signals GATE1, GATE2, GATE3, and GATE4.

[0055] However, this disclosure is not limited thereto, such that only the switching transistor SWT is connected to the gate line GL and the sensing transistor SET can be connected to a separate sensing line. Therefore, the scan signal SCAN is applied to the switching transistor SWT via the gate line GL, and the sensing signal SENSE is applied to the sensing transistor SET via the sensing line.

[0056] Therefore, the reference voltage Vref is applied to the source electrode of the driving transistor DT via the sensing transistor SET. Furthermore, the threshold voltage Vth or the mobility α of the driving transistor DT is detected by the reference voltage line RVL. Additionally, the data driver 130 can compensate for the data voltage DATA based on changes in the threshold voltage Vth or the mobility α of the driving transistor DT.

[0057] In the following text, reference will be made to Figure 3 Describes the arrangement relationship of multiple sub-pixels.

[0058] Figure 3 This is a block diagram used to explain the placement relationship of sub-pixels in a display device according to exemplary embodiments of the present disclosure.

[0059] For ease of description, Figure 3In the image, only 8 pixels are shown, arranged in a 4×2 matrix, and the arrangement of these 8 pixels in a 4×2 matrix is ​​repeated throughout the display area. (Reference) Figure 3 A pixel PX consists of four sub-pixels: R, G, B, and W. For example, as... Figure 3 As shown, pixel PX may include a first sub-pixel B, a second sub-pixel R, a third sub-pixel W, and a fourth sub-pixel G. Further, the first sub-pixel B is a blue sub-pixel, the second sub-pixel R is a red sub-pixel, the third sub-pixel W is a white sub-pixel, and the fourth sub-pixel G is a green sub-pixel. However, this disclosure is not limited to this, and the multiple sub-pixels can be changed to various colors, such as magenta, yellow, and cyan.

[0060] The first sub-pixel B, the second sub-pixel R, the third sub-pixel W, and the fourth sub-pixel G are set in the same column in sequence.

[0061] Specifically, the arrangement order of the first sub-pixel B, the second sub-pixel R, the third sub-pixel W, and the fourth sub-pixel G in the odd-numbered columns (columns 4n-3 and 4n-1) can be different from the arrangement order of the first sub-pixel B, the second sub-pixel R, the third sub-pixel W, and the fourth sub-pixel G in the even-numbered columns (columns 4n-2 and 4n).

[0062] That is, in the odd-numbered columns (columns 4n-3 and 4n-1), the first sub-pixel B, the second sub-pixel R, the third sub-pixel W, and the fourth sub-pixel G are arranged in this order to construct the first pixel PX1.

[0063] That is, in the even-numbered columns (columns 4n-2 and 4n), the third sub-pixel W, the fourth sub-pixel G, the first sub-pixel B, and the second sub-pixel R are set in this order to construct the second pixel PX2.

[0064] More specifically, such as Figure 3As shown, in odd-numbered columns (columns 4n-3 and 4n-1), the first sub-pixel B is located in rows 8m-7 and 8m-3, and in even-numbered columns (columns 4n-2 and 4n), the first sub-pixel B is located in rows 8m-5 and 8m-1. In odd-numbered columns (columns 4n-3 and 4n-1), the second sub-pixel R is located in rows 8m-6 and 8m-2, and in even-numbered columns (columns 4n-2 and 4n), the second sub-pixel R is located in rows 8m-4 and 8m. In odd-numbered columns (columns 4n-3 and 4n-1), the third sub-pixel W is located in rows 8m-5 and 8m-1, and in even-numbered columns (columns 4n-2 and 4n), the third sub-pixel W is located in rows 8m-7 and 8m-3. In odd-numbered columns (columns 4n-3 and 4n-1), the fourth sub-pixel G is set in rows 8m-4 and 8m, and in even-numbered columns (columns 4n-2 and 4n), the fourth sub-pixel G is set in rows 8m-6 and 8m-2. Here, m and n are natural numbers of 1 or greater.

[0065] However, this is not the only limitation; it allows switching the arrangement order of the second sub-pixel R and the third sub-pixel W of the first pixel PX1, and also allows switching the arrangement order of the first sub-pixel B and the fourth sub-pixel G of the first pixel PX1. Furthermore, it allows switching the arrangement order of the second sub-pixel R and the third sub-pixel W of the second pixel PX2, and also allows switching the arrangement order of the first sub-pixel B and the fourth sub-pixel G of the second pixel PX2.

[0066] The first sub-pixel B includes a first light-emitting diode BE and a first circuit element BC, and the second sub-pixel R includes a second light-emitting diode RE and a second circuit element RC. The third sub-pixel W includes a third light-emitting diode WE and a third circuit element WC, and the fourth sub-pixel G includes a fourth light-emitting diode GE and a fourth circuit element GC.

[0067] The first circuit element BC, the second circuit element RC, the third circuit element WC, and the fourth circuit element GC are arranged diagonally relative to the sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1, and SDL4-2. The first light-emitting diode BE, the second light-emitting diode RE, the third light-emitting diode WE, and the fourth light-emitting diode GE are arranged diagonally relative to the sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1, and SDL4-2. In other words, the various light-emitting diodes and corresponding circuit elements can be arranged in an alternating zigzag pattern, but are not limited to this.

[0068] That is, the first circuit element BC, the second circuit element RC, the third circuit element WC, and the fourth circuit element GC are arranged in the vertical and horizontal directions relative to the first light-emitting diode BE, the second light-emitting diode RE, the third light-emitting diode WE, and the fourth light-emitting diode GE. However, the first light-emitting diode BE, the second light-emitting diode RE, the third light-emitting diode WE, and the fourth light-emitting diode GE are not arranged to be adjacent to each other in the vertical and horizontal directions.

[0069] Each of the multiple data lines DL1, DL2, DL3, and DL4 can be divided into multiple sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1, and SDL4-2. For example, each data line can branch into a pair of two sub-data lines to extend along opposite sides of a pixel unit comprising four sub-pixels, thereby providing an efficient wiring layout for supplying corresponding data signals to each of the light-emitting diodes arranged in an alternating zigzag pattern.

[0070] That is, the first data line DL1 is divided into sub-data line SDL1-1 (1-1) and sub-data line SDL1-2 (1-2). The second data line DL2 is divided into sub-data line SDL2-1 (2-1) and sub-data line SDL2-2 (2-2). The third data line DL3 is divided into sub-data line SDL3-1 (3-1) and sub-data line SDL3-2 (3-2). The fourth data line DL4 is divided into sub-data line SDL4-1 (4-1) and sub-data line SDL4-2 (4-2).

[0071] Multiple sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1 and SDL4-2 are positioned on both sides of multiple sub-pixels R, G, B, W arranged in a column to connect to the multiple sub-pixels R, G, B, W.

[0072] In other words, sub-data lines SDL1-1 (1st generation) and SDL3-1 (3rd generation) are positioned on one side of the multiple sub-pixels R, G, B, and W located in the odd-numbered columns (columns 4n-3 and 4n-1). Sub-data lines SDL1-2 (1st generation) and SDL3-2 (3rd generation) are positioned on the other side of the multiple sub-pixels R, G, B, and W located in the odd-numbered columns (columns 4n-3 and 4n-1). Sub-data lines SDL2-1 (2nd generation) and SDL4-1 (4th generation) are positioned on one side of the multiple sub-pixels R, G, B, and W located in the even-numbered columns (columns 4n-2 and 4n). Sub-data lines SDL2-2 (2nd-2nd) and SDL4-2 (4th-2nd) are positioned on the other side of multiple sub-pixels R, G, B, W that are located in even-numbered columns (columns 4n-2nd and 4nth).

[0073] For example, sub-data lines SDL1-1 (1st generation) and SDL3-1 (3rd generation) are positioned to the left of multiple sub-pixels R, G, B, and W located in odd-numbered columns (columns 4n-3) to connect to multiple first sub-pixels B and multiple third sub-pixels W located in odd-numbered columns (columns 4n-3). Furthermore, sub-data lines SDL1-2 (1st generation) and SDL3-2 (3rd generation) are positioned to the right of multiple sub-pixels R, G, B, and W located in odd-numbered columns (columns 4n-3) to connect to multiple first sub-pixels B and multiple third sub-pixels W located in even-numbered columns (columns 4n-2).

[0074] Sub-data lines SDL2-1 (2nd generation) and SDL4-1 (4th generation) are positioned to the left of multiple sub-pixels R, G, B, and W located in even-numbered columns (column 4n-2) to connect to multiple second sub-pixels R and multiple fourth sub-pixels G located in odd-numbered columns (column 4n-3). Similarly, sub-data lines SDL2-2 (2nd generation) and SDL4-2 (4th generation) are positioned to the right of multiple sub-pixels R, G, B, and W located in even-numbered columns (column 4n-2) to connect to multiple second sub-pixels R and multiple fourth sub-pixels G located in even-numbered columns (column 4n-2).

[0075] A first data voltage DATA1, which is a blue data voltage, is applied to the first data line DL1, and a second data voltage DATA2, which is a red data voltage, is applied to the second data line DL2. Furthermore, a third data voltage DATA3, which is a white data voltage, is applied to the third data line DL3, and a fourth data voltage DATA4, which is a green data voltage, is applied to the fourth data line DL4.

[0076] Therefore, the first data voltage DATA1, which is the blue data voltage, is applied to data lines SDL1-1 (1-1) and SDL1-2 (1-2). The second data voltage DATA2, which is the red data voltage, is applied to data lines SDL2-1 (2-1) and SDL2-2 (2-2). The third data voltage DATA3, which is the white data voltage, is applied to data lines SDL3-1 (3-1) and SDL3-2 (3-2). The fourth data voltage DATA4, which is the green data voltage, is applied to data lines SDL4-1 (4-1) and SDL4-2 (4-2).

[0077] although Figure 3 As not shown, for ease of manufacturing, multiple dummy lines can be further positioned to the left of the multiple sub-pixels R, W, B, and G located in the 4n-3rd column. These dummy lines can be positioned on both sides of the high-potential voltage line VDDL, which is positioned to the left of the multiple sub-pixels R, W, B, and G located in the 4n-3rd column.

[0078] Alternatively, multiple dummy lines can be further positioned to the right of the multiple sub-pixels R, W, B, and G located in the 4n column. These multiple dummy lines can also be positioned on both sides of the high-potential voltage line VDDL to the right of the multiple sub-pixels R, W, B, and G located in the 4n column.

[0079] The aforementioned multiple dummy lines can be set on the same layer as the multiple sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1, and SDL4-2.

[0080] Each of the multiple high-potential voltage lines VDDL can be set between multiple adjacent sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1, and SDL4-2.

[0081] In other words, the high-potential voltage line VDDL is positioned between multiple sub-pixels R, W, B, G located in odd-numbered columns (columns 4n-3 and 4n-1) and multiple sub-pixels R, W, B, G located in even-numbered columns (columns 4n-4 and 4n).

[0082] Therefore, at least one of the multiple adjacent sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1, and SDL4-2 can overlap with the high-potential voltage line VDDL. For example, in Figure 3In the middle, the 3-1 sub-data line SDL3-1 overlaps with the high-potential voltage line VDDL to connect to the third sub-pixel W.

[0083] Each of the multiple reference voltage lines RVL can be set in each of the multiple sub-pixels R, G, B, W.

[0084] Specifically, each of the multiple reference lines RVL is positioned between the first light-emitting diode BE and the first circuit element BC, between the second light-emitting diode RE and the second circuit element RC, between the third light-emitting diode WE and the third circuit element WC, and between the fourth light-emitting diode GE and the fourth circuit element GC. For example, each reference line RVL may be positioned below the center of the corresponding pixel unit, for example, extending along the center of an alternating zigzag pattern including light-emitting diodes and circuit elements, and dividing it into two halves (e.g., see...). Figure 3 ).

[0085] Any one of the multiple reference voltage lines RVL is connected to multiple sub-pixels R, G, B, W located in odd-numbered columns (columns 4n-3 and 4n-1). Another reference voltage line RVL is connected to multiple sub-pixels R, G, B, W located in even-numbered columns (columns 4n-2 and 4n).

[0086] The first circuit element BC and the third circuit element WC are configured to be opposite the second circuit element RC and the fourth circuit element GC with respect to each of the multiple reference voltage lines RVL.

[0087] That is, regarding the multiple sub-pixels R, G, B, W set in the odd-numbered columns (columns 4n-3 and 4n-1), the first circuit element BC and the third circuit element WC are set to the left of the reference voltage line RVL, and the second circuit element RC and the fourth circuit element GC are set to the right of the reference voltage line RVL.

[0088] Furthermore, regarding the multiple sub-pixels R, G, B, W set in even-numbered columns (columns 4n-2 and 4n), the first circuit element BC and the third circuit element WC are set to the left of the reference voltage line RVL, and the second circuit element RC and the fourth circuit element GC are set to the right of the reference voltage line RVL.

[0089] The first LED BE and the third LED WE are configured to be opposite the second LED RE and the fourth LED GE with respect to each of the multiple reference voltage lines RVL.

[0090] Multiple gate lines GL1 to GL4 can be disposed in multiple sub-pixels R, W, B, and G. That is, multiple gate lines GL1 to GL4 are disposed between the first sub-pixel B and the second sub-pixel R, or between the third sub-pixel W and the fourth sub-pixel G.

[0091] Specifically, odd-numbered gate lines GL1 and GL3 are positioned between the first sub-pixel B and the second sub-pixel R in odd-numbered columns (columns 4n-3 and 4n-1), and between the third sub-pixel W and the fourth sub-pixel G in even-numbered columns (columns 4n-2 and 4n). For example, the gate lines can be interwoven alternately between different sub-pixels within each sub-pixel unit based on whether the pixel unit is in an odd or even column (e.g., the arrangement of sub-pixels in odd-numbered columns can be slightly shifted downwards relative to the arrangement of sub-pixels in even-numbered columns, and the gate lines can intersect through the shifted arrangement of sub-pixels, see [reference]). Figure 3 ).

[0092] In other words, for a single pixel PX1 and PX2, an odd-numbered gate line GL1 and GL3 can be disposed between multiple sub-pixels R, W, G, and B. For example, the first gate line GL1 is disposed between the first sub-pixel B of the first pixel PX1 and the third sub-pixel W of the second pixel PX2, which are disposed in row 8m-7, and between the second sub-pixel R of the first pixel PX1 and the fourth sub-pixel G of the second pixel PX2, which are disposed in row 8m-6. Furthermore, the first gate line GL1 is connected to the first sub-pixel B and the second sub-pixel R of the first pixel PX1, and the third sub-pixel W and the fourth sub-pixel G of the second pixel PX2.

[0093] Even-numbered gate lines GL2 and GL4 can be positioned between the third sub-pixel W and the fourth sub-pixel G in odd-numbered columns (columns 4n-3 and 4n-1), and between the first sub-pixel B and the second sub-pixel R in even-numbered columns (columns 4n-2 and 4n).

[0094] In other words, for a given pixel PX1 or PX2, an even-numbered gate line GL2 can be disposed between multiple sub-pixels R, W, G, and B. For example, the second gate line GL2 is disposed between the first sub-pixel B of the second pixel PX2 and the third sub-pixel W of the first pixel PX1, which are disposed in row 8m-5, and between the second sub-pixel R of the second pixel PX2 and the fourth sub-pixel G of the first pixel PX1, which are disposed in row 8m-4. Furthermore, the second gate line GL2 is connected to the third sub-pixel W and the fourth sub-pixel G of the first pixel PX1, as well as the first sub-pixel B and the second sub-pixel R of the second pixel PX2.

[0095] Meanwhile, in the multiple sub-pixels R, W, B, G arranged in a column, each of the multiple gate lines GL1 to GL4 can be bent at the portion entering the multiple sub-pixels R, W, B, G arranged in adjacent columns.

[0096] That is, each of the multiple gate lines GL1 to GL4 can be bent between multiple sub-pixels R, W, B, G that are set to adjacent columns (gate line bending).

[0097] For example, odd-numbered gate lines GL1 and GL3 bend downwards as they pass through multiple first pixels PX1 and reach multiple second pixels PX2. Odd-numbered gate lines GL1 and GL3 bend upwards as they pass through multiple second pixels PX2 and reach multiple first pixels PX1.

[0098] Even-numbered gate lines GL2 and GL4 bend upwards as they pass through multiple first pixels PX1 and reach multiple second pixels PX2. Even-numbered gate lines GL2 and GL4 bend downwards as they pass through multiple second pixels PX2 and reach multiple first pixels PX1.

[0099] The display device according to an exemplary embodiment of the present disclosure is designed such that the second light-emitting diode RE of the second sub-pixel R and the third light-emitting diode WE of the third sub-pixel W, which emit a relatively large amount of light, are both relatively large. Therefore, the current intensity applied to the second light-emitting diode RE of the second sub-pixel R and the third light-emitting diode WE of the third sub-pixel W is reduced, thereby minimizing the degradation of the second sub-pixel R and the third sub-pixel W.

[0100] Therefore, the sizes of the second sub-pixel R and the third sub-pixel W can be larger than the sizes of the first sub-pixel B and the fourth sub-pixel G. Thus, each of the multiple gate lines GL1 to GL4 can be bent as it passes through the multiple first pixels PX1 and reaches the multiple second pixels PX2, or vice versa.

[0101] Meanwhile, each of the multiple gate lines GL1 to GL4 can be configured as a double layer including a first electrode layer and a second electrode layer.

[0102] The first electrode layer may be the same electrode layer as the gate electrode of the multiple transistors, and the second electrode layer may be the same electrode layer as the source electrode and drain electrode of the multiple transistors.

[0103] Furthermore, the second electrode can be the same electrode layer as the light-shielding layer disposed below the source and drain electrodes of the multiple transistors. However, the interlayer structure of the second electrode is not limited to this, and can be constructed from a metal layer disposed on a layer other than the gate electrodes of the multiple transistors.

[0104] The aforementioned transistors refer to Figure 2 At least one of the switching transistor SWT, driving transistor DT, and sensing transistor SET shown.

[0105] Meanwhile, in the planar diagram, the second electrode layer can be disposed between multiple sub-pixels R, W, B, and G. More specifically, the second electrode layer can be the same electrode layer as the source and drain electrodes of multiple transistors. Therefore, the second electrode layer does not need to be formed in the region where multiple gate lines GL1 to GL4 and multiple sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1, and SDL4-2 intersect.

[0106] Therefore, the second electrode layer can be formed only in the region where the multiple gate lines GL1 to GL4 do not intersect with the multiple sub-data lines SDL1-1, SDL1-2, SDL2-1, SDL2-2, SDL3-1, SDL3-2, SDL4-1, and SDL4-2, but the arrangement structure of the second electrode layer can have various forms.

[0107] In other words, each of the multiple gate lines GL1 to GL4 can be formed as a double-layer line constructed from a first electrode layer and a second electrode layer. Therefore, the linear resistance of the multiple gate lines GL1 to GL4 can be reduced. For example, by forming each of the multiple gate lines GL1 to GL4 as a double-layer line, the linear resistance can be reduced compared to a single-layer wiring line. Therefore, the total resistance of the gate lines is reduced, thereby reducing the RC delay of the gate voltage. Consequently, the charging rate of the gate voltage can be increased.

[0108] Figure 4 It is the waveform of the gate voltage of the display device according to an exemplary embodiment of the present disclosure.

[0109] In existing display devices, the gate line is formed by a single layer of wire, which allows for a relatively low charging speed of the gate voltage. For example... Figure 4 As shown, in existing display devices, when the gate voltage reaches 20V, the rise time of the gate voltage is measured to be 4.03μs.

[0110] Conversely, in the display device according to an exemplary embodiment of the present disclosure, the wiring is formed as a double-layered line, allowing for a relatively low charging rate of the gate voltage. For example... Figure 4 As shown, in a display device according to an exemplary embodiment of the present disclosure, when the gate voltage reaches 20V, the rise time of the gate voltage is measured to be 3.49μs.

[0111] In other words, the gate voltage rise time of the display device according to the exemplary embodiments of the present disclosure is shortened, thereby enabling faster charging of the gate voltage.

[0112] In the following text, reference will be made to Figures 5 to 7 A driving method for a display device according to an exemplary embodiment of the present disclosure is described.

[0113] Figure 5 This is a view used to explain the driving order in odd-numbered frames of a display device according to exemplary embodiments of the present disclosure.

[0114] Figure 6 This is a view used to explain the driving order in even-numbered frames of a display device according to exemplary embodiments of the present disclosure.

[0115] Figure 7 This is a view used to explain the charging rate of the data voltage of the display device according to an exemplary embodiment of the present disclosure.

[0116] Despite Figure 5 and Figure 6 For ease of description, the vertically arranged data lines, reference voltage lines, and high-potential voltage lines are not shown, but their placement is similar to that of the data lines, reference voltage lines, and high-potential voltage lines. Figure 3 The same as described in [the text].

[0117] like Figure 5 and Figure 6 As shown, a horizontal stripe pattern is described, wherein multiple sub-pixels R, G, B, W set in rows 8m-7 and 8m-4 emit light, and multiple sub-pixels R, G, B, W set in rows 8m-3 and 8m do not emit light.

[0118] In the following text, although the data charging rates of multiple second sub-pixels R will be described in detail, the same principles as those for the data charging rates of multiple second sub-pixels R will be used to describe the data charging rates of multiple first sub-pixels B, multiple third sub-pixels W, and multiple fourth sub-pixels G.

[0119] like Figure 7 As shown, when displaying a horizontal stripe pattern, the charging rate of the third data voltage DATA3 can increase during the first horizontal period (1) and the second horizontal period (3), and the charging rate of the third data voltage DATA3 can decrease during the third horizontal period (3) and the fourth horizontal period (4). The charging rate waveform of the third data voltage DATA3 can be repeated.

[0120] exist Figure 5 and Figure 6 In the odd-numbered frames, the turn-on sequence of multiple gate lines GL1, GL2, GL3, and GL4 can be different from that of multiple gate lines GL1, GL2, GL3, and GL4 in the even-numbered frames.

[0121] Specifically, the first gate line GL1, the second gate line GL2, the fourth gate line GL4, and the third gate line GL3 are turned on sequentially in odd-numbered frames, and the second gate line GL2, the first gate line GL1, the third gate line GL3, and the fourth gate line GL4 are turned on sequentially in even-numbered frames.

[0122] Meanwhile, the turn-on sequence of multiple gate lines GL1, GL2, GL3, and GL4 in odd-numbered frames can be switched to the turn-on sequence of multiple gate lines GL1, GL2, GL3, and GL4 in even-numbered frames.

[0123] For example, refer to Figure 5 During odd-numbered frames, in the first horizontal period (1), the first gate voltage GATE1 is applied to the first gate line GL1 which is at the on level to charge the second sub-pixel R located in the 8m-6 row using the data voltage.

[0124] During odd frames, in the second horizontal period (2), the second gate voltage GATE2 is applied to the second gate line GL2 which is at the on level to charge the second sub-pixel R located in the 8m-4 row using the data voltage.

[0125] During odd-numbered frames, in the third horizontal period (3), the fourth gate voltage GATE4 is applied to the fourth gate line GL4 which is at the on level to charge the second sub-pixel R located in the 8m row using the data voltage.

[0126] During odd-numbered frames, in the fourth horizontal period (4), the third gate voltage GATE3 is applied to the third gate line GL3, which is at the on level, to charge the second sub-pixel R located in row 8m-2 using the data voltage. In other words, referencing Figure 5 and Figure 6 Each specific color subpixel (e.g., see red RE) within four adjacent pixel units (e.g., each pixel unit comprises four subpixels) can be arranged in a quadrilateral (e.g., parallelogram) shape, and for even and odd frames, the quadrilateral arrangement of subpixels in four different pixel units of the same color can be driven alternately. For example, the quadrilateral arrangement of subpixels of the same color can be driven in a clockwise firing sequence during even frames and in a counterclockwise firing sequence during odd frames. Moreover, the alternating clockwise / counterclockwise firing sequence of the four subpixels can always be initiated at the same subpixel, or can be initiated alternately at different subpixels based on whether it is an odd or even frame (e.g., in...). Figure 5 In the middle, the red sub-pixel RE in the upper left corner begins to emit first during odd-numbered frames, while... Figure 6In the diagram, the red subpixel RE in the upper right corner begins to emit first during even-numbered frames. Furthermore, different subpixels in the quadrilateral arrangement of subpixels can be selected as the starting subpixel each time, or randomly selected for each subsequent frame. Thus, even when displaying very specific or difficult patterns (such as horizontal stripes or checkerboard images), the implemented invention can improve the brightness uniformity between pixel units that are close to each other.

[0127] refer to Figure 6 During even-numbered frames, in the first horizontal period (1), the second gate voltage GATE2 is applied to the second gate line GL2 which is at the on level, so as to charge the second sub-pixel R located in the 8m-4 row using the data voltage.

[0128] During even frames, in the second horizontal period (2), the first gate voltage GATE1 is applied to the first gate line GL1 which is at the on level to charge the second sub-pixel R located in the 8m-6 row using the data voltage.

[0129] During even-numbered frames, in the third horizontal period (3), the third gate voltage GATE3 is applied to the third gate line GL3 which is at the on level to charge the second sub-pixel R located in the 8m-2 row using the data voltage.

[0130] During even-numbered frames, in the fourth horizontal period (4), the fourth gate voltage GATE4 is applied to the fourth gate line GL4 which is at the on level to charge the second sub-pixel R located in the 8m row using the data voltage.

[0131] As mentioned above, when implementing vertical stripe patterns, the following will be further referenced. Figure 7 Describes the data charging rate of multiple second sub-pixels R.

[0132] During odd-numbered frames, in the first horizontal period (1) at the start of data voltage charging, the data charging rate of the second sub-pixel R in row 8m-6 can be 70% (weak charging).

[0133] During odd-numbered frames, in the second horizontal period (2) after the charging of the data voltage ends, the charging rate of the second sub-pixel R set in row 8m-4 can be 100% (strong charging).

[0134] During odd-numbered frames, in the third level period (3) and the fourth level period (4) when the data voltage is discharged, the charging rate of the second sub-pixel R set in the 8m-2 row and the second sub-pixel R set in the 8th row can be 0%.

[0135] During even-numbered frames, in the first horizontal period (1) at the start of data voltage charging, the data charging rate of the second sub-pixel R in row 8m-4 can be 70% (weak charging).

[0136] During even-numbered frames, in the second horizontal period (2) after the charging of the data voltage ends, the charging rate of the second sub-pixel R in row 8m-6 can be 100% (strong charging).

[0137] During even-numbered frames, in the third level period (3) and the fourth level period (4) when the data voltage is discharged, the charging rate of the second sub-pixel R set in the 8m row and the second sub-pixel R set in the 8m-2 row can be 0%.

[0138] In summary, the data charging rate of the second sub-pixel R in row 8m-4 is 100% (strong charging) during odd-numbered frames and 70% (weak charging) during even-numbered frames. Therefore, the average data charging rate of the second sub-pixel R in row 8m-4 can be 85%.

[0139] The data charge rate of the second sub-pixel R in row 8m-6 is 100% (strong charge) during even frames and 70% (weak charge) during odd frames. Therefore, the average data charge rate of the second sub-pixel R in row 8m-6 can be 85%.

[0140] Therefore, the display device according to an exemplary embodiment of this disclosure sets a different gate turn-on sequence for each frame so that the average data charge rate of the sub-pixels emitting light from the vertical stripe pattern is set to be the same. For example, even when displaying difficult patterns (such as horizontal stripes or checkerboard patterns), line defects can be prevented, and viewers can experience high image quality and realism.

[0141] Therefore, in the display device according to an exemplary embodiment of the present disclosure, no line defects are generated even in a specific pattern, and the pattern can be implemented accurately. As a result, the image quality of the display device according to another exemplary embodiment of the present disclosure can be improved.

[0142] Exemplary embodiments of this disclosure can also be described as follows:

[0143] According to one aspect of this disclosure, a display device includes: a display panel having a plurality of pixels, the plurality of pixels including a plurality of sub-pixels of different colors; a data driver configured to supply data voltage to the plurality of pixels via a plurality of data lines; and a gate driver configured to supply gate signals to the plurality of pixels via a plurality of gate lines, wherein the plurality of sub-pixels are sequentially arranged in the same column, each of the plurality of data lines is divided into a plurality of sub-data lines, and each of the plurality of sub-data lines is disposed on both sides of the plurality of sub-pixels sequentially arranged in the same column.

[0144] The arrangement order of multiple sub-pixels in odd-numbered columns can be different from the arrangement order of multiple sub-pixels in even-numbered columns.

[0145] Multiple sub-pixels may include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in sequence. The first sub-pixel may include a first light-emitting diode and a first circuit element. The second sub-pixel may include a second light-emitting diode and a second circuit element. The third sub-pixel may include a third light-emitting diode and a third circuit element. The fourth sub-pixel may include a fourth light-emitting diode and a fourth circuit element.

[0146] The display device may also include multiple reference voltage lines for sensing multiple pixels, and each of the multiple reference voltage lines may be disposed between a first light-emitting diode and a first circuit element, between a second light-emitting diode and a second circuit element, between a third light-emitting diode and a third circuit element, and between a fourth light-emitting diode and a fourth circuit element.

[0147] For each of the multiple sub-pixels, the first and third circuit elements can be configured to be opposite the second and fourth circuit elements with respect to multiple reference voltage lines.

[0148] Each of the multiple data lines may include a first data line configured to supply a first data voltage, a second data line configured to supply a second data voltage, a third data line configured to supply a third data voltage, and a fourth data line configured to supply a fourth data voltage. The first data line may be divided into a first-1 sub-data line and a first-2 sub-data line, the second data line may be divided into a second-1 sub-data line and a second-2 sub-data line, the third data line may be divided into a third-1 sub-data line and a third-2 sub-data line, and the fourth data line may be divided into a fourth-1 sub-data line and a fourth-2 sub-data line.

[0149] The 1-1 sub-data line can be set on one side of multiple sub-pixels set in odd-numbered columns. The 1-2 sub-data line can be set on the other side of multiple sub-pixels set in odd-numbered columns. The 2-1 sub-data line can be set on one side of multiple sub-pixels set in even-numbered columns. The 2-2 sub-data line can be set on the other side of multiple sub-pixels set in even-numbered columns. The 3-1 sub-data line can be set on one side of multiple sub-pixels set in odd-numbered columns. The 3-2 sub-data line can be set on the other side of multiple sub-pixels set in odd-numbered columns. The 4-1 sub-data line can be set on one side of multiple sub-pixels set in even-numbered columns. The 4-2 sub-data line can be set on the other side of multiple sub-pixels set in even-numbered columns.

[0150] The high-potential voltage line can be positioned between at least one of the first-2 sub-data lines and the third-2 sub-data lines and at least one of the second-1 sub-data lines and the fourth-1 sub-data lines, and the high-potential voltage line can be positioned between at least one of the first-1 sub-data lines and the third-1 sub-data lines and at least one of the second-2 sub-data lines and the fourth-2 sub-data lines.

[0151] Each of the multiple gate lines can be positioned between the first sub-pixel and the second sub-pixel, or between the third sub-pixel and the fourth sub-pixel.

[0152] The odd-numbered gate lines in the multiple gate lines can be positioned between the first and second sub-pixels in the odd-numbered columns, and can be positioned between the third and fourth sub-pixels in the even-numbered columns.

[0153] The even-numbered gate lines in the multiple gate lines can be positioned between the third and fourth sub-pixels in the odd-numbered columns, and can also be positioned between the first and second sub-pixels in the even-numbered columns.

[0154] The turn-on sequence of multiple gate lines in an even-numbered frame may differ from the turn-on sequence of multiple gate lines in an odd-numbered frame.

[0155] Multiple gate lines may include a first gate line, a second gate line, a third gate line, and a fourth gate line that can be sequentially configured. In even-numbered frames, the first gate line, the second gate line, the fourth gate line, and the third gate line can be turned on in this order, and in odd-numbered frames, the second gate line, the first gate line, the third gate line, and the fourth gate line can be turned on in this order.

[0156] Each of the multiple sub-pixels may include a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light-emitting diode, and the sensing transistor outputs a voltage used to sense the threshold voltage and mobility of the driving transistor to a reference voltage line.

[0157] Each of the multiple gate lines can be constructed with a double layer including a first electrode layer and a second electrode layer. The first electrode layer can be the same layer as the gate electrode of the switching transistor, the driving transistor, and the sensing transistor, and the second electrode layer can be the same layer as the source electrode and the drain electrode of the switching transistor, the driving transistor, and the sensing transistor.

[0158] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within the scope of their equivalents should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel is provided with a plurality of pixels, the plurality of pixels including a plurality of sub-pixels with different colors; A data driver is configured to supply data voltage to the plurality of pixels via multiple data lines; as well as A gate driver is configured to supply gate signals to the plurality of pixels via multiple gate lines. The plurality of sub-pixels are arranged sequentially in the same column, and the corresponding light-emitting elements of the plurality of sub-pixels arranged in the same column are arranged in a zigzag pattern. Each of the multiple data lines is divided into a pair of sub-data lines, and The pair of sub-data lines are positioned on both sides of the plurality of sub-pixels in the corresponding column.

2. The display device according to claim 1, in, The arrangement order of the multiple sub-pixels in the odd-numbered columns is different from the arrangement order of the multiple sub-pixels in the even-numbered columns.

3. The display device according to claim 1, in, The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in sequence. The first sub-pixel includes a first light-emitting diode and a first circuit element. The second sub-pixel includes a second light-emitting diode and a second circuit element. The third sub-pixel includes a third light-emitting diode and a third circuit element. The fourth sub-pixel includes a fourth light-emitting diode and a fourth circuit element.

4. The display device according to claim 3, further comprising: Multiple reference voltage lines of the multiple pixels are sensed. Each of the plurality of reference voltage lines is disposed between the first light-emitting diode and the first circuit element, between the second light-emitting diode and the second circuit element, between the third light-emitting diode and the third circuit element, and between the fourth light-emitting diode and the fourth circuit element.

5. The display device according to claim 4, in, For each of the plurality of sub-pixels, the first circuit element and the third circuit element are configured to be opposite the second circuit element and the fourth circuit element with respect to the plurality of reference voltage lines.

6. The display device according to claim 3, in, Each of the plurality of data lines includes a first data line configured to supply a first data voltage, a second data line configured to supply a second data voltage, a third data line configured to supply a third data voltage, and a fourth data line configured to supply a fourth data voltage. The first data line is divided into sub-data line 1-1 and sub-data line 1-2. The second data line is divided into sub-data line 2-1 and sub-data line 2-2. The third data line is divided into the 3-1 sub-data line and the 3-2 sub-data line, and The fourth data line is divided into the 4-1 sub-data line and the 4-2 sub-data line.

7. The display device according to claim 6, in, The first-1 sub-data line is disposed on one side of the plurality of sub-pixels arranged in the odd-numbered columns, and the first-2 sub-data line is disposed on the other side of the plurality of sub-pixels arranged in the odd-numbered columns. The second-1st sub-data line is disposed on one side of the plurality of sub-pixels arranged in the even-numbered columns, and the second-2nd sub-data line is disposed on the other side of the plurality of sub-pixels arranged in the even-numbered columns. The 3-1st sub-data line is disposed on one side of the plurality of sub-pixels arranged in the odd-numbered columns, and the 3-2nd sub-data line is disposed on the other side of the plurality of sub-pixels arranged in the odd-numbered columns. The 4-1 sub-data line is disposed on one side of the plurality of sub-pixels disposed in the even-numbered columns, and the 4-2 sub-data line is disposed on the other side of the plurality of sub-pixels disposed in the even-numbered columns.

8. The display device according to claim 6, in, A high-potential voltage line is positioned between at least one of the first-2 sub-data lines and the third-2 sub-data lines and at least one of the second-1 sub-data lines and the fourth-1 sub-data lines, and A high-potential voltage line is disposed between at least one of the first-1 sub-data line and the third-1 sub-data line and at least one of the second-2 sub-data line and the fourth-2 sub-data line.

9. The display device according to claim 3, in, Each of the plurality of gate lines is disposed between the first sub-pixel and the second sub-pixel or between the third sub-pixel and the fourth sub-pixel.

10. The display device according to claim 3, in, The odd-numbered gate lines are disposed between the first and second sub-pixels in the odd-numbered columns, and between the third and fourth sub-pixels in the even-numbered columns.

11. The display device according to claim 3, in, The even-numbered gate lines are disposed between the third and fourth sub-pixels in the odd-numbered columns, and between the first and second sub-pixels in the even-numbered columns.

12. The display device according to claim 1, in, The turn-on sequence of the multiple gate lines in even-numbered frames is different from the turn-on sequence of the multiple gate lines in odd-numbered frames.

13. The display device according to claim 12, in, The plurality of gate lines include a first gate line, a second gate line, a third gate line, and a fourth gate line arranged in sequence. In the even-numbered frames, the first gate line, the second gate line, the fourth gate line, and the third gate line are turned on in this order, and in the odd-numbered frames, the second gate line, the first gate line, the third gate line, and the fourth gate line are turned on in this order.

14. The display device according to claim 1, in, Each of the plurality of sub-pixels includes: Switching transistors, driving transistors, storage capacitors, sensing transistors, and light-emitting diodes, and The sensing transistor outputs a voltage to the reference voltage line, which is used to sense the threshold voltage and mobility of the driving transistor.

15. The display device according to claim 14, in, Each of the plurality of gate lines is constructed in a double-layer configuration, comprising a first electrode layer and a second electrode layer. The first electrode layer is the same as the gate electrode of the switching transistor, the driving transistor, and the sensing transistor, and the second electrode layer is the same as the source and drain electrodes of the switching transistor, the driving transistor, and the sensing transistor.

16. A display device, comprising: The display panel includes a plurality of sub-pixels, the plurality of sub-pixels having a first group of sub-pixels arranged in a first column that are adjacent to a second group of sub-pixels arranged in a second column; A data driver is configured to supply data voltage to the plurality of sub-pixels via multiple data lines; A gate driver is configured to supply gate signals to the plurality of sub-pixels via a plurality of gate lines; as well as A timing controller is configured to control the data driver and the gate driver. The first group of sub-pixels is arranged in a first zigzag pattern. The second group of sub-pixels is arranged as a second zigzag pattern that is vertically shifted relative to the first zigzag pattern, and The timing controller is configured as follows: The first emission sequence in the odd-numbered frames drives the sub-pixels of the first and second groups that have the same color. The first and second groups of sub-pixels with the same color are driven according to a second emission sequence in even-numbered frames, the second emission sequence being different from the first emission sequence.

17. The display device according to claim 16, wherein, When the same horizontal stripe pattern is displayed, the subpixels with the same color have the same average charge rate across the set of even and odd frames.

18. The display device according to claim 16, wherein, The first group of sub-pixels includes a first pixel unit and a second pixel unit, and each of the first pixel unit and the second pixel unit includes a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a fourth color sub-pixel. The second group of sub-pixels includes a third pixel unit and a fourth pixel unit, each of which includes a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a fourth color sub-pixel. The first color sub-pixel of the first pixel unit, the first color sub-pixel of the second pixel unit, the first color sub-pixel of the third pixel unit, and the first color sub-pixel of the fourth pixel unit emit light of the same color and are arranged in a quadrilateral shape.

19. The display device according to claim 18, wherein, The timing controller is further configured to: During odd-numbered frames, the first color sub-pixels of the first pixel units, the second pixel units, the third pixel units, and the fourth pixel units, arranged in the quadrilateral shape, are driven according to a clockwise emission pattern. During even-numbered frames, the first color sub-pixels of the first pixel unit, the first color sub-pixels of the second pixel unit, the first color sub-pixels of the third pixel unit, and the first color sub-pixels of the fourth pixel unit, which are arranged in the quadrilateral shape, are driven according to a counter-clockwise emission pattern.

20. The display device according to claim 19, wherein, The timing controller is further configured to: In the clockwise emission pattern, a sub-pixel is selected as the initial emission element from the first color sub-pixels of the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit, which are arranged in the quadrilateral shape. In the counter-clockwise emission pattern, different sub-pixels are selected as the initial emission elements from the first color sub-pixels of the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit, which are arranged in the quadrilateral shape. Wherein, the one sub-pixel and the different sub-pixels do not correspond to the same sub-pixel among the first color sub-pixels of the first pixel unit, the first color sub-pixels of the second pixel unit, the first color sub-pixels of the third pixel unit, and the first color sub-pixels of the fourth pixel unit arranged in the quadrilateral shape.

21. The display device according to claim 18, wherein, The timing controller is further configured to: During odd-numbered frames, the first color sub-pixels of the first pixel units, the second pixel units, the third pixel units, and the fourth pixel units, arranged in the quadrilateral shape, are driven according to a counter-clockwise emission pattern. During even-numbered frames, the first color sub-pixels of the first pixel unit, the first color sub-pixels of the second pixel unit, the first color sub-pixels of the third pixel unit, and the first color sub-pixels of the fourth pixel unit, which are arranged in the quadrilateral shape, are driven according to a clockwise emission pattern.

22. The display device according to claim 17, further comprising: A voltage reference line is provided, which is positioned along the center of the first zigzag pattern of the first group of sub-pixels. Among the multiple data lines, the first data line branches into a first sub-data line and a second sub-data line. The first sub-data line is disposed on one side of the first zigzag pattern, and the second sub-data line is disposed on the other side of the first zigzag pattern.

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