Clock synchronization method and apparatus

Abstract

The application discloses a clock synchronization method and device, wherein the clock synchronization method comprises the following steps: presetting a first field on an incoming direction port table; the first field defines whether a peer chip of an incoming direction connection is a chip supporting a synchronization domain; presetting a second field on an outgoing direction port table; the second field defines whether a peer chip of an outgoing direction connection is a chip supporting a synchronization domain; and according to a logical combination of the first field and the second field, a CF value of a PTP message is selected to be updated to adapt to a chip stacking system in a synchronization domain or a non-synchronization domain. Through the device and the method, the problems of low time precision or poor system expansion of an existing PTP TC clock synchronization mechanism can be solved.

Description

Technical Field

[0001] This invention relates to network communication technology, and in particular to a clock synchronization method and apparatus. Background Technology

[0002] The clock synchronization mechanisms of Precision Time Protocol (PTP) in current chip stacking systems include the following typical schemes:

[0003] (1) In a discrete chip, the individual chips cannot be guaranteed to be powered on at the same time, nor is internal time synchronization between chips performed. In this case, each chip maintains its own local timestamp. Each chip obtains its dwell time ΔT by subtracting the in-direction timestamp from its local out-direction timestamp. For the latency on the interconnected port lines between the chips, static compensation is performed on each port by static configuration (the static configuration value may be obtained by another mechanism and may be updated periodically, but it is impossible to be accurate in real time).

[0004] This method allows each chip to operate independently, resulting in simple configuration. Each chip's timestamp only needs to be maintained individually, ensuring that the dwell time (measured in nanoseconds) obtained by subtracting the input time from the local output time is accurate. However, older chips using this method typically do not support time synchronization within a stacked system based on Time-of-Depth (ToD) time. Its drawback is that, because the compensation value is statically configured, it cannot reflect jitter caused by devices at the port, leading to relatively lower time accuracy.

[0005] (2) While it is impossible for all chips to power on at the same time, they will synchronize their internal time in real time. A typical application is in the backplane frame, where the clock card broadcasts clock information to each service chip in real time through backplane traces, so that the time of each chip is basically consistent.

[0006] At this point, to calculate the dwell time, simply subtract the inbound timestamp of the entry chip from the original CF value, and add the outbound timestamp to the CF on the exit chip to obtain the complete dwell time for entering and exiting the entire stack system.

[0007] This method has good accuracy, but its disadvantage is that it requires a unified clock card for clock synchronization between chips, and each chip needs a unified clock synchronization line or internal synchronization mechanism, which makes it inconvenient to expand. Summary of the Invention

[0008] The technical problem to be solved by the embodiments of the present invention is how to solve the problems of low time accuracy or poor system scalability of the existing PTP TC clock synchronization mechanism.

[0009] To address the aforementioned technical problems, embodiments of the present invention provide a clock synchronization method applied to the stacking port of a chip stacking system, comprising: pre-setting a first field in the inbound port table; the first field defining whether the peer chip connected in the inbound direction supports the synchronization domain; and pre-setting a second field in the outbound port table; the second field defining whether the peer chip connected in the outbound direction supports the synchronization domain; and updating the CF value of the PTP message according to a logical combination of the first field and the second field to adapt to the chip stacking system of synchronization domain or non-synchronization domain.

[0010] In the above clock synchronization method, the step of selecting to update the CF value of the PTP message according to the first field and the second field includes: when both the first field and the second field are negative, calculating the dwell time of the chip and adding it to the CF value of the PTP message.

[0011] In the above clock synchronization method, the step of selecting to update the CF value of the PTP packet according to the first field and the second field includes: when the first field is negative and the second field is positive, calculating the CF value of the PTP packet minus the inbound timestamp and updating it to the CF value of the PTP packet.

[0012] In the above clock synchronization method, the step of selecting to update the CF value of the PTP message according to the first field and the second field includes: when the first field is yes and the second field is no, calculating the CF value of the PTP message plus the outgoing timestamp and updating it to the CF value of the PTP message.

[0013] In the above clock synchronization method, the step of selecting to update the CF value of the PTP packet according to the first field and the second field includes: when both the first field and the second field are true, the CF value of the PTP packet remains unchanged.

[0014] To address the aforementioned technical problems, this invention also provides a clock synchronization device applied to the stacking port of a chip stacking system, comprising: a setting unit for presetting a first field in an inbound port table; the first field defining whether the peer chip connected in the inbound direction is a chip that supports the synchronization domain; and a second field in an outbound port table; the second field defining whether the peer chip connected in the outbound direction is a chip that supports the synchronization domain; and a processing unit for selecting to update the CF value of a PTP packet based on the first field and the second field.

[0015] In the aforementioned clock synchronization device, the processing unit is used to: calculate the dwell time of the chip when both the first field and the second field are negative, and add it to the CF value of the PTP message.

[0016] In the aforementioned clock synchronization device, the processing unit is configured to: when the first field is negative and the second field is positive, calculate the CF value of the PTP message minus the inbound timestamp, and update the CF value of the PTP message.

[0017] In the aforementioned clock synchronization device, the processing unit is configured to: when the first field is yes and the second field is no, calculate the CF value of the PTP message, add the outgoing direction timestamp, and update the CF value of the PTP message.

[0018] In the aforementioned clock synchronization device, the processing unit is configured to: keep the CF value of the PTP message unchanged when both the first field and the second field are true.

[0019] This invention addresses the problems in existing technologies by defining the roles of peer chips and configuring ports in the inbound and outbound directions. This allows for the selection of which to update the CF value of PTP packets based on a combination of preset fields. This adaptively achieves synchronization for synchronization domains capable of real-time inter-chip time synchronization, or for asynchronous domains where latency is calculated based on local time. This invention supports mixed connections of chips with different synchronization types, is simple to configure, and greatly improves system compatibility. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an application environment topology for the clock synchronization method in this embodiment. Detailed Implementation

[0021] In existing technologies, the clock synchronization mechanism of PTP TC in chip stacking systems mainly includes two methods. One is that each chip maintains its own local timestamp. Each chip obtains its dwell time ΔT by subtracting the inbound timestamp from its local outbound timestamp. For the latency on the interconnecting ports between the chips, static compensation is performed on each port. The other is to perform real-time internal time synchronization between chips and broadcast clock information to each service chip in real time, so that the time between the chips is basically consistent.

[0022] However, both methods have their drawbacks. The first method has relatively poor time accuracy, while the second method has better accuracy but requires a unified clock card for clock synchronization between chips. Each chip needs a unified clock synchronization line or an internal synchronization mechanism, which makes it inconvenient to expand.

[0023] This invention addresses the problems in existing technologies by defining the roles of peer chips and configuring ports in the inbound and outbound directions. This allows for the selection of which to update the CF value of PTP packets based on a combination of preset fields, thus adaptively adapting to synchronization domains that can perform real-time inter-chip time synchronization or to asynchronous domains that calculate latency based on local time. This invention supports mixed connections of chips with different synchronization types, is simple to configure, and enables unified timestamp synchronization in a stacked environment. Furthermore, it allows for mixed connections with older discrete chips, significantly improving compatibility.

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Example 1

[0026] This invention discloses a clock synchronization method applicable to a chip stacking system that uses PTP for time synchronization. The chip supports PTP 1-step transparent clock (TC) and can receive synchronization messages from an ordinary clock (OC). The PTP Sync message contains two fields: TS and CF. The TS field is in ToD (Time-of-Day) format (s+ns), 48 bits + 32 bits, where ns returns to 0 upon reaching 10^9 and carries over to the seconds place. The CF field is in pure ns format (48 bits, value range [0, 2^48-1]). Specifically, the clock synchronization method includes:

[0027] Step S101: Preset a first field in the inbound port table;

[0028] The inbound port table is indexed by port number and can be a physical port table or a logical port table that maps the index using Port and packet VLAN information. The first field S1 defines whether the peer chip connected in the inbound direction is a chip that supports the synchronization domain. A chip that supports the synchronization domain is a chip that has the function of supporting the synchronization domain and has enabled the function; while a chip that does not support the synchronization domain may be a chip that does not support the synchronization domain function, or a chip that has the function but has not enabled the function in actual application. The function of supporting the synchronization domain refers to whether it can support dwell time updates. If it cannot support it, it indicates that the peer is a separate chip in the background technology (1); if it can support it, it is a chip in the background technology (2) that can realize internal time synchronization between chips. If the inbound port is a stacked port and the peer connected is a chip that supports end-to-end dwell time updates, the first field S1 is set to 1; otherwise, it is set to 0.

[0029] It is understood that the chip stacking system of this embodiment of the invention has a stacking port, so if it is a non-stacked port, the first field S1 will not be set.

[0030] Step S102: Preset a second field in the outgoing port table;

[0031] The outgoing port table is indexed by port number and can be a physical port table or a logical port table mapped by combining port information with packet VLAN information. The second field S2 defines whether the peer chip in the outgoing connection supports dwell time updates, i.e., whether it supports and has enabled the synchronization domain function. If the outgoing port is a stacked port and the peer chip supports end-to-end dwell time updates, then the second field S2 is set to 1; otherwise, it is set to 0.

[0032] It is understood that the chip stacking system of this embodiment of the invention has a stacking port, so if it is a non-stacked port, the second field S2 will not be set.

[0033] Step S103: Based on the first field and the second field, select to update the CF value of the PTP message.

[0034] When a PTP Sync message enters the inbound chip, and if the outbound chip is across chips, it will enter another chip for processing, then S1 is carried in the stack header, and it is determined whether the dwell time needs to be updated in the CF field of the PTP Sync message.

[0035] At this point, the CF value update action can be determined by the combinational logic of the concatenation operator {S1, S2}: (1) When {S1, S2} = 2'b00, that is, when the first field S1 and the second field S2 are both equal to 0, it is determined that the peer chip connected in the inbound direction and the peer chip connected in the outbound direction are both chips that do not support the synchronization domain function. Since chips that do not support the synchronization domain function, such as discrete chips, calculate the delay based on the local time, they cannot calculate the delay to be added to the CF across devices. Therefore, at this time, the dwell time (Tegress-Tingress) of this chip is calculated and added to the CF value of the message, that is, CFnew = CFold + Tegress-Tingress. The dwell time is measured in ns.

[0036] In practical applications, the actual deployment will have a positive and negative correction value for the Path Delay on the port. As an independent configurable item on the port, the positive and negative correction value of the Path Delay can be optionally added or subtracted into CF.

[0037] (2) When {S1, S2} = 2'b01, that is, when the first field S1 is 0 and the second field S2 is 1, it is determined that the peer chip connected in the inbound direction is a chip that does not support the synchronization domain, while the peer chip connected in the outbound direction is a chip that supports the synchronization domain. At this time, the inbound timestamp Tingress of this chip is subtracted from the CF value of the message (CFnew = CFold - Tingress). Here, Tingress needs to be converted from ToD format to pure ns format. Figure 1 As shown, Chips A, B, C, and D are chips that support dwell time updates (labeled "New Chip" in the diagram). Consecutive "New Chip" connections form a new stacking ring, constituting an end-to-end mechanism within the internal synchronization domain. Chips E and F are chips that do not support dwell time updates (labeled "Old Chips" in the diagram). Their connections with Chips A, B, C, and D constitute a hop-by-hop mechanism between non-internal synchronization domains. Taking Chip C as an example, this chip is the upper node of the stacking ring. When it receives a PTP Sync message from OC3, it updates CFold-Tingress to CFnew.

[0038] (3) {S1, S2} = 2'b11, meaning that when both the first field S1 and the second field S2 are 1, it is determined that the chips at the opposite ends of the input and output directions are chips that support the synchronization domain, and the CF value remains unchanged. For example... Figure 1 As shown, when ChipA receives a PTP Sync message from ChipC, or ChipB receives a PTP Sync message from ChipA and sends it to ChipD, since they are all chips belonging to the same synchronization domain, the CF in the PTP message can remain unchanged.

[0039] (4) When {S1, S2} = 2'b10, that is, when the first field S1 is 1 and the second field S2 is 0, it is determined that the peer chip connected in the inbound direction is a chip that supports the synchronization domain, while the peer chip connected in the outbound direction is a chip that does not support the synchronization domain. At this time, the inbound timestamp Tegress of this chip is added to the CF value of the message (CFnew = CFold + Tegress). Figure 1 As shown, ChipD is the next node. When a PTP Sync message is received from ChipB and sent to OC4, the outgoing timestamp Tegress of ChipD is added to obtain the time delay from the Chip C entry point to the Chip D exit point in the synchronization domain, thus completing the CF update.

[0040] This embodiment combines the role definition of port configuration with the corresponding {S1, S2} combinational logic to provide an end-to-end calculation mechanism within the internal synchronization domain and a hop-by-hop calculation mechanism between non-internal synchronization domains. Through this embodiment, the switching chip can support unified timestamp synchronization in a stacked environment and can also be hybridly connected with older discrete chips, greatly improving compatibility.

[0041] Example 2

[0042] To address the problems in the prior art, this embodiment also discloses a clock synchronization device, specifically comprising:

[0043] The setting unit is configured to preset a first field in the inbound port table; the first field defines whether the peer chip connected in the inbound direction is a chip that supports the synchronization domain; and to preset a second field in the outbound port table; the second field defines whether the peer chip connected in the outbound direction is a chip that supports the synchronization domain; and the processing unit is configured to select to update the CF value of the PTP packet according to the first field and the second field.

[0044] In a specific implementation, the processing unit is used to: calculate the dwell time of the chip when both the first field and the second field are negative, and add it to the CF value of the PTP message.

[0045] In a specific implementation, the processing unit is used to: when the first field is negative and the second field is positive, calculate the CF value of the PTP packet minus the inbound timestamp, and update the CF value of the PTP packet.

[0046] In a specific implementation, the processing unit is used to: when the first field is yes and the second field is no, calculate the CF value of the PTP packet, add the outgoing direction timestamp, and update the CF value of the PTP packet.

[0047] In a specific implementation, the processing unit is used to: keep the CF value of the PTP message unchanged when both the first field and the second field are true.

[0048] Those skilled in the art will understand that the clock synchronization device of this embodiment and the clock synchronization method of Embodiment 1 are based on the same inventive concept. Therefore, the relevant content of this embodiment can be referred to the corresponding content above, and will not be repeated here.

[0049] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include ROM, RAM, disk, or optical disk, etc.

[0050] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A clock synchronization method, characterized in that, Stacking ports used in chip stacking systems include: In the inbound port table, a first field is preset; the first field defines whether the peer chip connected in the inbound direction is a chip that supports the synchronization domain; and, In the outgoing port table, a second field is preset; the second field defines whether the peer chip of the outgoing connection is a chip that supports the synchronization domain. Based on the logical combination of the first field and the second field, the CF value of the PTP message is selected to be updated to adapt to the chip stacking system of synchronous domain or asynchronous domain. The step of updating the CF value of the PTP packet based on the first field and the second field includes: when both the first field and the second field are negative, calculating the dwell time of the chip and adding it to the CF value of the PTP packet; when the first field is negative and the second field is positive, calculating the CF value of the PTP packet minus the inbound timestamp and updating it to the CF value of the PTP packet; when the first field is positive and the second field is negative, calculating the CF value of the PTP packet plus the outbound timestamp and updating it to the CF value of the PTP packet; when both the first field and the second field are positive, keeping the CF value of the PTP packet unchanged.

2. A clock synchronization device, characterized in that, Stacking ports used in chip stacking systems include: The configuration unit is used to pre-define a first field in the inbound port table; the first field defines whether the peer chip connected in the inbound direction is a chip that supports the synchronization domain; and, In the outgoing port table, a second field is preset; the second field defines whether the peer chip in the outgoing direction connection is a chip that supports the synchronization domain; and, The processing unit is configured to select the CF value of the PTP packet to update based on the first field and the second field. The selection to update the CF value of the PTP packet based on the first field and the second field includes: when both the first field and the second field are negative, calculating the dwell time of the chip and adding it to the CF value of the PTP packet; when the first field is negative and the second field is positive, calculating the CF value of the PTP packet minus the inbound timestamp and updating it to the CF value of the PTP packet; when the first field is positive and the second field is negative, calculating the CF value of the PTP packet plus the outbound timestamp and updating it to the CF value of the PTP packet; when both the first field and the second field are positive, keeping the CF value of the PTP packet unchanged.

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