Output stage for an ethernet network transmitter

Abstract

An output stage of an Ethernet transmitter coupled with a resistor includes a first output terminal, a second output terminal, a first transistor and a first transistor group. The resistor is coupled between the first output terminal and the second output terminal. The first transistor has a first source coupled with a first reference voltage, a first drain coupled with the second output terminal and a first gate. The first transistor group is coupled with the first reference voltage and the first output terminal. The first transistor group includes a plurality of transistors connected in parallel, and the current flowing to the first output terminal is related to the number of the plurality of transistors turned on.

Description

Technical Field

[0001] This invention relates to Ethernet networks, and more particularly to impedance matching of the output stage of an Ethernet transmitter. Background Technology

[0002] Figure 1 is a schematic diagram of a conventional Ethernet transmitter circuit. The Ethernet transmitter circuit 120 includes a driver circuit 125, two feedback resistors Rf, and two termination resistors Rs. The feedback resistors Rf are coupled between the output terminal (vop / von) and the input terminal of the driver circuit 125. The termination resistors Rs are coupled between the output terminal (vop / von) and the output terminal (MDIP / MDIN). The output terminal (MDIP / MDIN) is the output port of a component (e.g., a chip), coupled to a load resistor RL, which is located outside the component. The main function of the Ethernet transmitter circuit 120 is to amplify the signal source 110 (e.g., the output signal of an amplifier) ​​and output the amplified signal from the output terminal (MDIP / MDIN).

[0003] Due to process drift, terminating resistors Rs typically require calibration. Figure 2 shows a schematic diagram of an existing terminating resistor Rs. The traditional calibration method involves providing multiple parallel resistor (R0~Rn)-switch (SW0~SWn) pairs. By controlling the conduction state of these switches (SW0~SWn), different equivalent resistance values ​​(i.e., the resistance value of the terminating resistor Rs) are generated. In Figure 2, switches SW0~SWn are implemented using transmission gates, and signals powb_h, pow_h, tap_h, and tapb_h are the control signals for these transmission gates.

[0004] However, transmission gates manufactured using advanced processes have lower withstand voltages and cannot withstand high voltages, so existing calibration methods are not suitable for advanced processes. Therefore, there is a need for an Ethernet transmitter circuit that can still calibrate the termination resistor Rs in advanced processes. Summary of the Invention

[0005] One of the objectives of this invention is to provide an output stage for an Ethernet transmitter to improve upon the shortcomings of prior art.

[0006] This invention provides an output stage of an Ethernet transmitter, coupled with a resistor, comprising: a first output terminal, a second output terminal, a first transistor, and a first transistor group. The resistor is coupled between the first output terminal and the second output terminal. The first transistor has a first source, a first drain, and a first gate; the first source is coupled to a first reference voltage, and the first drain is coupled to the second output terminal. The first transistor group is coupled to the first reference voltage and the first output terminal. The first transistor group includes multiple transistors connected in parallel, and the magnitude of the current flowing to the first output terminal is related to the number of transistors that are turned on.

[0007] The output stage of the Ethernet transmitter of this invention achieves characteristic impedance correction by adjusting the current. Compared with the prior art, since this invention does not correct the termination resistor by connecting a resistor in series with a transmission gate, it is suitable for advanced manufacturing processes.

[0008] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0009] Figure 1 is a schematic diagram of an existing Ethernet transmitter circuit;

[0010] Figure 2 is a schematic diagram of an existing termination resistor;

[0011] Figure 3 This is a simplified circuit diagram of the output stage of the Ethernet transmitter of the present invention;

[0012] Figure 4 This is a circuit diagram of the output stage of the Ethernet transmitter of the present invention; and

[0013] Figure 5 This is a circuit diagram of the output stage of the Ethernet transmitter of the present invention. Detailed Implementation

[0014] The technical terms used in the following description are conventional terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0015] The present invention discloses an output stage of an Ethernet transmitter. Since some components of the output stage of the Ethernet transmitter may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the invention.

[0016] In the following description, each transistor has a first terminal, a second terminal, and a control terminal. When a transistor is used as a switch, the first and second terminals are the two ends of the switch, and the control terminal controls whether the switch is turned on (transistor turned on) or off (transistor turned off). For a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the first terminal can be either the source or the drain, the second terminal is either the source or the drain, and the control terminal is the gate. For a bipolar junction transistor (BJT), the first terminal can be either the collector or the emitter, the second terminal is either the collector or the emitter, and the control terminal is the base.

[0017] Please see Figure 3 , Figure 3 This is a simplified circuit diagram of the Ethernet transmitter circuit of this invention. For ease of explanation, Figure 3 Only single-ended (i.e., corresponding to VOP or von in Figure 1) is shown. Voltages Vx and Vo are the output voltages of the driver circuit 320. Voltage Vx corresponds to the output terminals VOP or von in Figure 1, while voltage Vo corresponds to the output terminals MDIP or MDIN in Figure 1. The driver circuit 320 includes an operational amplifier 325, a transistor group MP1, and a transistor MPN, where the transistor group MP1 and transistor MPN constitute the output stage of the Ethernet transmitter circuit. One end of the operational amplifier 325 is coupled to a signal source 310. The output current of the transistor group MP1 is Im, while the output current of the transistor MPN is X*Im (i.e., the ratio of the two is 1:X, where the arrow on the number "1" indicates that the current Im is adjustable). The goal of the circuit design is to ensure that no current flows through the resistor Rss (i.e., Vx = Vo), therefore, Vo = (Im + X*Im)*RL = (1 + X)*Im*RL. Because (Assuming Rss >> RL), then Im * Rss = (1 + X) * Im * RL; therefore, Rss = (1 + X) * RL. In other words, from the outside, the characteristic impedance or output impedance of the Ethernet transmitter circuit is Rss / (1 + X). This invention fixes the resistor Rss and corrects the characteristic impedance of the output stage by adjusting the ratio (1:X). In other words, the resistor Rss is a simple resistor and does not include a switch; that is, there is no switch between the output terminal vop or von and the output terminal MDIP or MDIN, which may be implemented by a transistor, transmission gate, or other components.

[0018] Figure 3 This invention only displays single-ended signals; however, it is also applicable to differential signals. Circuitry for differential signals will be described below. Figure 4 Provide an explanation.

[0019] Please see Figure 4 , Figure 4 This is a circuit diagram of the output stage of the Ethernet transmitter of the present invention. The output stage 400 includes transistors MPN, MNN, MPCN, MNCN, MPC1, MNC1, transistor group MP1, and transistor group MN1. Transistor group MP1 includes transistor MP1_0, switch SWP1_0, transistor MP1_n, and switch SWP1_n. Transistor group MN1 includes transistor MN1_0, switch SWN1_0, transistor MN1_n, and switch SWN1_n. Figure 3 The magnitude of the current Im is related to the number of transistors turned on in transistor group MP1 and / or transistor group MN1, which will be described in detail below.

[0020] Please note that, for the sake of brevity and focusing on the present invention, Figure 4 The feedback resistor Rf is omitted. Those skilled in the art can [do something]. Figure 3 It is understood that the feedback resistor Rf should be placed in Figure 4 Where the circuit is located (e.g., between the output of a digital-to-analog converter (DAC) (not shown) and the output vop / von).

[0021] The source of transistor MPN is coupled or electrically connected to a first reference voltage (e.g., voltage source VDD); the gate of transistor MPN is coupled or electrically connected to node x. The source of transistor MNN is coupled or electrically connected to a second reference voltage (e.g., ground GND, VDD>GND); the gate of transistor MNN is coupled to node y. The source of transistor MPCN is coupled or electrically connected to the drain of transistor MPN; the drain of transistor MPCN is coupled or electrically connected to output terminal MDIP or MDIN; the gate of transistor MPCN is coupled or electrically connected to the receive voltage PMOS-biasP. The source of transistor MNCN is coupled or electrically connected to the drain of transistor MNN; the drain of transistor MNCN is coupled or electrically connected to output terminal MDIP or MDIN; the gate receive voltage NMOS-biasN of transistor MNCN. The drain of transistor MPC1 is coupled or electrically connected to output terminal vop or von; the gate receive voltage PMOS-biasP of transistor MPC1. The drain of transistor MNC1 is coupled or electrically connected to the output terminal vop or von; the gate receive voltage of transistor MNC1 is NMOS-biasN.

[0022] The source of transistor MP1_0 is coupled to or electrically connected to a first reference voltage; the drain of transistor MP1_0 is coupled to or electrically connected to the source of transistor MPC1; the gate of transistor MP1_0 is coupled to or electrically connected to node x (i.e., the gate of transistor MPN) and is coupled to the first reference voltage or signal vop_g via switch SWP1_0. Switch SWP1_0 is controlled by control signal powb_P_0.

[0023] The source of transistor MP1_n is coupled to or electrically connected to a first reference voltage; the drain of transistor MP1_n is coupled to or electrically connected to the source of transistor MPC1; the gate of transistor MP1_n is coupled to the first reference voltage or signal vop_g through switch SWP1_n. Switch SWP1_n is controlled by control signal powb_P_n.

[0024] The source of transistor MN1_0 is coupled to or electrically connected to a second reference voltage; the drain of transistor MN1_0 is coupled to or electrically connected to the source of transistor MNC1; the gate of transistor MN1_0 is coupled to or electrically connected to node y (i.e., the gate of transistor MNN) and is coupled to the second reference voltage or signal von_g via switch SWN1_0. Switch SWN1_0 is controlled by control signal powbb_N_0.

[0025] The source of transistor MN1_n is coupled to or electrically connected to a second reference voltage; the drain of transistor MN1_n is coupled to or electrically connected to the source of transistor MNC1; the gate of transistor MN1_n is coupled to the second reference voltage or signal von_g through switch SWN1_n. Switch SWN1_n is controlled by control signal powbb_N_n.

[0026] The aforementioned transistors (MP1_k or MN1_k) and switches (SWP1_k or SWN1_k) coupled to or electrically connected to their gates form a switch-transistor pair (0≦k≦n), while the output stage 400 includes 2*(n+1) switch-transistor pairs (n≧1) (i.e., Figure 3 Transistor group MP1 includes n+1 transistors MP1_0 to MP1_n and n+1 switches SWP1_0 to SWP1_n, and transistor group MN1 includes n+1 transistors MN1_0 to MN1_n and n+1 switches SWN1_0 to SWN1_n. When switch SWP1_k (or SWN1_k) switches to the first reference voltage (or the second reference voltage), the gate of transistor MP1_k (or MN1_k) receives the first reference voltage (or the second reference voltage) and is therefore turned off (not conducting). When switch SWP1_k (or SWN1_k) switches to the signal vop_g (or the signal von_g), the gate of transistor MP1_k (or MN1_k) receives the signal vop_g (or the signal von_g) and is turned on (conducting). The more (fewer) transistors are conducting, the greater (smaller) the current flowing through transistor group MP1 (i.e., equivalent to...). Figure 3 The larger (smaller) the current Im, the better. Therefore, it can be adjusted by controlling the switches (SWP1_0~SWP1_n and SWN1_0~SWN1_n). Figure 3 The ratio (1:X) is used to correct the characteristic impedance Rss / (1+X).

[0027] Please see Figure 5 , Figure 5 This is a circuit diagram of the output stage of the Ethernet transmitter of the present invention. Output stage 500 is a detailed embodiment of output stage 400, and more specifically, Figure 5 show Figure 4 The internal circuitry of switches SWP1_k and SWN1_k. Figure 5In the example, switch SWP1_k (or SWN1_k) includes two transistors. For example, switch SWP1_0 includes transistors MP1_0_vo and MP1_0_PWD. The source of transistor MP1_0_vo is coupled or electrically connected to node x and the gate of transistor MP1_0; the drain of transistor MP1_0_vo receives signal vop_g (i.e., coupled or electrically connected to a signal source (not shown)); the gate of transistor MP1_0_vo receives control signal powb_P_0. The source of transistor MP1_0_PWD is coupled or electrically connected to a first reference voltage; the drain of transistor MP1_0_PWD is coupled or electrically connected to node x and the gate of transistor MP1_0; the gate of transistor MP1_0_PWD receives control signal powbb_P_0. powb_P_0 and powbb_P_0 are each other's inverted signals. When the control signal powb_P_0 is high, transistor MP1_0_vo is not turned on while transistor MP1_0_PWD is turned on, causing transistor MP1_0 to be turned off (i.e., it does not contribute to the current Im). When the control signal powb_P_0 is low, transistor MP1_0_vo is turned on while transistor MP1_0_PWD is not turned on, causing transistor MP1_0 to be turned on and receive the signal vop_g (i.e., it contributes to the current Im). Those skilled in the art can understand the operating principles of other switches from the above discussion of switch SWP1_0, so they will not be described in detail here.

[0028] In some embodiments, the paired switches (i.e., SWP1_k and SWN1_k) are turned on or off together. For example, when the gate of transistor MP1_0 (or MP1_n) receives a first reference voltage, the gate of transistor MN1_0 (or MN1_n) receives a second reference voltage; when the gate of transistor MP1_0 (or MP1_n) receives signal vop_g, the gate of transistor MN1_0 (or MN1_n) receives signal von_g.

[0029] In some embodiments, transistors MP1_0 and MN1_0 are always on, while the other transistors (MP1_1 to MP1_n and MN1_1 to MN1_n) are turned on or off as needed (i.e., the aforementioned ratio (1:X)).

[0030] In practice, the user performs calibration by controlling multiple control signals (including powb_P_0, ..., powb_P_k, ..., powb_P_n, powbb_N_0, ..., powbb_N_k, ..., powbb_N_n). The control signals powbb_P_n, powb_N_0, and powb_N_n are the inverted versions of the control signals powb_P_n, powbb_N_0, and powbb_N_n, respectively.

[0031] Figure 4 and Figure 5 Transistors MPCN, MNCN, MPC1, and MNC1 are used for protection to prevent other transistors from being subjected to excessive voltage. PMOS-biasP and NMOS-biasN are the bias voltages of these transistors. In some embodiments, transistors MPCN, MNCN, MPC1, and MNC1 can be omitted if other transistors will not be subjected to excessive voltage.

[0032] Please note, Figure 4 and Figure 5 The dashed lines on the transistor indicate the base bias voltage of the transistor; however, this is only one implementation and the present invention is not limited thereto. Other base bias methods are also within the scope of the present invention.

[0033] In summary, the output stage of the Ethernet transmitter of the present invention includes multiple transistors connected in parallel, and the output current ratio is adjusted by controlling these multiple transistors to turn on or off (i.e., Figure 3 The ratio (1:X) is used to correct the characteristic impedance. Furthermore, since this invention does not correct the terminating resistor by connecting a resistor in series with a transmission gate (as shown in Figure 2), this invention is applicable to advanced processes. Of course, this invention is also applicable to non-advanced processes.

[0034] Please note that the shapes, sizes, and proportions of the components in the previously disclosed icons are merely illustrative to help those skilled in the art understand the present invention, and are not intended to limit the present invention.

[0035] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of the present invention.

[0036] Explanation of reference numerals in the attached figures:

[0037] 120: Ethernet Transmitter Circuit

[0038] 125, 320: Drive circuit

[0039] vop, von, MDIP, MDIN: Output terminals

[0040] Rf: Feedback resistor

[0041] Rs: Termination resistor

[0042] RL: Load resistor

[0043] 110, 310: Signal source

[0044] Vx, Vo, PMOS-biasP, NMOS-biasN: Voltage

[0045] 325: Operational Amplifier

[0046] MP1, MN1: Transistor groups

[0047] Im: Current

[0048] MPN, MNN, MPCN, MNCN, MPC1, MNC1, MP1_0, MP1_n, MN1_0, MN1_n, MP1_0_vo, MP1_0_PWD: transistor

[0049] R0, R1, R2, Rn, Rss: Resistors

[0050] SW0, SW1, SW2, SWn, SWP1_0, SWP1_n, SWN1_0, SWN1_n: switch

[0051] 400, 500: Output stage

[0052] VDD: Voltage source

[0053] GND: Ground

[0054] x, y: Nodes

[0055] vop_g, von_g: signals

[0056] powb_P_0, powb_P_n, powbb_N_0, powbb_N_n, powbb_P_0, powbb_P_n, powb_N_0, powb_N_n: Control signals

Claims

1. An output stage of an Ethernet transmitter, the output stage being coupled to a resistor and comprising: First output terminal; The second output terminal, wherein the resistor is coupled between the first output terminal and the second output terminal; A first transistor has a first source, a first drain, and a first gate, the first source being coupled to a first reference voltage, and the first drain being coupled to the second output terminal; and A first transistor group is coupled to the first reference voltage and the first output terminal; The first transistor group comprises multiple transistors connected in parallel, and the magnitude of the current flowing to the first output terminal is related to the number of transistors that are turned on. The first voltage at the first output terminal is substantially the same as the second voltage at the second output terminal, so that no current flows through the resistor.

2. The output stage according to claim 1, wherein, The first group of transistors includes: The second transistor has a second source, a second drain, and a second gate. The second source is coupled to the first reference voltage, the second drain is coupled to the first output terminal, and the second gate is coupled to the first gate.

3. The output stage according to claim 2, wherein, The first group of transistors also includes: The third transistor has a third source, a third drain, and a third gate. The third source is coupled to the first reference voltage, and the third drain is coupled to the first output terminal.

4. The output stage according to claim 3, wherein, The output stage receives signals, and the first transistor group also includes: A first switch, coupled to the second gate, causes the second gate to receive the first reference voltage or the signal according to a first control signal; and The second switch is coupled to the third gate, and the third gate receives the first reference voltage or the signal according to the second control signal.

5. The output stage according to claim 4, wherein, The first switch and the second switch each include: A fourth transistor has a fourth source, a fourth drain, and a fourth gate. The fourth source is coupled to the first reference voltage, and the fourth drain is coupled to either the second gate or the third gate. The fourth gate receives the inverted signal of the first control signal or the inverted signal of the second control signal. The fifth transistor has a fifth source, a fifth drain, and a fifth gate. The fifth source is coupled to the second gate or the third gate. The fifth drain receives the signal, and the fifth gate receives the first control signal or the second control signal.

6. The output stage according to claim 1, further comprising: The second transistor has a second source, a second drain and a second gate, the second source being coupled to a second reference voltage and the second drain being coupled to the second output terminal. as well as A second transistor group, coupled to the second reference voltage and the first output terminal, and comprising a plurality of transistors connected in parallel.

7. The output stage according to claim 6, wherein, The second group of transistors includes: The third transistor has a third source, a third drain, and a third gate. The third source is coupled to the second reference voltage, the third drain is coupled to the first output terminal, and the third gate is coupled to the second gate.

8. The output stage according to claim 7, wherein, The second transistor group also includes: The fourth transistor has a fourth source, a fourth drain, and a fourth gate, the fourth source being coupled to the second reference voltage, and the fourth drain being coupled to the first output terminal.

9. The output stage according to claim 8, wherein, The output stage receives signals, and the second transistor group also includes: A first switch, coupled to the third gate, causes the third gate to receive the second reference voltage or the signal according to a first control signal; and The second switch is coupled to the fourth gate, and the fourth gate receives the second reference voltage or the signal according to the second control signal.

10. The output stage according to claim 6, further comprising: The third transistor has a third source and a third drain, the third source being coupled to the first drain and the third drain being coupled to the second output terminal; The fourth transistor has a fourth source and a fourth drain, the fourth source being coupled to the second drain and the fourth drain being coupled to the second output terminal; The fifth transistor has a fifth source and a fifth drain, the fifth source being coupled to the first transistor group and the fifth drain being coupled to the first output terminal; as well as The sixth transistor has a sixth source and a sixth drain, the sixth source being coupled to the second transistor group and the sixth drain being coupled to the first output terminal.

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