Test method, test device and electronic equipment for central processing unit power supply

Abstract

Embodiments of the present application provide a kind of central processing unit power supply test method, testing device and electronic equipment, wherein the method comprises: determining whether there is contact bad phenomenon between test equipment and central processing unit;In the case where there is contact bad phenomenon between test equipment and central processing unit, error impedance value is determined;According to error impedance value and target impedance value, actual impedance value is determined;At least according to actual impedance value, first near-end voltage and first far-end voltage are determined respectively.Through the present application, the problem that the accuracy of CPU power supply test result is not high is solved, and then the effect of improving CPU power supply test is achieved.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method for testing a central processing unit (CPU) power supply, a CPU power supply testing apparatus, a computer-readable storage medium, and an electronic device. Background Technology

[0002] With the continuous development of the internet industry, the demand for server production capacity is gradually increasing, and more and more server brands are emerging. Among them, the most representative is the server from Advanced Micro Devices (AMD). AMD's Central Processing Unit (CPU) has been updated to the Genoa E generation, and a matching CPU power supply testing tool—the StarDustLoad Emulator (SDLE)—has also been launched. SDLE applies the load directly to the CPU side by directly covering the load pod (LP) with the voltage regulator (Load Pod), resulting in a simpler structure.

[0003] However, in practical applications, poor contact often occurs between the CPU pins and the power supply (LP), which leads to additional line losses and affects the accuracy of CPU power supply test results.

[0004] Therefore, there is an urgent need for a method to solve the problem of inaccurate CPU power supply test results. Summary of the Invention

[0005] This application provides a method for testing a central processing unit (CPU) power supply, a CPU power supply testing device, a computer-readable storage medium, and an electronic device, to at least solve the problem of low accuracy of power supply test results in related technologies.

[0006] According to one embodiment of this application, a method for testing a central processing unit (CPU) power supply is provided. The CPU is a server CPU. The testing method includes: determining whether there is poor contact between a testing device and the CPU, wherein the testing device is used to test the CPU; and, if poor contact exists between the testing device and the CPU, determining an error impedance value, wherein the error impedance value is the impedance value at the connection between the testing device and the CPU when the impedance value of the voltage divider device of the load cell is 0, wherein the load cell is communicatively connected to the CPU and is used to test the CPU. The signal processor performs voltage division; based on the error impedance value and the target impedance value, the actual impedance value is determined, wherein the target impedance value is the impedance value of the voltage divider device set by the load instrument, and the actual impedance value is the actual impedance value of the voltage divider device of the load instrument; based at least on the actual impedance value, a first near-end voltage and a first far-end voltage are determined, wherein the first near-end voltage is the actual voltage of the power supply of the central processing unit monitored by the signal processor, and the first far-end voltage is the actual voltage of the power supply of the central processing unit monitored by the load instrument; the signal processor is communicatively connected to the central processing unit, and the signal processor is used to process the signals output by the central processing unit.

[0007] In one exemplary embodiment, determining whether there is a poor contact between the test device and the central processing unit includes: acquiring a second proximal voltage and a second distal voltage, wherein the second proximal voltage is the voltage of the power supply of the central processing unit monitored by the signal processor, and the second distal voltage is the voltage of the power supply of the central processing unit monitored by the load cell; and determining that there is a poor contact between the test device and the central processing unit if the second proximal voltage and the second distal voltage are not equal.

[0008] In yet another exemplary embodiment, determining the error impedance value includes: acquiring a third far-end voltage and a third near-end voltage when the impedance of the voltage divider device of the load instrument is 0, wherein the three far-end voltages are the voltages of the central processing unit power supply monitored by the load instrument when the impedance of the voltage divider device of the load instrument is 0, and the third near-end voltage is the voltage of the central processing unit power supply monitored by the signal processor when the impedance of the voltage divider device of the load instrument is 0; according to the formula The error impedance value is determined, wherein R1 is the error impedance value, U1 is the third far-end voltage, U2 is the third near-end voltage, and I is the current value of the central processing unit power supply.

[0009] In another exemplary embodiment, determining the actual impedance value based on the error impedance value and the target impedance value includes: determining the actual impedance value according to the formula R3 = R2 - R1, wherein R3 is the actual impedance value, R2 is the target impedance value, and R1 is the error impedance value.

[0010] In another exemplary embodiment, determining the first near-end voltage based at least on the actual impedance value includes: determining the first near-end voltage according to the formula U3 = U2 - I × R3 - I × R1, where U3 is the first near-end voltage, U2 is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0, I is the current of the central processing unit power supply, R3 is the actual impedance value, and R1 is the error impedance value.

[0011] In yet another exemplary embodiment, determining the first remote voltage based at least on the actual impedance value includes: determining the first remote voltage according to the formula U4 = U2 - I × R3, where U4 is the first remote voltage, U2 is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0, R3 is the actual impedance value, and I is the current of the central processing unit power supply.

[0012] In yet another exemplary embodiment, after determining the first proximal voltage and the first distal voltage, the testing method further includes: storing the first proximal voltage and the first distal voltage in a batch file, the batch file being used to store test parameters of the central processing unit power supply.

[0013] According to another embodiment of this application, a testing device for a central processing unit (CPU) power supply is provided, comprising: a first determining module, configured to determine whether there is a poor contact between a testing device and the CPU, wherein the testing device is used to test the CPU; a second determining module, configured to determine an error impedance value when the poor contact exists between the testing device and the CPU, wherein the error impedance value is the impedance value at the connection between the testing device and the CPU when the impedance value of the voltage divider device of the load cell is 0, the load cell being communicatively connected to the CPU and used to perform voltage division on the CPU; and a third determining module. A first determining module is used to determine the actual impedance value based on the error impedance value and the target impedance value, wherein the target impedance value is the impedance value of the voltage divider device set by the load instrument, and the actual impedance value is the actual impedance value of the voltage divider device of the load instrument; a fourth determining module is used to determine a first near-end voltage and a first far-end voltage based at least on the actual impedance value, wherein the first near-end voltage is the actual voltage of the power supply of the central processing unit monitored by the signal processor, and the first far-end voltage is the actual voltage of the power supply of the central processing unit monitored by the load instrument, the signal processor is communicatively connected to the central processing unit, and the signal processor is used to process the signal output by the central processing unit.

[0014] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0015] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0016] This application directly pinpoints the cause of inaccurate CPU power supply test results to poor contact between the CPU socket pins and the voltage regulator, leading to additional losses. It also adds a process for determining the error impedance value for calibration and can accurately determine the near-end and far-end voltages of the CPU power supply, thus improving the accuracy of CPU power supply testing. Therefore, it can solve the problem of low accuracy in CPU power supply test results. Attached Figure Description

[0017] Figure 1 This is a hardware structure block diagram of a central processing unit power supply testing method according to an embodiment of this application;

[0018] Figure 2This is a flowchart of a method for testing a central processing unit power supply according to an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of a method for testing the power supply of a central processing unit according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of the structure of a test device for a central processing unit power supply according to an embodiment of this application.

[0021] The above figures include the following reference numerals:

[0022] 102. Processor; 104. Memory; 106. Transmission device; 108. Input / output device; 200. CPU; 300. Signal processor; 400. Host; 500. Load cell. Detailed Implementation

[0023] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0025] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application:

[0026] CPU: The Central Processing Unit (CPU) is the core of a computer system for computation and control, and is the final execution unit for information processing and program execution.

[0027] LP: Load Pod (LP) is a voltage regulator that connects to a pin on the CPU and regulates the voltage.

[0028] VR: Voltage Regulator (VR) can prevent the CPU voltage from becoming too high, thus protecting the CPU.

[0029] SDLE: StarDust Load Emulator (SDLE) is a power testing tool for CPU cores that is compatible with AMD Genoa E generation CPUs.

[0030] GUI: Graphical User Interface (GUI) refers to a computer operating user interface that uses graphics.

[0031] DCLL: Direct Current Load Line (DCLL). In situations with high current, VR sets up a DCLL in the CPU0 circuit to prevent the CPU voltage from becoming too high. For AMD Genoa E generation CPUs, AMD specifies a DCLL range of approximately 0.4 mohm.

[0032] The methods and embodiments provided in this application can be executed on a mobile terminal, computer terminal, or similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal for a method of testing the power supply of a central processing unit according to an embodiment of this application. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0033] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the central processing unit power supply testing method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0034] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0035] This embodiment provides a method for testing the power supply of the central processing unit running on the aforementioned mobile terminal. Figure 2 This is a flowchart of a method for testing the power supply of a central processing unit according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0036] Step S202: Determine whether there is poor contact between the test equipment and the central processing unit, wherein the test equipment is used to test the central processing unit.

[0037] Specifically, the poor contact in the above steps can be a poor contact between the voltage regulator and the central processing unit during the testing of the central processing unit, or a poor contact between other testing equipment and the central processing unit.

[0038] Step S204: In the case of poor contact between the test equipment and the central processing unit, the error impedance value is determined. The error impedance value is the impedance value at the connection between the test equipment and the central processing unit when the impedance value of the voltage divider device of the load instrument is 0. The load instrument is communicatively connected to the central processing unit and is used to divide the voltage of the central processing unit.

[0039] Specifically, compared to CPU core power testing using traditional electronic load testers, SDLE uses the method of directly pressing the LP onto the CPU socket to load the CPU, which allows the load to be applied directly to the CPU side, resulting in a more direct and simple structure. Figure 3 This is a schematic diagram of the structure of a central processing unit power supply testing method according to an embodiment of this application, as shown below. Figure 3As shown, the structure includes a CPU 200, a signal processor 300, a host 400, and a load cell 500. The CPU 200 is connected to the host 400 via the signal processor 300 and a ribbon cable. Commands are issued to the host 400 through the GUI to perform tests such as load testing and voltage regulation. To ensure CPU safety, the load cell 500 needs to actively configure the DCLL. However, in actual testing, the step of tightening the LP and slot using screws and a base plate can lead to additional line losses due to poor contact between the pins and the LP. Such losses can significantly affect the test results and accuracy.

[0040] Step S206: Determine the actual impedance value based on the above error impedance value and target impedance value, wherein the above target impedance value is the impedance value of the voltage divider device set in the above load instrument, and the above actual impedance value is the actual impedance value of the voltage divider device in the above load instrument.

[0041] Specifically, due to the existence of the error impedance value, the target impedance value is not the actual impedance value. Therefore, based on the error impedance value and the target impedance value, the accurate actual impedance value can be determined.

[0042] Step S208: Determine the first near-end voltage and the first far-end voltage based at least on the actual impedance value, wherein the first near-end voltage is the actual voltage of the power supply of the central processing unit monitored by the signal processor, and the first far-end voltage is the actual voltage of the power supply of the central processing unit monitored by the load instrument. The signal processor is communicatively connected to the central processing unit and is used to process the signal output by the central processing unit.

[0043] Specifically, the near-end voltage is actually the voltage near the CPU pin, but since this pin is pressed down by the LP (Limited LP) and cannot be directly measured, the CPU voltage obtained from the signal processor can be used as the aforementioned first near-end voltage. In the presence of poor contact, if calculations are still performed according to the DCLL setting of VR (Vibration Controlled Limit), both the near-end and far-end voltages will be inaccurate. After obtaining the accurate actual impedance value, the accurate first near-end voltage and second far-end voltage can be obtained based on this actual impedance value.

[0044] By following the steps above, the cause of inaccurate CPU power supply test results is directly located to poor contact between the CPU socket pins and the voltage regulator, resulting in additional losses. This process adds the step of determining the error impedance value for calibration and also allows for the accurate determination of the near-end and far-end voltages of the CPU power supply, thus improving the accuracy of CPU power supply testing. Therefore, the problem of low accuracy in CPU power supply test results can be solved.

[0045] In an exemplary embodiment, based on the above steps S202 to S208, step S202 is further refined, including: step S2022, acquiring a second proximal voltage and a second distal voltage, wherein the second proximal voltage is the voltage of the power supply of the central processing unit monitored by the signal processor, and the second distal voltage is the voltage of the power supply of the central processing unit monitored by the load instrument; step S2024, determining that there is a poor contact phenomenon between the test device and the central processing unit when the second proximal voltage and the second distal voltage are not equal.

[0046] Specifically, in static mode, taking CPU loop 0 as an example, apply loads of 0A, 40A, and 80A respectively, record the corresponding voltage values, and calculate the current DCLL based on the voltage and current. Under normal circumstances, the voltage detected by the signal processor at the near end of the CPU and the voltage measured by the VR remote end should theoretically be basically the same. If the current DCLL is greater than the value set in the VR controller, it proves that there are additional lines besides the originally set value. In this case, the near-end voltage in the performance test results will have a large error because the voltage here is read from the near end of the CPU, while the remote end voltage measured by the VR controller is only calculated based on the set DCLL. The above steps can quickly determine whether there is a poor contact between the test equipment and the central processing unit as described above.

[0047] In an exemplary embodiment, based on steps S202 to S208 described above, step S204 is further refined, including: step S2042, obtaining a third far-end voltage and a third near-end voltage when the impedance value of the voltage divider device of the load instrument is 0, wherein the third far-end voltage is the voltage of the central processing unit power supply monitored by the load instrument when the impedance value of the voltage divider device of the load instrument is 0, and the third near-end voltage is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0; step S2044, according to formula The above error impedance value is determined, where R1 is the above error impedance value, U1 is the above third far-end voltage, U2 is the above third near-end voltage, and I is the above central processing unit power supply current value.

[0048] Specifically, taking SDLE as an example, the following is the testing method for CPU core power: First, import the batch file corresponding to the power rail and run the entire test. Taking the SA5280A7B as an example, this CPU has four core power rails: CPU0 circuit, CPU1 circuit, VDDIO circuit, and SOC circuit. CPU0, CPU1, and SOC circuits supply power to the CPU, while the VDDIO circuit primarily supplies power to the CPU's I / O ports. When performing CPU core power performance testing in SDLE, the CPU0 circuit, CPU1 circuit, VDDIO circuit, and SOC circuit need to be tested sequentially. Taking the CPU0 circuit as an example, because the CPU0 circuit has a large load capacity and directly supplies power to the CPU, a DCLL needs to be actively set at the VR end to ensure CPU safety. This ensures that the CPU voltage will not be too high under high current conditions. For AMD Genoa E generation CPUs, AMD provides a DCLL range of approximately 0.4 mohm. Therefore, the VR controller needs to set a DCLL of approximately 0.4 mohm for this circuit. The voltage loss in the performance test comes from the internal settings of the VR controller. At this point, set DCLL to 0 in the VR controller, and then determine the error voltage based on the difference between the far-end voltage and the near-end voltage. Based on the ratio of the error voltage to the current, the DCLL value on the additional line, i.e., the error impedance value, can be determined.

[0049] In an exemplary embodiment, based on the above steps S202 to S208, step S206 is further refined, including: step S2062, determining the above actual impedance value according to the formula R3 = R2 - R1, wherein R3 is the above actual impedance value, R2 is the above target impedance value, and R1 is the above error impedance value.

[0050] Specifically, taking the power supply scheme of SA5280A7B as an example, a CPU core has four power channels: CR_CPU0, CR_SOC, CR_CPU1, and CR_VDDIO. CR_CPU0 and CR_CPU1 have a DCLL of 0.3984 mohm within VR. Therefore, using 0.3984 mohm as the target impedance value, the precise actual impedance value can be determined using R3 = 0.3984 - R1, where R1 is the error impedance value calculated in the previous step.

[0051] In an exemplary embodiment, based on steps S202 to S208, step S208 is further refined, including: step S2082, determining the first near-end voltage according to the formula: U3 = U2 - I × R3 - I × R1, where U3 is the first near-end voltage, U2 is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0, I is the current of the central processing unit power supply, R3 is the actual impedance value, and R1 is the error impedance value.

[0052] Specifically, after considering the error impedance value, U2 actually consists of three parts: the actual near-end voltage, the voltage division of the error impedance value, and the voltage division of the actual impedance value of VR. Therefore, the accurate first near-end voltage should be the near-end voltage measured by the signal processor minus the voltage division of the error impedance value and the voltage division of the actual impedance value of VR when the load impedance is 0.

[0053] In an exemplary embodiment, based on steps S202 to S208, step S208 is further refined, including: step S2084, determining the first remote voltage according to the formula U4 = U2 - I × R3, wherein U4 is the first remote voltage, U2 is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0, R3 is the actual impedance value, and I is the current of the central processing unit power supply.

[0054] Specifically, after considering the error impedance value, U2 actually consists of two parts: the actual far-end voltage and the voltage division of the error impedance value. Therefore, the accurate first far-end voltage should be the near-end voltage measured by the signal processor minus the voltage division of the error impedance value when the load impedance is 0.

[0055] In an exemplary embodiment, in addition to steps S202 to S208, step S209 is further included after step S208: storing the first near-end voltage and the first far-end voltage into a batch file, wherein the batch file is used to store the test parameters of the central processing unit power supply.

[0056] Specifically, during power supply testing, after installing the power supply (LP) and ensuring proper cooling, the batch program is run in batch mode within the Stardust GUI. If the installation proceeds without issues, the test results are acceptable. However, in actual installation, additional line loss due to poor contact often occurs. Therefore, calibrating the first near-end voltage and the first far-end voltage before running the batch program can yield more accurate test results.

[0057] The entities that perform the above steps can be servers, terminals, etc., but are not limited to these.

[0058] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0059] This embodiment also provides a central processing unit power supply testing device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0060] Figure 4 A structural block diagram of the central processing unit power supply testing device according to an embodiment of this application is shown below. Figure 4 The device includes:

[0061] The first determining module 22 is used to determine whether there is poor contact between the test equipment and the central processing unit, wherein the test equipment is used to test the central processing unit.

[0062] Specifically, poor contact in the above modules can be a poor contact between the voltage regulator and the central processing unit during the testing of the central processing unit, or a poor contact between other testing equipment and the central processing unit.

[0063] The second determining module 24 is used to determine the error impedance value when there is poor contact between the test equipment and the central processing unit. The error impedance value is the impedance value at the connection between the test equipment and the central processing unit when the impedance value of the voltage divider device of the load instrument is 0. The load instrument is communicatively connected to the central processing unit and is used to divide the voltage of the central processing unit.

[0064] Specifically, compared to CPU core power testing using traditional electronic load testers, SDLE uses the method of directly pressing the LP onto the CPU socket to load the CPU, which allows the load to be applied directly to the CPU side, resulting in a more direct and simple structure. Figure 3 This is a schematic diagram of the structure of a central processing unit power supply testing method according to an embodiment of this application, as shown below. Figure 3 As shown, the structure includes a CPU 200, a signal processor 300, a host 400, and a load cell 500. The CPU 200 is connected to the host 400 via the signal processor 300 and a ribbon cable. Commands are issued to the host 400 through the GUI to perform tests such as load testing and voltage regulation. To ensure CPU safety, the load cell 500 needs to actively configure the DCLL. However, in actual testing, the step of tightening the LP and slot using screws and a base plate can lead to additional line losses due to poor contact between the pins and the LP. Such losses can significantly affect the test results and accuracy.

[0065] The third determining module 26 is used to determine the actual impedance value based on the above error impedance value and the target impedance value, wherein the above target impedance value is the impedance value of the voltage divider device set in the above load instrument, and the above actual impedance value is the actual impedance value of the voltage divider device in the above load instrument.

[0066] Specifically, due to the existence of the error impedance value, the target impedance value is not the actual impedance value. Therefore, based on the error impedance value and the target impedance value, the accurate actual impedance value can be determined.

[0067] The fourth determining module 28 is used to determine the first near-end voltage and the first far-end voltage based at least on the actual impedance value, wherein the first near-end voltage is the actual voltage of the power supply of the central processing unit monitored by the signal processor, and the first far-end voltage is the actual voltage of the power supply of the central processing unit monitored by the load instrument. The signal processor is communicatively connected to the central processing unit and is used to process the signal output by the central processing unit.

[0068] Specifically, the near-end voltage is actually the voltage near the CPU pin, but since this pin is pressed down by the LP (Limited LP) and cannot be directly measured, the CPU voltage obtained from the signal processor can be used as the aforementioned first near-end voltage. In the presence of poor contact, if calculations are still performed according to the DCLL setting of VR (Vibration Controlled Limit), both the near-end and far-end voltages will be inaccurate. After obtaining the accurate actual impedance value, the accurate first near-end voltage and second far-end voltage can be obtained based on this actual impedance value.

[0069] The aforementioned device directly pinpoints the cause of inaccurate CPU power supply test results to poor contact between the CPU socket pins and the voltage regulator, leading to additional losses. It also adds a process for determining the error impedance value for calibration and can accurately determine the near-end and far-end voltages of the CPU power supply, thus improving the accuracy of CPU power supply testing. Therefore, it can solve the problem of low accuracy in CPU power supply test results.

[0070] In an exemplary embodiment, based on the aforementioned first determining module, second determining module, third determining module, and fourth determining module, the first determining module is further refined to include a first acquisition submodule and a first determining submodule. The first acquisition submodule is used to acquire a second proximal voltage and a second distal voltage. The second proximal voltage is the voltage of the central processing unit's power supply monitored by the signal processor, and the second distal voltage is the voltage of the central processing unit's power supply monitored by the load cell. The first determining submodule is used to determine that a poor contact exists between the test equipment and the central processing unit when the second proximal voltage and the second distal voltage are not equal.

[0071] Specifically, in static mode, taking CPU loop 0 as an example, 0A, 40A, and 80A are applied respectively, and the corresponding voltage values ​​are recorded. The current DCLL is then calculated based on the voltage and current. Under normal circumstances, the voltage detected by the signal processor at the near end of the CPU and the voltage measured by the VR remote end should theoretically be basically the same. If the current DCLL is greater than the value set in the VR controller, it proves that there are additional lines besides the originally set value. In this case, the near-end voltage in the performance test results will have a large error because the voltage here is read from the near end of the CPU, but the remote end voltage obtained by the VR controller is only calculated based on the set DCLL. The above module can quickly determine whether there is the aforementioned poor contact phenomenon between the test equipment and the central processing unit.

[0072] In an exemplary embodiment, based on the aforementioned first determining module, second determining module, third determining module, and fourth determining module, the second determining module is further refined to include a second acquisition submodule and a second determining submodule. The second acquisition submodule is used to acquire a third far-end voltage and a third near-end voltage when the impedance value of the voltage divider device of the load instrument is 0. The third far-end voltage is the voltage of the central processing unit power supply monitored by the load instrument when the impedance value of the voltage divider device of the load instrument is 0, and the third near-end voltage is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0. The second determining submodule is used to determine the voltage of the central processing unit power supply according to the formula... The above error impedance value is determined, where R1 is the above error impedance value, U1 is the above third far-end voltage, U2 is the above third near-end voltage, and I is the above central processing unit power supply current value.

[0073] Specifically, taking SDLE as an example, the following is the testing method for CPU core power: First, import the batch file corresponding to the power rail and run the entire test. Taking the SA5280A7B as an example, this CPU has four core power rails: CPU0 circuit, CPU1 circuit, VDDIO circuit, and SOC circuit. CPU0, CPU1, and SOC circuits supply power to the CPU, while the VDDIO circuit primarily supplies power to the CPU's I / O ports. When performing CPU core power performance testing in SDLE, the CPU0 circuit, CPU1 circuit, VDDIO circuit, and SOC circuit need to be tested sequentially. Taking the CPU0 circuit as an example, because the CPU0 circuit has a large load capacity and directly supplies power to the CPU, a DCLL needs to be actively set at the VR end to ensure CPU safety. This ensures that the CPU voltage will not be too high under high current conditions. For AMD Genoa E generation CPUs, AMD provides a DCLL range of approximately 0.4 mohm. Therefore, the VR controller needs to set a DCLL of approximately 0.4 mohm for this circuit. The voltage loss in the performance test comes from the internal settings of the VR controller. At this point, set DCLL to 0 in the VR controller, and then determine the error voltage based on the difference between the far-end voltage and the near-end voltage. Based on the ratio of the error voltage to the current, the DCLL value on the additional line, i.e., the error impedance value, can be determined.

[0074] In an exemplary embodiment, based on the first determining module, the second determining module, the third determining module, and the fourth determining module described above, the third determining module is further refined to include a third determining sub-module. The third determining sub-module is used to determine the actual impedance value according to the formula R3 = R2 - R1, wherein R3 is the actual impedance value, R2 is the target impedance value, and R1 is the error impedance value.

[0075] Specifically, taking the power supply scheme of SA5280A7B as an example, a CPU core has four power channels: CR_CPU0, CR_SOC, CR_CPU1, and CR_VDDIO. Within VR, CR_CPU0 and CR_CPU1 have a DCLL of 0.3984 mohm. Therefore, using 0.3984 mohm as the target impedance value, the precise actual impedance value can be determined using R3 = 0.3984 - R1, where R1 is the error impedance value calculated in the previous module.

[0076] In an exemplary embodiment, based on the first determining module, the second determining module, the third determining module, and the fourth determining module described above, the fourth determining module is further refined to include a fourth determining submodule. The fourth determining submodule is used to determine the first near-end voltage according to the formula U3 = U2 - I × R3 - I × R1, where U3 is the first near-end voltage, U2 is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0, I is the current of the central processing unit power supply, R3 is the actual impedance value, and R1 is the error impedance value.

[0077] Specifically, after considering the error impedance value, U2 actually consists of three parts: the actual near-end voltage, the voltage division of the error impedance value, and the voltage division of the actual impedance value of VR. Therefore, the accurate first near-end voltage should be the near-end voltage measured by the signal processor minus the voltage division of the error impedance value and the voltage division of the actual impedance value of VR when the load impedance is 0.

[0078] In an exemplary embodiment, based on the first determining module, the second determining module, the third determining module, and the fourth determining module described above, the above and the fourth determining module are further refined to include a fifth determining submodule. The fifth determining submodule is used to determine the first remote voltage according to the formula U4 = U2 - I × R3, where U4 is the first remote voltage, U2 is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0, R3 is the actual impedance value, and I is the current of the central processing unit power supply.

[0079] Specifically, after considering the error impedance value, U2 actually consists of two parts: the actual far-end voltage and the voltage division of the error impedance value. Therefore, the accurate first far-end voltage should be the near-end voltage measured by the signal processor minus the voltage division of the error impedance value when the load impedance is 0.

[0080] In one exemplary embodiment, in addition to the first determining module, the second determining module, the third determining module, and the fourth determining module described above, a storage module is further included. The storage module is used to store the first near-end voltage and the first far-end voltage into a batch file, and the batch file is used to store the test parameters of the central processing unit power supply.

[0081] Specifically, during power supply testing, after installing the power supply (LP) and ensuring proper cooling, the batch program is run in batch mode within the Stardust GUI. If the installation proceeds without issues, the test results are acceptable. However, in actual installation, additional line loss due to poor contact often occurs. Therefore, calibrating the first near-end voltage and the first far-end voltage before running the batch program allows for more accurate test results.

[0082] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0083] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when it is run.

[0084] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0085] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0086] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0087] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0088] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0089] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for testing a central processing unit power supply, characterized in that, The central processing unit is the central processing unit of a server, and the testing method includes: To determine whether there is poor contact between the test equipment and the central processing unit, wherein the test equipment is used to test the central processing unit; In the event of poor contact between the test equipment and the central processing unit, an error impedance value is determined. The error impedance value is the impedance value at the connection between the test equipment and the central processing unit when the impedance value of the voltage divider device of the load instrument is 0. The load instrument is communicatively connected to the central processing unit and is used to perform voltage division on the central processing unit. The actual impedance value is determined based on the error impedance value and the target impedance value, wherein the target impedance value is the impedance value of the voltage divider device set by the load instrument, and the actual impedance value is the actual impedance value of the voltage divider device of the load instrument. Based at least on the actual impedance value, a first near-end voltage and a first far-end voltage are determined, wherein the first near-end voltage is the actual voltage of the central processing unit's power supply as monitored by the signal processor, and the first far-end voltage is the actual voltage of the central processing unit's power supply as monitored by the load cell. The signal processor is communicatively connected to the central processing unit and is used to process the signals output by the central processing unit. Determining the first near-end voltage, at least based on the actual impedance value, includes: according to the formula Determine the first proximal voltage, wherein, The first proximal voltage, The voltage of the central processing unit power supply monitored by the signal processor when the impedance of the voltage divider device of the load cell is 0. The current of the power supply to the central processing unit. The actual impedance value, The error impedance value; determining the first far-end voltage based at least on the actual impedance value, including: according to the formula Determine the first remote voltage, wherein, The first far-end voltage, The voltage of the central processing unit power supply monitored by the signal processor when the impedance of the voltage divider device of the load cell is 0. The actual impedance value, The current is the power supply current of the central processing unit.

2. The method according to claim 1, characterized in that, Determine if there is poor contact between the test equipment and the central processing unit, including: Acquire a second proximal voltage and a second distal voltage, wherein the second proximal voltage is the voltage of the central processing unit power supply monitored by the signal processor, and the second distal voltage is the voltage of the central processing unit power supply monitored by the load cell. If the second proximal voltage and the second distal voltage are not equal, it is determined that there is a poor contact between the test equipment and the central processing unit.

3. The method according to claim 1, characterized in that, Determine the error impedance value, including: When the impedance value of the voltage divider device of the load instrument is 0, a third far-end voltage and a third near-end voltage are obtained, wherein the third far-end voltage is the voltage of the central processing unit power supply monitored by the load instrument when the impedance value of the voltage divider device of the load instrument is 0, and the third near-end voltage is the voltage of the central processing unit power supply monitored by the signal processor when the impedance value of the voltage divider device of the load instrument is 0. According to the formula Determine the error impedance value, wherein, The error impedance value is... The third far-end voltage, The third proximal voltage, The current value of the power supply to the central processing unit.

4. The method according to claim 1, characterized in that, Based on the error impedance value and the target impedance value, the actual impedance value is determined, including: According to the formula Determine the actual impedance value, wherein, The actual impedance value, The target impedance value, The error impedance value is given.

5. The method according to claim 1, characterized in that, After determining the first proximal voltage and the first distal voltage, the test method further includes: The first near-end voltage and the first far-end voltage are stored in a batch file, which is used to store the test parameters of the central processing unit power supply.

6. A testing device for a central processing unit power supply, characterized in that, include: The first determining module is used to determine whether there is poor contact between the test equipment and the central processing unit, wherein the test equipment is used to test the central processing unit; The second determining module is used to determine the error impedance value when there is poor contact between the test equipment and the central processing unit. The error impedance value is the impedance value at the connection between the test equipment and the central processing unit when the impedance value of the voltage divider device of the load instrument is 0. The load instrument is communicatively connected to the central processing unit and is used to perform voltage division on the central processing unit. The third determining module is used to determine the actual impedance value based on the error impedance value and the target impedance value, wherein the target impedance value is the impedance value of the voltage divider device set by the load instrument, and the actual impedance value is the actual impedance value of the voltage divider device of the load instrument. The fourth determining module is used to determine, at least based on the actual impedance value, a first near-end voltage and a first far-end voltage, wherein the first near-end voltage is the actual voltage of the central processing unit's power supply as monitored by the signal processor, and the first far-end voltage is the actual voltage of the central processing unit's power supply as monitored by the load cell. The signal processor is communicatively connected to the central processing unit and is used to process the signal output by the central processing unit, wherein, according to the formula... Determine the first proximal voltage, wherein, The first proximal voltage, The voltage of the central processing unit power supply monitored by the signal processor when the impedance of the voltage divider device of the load cell is 0. The current of the power supply to the central processing unit. The actual impedance value, The error impedance value is given; according to the formula Determine the first remote voltage, wherein, The first far-end voltage, The voltage of the central processing unit power supply monitored by the signal processor when the impedance of the voltage divider device of the load cell is 0. The actual impedance value, The current is the power supply current of the central processing unit.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 5.

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