Dmd high frame rate display system and method with matched photoelectric integration time

Abstract

This application discloses a DMD high frame rate display system and method that matches photoelectric integration time. The system includes a detector, a host computer, a main control board, a DMD, a light source driver, an illumination system, and a projection screen. The DMD calculates the frame period of the displayed image based on phase modulation information, the detector's synchronization signal, and photoelectric integration time data, and calculates the maximum frame rate of the displayed image based on binary pulse width modulation. When the detector's photoelectric integration time changes, the changed photoelectric integration time is acquired, and a new time base is calculated. The parameters of the registers in the control timing are modified according to the new time base to adjust the image display frame rate. This application can use the detector's synchronization signal to deduce the display time base from the detector's photoelectric integration time, achieving synchronization between the detector's photoelectric integration time and the DMD display frame rate. This avoids false signals, flickering, and image confusion, and achieves optimal imaging results.

Description

Technical Field

[0001] This application relates to the field of DMD high frame rate display technology, specifically to a DMD high frame rate display system and method that matches photoelectric integration time. Background Technology

[0002] Digital micromirror devices (DMDs) are a type of reflective spatial modulation technology based on micromechanical structures. Developed by Texas Instruments in 1987, each DMD consists of hundreds or thousands of micromirrors, each representing a pixel. Each micromirror has two stable states: a 12° clockwise deflection and a 12° counterclockwise deflection. The image display is controlled by adjusting the deflection state of the micromirrors. Due to its advantages such as high resolution, high frame rate, high grayscale levels, no dead pixels, and high uniformity, DMD technology was initially widely used in visible light projection systems and has secured a place in the visible light projection market. Similar to visible light projection using DMDs, infrared image projection can be achieved by changing the projection window of the DMD, thus this technology has also received considerable attention in the field of infrared target simulators. Optical Science Corporation (OSC) in the United States developed infrared target simulators based on digital micromirror devices (DMDs) in the 1990s. In 2001, they developed a mid-wave infrared target simulator based on DMDs with a resolution of 800×600 and a frame rate of 100Hz for displaying 8-bit grayscale images. In 2005, they achieved an infrared target simulator with a resolution of 1024×768 and a frame rate of 226Hz for displaying 8-bit grayscale images using DMDs. In 2010, OPTRA in the United States developed a dual-band infrared target simulator based on DMDs, which could display 10-bit grayscale images at a frame rate of 40Hz. Although research on DMD-based infrared target simulators in China started later, it has developed rapidly. This technology was proposed in 2003 by Chen Erzhu, Liang Pingzhi, and others from the Chinese Academy of Sciences. In 2008, Kang Weimin et al. from Harbin Institute of Technology developed an infrared target simulator based on digital micromirror devices with a resolution of 800×600 and a frame rate of up to 60Hz for displaying 8-bit grayscale images. In 2011, Zhang Kai et al. from Northwestern Polytechnical University developed an infrared target simulator based on digital micromirror devices with a resolution of 1024×768 and a frame rate of up to 100Hz for displaying 8-bit grayscale images. In 2013, Yao Yuan et al. from the Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, developed an infrared target simulator based on digital micromirror devices with a grayscale of 14 bits. In 2016, Zhang Ning et al. from the Shanghai Institute of Technical Physics, Chinese Academy of Sciences, developed an infrared simulation projection system based on digital micromirror devices with a resolution of 1024×768, a grayscale of 10-12 bits, and a frame rate of 120Hz.Xi'an University of Electronic Science and Technology has adopted a "low-level plane cancellation" method to reduce the time base of pulse width modulation by loading an inverted plane. Theoretically, this can make the time base infinitely approach 0 and achieve a frame rate of 2565.75Hz. However, the problem with this method is that when the display frequency approaches the frame rate limit, the display brightness also approaches 0. Therefore, this design ultimately increases the display frame rate of 1024×768 resolution 8-bit grayscale images based on DMD to 200Hz.

[0003] Because the DMD uses modulated reflected light, adjusting brightness by controlling the duration of light reflection from each micromirror, it can only be used with a staring array infrared detector. Therefore, it only detects external light energy during its photoelectric integration time, remaining unresponsive at other times. This causes a missynchronization between the detector's photoelectric integration time and the DMD's display frame rate, resulting in false signals, flickering, and image confusion.

[0004] When imaging a moving target, an infrared detector adaptively adjusts its photoelectric integration time based on factors such as light intensity to achieve optimal imaging results. Furthermore, as the infrared detector gets closer to the target, its photoelectric integration time decreases. This presents a limitation: the photoelectric integration time cannot be perfectly matched to achieve the optimal imaging effect. Summary of the Invention

[0005] This application provides a DMD high frame rate display system and method that matches photoelectric integration time. This solves the problem that the current DMD uses an infrared detector that only detects external light energy during its photoelectric integration time when modulating reflected light, and does not respond at other times. This causes the photoelectric integration time of the detector to be out of sync with the DMD display frame rate, resulting in false signals, flickering and image confusion. Furthermore, it cannot match the photoelectric integration time to achieve the best imaging effect.

[0006] This application provides a DMD high frame rate display system that matches photoelectric integration time, including a detector, a host computer, a main control board, a DMD, a light source driver, an illumination system, and a projection screen;

[0007] The detector is used to generate synchronization signals and photoelectric integration time data;

[0008] The host computer is used to generate image data;

[0009] The main control board is used to acquire and cache image data, phase modulation information, detector synchronization signal and photoelectric integration time data generated by the host computer; when displaying an image, it sends the cached image data, phase modulation information, detector synchronization signal and photoelectric integration time data to the DMD.

[0010] The DMD calculates the frame period of the displayed image based on phase modulation information, the detector's synchronization signal, and photoelectric integration time data, and calculates the maximum frame frequency of the displayed image based on binary pulse width modulation. When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained and a new time base is calculated. The parameters of the registers in the control timing are modified according to the new time base to adjust the display frame frequency of the image.

[0011] The main control board is used to synchronize the photoelectric integration time of the detector with the display frame rate generated by the DMD using the detector's synchronization signal. When displaying an image, it controls the light source to drive the lighting system to display the output image of the DMD on the projection screen.

[0012] Furthermore, the main control board includes a main control chip, an interface board, and a driver board; the interface board is connected to the driver board, the main control chip, and the host computer, and the driver board is connected to the DMD and the light source driver.

[0013] Furthermore, the interface board is equipped with a PCIe high-speed interface, an RS422 interface, and a JTAG interface; the PCIe high-speed interface is connected to the host computer for transmitting image data generated by the host computer; the RS422 interface is connected to the detector for transmitting photoelectric integration time data of the detector; and the JTAG interface is used to program the main control chip.

[0014] Furthermore, the driver board includes a main control chip, a third-generation double-rate synchronous dynamic random access memory (DRAM), a first non-volatile memory (NRAM), a second non-volatile memory (NRAM), a DMD driver chip, and a DMD micromirror flip voltage control chip. The main control chip is connected to the PCIe high-speed interface and the RS422 interface, the third-generation double-rate synchronous dynamic random access memory, and the DMD chip assembly. The JTAG interface is connected to the main control chip via the first NRAM, the second NRAM, and the DMD driver chip. The DMD driver chip is connected to the DMD micromirror flip voltage control chip.

[0015] Furthermore, the DMD is provided with a ribbon cable interface and a DMD chip, and the DMD driver chip and the DMD micromirror flip voltage control chip are connected to the DMD chip through the ribbon cable interface.

[0016] Furthermore, the DMD driver chip is model DDC4100; the DMD micromirror flip voltage control chip is model DAD2000, used to generate the voltage that flips the DMD micromirrors and to generate the level signal for DMD block reset or global reset; the ribbon cable interface uses a .7XGA DMD data cable with a line width of 32 bits; the DMD chip integrates 1024×768 micromirrors, corresponding to an image resolution of 1024×768.

[0017] Furthermore, the DMD calculates the frame period of the displayed image based on phase modulation information, the detector's synchronization signal, and photoelectric integration time data, and calculates the maximum frame frequency of the displayed image based on binary pulse width modulation. When the photoelectric integration time of the detector changes, the changed photoelectric integration time is acquired and a new time base is calculated. The parameters of the registers in the control timing are modified according to the new time base to adjust the display frame frequency of the image, specifically including:

[0018] Get the DMD data loading time t load DMD block reset time t reset The display hold time t of the DMD base ;

[0019] Calculate the frame period t for displaying an n-bit grayscale image, where t = 2t. load +10t reset +(2 n -1)t base ;

[0020] Calculate the maximum frame rate F for displaying an n-bit grayscale image.

[0021] When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained as T, and then substituted into the formula for calculating the maximum frame rate F to form a corresponding relationship.

[0022] The new time base is calculated according to the formula.

[0023] ′

[0024] Based on the new time base t base The display frame rate of the image can be adjusted by modifying the parameters of the registers in the control timing.

[0025] This application also provides a DMD high frame rate display method that matches the photoelectric integration time, which includes:

[0026] When displaying an image, image data, phase modulation information, detector synchronization signals, and photoelectric integration time data are acquired.

[0027] The frame period of the displayed image is calculated based on the phase modulation information, the detector's synchronization signal, and the photoelectric integration time data.

[0028] The maximum frame rate of the displayed image is calculated based on the binary pulse width modulation method.

[0029] When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained and the new time base is calculated.

[0030] The display frame rate of the image is adjusted by modifying the parameters of the registers in the control timing according to the new time base;

[0031] The photoelectric integration time of the detector is synchronized with the display frame rate generated by the DMD using the detector's synchronization signal.

[0032] Furthermore, the method specifically includes:

[0033] Get the DMD data loading time t load DMD block reset time t reset The display hold time t of the DMD base ;

[0034] Calculate the frame period t for displaying an n-bit grayscale image, where t = 2t. load +10t reset +(2 n -1)t base ;

[0035] Calculate the maximum frame rate F for displaying an n-bit grayscale image.

[0036] When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained as T, and then substituted into the formula for calculating the maximum frame rate F to form a corresponding relationship.

[0037] The new time base is calculated according to the formula.

[0038] ′

[0039] Based on the new time base t base The display frame rate of the image can be adjusted by modifying the parameters of the registers in the control timing.

[0040] The photoelectric integration time of the detector is synchronized with the display frame rate generated by the DMD using the detector's synchronization signal. When displaying an image, the output image of the DMD is displayed on the projection screen.

[0041] Furthermore, the display of an n-bit grayscale image using pulse width modulation requires n bit planes to achieve the modulation effect, corresponding to the display of 2 nThere are 8 gray levels, where n = 8.

[0042] The DMD high frame rate display system and method provided in this application, which matches the photoelectric integration time, is based on the traditional pulse width modulation method. By adjusting the display time base, the display period can be changed to match the detector's photoelectric integration time. Therefore, the display time base can be calculated backward from the detector's photoelectric integration time using the detector's synchronization signal to meet the requirements of matching the photoelectric integration time. This achieves synchronization between the detector's photoelectric integration time and the DMD display frame rate, eliminating false signals, flickering, and image confusion, and achieving optimal imaging results through matching the photoelectric integration time. Attached Figure Description

[0043] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0044] Figure 1 A schematic diagram of the structure of a DMD high frame rate display system with matching photoelectric integration time provided in an embodiment of this application.

[0045] Figure 2 A schematic diagram of the data transmission process of the main control board in the DMD high frame rate display system with matching photoelectric integration time provided in the application embodiment.

[0046] Figure 3 A schematic diagram showing the connection between the main control board and the DMD structure in a DMD high frame rate display system with matching photoelectric integration time provided in the application embodiment.

[0047] Figure 4 The timing diagram of block clearing pulse width modulation in DMD serial mode provided in the embodiments of this application is shown.

[0048] Figure 5 A schematic diagram of pulse width modulation provided for an embodiment of this application.

[0049] Figure 6 This is a schematic diagram of bit plane pulse width modulation provided in an embodiment of this application.

[0050] Figure 7 A flowchart of a DMD high frame rate display method with matching photoelectric integration time provided in an embodiment of this application. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0052] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that allows communication between the components; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0053] Example 1

[0054] As described in the background section, since the DMD uses modulated reflected light, brightness is adjusted by controlling the duration of light reflection from each micromirror. It can only be used with a staring array infrared detector, and therefore only detects external light energy during its photoelectric integration time, remaining unresponsive at other times. To obtain an ideal simulation scenario, the detector's photoelectric integration time must be synchronized with the DMD display frame rate; otherwise, false signals, flickering, and image confusion will occur.

[0055] When imaging a moving target, an infrared detector adaptively adjusts its photoelectric integration time based on factors such as light intensity to achieve optimal imaging results. Furthermore, as the infrared detector gets closer to the target, its photoelectric integration time decreases. Therefore, the DMD display system needs to match the photoelectric integration time to simulate the entire detector process.

[0056] This application addresses the dynamic operating characteristics of infrared detectors, specifically the photoelectric integration time. It designs a DMD high frame rate display system and method that can match the photoelectric integration time for full-process detector simulation.

[0057] like Figure 1 As shown, the DMD high frame rate display system with matching photoelectric integration time includes a detector, a host computer, a main control board, a DMD, a light source driver, an illumination system, and a projection screen; the detector is not shown in the figure, but is preferably an infrared detector.

[0058] The detector is used to generate synchronization signals and photoelectric integration time data;

[0059] The host computer is used to generate image data;

[0060] The main control board is used to acquire and cache image data, phase modulation information, detector synchronization signal and photoelectric integration time data generated by the host computer; when displaying an image, it sends the cached image data, phase modulation information, detector synchronization signal and photoelectric integration time data to the DMD.

[0061] The DMD calculates the frame period of the displayed image based on phase modulation information, the detector's synchronization signal, and photoelectric integration time data, and calculates the maximum frame frequency of the displayed image based on binary pulse width modulation. When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained and a new time base is calculated. The parameters of the registers in the control timing are modified according to the new time base to adjust the display frame frequency of the image.

[0062] The main control board is used to synchronize the photoelectric integration time of the detector with the display frame rate generated by the DMD using the detector's synchronization signal. When displaying an image, it controls the light source to drive the lighting system to display the output image of the DMD on the projection screen.

[0063] Please see Figure 2 , Figure 3 The main control board includes a main control chip, an interface board, and a driver board; the interface board is connected to the driver board, the main control chip, and the host computer, and the driver board is connected to the DMD and the light source driver.

[0064] Furthermore, the interface board is equipped with a PCIe high-speed interface, an RS422 interface, and a JTAG interface; the PCIe high-speed interface is connected to the host computer for transmitting image data generated by the host computer; the RS422 interface is connected to the detector for transmitting photoelectric integration time data of the detector; and the JTAG interface is used to program the main control chip.

[0065] Furthermore, the driver board includes a main control chip, a third-generation double-data-rate synchronous dynamic random access memory (DDR3), a first non-volatile memory, a second non-volatile memory, a DMD driver chip, and a DMD micromirror flip-flop voltage control chip. The main control chip is connected to the PCIe high-speed interface and the RS422 interface, the third-generation double-data-rate synchronous dynamic random access memory, and the DMD chip assembly. The JTAG interface is connected to the main control chip through the first non-volatile memory, the second non-volatile memory, and the DMD driver chip, which is connected to the DMD micromirror flip-flop voltage control chip.

[0066] Furthermore, the DMD is provided with a ribbon cable interface and a DMD chip, and the DMD driver chip and the DMD micromirror flip voltage control chip are connected to the DMD chip through the ribbon cable interface.

[0067] Furthermore, the DMD driver chip is model DDC4100; the DMD micromirror flip voltage control chip is model DAD2000, used to generate the voltage that flips the DMD micromirrors and to generate the level signal for DMD block reset or global reset; the ribbon cable interface uses a .7XGA DMD data cable with a line width of 32 bits; the DMD chip integrates 1024×768 micromirrors, corresponding to an image resolution of 1024×768.

[0068] correspond Figure 3 The diagram shows the connection between the main control board and the DMD structure. The specific structure of the main control board is described below.

[0069] PCIe high-speed interface: A data interface conforming to the high-speed serial computer expansion bus standard. In the system, it serves as the interface between the FPGA and the host computer, buffering image data in DDR and transmitting it to the DDC4100 during display.

[0070] RS422: A data interface conforming to the RS422 serial physical interface standard. In the system, it serves as the interface between the detector and the system, sending the photoelectric integration time of the detector to the FPGA.

[0071] DDR3: Third-generation Double Data Rate Synchronous Dynamic Random Access Memory. The high bandwidth required for display makes it difficult for existing interfaces to handle direct data transfer from the host computer to the DMD; therefore, DDR is being considered as a cache.

[0072] FPGA: An integrated chip primarily composed of digital circuits, belonging to the category of Programmable Logic Devices (PLDs). It possesses abundant logic resources and can implement relatively complex algorithms.

[0073] PROM: Non-volatile memory used to store the drivers for the FPGA and DDC4100, enabling the main control board to project the display immediately upon power-up, without needing to download the display program to the main control FPGA via the JTAG port.

[0074] JTAG interface (Joint Test Action Group) is an international standard test protocol used to program the host FPGA.

[0075] DDC4100: This is a DMD driver chip developed by Texas Instruments to simplify the development interface logic of DMD. The input signals of DDC4100 are 32-bit LVDS (Low Voltage Differential Signaling) data and control information from the main control FPGA. It sends LVDS image data to DMD and generates control information for DMD and DAD2000.

[0076] DAD2000: The DAD2000 is used to generate the voltage that causes the DMD micromirrors to flip, and to generate various level signals for DMD block reset or global reset. The control signals of the DDC4100 and DAD2000 are connected to the .7XGA DMD via ribbon cables.

[0077] .7XGA DMD: DMD chip, which integrates 1024×768 micromirrors, meaning the image resolution is 1024×768.

[0078] Furthermore, the DMD calculates the frame period of the displayed image based on phase modulation information, the detector's synchronization signal, and photoelectric integration time data, and calculates the maximum frame frequency of the displayed image based on binary pulse width modulation. When the photoelectric integration time of the detector changes, the changed photoelectric integration time is acquired and a new time base is calculated. The parameters of the registers in the control timing are modified according to the new time base to adjust the display frame frequency of the image, specifically including:

[0079] Get the DMD data loading time t load DMD block reset time t reset The display hold time t of the DMD base ;

[0080] Calculate the frame period t for displaying an n-bit grayscale image, where t = 2t. load +10t reset +(2 n -1)t base ;

[0081] Calculate the maximum frame rate F for displaying an n-bit grayscale image.

[0082] When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained as T, and then substituted into the formula for calculating the maximum frame rate F to form a corresponding relationship.

[0083] The new time base is calculated according to the formula.

[0084] ′

[0085] Based on the new time base t base The display frame rate of the image can be adjusted by modifying the parameters of the registers in the control timing.

[0086] like Figure 4 As shown, Figure 4 This is a timing diagram for block clearing pulse width modulation in DMD serial mode.

[0087] The .7XGA model's DMD data bus width is 32 bits, transmitting at double data rate (DDR), meaning data is written once on both the rising and falling edges. Loading one line of 1024 bits of data requires 32 clock edges, or 16 clock cycles. Based on the maximum clock speed supported by the .7XGA model at 400MHz, loading one line of data takes 40ns, and loading all 768 lines of data takes 30.72us. Therefore, the loading time is: 1 / 400M * 32 / 2 * 768 / 1000 = 30.72us.

[0088] The frame rate limitation of traditional pulse width modulation methods lies in the display time base t. base The data loading time is no less than 30.72µs. In pulse width modulation (PWM) coding, the display time of a bit plane is exponentially related to the grayscale level; the sum of the display times for bit planes 0-7 is 255 times the time base, while the data loading time for one frame is only 8 times the time base. The display hold time of a bit plane is an order of magnitude larger than the bit plane data loading time, meaning the DMD is inactive for most of the time a frame is displayed. Therefore, reducing the time base is an effective way to increase the frame rate. Since the micromirrors need to remain unchanged for at least 8µs after flipping, the minimum display hold time is 8µs.

[0089] In operation, a hardware platform for the DMD system is built. The system's hardware components mainly include: a host computer for generating simulated images, an interface board for receiving signals, a main control board for driving the DMD, and an optical system. The optical system comprises a light source driver, an illumination system, and a projection screen for the imager. During operation, image data is processed into the bit-plane data required for display. The interface board has a high-speed data transmission interface for receiving image data, phase modulation information, detector synchronization signals, and photoelectric integration time data generated by the host computer, and transmitting the obtained data and signals to the main control board. For display, the image is read from the buffer and transmitted to the DMD driver for display. Optically, an infrared heat source is projected onto the DMD via the optical system, and then onto the projection screen of the imager.

[0090] Based on the characteristic that the flipping stabilization of DMD micromirrors requires a certain amount of time, the maximum frame rate of the displayed image is calculated using the binary pulse width modulation method.

[0091] like Figure 5 As shown, Figure 5 This is a schematic diagram of pulse width modulation (PWM). Figure 6 As shown, Figure 6 This is a schematic diagram of bit-plane pulse width modulation.

[0092] Pulse width modulation (PWM) encodes grayscale information. Compared to ordinary frame grayscale modulation, which requires 255 binary numbers to represent 255 grayscale levels, PWM only requires 8 binary bits. It assigns different weights to high-order and low-order grayscale information, with the brightness of the high-order bits being twice that of the low-order bits. The brightness difference between different bits is achieved by varying the duty cycle of that bit within the frame period. By dividing a frame into segments and controlling the display time of different bit planes, grayscale modulation is achieved. To display 2... n To achieve a grayscale level, only n bit planes are needed to achieve the modulation effect. Here, n = 8.

[0093] Combination Figure 4 If we take 8µs as the time base for pulse width modulation (PWM), we can calculate the expression for the frame period t:

[0094] t = 2t load +10t reset +(2 8 -1)t base =(2*30.72+5*10+255*8)us=2151.44us;

[0095] Where t load =30.72us,t reset =5us,t base =8us. t load The data loading time for the DMD (calculated), t reset t is the block reset time for the DMD. base This is the display hold time for the DMD (also used as the time base for PWM modulation).

[0096] Corresponding frame rate: 1 / 2151.44us = 464.8Hz.

[0097] System frame rate and t base The relationship between them is:

[0098]

[0099] Where 111.44 = 2 * 30.72 + 10 * 5, which is 2t load +10t reset .

[0100] When the time base t base When the minimum value is 8µs, the display frame rate reaches a maximum of 464.8Hz. When a lower display frame rate is required, the time base t is calculated backwards using the formula. base This is to meet the requirements of real-time photoelectric integration time.

[0101] Based on the detector synchronization signal, a variable frame rate modulation scheme is designed. By modifying the parameters of the registers in the control timing, the display frame rate can be adjusted, enabling the DMD system to match the photoelectric integration time.

[0102] Back-calculation of time base t base The specific steps are as follows:

[0103] Once the photoelectric integration time of the detector is known at a certain moment, the system needs to change the display frame rate to match the photoelectric integration time of the detector. Let's assume that the photoelectric integration time is T at this moment.

[0104] Substitute these values ​​into the above formula to calculate the new time base: That is, T = 111.44us + 255t′ base That is, 255t′ base =T-111.44us=T-2t load -10t reset .

[0105] In other words, after the detector's photoelectric integration time changes, it is sent to the DMD master controller via serial port, and the master controller calculates the new time base t′ according to the formula. base This is used to change the frame period of the DMD system to match the photoelectric integration time of the detector.

[0106] The display period of a single frame of grayscale image in a DMD system consists of three parts: data loading time, global reset time, and display hold time. Based on the traditional pulse width modulation method, adjusting the display time base can change the display period to match the detector's photoelectric integration time. Therefore, the display time base can be calculated backward from the detector's photoelectric integration time using an external synchronization signal to meet the requirement of matching the detector's real-time changing photoelectric integration time.

[0107] Example 2

[0108] like Figure 7 As shown, this application also provides a DMD high frame rate display method that matches photoelectric integration time, which includes the following steps:

[0109] S1. When displaying an image, acquire image data, phase modulation information, detector synchronization signal, and photoelectric integration time data;

[0110] S2. Calculate the frame period of the displayed image based on the phase modulation information, the detector's synchronization signal, and the photoelectric integration time data;

[0111] S3. Calculate the maximum frame rate of the displayed image based on the binary pulse width modulation method;

[0112] S4. When the photoelectric integration time of the detector changes, obtain the changed photoelectric integration time and calculate the new time base.

[0113] S5. Adjust the display frame rate of the image by modifying the parameters of the registers in the control timing according to the new time base;

[0114] S6. Use the detector's synchronization signal to synchronize the detector's photoelectric integration time with the display frame rate generated by the DMD.

[0115] Furthermore, the method specifically includes:

[0116] Get the DMD data loading time t load DMD block reset time t reset The display hold time t of the DMD base ;

[0117] Calculate the frame period t for displaying an n-bit grayscale image, where t = 2t. load +10t reset +(2 n -1)t base ;

[0118] Calculate the maximum frame rate F for displaying an n-bit grayscale image.

[0119] When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained as T, and then substituted into the formula for calculating the maximum frame rate F to form a corresponding relationship.

[0120] The new time base is calculated according to the formula.

[0121] ′

[0122] Based on the new time base t base The display frame rate of the image can be adjusted by modifying the parameters of the registers in the control timing.

[0123] The photoelectric integration time of the detector is synchronized with the display frame rate generated by the DMD using the detector's synchronization signal. When displaying an image, the output image of the DMD is displayed on the projection screen.

[0124] Furthermore, the display of an n-bit grayscale image using pulse width modulation requires n bit planes to achieve the modulation effect, corresponding to the display of 2 n There are 8 gray levels, where n = 8.

[0125] For specific limitations on the DMD high frame rate display method that matches the photoelectric integration time, please refer to the limitations on the DMD high frame rate display system that matches the photoelectric integration time mentioned above, which will not be repeated here.

[0126] The DMD high frame rate display system and method provided in this application, which matches the photoelectric integration time, is based on the traditional pulse width modulation method. By adjusting the display time base, the display period can be changed to match the detector's photoelectric integration time. Therefore, the display time base can be calculated backward from the detector's photoelectric integration time using the detector's synchronization signal to meet the requirements of matching the photoelectric integration time. This achieves synchronization between the detector's photoelectric integration time and the DMD display frame rate, eliminating false signals, flickering, and image confusion. Furthermore, matching the detector's real-time changing photoelectric integration time enables optimal imaging results.

[0127] DMD high frame rate display technology, which matches the real-time changing photoelectric integration time of the detector, can adjust the photoelectric integration time in real time during imaging to avoid overexposure or underexposure of the image, thereby obtaining higher quality images. This technology has wide applications in scientific research, medical imaging, industrial production, and other fields.

[0128] Specifically, this technology can improve the temporal resolution of imaging, making the imaging of fast dynamic processes clearer; at the same time, it can improve the spatial resolution, resulting in more detailed images. Furthermore, this technology can achieve full-process simulation of infrared detectors, improving the reliability of infrared detectors and reducing the cost of researching and developing infrared detectors.

[0129] In summary, DMD high frame rate display technology, which matches the real-time changing photoelectric integration time of the detector, has broad application value and significance, and has great development prospects in different fields.

[0130] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0131] The above provides a detailed description of a DMD high frame rate display system and method with matching photoelectric integration time provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A DMD high frame rate display system with matching photoelectric integration time, characterized in that, Includes detector, host computer, main control board, DMD, light source driver, lighting system and projection screen; The detector is used to generate synchronization signals and photoelectric integration time data; The host computer is used to generate image data; The main control board is used to acquire and cache image data, phase modulation information, detector synchronization signal and photoelectric integration time data generated by the host computer; when displaying an image, it sends the cached image data, phase modulation information, detector synchronization signal and photoelectric integration time data to the DMD. The DMD calculates the frame period of the displayed image based on phase modulation information, the detector's synchronization signal, and photoelectric integration time data, and calculates the maximum frame frequency of the displayed image based on binary pulse width modulation. When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained and a new time base is calculated; the parameters of the registers in the control timing are modified according to the new time base to adjust the display frame rate of the image. The main control board is used to synchronize the photoelectric integration time of the detector with the display frame rate generated by the DMD using the detector's synchronization signal. When displaying an image, it controls the light source to drive the lighting system to display the output image of the DMD on the projection screen. Specifically, the DMD calculates the frame period of the displayed image based on phase modulation information, the detector's synchronization signal, and photoelectric integration time data, and calculates the maximum frame frequency of the displayed image based on binary pulse width modulation. When the detector's photoelectric integration time changes, the changed photoelectric integration time is acquired and a new time base is calculated. The parameters of the registers in the control timing are modified according to the new time base to adjust the image display frame frequency, specifically including: Get DMD data loading time DMD block reset time DMD display hold time ; Calculate the frame period t for displaying an n-bit grayscale image. ; Calculate the maximum frame rate F for displaying an n-bit grayscale image. ; When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained as T, and then substituted into the formula for calculating the maximum frame rate F to form a corresponding relationship. ; The new time base is calculated according to the formula. ; Based on the new time base The display frame rate of the image can be adjusted by modifying the parameters of the registers in the control timing.

2. The DMD high frame rate display system with matching photoelectric integration time as described in claim 1, characterized in that, The main control board includes a main control chip, an interface board, and a driver board; the interface board is connected to the driver board, the main control chip, and the host computer, and the driver board is connected to the DMD and the light source driver.

3. The DMD high frame rate display system with matching photoelectric integration time as described in claim 2, characterized in that, The interface board is equipped with a PCIe high-speed interface, an RS422 interface, and a JTAG interface; the PCIe high-speed interface is connected to the host computer and is used to transmit image data generated by the host computer; the RS422 interface is connected to the detector and is used to transmit the photoelectric integration time data of the detector; the JTAG interface is used to program the main control chip.

4. The DMD high frame rate display system with matching photoelectric integration time as described in claim 3, characterized in that, The driver board is equipped with a main control chip, a third-generation double-rate synchronous dynamic random access memory, a first non-volatile memory, a second non-volatile memory, a DMD driver chip, and a DMD micromirror flip voltage control chip; the main control chip is connected to the PCIe high-speed interface and the RS422 interface, the main control chip is connected to the third-generation double-rate synchronous dynamic random access memory, and the main control chip is connected to the DMD driver chip; The JTAG interface is connected to the main control chip through the first non-volatile memory, the JTAG interface is connected to the DMD driver chip through the second non-volatile memory, and the DMD driver chip is connected to the DMD micromirror flip voltage control chip.

5. The DMD high frame rate display system with matching photoelectric integration time as described in claim 4, characterized in that, The DMD is equipped with a ribbon cable interface and a DMD chip. The DMD driver chip and the DMD micromirror flip voltage control chip are connected to the DMD chip through the ribbon cable interface.

6. The DMD high frame rate display system with matching photoelectric integration time as described in claim 5, characterized in that, The DMD driver chip is model DDC4100; the DMD micromirror flip voltage control chip is model DAD2000, which generates the voltage to flip the DMD micromirrors and generates the level signal for DMD block reset or global reset; the ribbon cable interface uses a .7XGA DMD data cable with a line width of 32 bits; the DMD chip integrates 1024×768 micromirrors, corresponding to an image resolution of 1024×768.

7. A DMD high frame rate display method matching photoelectric integration time, characterized in that, include: When displaying an image, image data, phase modulation information, detector synchronization signals, and photoelectric integration time data are acquired. The frame period of the displayed image is calculated based on the phase modulation information, the detector's synchronization signal, and the photoelectric integration time data. The maximum frame rate of the displayed image is calculated based on the binary pulse width modulation method; When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained and the new time base is calculated. The display frame rate of the image is adjusted by modifying the parameters of the registers in the control timing according to the new time base; The photoelectric integration time of the detector is synchronized with the display frame rate generated by the DMD using the detector's synchronization signal; Specifically, the method includes: Get DMD data loading time DMD block reset time DMD display hold time ; Calculate the frame period t for displaying an n-bit grayscale image. ; Calculate the maximum frame rate F for displaying an n-bit grayscale image. ; When the photoelectric integration time of the detector changes, the changed photoelectric integration time is obtained as T, and then substituted into the formula for calculating the maximum frame rate F to form a corresponding relationship. ; The new time base is calculated according to the formula. ; Based on the new time base The display frame rate of the image can be adjusted by modifying the parameters of the registers in the control timing. The photoelectric integration time of the detector is synchronized with the display frame rate generated by the DMD using the detector's synchronization signal. When displaying an image, the output image of the DMD is displayed on the projection screen.

8. The DMD high frame rate display method with matching photoelectric integration time as described in claim 7, characterized in that, The display of an n-bit grayscale image using pulse width modulation requires n bit planes to achieve the modulation effect, corresponding to the display There are 8 gray levels, where n=8.

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