Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes a first semiconductor element and a second semiconductor element, wherein the first semiconductor element has a plurality of connection pads, and the second semiconductor element has a plurality of bonding regions bonded to the plurality of connection pads in a one-to-one correspondence, wherein each bonding region includes a plurality of bonding pads, and the area of ​​the bonding region is greater than the area of ​​the connection pad; when the connection pad and the corresponding bonding region are in a limit bonding position and a target bonding position, the effective bonding area of ​​the connection pad and the bonding pad in the bonding region is equal to the target area. The present disclosure can make the bonding region and the connection pad have a good positional offset when bonding without increasing the size of the connection pad and the bonding pad, thereby reducing the risk of bonding failure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] When hybrid bonding is performed on two semiconductor components, in order to ensure a good bonding effect, the corresponding pads on the two semiconductor components are usually designed to have a larger and a smaller size, so as to increase the positional displacement of the semiconductor components. However, in this method, the allowable positional displacement during hybrid bonding is still relatively small.

[0003] In order to increase the positional offset, the size of the larger pad is usually set larger. However, since hybrid bonding requires controlling the dishing on the pad to a reasonable size, setting a larger pad will easily increase the difficulty of controlling the dishing, affecting the electrical performance of the product connection pad after hybrid bonding. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0006] According to a first aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising a first semiconductor element and a second semiconductor element, the first semiconductor element having a plurality of connection pads, the second semiconductor element having a plurality of bonding regions bonded to the plurality of connection pads in a one-to-one correspondence, each of the bonding regions comprising a plurality of bonding pads, the area of ​​the bonding region being greater than the area of ​​the connection pads;

[0007] When the connection pad and the corresponding bonding region are at the extreme bonding position and the target bonding position, the effective bonding area between the connection pad and the bonding pad in the corresponding bonding region is equal to the target area.

[0008] According to some embodiments of the present disclosure, in each of the bonding regions, the distance between two adjacent bonding pads is a first distance, and the sizes of any two bonding pads are equal;

[0009] The connection pad and the bonding area are both square in shape. When the connection pad and the corresponding bonding area are at the target bonding position, the projection of the connection pad on the second semiconductor element is located within the corresponding bonding area, and the distances between the four edges of the connection pad and the four edges of the bonding area are all second distances.

[0010] According to some embodiments of the present disclosure, the bonding pad is in the shape of a square or a circle;

[0011] The extreme bonding position includes a first extreme bonding position. When the connection pad and the corresponding bonding area are at the first extreme bonding position relative to the target bonding position, the connection pad is offset by a first extreme distance in a direction perpendicular to an edge of the connection pad.

[0012] The first limit distance is equal to the sum of a third distance and the first distance, and the third distance is the difference between the side length or diameter of the bonding pad and the second distance.

[0013] According to some embodiments of the present disclosure, relative to the target bonding position, the extreme bonding position includes a first extreme bonding position, and when the connection pad and the corresponding bonding area are in the second extreme bonding position, the connection pad is offset by a second extreme distance along the diagonal direction of the connection pad.

[0014] According to some embodiments of the present disclosure, the second limit distance is equal to the sum of a fourth distance and a fifth distance, the fourth distance is the product of square root of two and the first distance, and the fifth distance is the product of square root of two and the third distance.

[0015] According to some embodiments of the present disclosure, the first distance is a minimum lithography pitch.

[0016] According to some embodiments of the present disclosure, each of the bonding regions includes four bonding pads arranged in an array.

[0017] According to some embodiments of the present disclosure, an area of ​​the connection pad is larger than an area of ​​the bonding pad.

[0018] According to some embodiments of the present disclosure, the connection pad is disposed in the first dielectric layer of the first semiconductor element, and the bonding surface of the connection pad is exposed outside the first dielectric layer;

[0019] The bonding pads of the bonding area are arranged in the second dielectric layer of the second semiconductor element, and the bonding surface of the bonding pads is exposed outside the second dielectric layer; in the bonding area, an isolation layer is arranged on the surface of the second dielectric layer between the bonding pads;

[0020] When the connection pad is bonded to the corresponding bonding area, part of the connection pad is in contact with the isolation layer.

[0021] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0022] Providing a first semiconductor element, wherein a plurality of connection pads are formed on the first semiconductor element;

[0023] Providing a second semiconductor element, on which a plurality of bonding regions corresponding to the plurality of connection pads are formed, each of the bonding regions comprising a plurality of bonding pads, and an area of ​​the bonding region being larger than an area of ​​the connection pads;

[0024] Each of the connection pads is bonded to the corresponding bonding region, and an effective bonding area between the connection pad and the bonding pad in the corresponding bonding region is equal to a target area.

[0025] In the semiconductor structure and manufacturing method provided by the present disclosure, a plurality of bonding pads are arranged in the bonding area on the second semiconductor element, and when the bonding area is bonded to the connection pad on the first semiconductor element, the connection pad and the bonding area can be at the limit bonding position deviating from the target bonding position, and the effective bonding area of ​​the two can still be equal to the target area. In this way, without increasing the size of the connection pad and the bonding pad, the bonding area and the connection pad can have a good position offset when bonding, reducing the risk of bonding failure.

[0026] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1a to Figure 1d A schematic diagram of a semiconductor structure at different bonding locations.

[0029] Figure 2 is a cross-sectional view of a semiconductor structure according to an exemplary embodiment.

[0030] Figure 3 is a diagram showing the bonding process at different bonding positions according to an exemplary embodiment. Figure 2 Cross-sectional view along the AA direction.

[0031] Figure 4 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0032] Figure 5 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0033] Figure 6 The cross-sectional view of a comparative embodiment at different bonding positions is shown.

[0034] Figure 7 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0035] Figure 8 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0036] Fig. 9 The cross-sectional view of a comparative embodiment at different bonding positions is shown.

[0037] Fig.10 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0038] Fig.11 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0039] Fig.12 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0040] Fig.13 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0041] Fig.14 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0042] Fig.15 According to another exemplary embodiment, Figure 2 Cross-sectional view along the AA direction.

[0043] Fig.16 is a schematic diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0044] Description of reference numerals:

[0045] 100, semiconductor structure; 10, first semiconductor element; 11, first pad; 101, connection pad; 102, first dielectric layer; 103, barrier layer; 20, second semiconductor element; 21, second pad; 201, bonding area; 211, bonding pad; 212, spacing area; 202, second dielectric layer; 203, isolation layer; 30, dished depression. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0047] When hybrid bonding is performed on two semiconductor components, in order to ensure that the connection pads after hybrid bonding have good electrical performance, the sizes of the corresponding pads on the two semiconductor components are usually designed to be large and small, so as to increase the positional displacement of the semiconductor components. Figure 1a and Figure 1b As shown in FIG. 1 , the size of the first pad 11 on the first semiconductor element 10 is set to be larger than the size of the second pad 21 on the second semiconductor element 20, so that the alignment accuracy between the first pad 11 and the second pad 21 is poor. Figure 1b When the position shown is the same, the contact area between the first pad 11 and the second pad 21 can still be equal to Figure 1a The expected alignment accuracy shown is the contact area between the two, that is, the area of ​​the second pad 21. That is, the first pad 11 and the second pad 21 adopt Figure 1b When bonding is performed at the bonding position shown, the electrical connection performance of the first semiconductor element 10 and the second semiconductor element 20 will not be affected by the alignment accuracy deviation. At this time, the position deviation amount of the hybrid bonding is equal to half of the difference between the size of the first pad 11 (denoted as A1) and the size of the second pad 21 (denoted as A2), and the position deviation amount can be expressed as (A1+A2) / 2.

[0048] However, when the alignment accuracy of the first pad 11 and the second pad 21 is Figure 1b The location shown is worse when referring to Figure 1cAs shown, the offset of the first semiconductor element 10 relative to the second semiconductor element 20 is greater than (A1+A2) / 2. At this time, the second pad 21 is in an incomplete contact state with the first pad 11, and the contact area between the first pad 11 and the second pad 21 is smaller than the area of ​​the second pad 21. Therefore, in the above setting method, the allowable position offset during hybrid bonding is relatively small, and the corresponding accuracy requirements for the corresponding pads on the two semiconductor elements are still relatively large, and the bonded semiconductor structure still has a greater risk of bonding failure.

[0049] In the prior art, in order to increase the positional offset when two semiconductor elements are aligned, the size of the larger pad is usually set to be larger, that is, to increase the size of the pad. Figure 1a The size of the first pad 11 on the first semiconductor element 10 shown in FIG. 1 is such that the positions of the first semiconductor element 10 and the second semiconductor element 20 can be shifted by an amount greater than (A1+A2) / 2.

[0050] It should be noted that, when hybrid bonding is performed, the bonding surface of the semiconductor element needs to be flattened by chemical-mechanical polishing (CMP), and at the same time, a dish-shaped depression of a reasonable size needs to be formed on the pad of the semiconductor element. Figure 1d As shown, the bonding surfaces of the first pad 11 and the second pad 21 relative to each other are provided with a dish-shaped recess 30 of a reasonable size, so that the first pad 11 and the second pad 21 expand during the hybrid bonding process to complete the firm bonding of the first pad 11 and the second pad 21, so that the first semiconductor element 10 and the second semiconductor element 20 form a good electrical connection. When the dish-shaped recess 30 is provided, the size of the dish-shaped recess 30 cannot be too large, so as to avoid the formation of a gap between the first pad 11 and the second pad 21 after the first pad 11 and the second pad 21 are bonded, thereby affecting the bonding effect of the first pad 11 and the second pad 21. At the same time, since the first pad 11 and the second pad 21 will expand slightly during the hybrid bonding process for bonding, a certain space needs to be reserved to meet the expansion requirements of the pads, and the size of the dish-shaped recess 30 cannot be too small.

[0051] If the size of the first pad 11 is further increased in order to increase the positional displacement, it will be more difficult to control the size of the dished recess 30 during the CMP process, which will easily affect the electrical performance between the first pad 11 and the second pad 21 after hybrid bonding.

[0052] In view of this, the present disclosure provides a semiconductor structure, the semiconductor structure includes a first semiconductor element and a second semiconductor element, the first semiconductor element has a plurality of connection pads, the second semiconductor element has a plurality of bonding areas bonded to the plurality of connection pads in a one-to-one correspondence, each bonding area includes a plurality of bonding pads, the area of ​​the bonding area is larger than the area of ​​the connection pad; when the connection pad and the corresponding bonding area are in the extreme bonding position and the target bonding position, the effective bonding area of ​​the connection pad and the bonding pad in the bonding area is equal to the target area. The present disclosure can make the bonding area and the connection pad have a good positional offset when bonding without increasing the size of the connection pad and the bonding pad, thereby reducing the risk of bonding failure.

[0053] The present disclosure is described below in conjunction with the accompanying drawings and specific embodiments. The exemplary embodiment of the present disclosure provides a semiconductor structure, such as Figure 2 As shown, Figure 2 1 is a cross-sectional view of a semiconductor structure according to an exemplary embodiment, wherein the semiconductor structure 100 includes a first semiconductor element 10 and a second semiconductor element 20, which are combined in a face-to-face (F2F) manner to form the semiconductor structure 100. The first semiconductor element 10 and the second semiconductor element 20 may be any one of a wafer, a die, or a substrate, respectively, so that the first semiconductor element 10 and the second semiconductor element 20 may be combined in a wafer-to-wafer (W2W), a die-to-die (D2D), a die-to-wafer (D2W), a die-to-substrate (D2S), or the like.

[0054] The first semiconductor element 10 has a plurality of connection pads 101, which are electrically connected to the semiconductor device in the first semiconductor element 10. The connection pads 101 may be metal pads formed on the surface of the first semiconductor element 10. The connection pads 101 are used to bond with other semiconductor elements such as the second semiconductor element 20. The bonding method may be, for example, hybrid bonding to achieve electrical connection between the first semiconductor element 10 and the second semiconductor element 20. Exemplarily, the connection pads 101 may be circular, rectangular, square, or the like.

[0055] refer to Figures 2 to 5The second semiconductor element 20 has a plurality of bonding regions 201, each of which includes a plurality of bonding pads 211, which are electrically connected to the semiconductor device in the second semiconductor element 20, and the bonding pads 211 may be metal pads formed on the surface of the second semiconductor element 20. It should be noted that the plurality of bonding pads 211 in each bonding region 201 are electrically connected, that is, the plurality of bonding pads 211 in each bonding region 201 transmit the same electrical signal. The bonding region 201 also includes a spacing region 212 for isolating adjacent bonding pads 211, and the spacing region 212 may be formed of an insulating material. The bonding region 201 is configured to include a spacing region 212 and a plurality of bonding pads 211 separated by the spacing region 212, so that the bonding area of ​​the bonding region 201 can be increased without increasing the difficulty of controlling the dish-shaped depression, thereby increasing the bonding deflection amount of the semiconductor structure 100. Exemplarily, the number of bonding pads 211 may be 2, 3, 4, 9, 16, etc., the shape of bonding pads 211 may be circular, square, rectangular, etc., and the shape of bonding area 201 may also be circular, square, rectangular, etc. Each bonding area 201 corresponds to a connection pad 101 on the first semiconductor element 10 one by one, so that each bonding area 201 can be bonded to one connection pad 101 one by one.

[0056] Exemplarily, the materials forming the bonding pad 211 and the connection pad 101 may include conductive metal materials such as copper, cobalt, aluminum, copper alloys, cobalt alloys, and aluminum alloys, and may also include any other suitable metal materials or alloy materials such as chromium, gold, silver, and nickel. In some embodiments, the materials forming the bonding pad 211 and the connection pad 101 are copper or copper-based alloys, and the copper-based alloys may include copper alloys containing a small amount of tin, zinc, manganese, titanium, magnesium, germanium, aluminum, and silicon. The activation energy of the lattice diffusion and the grain boundary diffusion binding energy of copper are both higher than those of aluminum, so that the electromigration of copper is much smaller than that of materials such as aluminum, so that the reliability of the bonding pad 211 and the connection pad 101 formed by copper is higher than that of other metals. Secondly, copper has a lower resistivity. The use of copper or copper-based alloys can greatly reduce the resistance of the interconnection after the bonding pad 211 and the connection pad 101 are bonded, thereby reducing the delay caused by the interconnection.

[0057] During the alignment process of the second semiconductor element 20 and the first semiconductor element 10, there may be process parameter errors, jig jitter and other reasons, which may cause the connection pad 101 to be unable to be in the target bonding position with the bonding area 201. Since the bonding area 201 includes multiple bonding pads 211, the area of ​​each bonding area 201 on the second semiconductor element 20 is set to be larger than the area of ​​the connection pad 101, so that when the connection pad 101 and the bonding area 201 are relatively offset within the allowable position offset during the alignment and placement process, the connection pad 101 can still contact with at least one bonding pad 211 in the bonding area 201, thereby reducing the impact of the deviation in alignment accuracy on the electrical performance of the semiconductor structure 100 after bonding. The target bonding position is the position where the connection pad 101 is exactly aligned with the corresponding bonding area 201, that is, the position when the connection pad 101 and the bonding area 201 are coaxially arranged. Combined with Figure 2 and Figure 3 , Figure 2 is a cross-sectional view of the semiconductor structure 100 when the connection pad 101 and the corresponding bonding area 201 are in the target bonding position, Figure 3 The graphs show the two are in the target bonding position and the limit bonding position. Figure 2 In the cross-sectional view along the AA direction in FIG, the second semiconductor element is omitted in the cross-sectional view. When the projection area of ​​the connection pad 101 on the corresponding bonding area 201 is ensured to be the same as the target area, the connection pad 101 and the bonding area 201 are in the extreme bonding position when the displacement of the connection pad 101 relative to the bonding area 201 reaches the maximum.

[0058] In some embodiments, reference Figure 3 As shown, when the bonding area 201 and the bonding pad 211 are both circular, the connection pad 101 is square, and the number of bonding pads 211 is 4, when the connection pad 101 and the bonding area 201 are in the target bonding position, the connection pad 101 is located at the center of the bonding area 201. At this time, the overlapping area of ​​the connection pad 101 and the multiple bonding pads 211 in the bonding area 201 is the effective bonding area, and the effective bonding area, that is, the target area, is the area of ​​one bonding pad 211. With this setting, continue to refer to Figure 3 , while ensuring that the projection area of ​​the connection pad 101 on the corresponding bonding area 201 is the same as the target area, the connection pad 101 can be offset in any direction relative to the bonding area 201, Figure 3 An extreme bonding position is shown in FIG.

[0059] For example, when the number of bonding pads 211 in the bonding area 201 is set to other numbers such as 2, 3 or other numbers, the connection pads 101 may be offset in the arrangement direction of the bonding pads 211. Figure 4 As shown, Figure 42 shows the corresponding positional relationship between the connection pad 101 and the corresponding bonding area 201 when the bonding area 201 includes three bonding pads 211, and the effective bonding area at the target bonding position and the limit bonding position is the target area. Figure 5 As shown, Figure 5 It shows that when the bonding area 201 includes two bonding pads 211, the connection pad 101 and the corresponding bonding area 201 are in the corresponding position relationship of the target bonding position and an extreme bonding position, and the effective bonding area at the target bonding position and the extreme bonding position are both the target area.

[0060] refer to Figure 6 As shown, Figure 6 FIG. 2 shows a configuration of a comparative embodiment. In this comparative embodiment, the bonding area 201 is provided with only one bonding pad 211. The bonding pad 211 is the bonding area 201. The bonding pad 211 is also circular and has a size similar to that of the bonding pad 211. Figures 3 to 5 The connection pad 101 is also square and has the same size as the embodiment shown in FIG. Figures 3 to 5 The same as the embodiment shown in FIG. Figures 3 to 6 , the target area in the embodiment provided by the present disclosure is the same as the target area in the comparative embodiment, which is the area of ​​the bonding pad 211. For example, when the diameter of the bonding pad 211 is 1, the distance between adjacent bonding pads is 1, and the side length of the connection pad 101 is 2, Figure 6 The limit bonding position in the comparative embodiment of the invention can be offset by (2-1) / 2=0.5 relative to the target bonding position. Figure 4 and Figure 5 The limit bonding position in can be offset by 1.5 relative to the target bonding position. Figure 3 The extreme bonding position in the embodiment provided by the present invention is offset diagonally relative to the target bonding position, and the offset amount is 2√2-0.5√2=1.5√2. It can be seen that, without increasing the size of the bonding pad 211 and the connecting pad 101, when ensuring that the effective bonding area at the extreme bonding position and the target bonding position are equal to the target area, the position offset amount of the extreme bonding position relative to the target bonding position in the embodiment provided by the present invention is much greater than the position offset amount of the extreme bonding position relative to the target bonding position in the comparative embodiment. Therefore, by adopting the method provided by the present invention, the bonding area 201 and the connecting pad 101 can have a good position offset amount during bonding without increasing the difficulty of forming the dish-shaped depression on the bonding pad 211 and the connecting pad 101, thereby reducing the alignment accuracy requirements of the first semiconductor element 10 and the second semiconductor element 20 and reducing the risk of bonding failure.

[0061] It should be noted that the shapes of the bonding area 201, the bonding pad 211 or the connecting pad 101 are not limited in the present disclosure, and the bonding area 201 only needs to surround multiple bonding pads 211 that transmit the same electrical signal. In the embodiments provided in the present disclosure, the bonding pad 211 may be in a square, rectangular or other shape, and the connecting pad 101 may be in a circular, rectangular or other shape. Of course, the bonding pads 211 in the same bonding area 201 may also be set to different shapes. When the shape of the bonding pad 211 or the connecting pad 101 is a rectangle, the extreme bonding position of the bonding pad 211 or the connecting pad 101 in the long side direction still has a good position offset, refer to the following example.

[0062] In some embodiments, reference Figure 7 As shown, Figure 7 The bonding area 201 and the bonding pad 211 in the bonding area 201 are shown in FIG. Figure 5 The embodiments shown are identical except that Figure 7 The connection pad 101 in the embodiment is in the shape of a rectangle. Figure 7 , the limit bonding position of the connection pad 101 offset in the long side direction of the connection pad 101 is Figure 5 The same as the embodiment shown in FIG. 1 , the corresponding position offset is also the same as Figure 5 The same as the embodiment shown in .

[0063] In other embodiments, reference Figure 8 As shown, Figure 8 The connection pads 101 shown in FIG. Figure 5 The embodiments shown are identical except that Figure 8 The shape of the bonding pad 211 in the bonding area 201 is a rectangle, and the shape of the bonding area 201 varies with the shape of the bonding pad 211, and can be set to be a rectangle surrounding multiple bonding pads 211. The effective bonding area of ​​the bonding area 201 and the connection pad 101 at the limit bonding position and the target bonding position, that is, the target area, is the area of ​​one bonding pad 211.

[0064] Fig. 9 For Figure 8 In a corresponding comparative embodiment, the bonding area 201 is provided with only one bonding pad 211, and the bonding pad 211 is the bonding area 201. The bonding pad 211 is also rectangular and has the same size as the bonding area 201. Figure 8 The connection pad 101 is also square and has the same size as the embodiment shown in FIG. Figure 8 The same as the embodiment shown in FIG. Figure 8 and Fig. 9 , Figure 8 and Fig. 9The target area in is the same as the area of ​​the bonding pad 211. It can be seen that without increasing the size of the bonding pad 211 and the connection pad 101, when the effective bonding area at the limit bonding position and the target bonding position is equal to the target area, Figure 8 The limit bonding position of the middle connection pad 101 in the long side direction of the bonding pad 211 can be offset relative to the target bonding position by a position greater than Fig. 9 The limit bonding position in the comparative example can be offset relative to the target bonding position.

[0065] In the semiconductor structure provided by the present disclosure, by setting the bonding area corresponding to the connection pad to include multiple bonding pads, and the area of ​​the bonding area is larger than the area of ​​the connection pad, the bonding area and the connection pad can have a good position offset when aligned before bonding, reducing the alignment accuracy requirements of the two semiconductor elements during bonding and reducing the risk of bonding failure. At the same time, there is no need to increase the size of the bonding area and the connection pad, avoiding increasing the difficulty of forming the bonding pad and the dish-shaped depression on the connection pad.

[0066] In an exemplary embodiment, reference Figures 2 to 5 ,as well as Figures 10 to 15 , in each bonding area 201, the distance between any two adjacent bonding pads 211 is equal, and the distance between two adjacent bonding pads 211 is a first distance (denoted as D1), and the first distance D1 can be a distance pre-set by a technician according to demand or experience. For example, since a plurality of bonding areas 201 need to be set on the second semiconductor element 20, in order to meet the number setting requirements of the bonding areas 201 and reduce the area occupied by each bonding area 201 on the second semiconductor element 20, the first distance D1 can be set to a distance as small as possible. However, if the first distance D1 is too small, it is easy to generate parasitic capacitance or parasitic resistance between two adjacent bonding pads 211, affecting the electrical performance of the semiconductor structure 100 after bonding. Therefore, the first distance D1 can be set as the minimum lithography spacing to meet the requirement that a sufficient number of bonding areas 201 can be formed on the second semiconductor element 20, and to minimize the parasitic capacitance or parasitic resistance between adjacent bonding pads 211. When forming the bonding pad 211, it is necessary to form multiple openings on the second semiconductor element 20 to accommodate the bonding pad 211. When forming a pattern of etching openings on the second semiconductor element 20, when the exposure process forms two adjacent openings on the second semiconductor element 20, the minimum spacing that can be formed between the two adjacent openings is the minimum photolithography spacing.

[0067] Among the multiple bonding pads 211 in each bonding area 201, the sizes of any two bonding pads 211 are equal. The size of the bonding pad 211 can be a size parameter such as side length, perimeter, diameter, etc. Figures 3 to 5 as well as Fig.10When the bonding pad 211 in the bonding area 201 is circular, the diameters of the plurality of bonding pads 211 in the bonding area 201 are the same, so that the areas of the plurality of bonding pads 211 are the same. Fig.11 When the bonding pads 211 in the bonding area 201 are square, the side lengths of the plurality of bonding pads 211 are the same, so that the areas of the plurality of bonding pads 211 are the same. In this way, it can be ensured that when the bonding area 201 and the corresponding connection pad 101 are in the target bonding position and the limit bonding position, the effective bonding area of ​​the connection pad 101 and the bonding pad 211 in the bonding area 201 is equal, that is, both are equal to the target area.

[0068] In this embodiment, combined with Figure 2 and Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 or Fig.15 When the connection pad 101 and the corresponding bonding area 201 are at the target bonding position, the projection of the connection pad 101 on the second semiconductor element 20 is located in the corresponding bonding area 201, so that the connection pad 101 can contact the multiple bonding pads 211 in the bonding area 201. At the same time, the shapes of the connection pad 101 and the bonding area 201 are both square, so that the distances between the four edges of the connection pad 101 and the four edges of the bonding area 201 are equal, that is, the connection pad 101 is at the center of the corresponding bonding area 201, and the distance between the two edges is the second distance (recorded as D2). Specifically, the second distance D2 can be determined based on the side length of the bonding area 201 and the side length of the connection pad 101.

[0069] When the connection pad 101 and the corresponding bonding area 201 are at the target bonding position, in some embodiments, refer to Fig.10 and Fig.11 As shown, the bonding area 201 and the connection pad 101 are both square. Fig.10 The bonding pads 211 in the embodiment are all circular. Fig.11 The bonding pads 211 in the figure are all square. Fig.10 and Fig.11 In the embodiment, the number of bonding pads 211 in each bonding area 201 is 4, and the distances between the edges of the connection pads 101 and the edges of the bonding area 201 are equal. Fig.12 and Fig.13 As shown, the bonding area 201 and the connection pad 101 are both square. Fig.12 The bonding pads 211 in the embodiment are all circular. Fig.13 The bonding pads 211 in the figure are all square. Fig.12 and Fig.13In the embodiment, the number of bonding pads 211 in each bonding area 201 is 9, and the distances between the edges of the connection pads 101 and the edges of the bonding area 201 are equal. Fig.14 and Fig.15 As shown, the bonding area 201 and the connection pad 101 are both square. Fig.14 The bonding pads 211 in the figure are all square. Fig.15 The bonding pads 211 in the embodiment are all circular. Fig.14 and Fig.15 In the embodiment, the number of the bonding pads 211 in each bonding region 201 is 3, and the distances between the edges of the connection pads 101 and the edges of the bonding region 201 are equal.

[0070] It should be noted that the bonding area 201 is set to be square in shape, so that the plurality of bonding pads 211 can be arranged in a uniform array in the bonding area 201. The connection pad 101 is set to be square in shape, so that when the connection pad 101 is offset to the extreme bonding position relative to the corresponding bonding area 201, no matter it is offset to the edge direction or diagonal direction of the connection pad 101, the connection pad 101 still has a good position offset relative to the bonding area 201.

[0071] In an exemplary embodiment, reference Figures 10 to 15 The shape of the bonding pad 211 in the bonding area 201 can be set to be circular or square. On the one hand, it can facilitate the uniform arrangement of the bonding pad 211 in the bonding area 201. On the other hand, since the diameter or side length of the circle and the square is the same, it can ensure that the effective bonding area is the target area. Under the premise of ensuring that the connecting pad 101 is offset to the extreme bonding position relative to the corresponding bonding area 201, regardless of offsetting to the edge direction or diagonal direction of the connecting pad 101, the connecting pad 101 still has a good position offset relative to the bonding area 201.

[0072] The extreme bonding positions of the connection pad 101 and the bonding area 201 may include a first extreme bonding position. Relative to the target bonding position, the first extreme bonding position is offset in a direction perpendicular to the edge of the connection pad 101. That is, when the connection pad 101 is offset by a first extreme distance in the upper, lower, left, and right directions of the bonding area 201, at this time, the connection pad 101 and the corresponding bonding area 201 are in the first extreme bonding position.

[0073] In some embodiments, reference Figures 10 to 13 When the number of bonding pads 211 in the bonding area 201 is exponentially distributed, for example, when the bonding area 201 includes 4, 9, 16, etc. bonding pads 211, the connection pad 101 can be offset by a first limit distance in the upper, lower, left, and right directions of the bonding area 201 to be in the first limit bonding position. Figure 4 , Figure 5 , Fig.14 and Fig.15 , when the number of bonding pads 211 in the bonding area 201 is non-exponentially distributed, for example, when the bonding area 201 includes 3 bonding pads 211, refer to Figure 4 , Fig.14 and Fig.15 , the connection pad 101 can be offset by a first limit distance in the upper and lower directions of the bonding area 201 to be in the first limit bonding position. For another example, when the bonding area 201 includes two bonding pads 211, the connection pad 101 can be offset by a first limit distance in the arrangement direction of the bonding pads 211 to be in the first limit bonding position. Figure 5 , the two bonding pads 211 in the bonding area 201 are arranged in a left and right manner. At this time, the connection pad 101 can be offset to the left and right directions of the bonding area 201 by a first limit distance.

[0074] refer to Figures 10 to 15 As shown, when the connection pad 101 and the bonding area 201 are in the target bonding position, the edges of the connection pad 101 are in contact with the bonding pad 211 at the edge of the bonding area 201, and because the shapes of the connection pad 101 and the bonding area 201 are both squares, the distances between the surrounding edges of the connection pad 101 and the surrounding edges of the bonding area 201 are all the second distance D2. Therefore, the contact distances between the surrounding edges of the connection pad 101 and the bonding pad 211 at the edge of the bonding area 201 are the difference between the diameter or side length of the bonding pad 211 and the second distance D2, that is, the third distance D3.

[0075] When the connection pad 101 is offset by a third distance D3 in a direction perpendicular to the edge of the connection pad 101, the connection pad 101 can contact with other bonding pads 211 in the bonding area 201 in the offset direction to bond, and its effective bonding area is still the target area. At this time, one side edge of the connection pad 101 and the edge of the offset portion of the bonding pad 211 are just in a staggered state, and there is a gap between two adjacent bonding pads 211, that is, the first distance D1. The connection pad 101 can also continue to offset the first distance D1 in the offset direction, and the effective bonding area of ​​the connection pad 101 and the bonding pad 211 in the bonding area 201 will not be changed. At this time, the distance that the connection pad 101 is offset in the direction perpendicular to the edge of the connection pad 101 is the sum of the third distance D3 and the first distance D1, that is, the first limit distance, and the connection pad 101 and the corresponding bonding area 201 are in the first limit bonding position.

[0076] Of course, it can be understood that for the bonding area 201 in which the number of bonding pads 211 is non-exponentially distributed, refer to Figure 4 and Figure 5After the connection pad 101 is offset by a first limit distance along a side edge perpendicular to the connection pad 101 and is at a first limit bonding position, the connection pad 101 still has a certain offset space in a direction perpendicular to the offset direction. Figure 4 , the connection pad 101 is offset upwards by a first limit distance relative to the bonding area 201 to reach the first limit bonding position in this direction. At this time, the lower edge of the connection pad 101 is just offset from the edge of a bonding pad 211, and the left and right edges of the connection pad 101 are not in contact with the bonding pad 211. In other words, on this basis, the connection pad 101 can continue to be offset by a certain distance relative to the left or right side of the bonding area 201, and the effective bonding area between the connection pad 101 and the bonding pad 211 in the bonding area 201 will not be changed. Figure 5 In a corresponding embodiment, the connection pad 101 may further be offset by a certain distance relative to the upper side or the lower side of the bonding area 201 , and the effective bonding area between the connection pad 101 and the bonding pad 211 in the bonding area 201 will not be changed.

[0077] In an exemplary embodiment, reference Figures 10 to 15 As shown, the extreme bonding position of the connection pad 101 and the bonding area 201 may also include a second extreme bonding position. Relative to the target bonding position, the second extreme bonding position is offset in the diagonal direction of the connection pad 101. That is, when the connection pad 101 is offset by the second extreme distance in the diagonal direction of the bonding area 201, for example, in the upper left, lower left, upper right, or lower right directions, then, the connection pad 101 and the corresponding bonding area 201 are in the second extreme bonding position.

[0078] In some embodiments, reference Figures 10 to 13 , when the number of bonding pads 211 in the bonding area 201 is exponentially distributed, for example, when the bonding area 201 includes 4, 9, 16, etc. bonding pads 211, the connection pad 101 can be offset by the second limit distance to the upper left, lower left, upper right, and lower right of the bonding area 201, respectively, so as to be in the second limit bonding position. Fig.14 and Fig.15 When the number of bonding pads 211 in the bonding area 201 is non-exponentially distributed, for example, when the bonding area 201 includes 3 bonding pads 211, the connection pad 101 can be offset by a second limit distance in a diagonal direction of the edge of the bonding area 201 with a larger number in the bonding area 201, so as to be in a second limit bonding position. Fig.14 and Fig.15 , the three bonding pads 211 in the bonding area 201 are arranged in a herringbone shape. At this time, the connection pad 101 can be offset to the lower left or lower right direction of the bonding area 201 by a second limit distance.

[0079] refer to Figures 10 to 15 As shown, when the connection pad 101 and the bonding area 201 are at the target bonding position, the contact distance between the edges of the connection pad 101 and the bonding pad 211 at the edge of the bonding area 201 is the difference between the diameter or side length of the bonding pad 211 and the second distance D2, that is, the third distance D3. Figures 10 to 13 As shown, when the number of bonding pads 211 in the bonding area 201 is exponentially distributed, the bonding pad 211 located at the edge of the bonding area 201 and on the diagonal of the connection pad 101 contacts and overlaps with the connection pad 101, and the third distance D3 in the horizontal direction and the third distance D3 in the vertical direction of the connection pad 101 form a small square. The length of the diagonal of the square is the contact distance between the connection pad 101 and the bonding pad 211 located at the edge of the bonding area 201 and on the diagonal of the connection pad 101, which is the fifth distance D5. The fifth distance D5 is the product of the square root of two and the third distance D3, that is, the fifth distance D5=D3√2.

[0080] When the connection pad 101 is offset by the fifth distance D5 along the diagonal direction of the connection pad 101, the connection pad 101 can contact with other bonding pads 211 in the bonding area 201 in the offset direction for bonding, and its effective bonding area is still the target area. At this time, one corner of the connection pad 101 is just in a staggered state with the edge of the offset portion of the bonding pad 211. On the diagonal line of the connection pad 101, there is a gap between the two bonding pads 211. Since the distance between the two adjacent bonding pads 211 is the first distance D1, the distance between the two bonding pads 211 on the diagonal line of the connection pad 101 is the product of the square root of two and the first distance D1, that is, the fourth distance D4 = D1√2. The connection pad 101 can also continue to offset the fourth distance D4 along the offset direction of the diagonal line, and it will not change the effective bonding area of ​​the connection pad 101 and the bonding pad 211 in the bonding area 201. At this time, the distance that the connecting pad 101 is offset along the diagonal direction of the connecting pad 101 is the sum of the fifth distance D5 and the fourth distance D4, that is, the second limit distance. The second limit distance can be expressed as D4+D5=D1√2+D3√2=√2(D1+D3), and the connecting pad 101 and the corresponding bonding area 201 are in the second limit bonding position.

[0081] Exemplarily, the area of ​​the connection pad 101 should be larger than the area of ​​the bonding pad 211, so that the connection pad 101 can completely cover at least one bonding pad 211 in the bonding area 201, so as to ensure that regardless of whether the connection pad 101 and the corresponding bonding area 201 are in the target bonding position, the first extreme bonding position or the second extreme bonding position, the effective bonding area between the connection pad 101 and the bonding pad 211 in the bonding area 201 can be equal to the area of ​​at least one bonding pad 211, so as to ensure good electrical contact between the connection pad 101 and the bonding area 201.

[0082] In an exemplary embodiment, reference Figure 2 , Figure 3 , Fig.10 and Fig.11 As shown, each bonding area 201 includes four bonding pads 211 arranged in an array, which can ensure that when the connection pad 101 is offset relative to its corresponding bonding area 201, the connection pad 101 can be offset to the upper, lower, left or right of the bonding area 201 by a first limit distance, or can be offset to the upper left, lower left, upper right or lower right of the bonding area 201 by a second limit distance. That is to say, under the premise of ensuring that the semiconductor structure 100 has good electrical properties, four bonding pads 211 arranged in an array are provided in each bonding area 201, and the first semiconductor element 10 and the second semiconductor element 20 have a relatively large positional offset.

[0083] In other embodiments, for example, when each bonding region 201 includes two bonding pads 211, refer to Figure 5 , Figure 7 and Figure 8 , the connection pad 101 can only be offset by a first limit distance in the arrangement direction of the two bonding pads 211, for example, to the left or right of the bonding area 201. Although it also has a good position offset, the offset direction has a large limitation. For another example, when each bonding area 201 includes three bonding pads 211, refer to Figure 4 , Fig.14 and Fig.15 , the connection pad 101 can only be offset to the upper or lower side of the bonding area 201 by a first limit distance, or to the lower left or lower right side of the bonding area 201 by a second limit distance. Although it also has a good position offset, the offset direction has certain limitations. For another example. When each bonding area 201 includes 9 bonding pads 211, refer to Fig.12 and Fig.13 Although the connection pad 101 can be offset by a first limit distance to the top, bottom, left or right of the bonding area 201, it can also be offset by a second limit distance to the upper left, lower left, upper right or lower right of the bonding area 201. However, a large number of bonding pads 211 are arranged in the bonding area 201. Compared with 4 bonding pads 211 are arranged in each bonding area 201, it is not possible to further increase the position offset amount, and the area occupied by each bonding area 201 on the second semiconductor element 20 will be increased, which may easily lead to the arrangement of the bonding area 201 failing to meet the preset requirements.

[0084] In an exemplary embodiment, reference Figure 2As shown, since the semiconductor structure 100 is formed by hybrid bonding of the first semiconductor element 10 and the second semiconductor element 20, in the first semiconductor element 10, the connection pad 101 can be arranged in the first dielectric layer 102 on the surface of the first semiconductor element 10, and the bonding surface of the connection pad 101 is exposed outside the first dielectric layer 102, so that the connection pad 101 can be bonded with the second semiconductor element 20. An electrical connection layer (not shown in the figure) electrically connected to the semiconductor device inside the first semiconductor element 10 and the connection pad 101 can also be arranged in the first dielectric layer 102, so that the connection pad 101 can transmit the electrical signal emitted from the inside of the first semiconductor element 10. Similarly, in the second semiconductor element 20, a plurality of bonding pads 211 in the bonding area 201 can be arranged in the second dielectric layer 202 on the surface of the second semiconductor element 20, and the bonding surface of the bonding pad 211 is exposed outside the second dielectric layer 202, so that the bonding pad 211 in the bonding area 201 can be bonded with the first semiconductor element 10. An electrical connection layer (not shown in the figure) electrically connected to the semiconductor device inside the second semiconductor element 20 and the bonding pad 211 in each bonding area 201 can also be provided in the second dielectric layer 202, so that the bonding pad 211 in each bonding area 201 can transmit the electrical signal emitted from the inside of the second semiconductor element 20. Exemplarily, the forming material of the first dielectric layer 102 and the second dielectric layer 202 can be an insulating material, including but not limited to silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc.

[0085] When copper or copper-based alloy is used as the material for forming the connection pad 101 and the bonding pad 211, the metal copper will diffuse through the materials such as silicon dioxide in the first dielectric layer 102 and the second dielectric layer 202, thereby causing contamination to other silicon devices in the first semiconductor element 10 and the second semiconductor element 20. Before forming the connection pad 101 and the bonding pad 211, a barrier layer 103 is provided on the sidewalls and bottom surface of the opening in the first dielectric layer 102 for forming the connection pad 101, so as to prevent the metal copper from diffusing in the first dielectric layer 102. Similarly, an isolation layer 203 is provided on the sidewalls and bottom surface of the opening in the second dielectric layer 202 for forming the bonding pad 211, so as to prevent the metal copper from diffusing in the second dielectric layer 202. When the isolation layer 203 is provided on the sidewalls and bottom surface of the opening for forming the bonding pad 211, the isolation layer 203 can be provided on the surface of the second dielectric layer 202 in the spacing area 212 between the bonding pads 211 in the bonding area 201 to reduce the diffusion of metal copper in the connection pad 101 into the second dielectric layer 202 after bonding.

[0086] The materials forming the barrier layer 103 and the isolation layer 203 must be incompatible with metallic copper and must be conductive materials. The materials forming the barrier layer 103 and the isolation layer 203 may include, for example, metallic tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten nitride (WN), Ti-TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN), etc. The diffusion activation energy of metallic copper in the barrier layer 103 or the isolation layer 203 formed of these materials is very high, which can prevent the diffusion of metallic copper. Exemplarily, the barrier layer 103 and the isolation layer 203 can adopt a double-layer structure of metal tantalum and tantalum nitride. A layer of tantalum nitride is first arranged to improve the adhesion between the connection pad 101 subsequently formed in the opening and the first dielectric layer 102, and to improve the adhesion between the bonding pad 211 subsequently formed and the second dielectric layer 202. Then a layer of metal tantalum is deposited to cover the tantalum nitride, so that the metal tantalum in the opening can easily obtain a large-grain copper seed layer, so as to improve the reliability of the formed connection pad 101 and the bonding pad 211.

[0087] When the connection pad 101 is bonded to the corresponding bonding area 201, no matter what bonding position the connection pad 101 and the bonding area 201 are in, part of the connection pad 101 is in contact with the isolation layer 203 on the surface of the second semiconductor element 20, so as to prevent the metal copper forming the connection pad 101 from diffusing in the semiconductor structure 100 after bonding, thereby ensuring the reliability of the semiconductor structure 100.

[0088] In an exemplary embodiment, the present disclosure also provides a method for manufacturing a semiconductor structure, referring to Fig.16 As shown, the manufacturing method is used to manufacture the semiconductor structure provided by the above embodiment of the present disclosure, and the manufacturing method comprises the following steps:

[0089] Step S100, providing a first semiconductor element, wherein a plurality of connection pads are formed on the first semiconductor element;

[0090] Step S200, providing a second semiconductor element, on which a plurality of bonding regions corresponding to the plurality of connection pads are formed, each bonding region including a plurality of bonding pads, and an area of ​​the bonding region is larger than an area of ​​the connection pads;

[0091] Step S300 , bonding each connection pad to its corresponding bonding region, and an effective bonding area between the connection pad and the bonding pad in the corresponding bonding region is equal to a target area.

[0092] In step S100, the first semiconductor element can be any one of a wafer, a crystal grain or a substrate. When forming a plurality of connection pads on the first semiconductor element, a plurality of openings can be formed on the surface of the first semiconductor element, each of which exposes an electrical connection layer electrically connected to the semiconductor device inside the first semiconductor element. A plurality of connection pads are formed by filling a metal material in the opening and flattening the surface of the first semiconductor element after filling the metal material. The plurality of connection pads are used to bond with other semiconductor elements such as the second semiconductor element to achieve electrical connection between the first semiconductor element and the second semiconductor element. Exemplarily, the metal material forming the connection pads may include conductive metal materials such as copper, cobalt, aluminum, copper alloy, cobalt alloy, aluminum alloy, and may also include any other suitable metal material or alloy material such as chromium, gold, silver, nickel, etc. In some embodiments, when copper or copper-based alloy is used to form the connection pads, a damascene process may be used to form a plurality of connection pads on the first semiconductor element.

[0093] In step S200, similar to step S100, the second semiconductor element can be any one of a wafer, a crystal grain or a substrate, and a plurality of bonding areas are formed on the second semiconductor element, and the position of each bonding area corresponds to the position of the plurality of connection pads on the first semiconductor element one by one, so that each connection pad can be bonded to a connection pad in the subsequent bonding process, so that the formed semiconductor structure has good electrical properties. A plurality of bonding pads are arranged in each bonding area, and the plurality of bonding pads can be formed by a process similar to that of forming the connection pads. A plurality of bonding pads are arranged in each bonding area, and the area of ​​the bonding area is larger than the area of ​​the connection pad, so that when the connection pad and the bonding area are relatively offset within the allowable position offset during the alignment placement process, the connection pad can still contact with at least one bonding pad in the bonding area, thereby reducing the influence of the deviation of the alignment accuracy on the electrical properties of the semiconductor structure after bonding.

[0094] In step S300, a side surface of the first semiconductor element provided with a connection pad is arranged opposite to a side surface of the second semiconductor element provided with a bonding area, and an alignment fixture is used to match the position of the connection pad with the bonding area one by one and make the connection pad contact the corresponding bonding area, so that the first semiconductor element and the second semiconductor element are arranged overlappingly. The overlapping first semiconductor element and the second semiconductor element are arranged in a high temperature environment, and each connection pad and the corresponding bonding area expand at high temperature to bond with each other, so that the first semiconductor element and the second semiconductor element are electrically connected to form a semiconductor structure. Since the effective bonding area of ​​the connection pad and the bonding pad in the corresponding bonding area is equal to the target area. Since multiple bonding pads are arranged in each bonding area on the second semiconductor element, and the area of ​​the bonding area is larger than the area of ​​the connection pad, the bonding area and the connection pad can have a good position offset when aligned before bonding, reducing the alignment accuracy requirements of the two semiconductor elements during bonding, and reducing the risk of bonding failure. At the same time, there is no need to increase the size of the bonding area and the connection pad, avoiding increasing the difficulty of forming the bonding pad and the dish-shaped depression on the connection pad.

[0095] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0096] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0097] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0098] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0099] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0100] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing technology and technology of the device are described below to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises a first semiconductor element and a second semiconductor element, the first semiconductor element has a plurality of connection pads, the second semiconductor element has a plurality of bonding regions bonded to the plurality of connection pads in a one-to-one correspondence, each of the bonding regions comprises a plurality of bonding pads, the area of ​​the bonding region is larger than the area of ​​the connection pads, the connection pads are arranged in a first dielectric layer of the first semiconductor element, and the bonding surface of the connection pads is exposed outside the first dielectric layer; The bonding pad of the bonding area is disposed in the second dielectric layer of the second semiconductor element, and the bonding surface of the bonding pad is exposed outside the second dielectric layer; In the bonding area, an isolation layer is provided on the surface of the second dielectric layer between the bonding pads, and when the connection pads are bonded to the corresponding bonding area, part of the connection pads are in contact with the isolation layer; When the connection pad and the corresponding bonding region are at the extreme bonding position and the target bonding position, the effective bonding area between the connection pad and the bonding pad in the corresponding bonding region is equal to the target area.

2. The semiconductor structure according to claim 1, characterized in that: In each of the bonding areas, the distance between two adjacent bonding pads is a first distance, and the sizes of any two bonding pads are equal; when the connection pad and the corresponding bonding area are in the target bonding position, the projection of the connection pad on the second semiconductor element is located in the corresponding bonding area, and the distances between the surrounding edges of the connection pad and the surrounding edges of the bonding area are all second distances.

3. The semiconductor structure according to claim 2, characterized in that: The extreme bonding position includes a first extreme bonding position. When the connection pad and the corresponding bonding area are at the first extreme bonding position relative to the target bonding position, the connection pad is offset by a first extreme distance in a direction perpendicular to an edge of the connection pad. The first limit distance is equal to the sum of a third distance and the first distance, and the third distance is the difference between the side length or diameter of the bonding pad and the second distance.

4. The semiconductor structure according to claim 3, characterized in that: The extreme bonding position includes a second extreme bonding position. Relative to the target bonding position, when the connection pad and the corresponding bonding area are in the second extreme bonding position, the connection pad is offset by a second extreme distance along a diagonal direction of the connection pad.

5. The semiconductor structure according to claim 4, characterized in that: The second limit distance is equal to the sum of a fourth distance and a fifth distance, the fourth distance is the product of square root of two and the first distance, and the fifth distance is the product of square root of two and the third distance.

6. The semiconductor structure according to claim 2, characterized in that: The first distance is the minimum photolithography spacing.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: Each of the bonding areas includes four bonding pads arranged in an array.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The area of ​​the connection pad is larger than the area of ​​the bonding pad.

9. The semiconductor structure according to claim 1, characterized in that: The connection pad and the bonding area are both square in shape, and the bonding pad is square or circular in shape.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a first semiconductor element, wherein a plurality of connection pads are formed on the first semiconductor element, the connection pads are arranged in a first dielectric layer of the first semiconductor element, and bonding surfaces of the connection pads are exposed outside the first dielectric layer; A second semiconductor element is provided, wherein a plurality of bonding regions corresponding to the plurality of connection pads are formed on the second semiconductor element, each of the bonding regions comprises a plurality of bonding pads, the bonding pads of the bonding regions are arranged in a second dielectric layer of the second semiconductor element, the bonding surfaces of the bonding pads are exposed outside the second dielectric layer, the area of ​​the bonding regions is larger than the area of ​​the connection pads, and an isolation layer is arranged on the surface of the second dielectric layer between the bonding pads in the bonding regions; Each of the connection pads is bonded to the corresponding bonding area, a portion of the connection pads is in contact with the isolation layer, and an effective bonding area between the connection pad and the bonding pad in the corresponding bonding area is equal to a target area.

Images