Power semiconductor element driving circuit, semiconductor device and power conversion device

Abstract

A drive circuit (100) drives a power semiconductor element (1) having a gate electrode (1g), a first main electrode (1c), and a second main electrode (1e). The drive circuit (100) comprises: a control unit (2) for controlling the on / off state of the power semiconductor element (1) according to an instruction received from the outside; a short circuit determination unit (3) for determining whether the power semiconductor element (1) is in a short circuit state when the power semiconductor element (1) is turned on, and outputting a determination signal indicating the determination result; and a filter (4) for receiving the determination signal from the short circuit determination unit (3), generating a delayed signal of the determination signal, and outputting the signal to the control unit (2). The delay time in the filter (4) is set to be longer than the length of the Miller period when the power semiconductor element (1) is turned on.

Description

Technical Field

[0001] The present disclosure relates to a drive circuit for a power semiconductor element, a semiconductor device, and a power conversion device. Background Art

[0002] In a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a large current flows when a short circuit occurs, so there is a possibility of thermal damage to the semiconductor element. Therefore, a function is required to detect the short circuit state of the power semiconductor element and protect the power semiconductor element.

[0003] In recent years, as power semiconductor devices have become smaller, short-circuit tolerance has decreased, and the need for high-speed short-circuit protection has increased. In short-circuit protection circuits that achieve high-speed short-circuit protection, malfunctions may occur due to the high or low responsiveness, and noise countermeasures such as filters have been implemented.

[0004] In Japanese Patent Publication No. 2017-143700 (Patent Document 1), a short circuit detection device is described that is configured to detect the short circuit state of a power semiconductor element by utilizing the disappearance of the Miller period of the gate voltage during a short circuit. The short circuit detection device detects that a short circuit has occurred in the power semiconductor element when the gate voltage reaches a reference voltage earlier than a predetermined time. The short circuit detection device further determines that no short circuit has occurred in the power semiconductor element when a decrease in the gate voltage is detected within a predetermined time even when a short circuit state is detected. That is, in Patent Document 1, by determining that no short circuit has occurred when the gate voltage temporarily exceeds the reference voltage due to noise, etc., false detection of a short circuit is suppressed.

[0005] Japanese Patent Publication No. 2014-117112 (Patent Document 2) describes a short-circuit detection circuit configured to detect a short-circuit current flowing in a power semiconductor element based on a voltage between terminals of a resistor connected to a sensing unit of the power semiconductor element. In Patent Document 2, a noise mask is connected to the output of the short-circuit detection circuit to remove high-order harmonics caused by switching noise from the output of the short-circuit detection circuit, thereby suppressing false detection of short circuits. Patent Document 2 further describes a structure in which a noise mask is connected to the output of a short-circuit detection circuit configured to detect a short circuit using a positive side voltage of a power semiconductor element (e.g., a collector voltage in the case of an IGBT).

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2017-143700

[0009] Patent Document 2: Japanese Patent Application Publication No. 2014-117112 Summary of the invention

[0010] However, the short-circuit detection device described in Patent Document 1 determines that no short circuit has occurred when a decrease in gate voltage is detected within a predetermined time. Therefore, the short-circuit detection device described in Patent Document 1 cannot be applied when physical quantities other than gate voltage (such as gate current and gate charge, etc.) are used for short-circuit determination or when short-circuit determination is performed based on the correlation between multiple physical quantities obtained from the gate electrode.

[0011] In the short-circuit detection circuit described in Patent Document 2, a resistor connected to a sensing unit of a power semiconductor element is used to detect a short-circuit current, so a sensing unit is required. Therefore, it cannot be applied when a sensing unit is not provided in the power semiconductor element. In addition, due to the provision of a sensing unit and a resistor, the power semiconductor element and the drive circuit may be enlarged. Even in the case of detecting a short circuit based on the positive side voltage of the power semiconductor element, a high withstand voltage diode is required, so the power semiconductor element and the drive circuit may be enlarged.

[0012] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to suppress malfunction due to erroneous determination in a drive circuit that can be applied to a wide range of power semiconductor devices and can easily determine the short-circuit state of the power semiconductor device.

[0013] The driving circuit of the power semiconductor element involved in the present disclosure is a driving circuit for driving the power semiconductor element having a gate electrode, a first main electrode and a second main electrode. The driving circuit comprises: a control unit for controlling the on / off state of the power semiconductor element according to an instruction received from the outside; a short-circuit determination unit for determining whether the power semiconductor element is in a short-circuit state when the power semiconductor element is turned on, and outputting a determination signal indicating the determination result; and a filter for receiving the determination signal from the short-circuit determination unit, generating a delayed signal of the determination signal and outputting it to the control unit. The delay time in the filter is set to be longer than the length of the Miller period when the power semiconductor element is turned on.

[0014] According to the present disclosure, in a drive circuit that can be applied to a wide range of power semiconductor elements and can easily determine the short-circuit state of a power semiconductor element, malfunctions due to erroneous determinations can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a diagram showing a first configuration example of a power semiconductor element and a driving circuit thereof according to the first embodiment.

[0016] Figure 2 This is a diagram showing a second configuration example of the power semiconductor element and the driving circuit thereof according to the first embodiment.

[0017] Figure 3 This is a waveform diagram schematically showing time changes of a gate voltage, a gate current, a determination signal, and a delay signal during an on-operation of a power semiconductor element.

[0018] Figure 4 This is a waveform diagram schematically showing time changes of a gate voltage, a gate current, a determination signal, and a delay signal when noise is applied to a gate electrode during an on-operation of a power semiconductor element.

[0019] Figure 5 This is a waveform diagram schematically showing time changes of a gate voltage, a gate current, a determination signal, and a delay signal when a turn-off operation is started during an turn-on operation of a power semiconductor element.

[0020] Figure 6 It is a diagram showing a first configuration example of a filter.

[0021] Fig. 7A It is a diagram showing a part of the second configuration example of the filter.

[0022] Figure 7B It is a diagram showing a second configuration example of a filter.

[0023] Figure 8 It is a diagram showing a first configuration example of the short-circuit determination unit.

[0024] Fig. 9 It is a waveform diagram schematically showing the time variation of the differential signal of the gate voltage and the gate charge.

[0025] Fig.10 This is a waveform diagram schematically showing time changes in a differential signal of a gate voltage and a gate charge when a turn-off operation is started during a turn-on operation of a power semiconductor element.

[0026] Fig.11 It is a diagram showing a second configuration example of the short-circuit determination unit.

[0027] Fig.12 This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the sixth embodiment is applied.

[0028] (Explanation of symbols)

[0029] 1: power semiconductor element; 1c: collector electrode; 1e: emitter electrode; 1g: gate electrode; 2: control unit; 3: short-circuit determination unit; 4: filter; 5: buffer circuit; 6a: on-gate resistor; 6b: off-gate resistor; 7: photocoupler; 8: MOSFET; 11, 12, 14: ground wires; 13, 15: power supply nodes; 31: gate electrode physical quantity operation circuit; 31a: first gate electrode physical quantity operation circuit; 31b: second gate electrode physical quantity operation circuit; 32: short-circuit determination circuit; 33a: first comparator; 33b: second comparator; 34: AND circuit; 41: input terminal; 42: output terminal; 100: drive circuit; 1000: power supply; 2000: power conversion device; 2010: main conversion circuit; 2020: semiconductor device; 2030: control circuit; 3000: load; R1 to R6: resistors; C1 to C4: capacitors. DETAILED DESCRIPTION

[0030] The embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In addition, the same reference numerals are added to the same or corresponding parts in the drawings without repeating their descriptions. In addition, each embodiment and modification example described below can also be appropriately combined.

[0031] Implementation method 1.

[0032] Figure 1 FIG. 1 is a diagram showing a first structural example of a semiconductor device having a driving circuit according to Embodiment 1. Figure 1 As shown, the semiconductor device according to the first configuration example includes a power semiconductor element 1 (hereinafter simply referred to as “semiconductor element 1 ”) and a drive circuit 100 .

[0033] The semiconductor element 1 includes a first main electrode, a second main electrode, and a gate electrode. The semiconductor element 1 may be made of any of Si (silicon), SiC (silicon carbide), GaN (gallium nitride), and Ga2O3 (gallium oxide).

[0034] exist Figure 1 In the example, an IGBT is illustrated as the semiconductor element 1, but it is not limited to the IGBT, and it may be a self-arc extinguishing semiconductor element such as a MOSFET. The semiconductor element 1 is included in a power converter such as an inverter that converts DC power into AC power and a forward converter that converts AC power into DC power.

[0035] The semiconductor element 1 has a collector electrode 1c, an emitter electrode 1e, and a gate electrode 1g. A higher voltage is applied to the collector electrode 1c than to the emitter electrode 1e. The gate electrode 1g corresponds to the "gate electrode", the collector electrode 1c corresponds to the "first main electrode", and the emitter electrode 1e corresponds to the "second main electrode".

[0036] The drive circuit 100 is connected to the gate electrode 1g of the semiconductor element 1 to drive the semiconductor element 1. The drive circuit 100 includes a control unit 2, a short-circuit determination unit 3, and a filter 4.

[0037] The control unit 2 receives an external command to control the on / off state of the semiconductor element 1. Specifically, when an on command is input from the outside, the control unit 2 applies a gate voltage Vg (hereinafter referred to as "on gate voltage Vg_on") to the gate electrode 1g of the semiconductor element 1 for causing the semiconductor element 1 to transition to a closed state (on state) (hereinafter referred to as "on"). As a result, the semiconductor element 1 is turned on and becomes a closed state.

[0038] When a shutdown command is input from the outside, the control unit 2 applies a gate voltage Vg (hereinafter referred to as "off gate voltage Vg_off") for transitioning the semiconductor element 1 to a disconnected state (off state) (hereinafter referred to as "off") to the gate electrode 1g of the semiconductor element 1. As a result, the semiconductor element 1 is turned off and enters the off state.

[0039] The short-circuit determination unit 3 is connected to the gate electrode 1g of the semiconductor element 1, and determines whether the semiconductor element 1 is in a short-circuit state based on the physical quantity detected at the gate electrode 1g. Here, the "short-circuit state" refers to a state in which the semiconductor element 1 is connected to the voltage source with a low resistance due to a major cause such as a failure or malfunction of peripheral parts of the semiconductor element 1, and an excessive short-circuit current flows.

[0040] The physical quantities obtained from the gate electrode 1g include a gate voltage Vg between the gate electrode 1g and the emitter electrode 1e and a gate current Ig flowing into the gate electrode 1g. The short circuit determination unit 3 determines the short circuit state of the semiconductor element 1 by utilizing the difference in waveforms of physical quantities during the normal and short circuit turn-on operations.

[0041] Specifically, in a normal state, in the waveform of the gate voltage Vg during the on-state operation, a period during which the gate voltage Vg is constant, i.e., a "Miller period", occurs until the gate voltage Vg reaches the on-state gate voltage Vg_on. On the other hand, in the case of a short circuit, the Miller period does not occur in the waveform of the gate voltage Vg, and the gate voltage Vg rises to the on-state gate voltage Vg_on in one go.

[0042] The short-circuit determination unit 3 is configured to determine the short-circuit state of the semiconductor element 1 by utilizing the disappearance of the Miller period in the gate voltage Vg during the on-action when the semiconductor element 1 is short-circuited. The short-circuit determination unit 3 outputs a determination signal Sj indicating the determination result. Specifically, the short-circuit determination unit 3 outputs a determination signal Sj of an "L (logic low)" level when the semiconductor element 1 is normal, and outputs a determination signal Sj of an "H (logic high)" level when the semiconductor element 1 is in a short-circuit state. That is, the short-circuit determination unit 3 outputs an H-level determination signal Sj when it is determined that the semiconductor element 1 is in a short-circuit state. The specific structure of the short-circuit determination unit 3 will be described later.

[0043] The filter 4 generates a delayed signal Sd by delaying the determination signal Sj output from the short circuit determination unit 3, and outputs the generated delayed signal Sd to the control unit 2. The filter 4 has a delay time longer than the Miller period T_miller of the semiconductor element 1. The specific structure of the filter 4 will be described later.

[0044] When the semiconductor element 1 is turned on, if noise is applied to the gate electrode 1g during the Miller period or if the turn-off operation is started during the Miller period, the physical quantity of the gate electrode 1g may change rapidly. Since the physical quantity changes rapidly during the Miller period, the short-circuit determination unit 3 may erroneously determine that the semiconductor element 1 is in a short-circuit state. Therefore, in the drive circuit 100 involved in the first embodiment, by setting the delay time of the filter 4 to be longer than the Miller period, the filter 4 can be used to attenuate or cut off the erroneous determination signal Sj output from the short-circuit determination unit 3.

[0045] Figure 2 1 is a diagram showing a second configuration example of a semiconductor device having a drive circuit according to Embodiment 1. The semiconductor device according to the second configuration example is different from the semiconductor device according to the first configuration example in that the drive circuit 100 has a different configuration. The drive circuit 100 according to the second configuration example is for Figure 1 The driving circuit 100 shown in the figure has a buffer circuit 5, an on-gate resistor 6a, and an off-gate resistor 6b added thereto. The other structures of the driving circuit 100 are the same as those of the driving circuit 100 according to the first structural example, and therefore detailed descriptions thereof will not be repeated here.

[0046] The buffer circuit 5 applies the on-gate voltage Vg_on input from the control unit 2 to the gate electrode 1g of the semiconductor element 1 via the on-gate resistor 6a. The buffer circuit 5 applies the off-gate voltage Vg_off input from the control unit 2 to the gate electrode 1g of the semiconductor element 1 via the off-gate resistor 6b.

[0047] Next, use Figures 3 to 5 The operation of the filter 4 in the drive circuit 100 according to the first embodiment will be described.

[0048] Figure 3 2 is a waveform diagram schematically showing the time variation of the gate voltage Vg and the gate current Ig during the on-operation of the semiconductor element 1. Figure 3 In FIG. 1 , the waveforms of the gate voltage Vg and the gate current Ig in a normal state are indicated by a solid line, and the waveforms of the gate voltage Vg and the gate current Ig in a short circuit state are indicated by a dotted line.

[0049] First, the gate voltage Vg and the gate current Ig during the normal on-operation will be described.

[0050] like Figure 3 As shown, when the command input to the control unit 2 changes from the off command to the on command at time t0, the control unit 2 applies the on gate voltage Vg_on to the gate electrode 1g of the semiconductor element 1. As a result, the gate voltage Vg of the semiconductor element 1 starts to change from the off gate voltage Vg_off to the on gate voltage Vg_on.

[0051] Specifically, after time t0, the gate current Ig flows from the control unit 2 into the gate electrode 1g, thereby charging the parasitic capacitance component (hereinafter referred to as "gate-emitter capacitance Cge") generated between the gate electrode 1g and the emitter electrode 1e, so that the gate voltage Vg gradually rises. The period from time t0 to t1 corresponds to the charging period of the gate-emitter capacitance Cge.

[0052] Next, when the gate voltage Vg exceeds the threshold voltage at time t1, the semiconductor element 1 starts to conduct. When the semiconductor element 1 becomes conductive, the collector current starts to flow between the collector electrode 1c and the emitter electrode 1e, and the potential of the collector electrode 1c starts to drop. As a result, the charge accumulated in the parasitic capacitance component (hereinafter referred to as "gate / collector capacitance Cgc") generated between the gate electrode 1g and the collector electrode 1c is discharged. During the period from time t1 to t4, most of the gate current Ig flows through the gate / collector capacitance Cgc but not the gate / emitter capacitance Cge, so the gate voltage Vg does not rise but remains constant.

[0053] In addition, the period during which the gate voltage Vg is constant, such as the period from time t1 to t4, is called the "Miller period". In addition, the constant voltage value (equivalent to Vm in the figure) is called the "Miller voltage". The Miller period is a period for discharging the charge accumulated in the gate / collector capacitance Cgc. The gate / collector capacitance Cgc is equivalent to the feedback capacitance in the semiconductor element 1. The length T_miller of the Miller period and the magnitude of the Miller voltage Vm vary according to the operating conditions such as the voltage Vce between the collector electrode 1c and the emitter electrode 1e of the semiconductor element 1 and the collector current.

[0054] After the discharge of the gate / collector capacitance Cgc is completed, the gate voltage Vg rises again while charging the gate / emitter capacitance Cge, reaching the on-gate voltage Vg_on. At this time, the gate / collector capacitance Cgc (feedback capacitance) is charged in the opposite direction to the direction before the on-action. After the transition of the semiconductor element 1 to the on-state is completed, the gate current Ig becomes zero.

[0055] Next, the gate voltage Vg and the gate current Ig during the on-operation in the case of a short circuit will be described.

[0056] At time t0, the control unit 2 responds to the on command input from the outside and applies the on gate voltage Vg_on to the gate electrode 1g of the semiconductor element 1. As a result, the gate voltage Vg of the semiconductor element 1 begins to transition from the off gate voltage Vg_off to the on gate voltage Vg_on. At this time, the gate current Ig flows from the control unit 2 to the gate electrode 1g of the semiconductor element 1.

[0057] When the semiconductor element 1 is in a short-circuited state, the peripheral circuit connected to the collector electrode 1c of the semiconductor element 1 is short-circuited, so that a large voltage is applied between the collector electrode 1c and the emitter electrode 1e. As a result, the potential of the collector electrode 1c of the semiconductor element 1 is greater than the potential of the gate electrode 1g, and the gate / collector capacitance Cgc (feedback capacitance) is not charged, so the Miller period does not appear in the gate voltage Vg. As a result, the gate voltage Vg rises to the on-gate voltage Vg_on in one go. The gate current Ig used to charge the feedback capacitance does not flow either, so the gate current Ig converges to zero at an earlier stage than normal after rising immediately after time t0.

[0058] Here, when the amount of charge accumulated in the gate-collector capacitance Cgc is represented by Qgc and the gate current Ig in the Miller period is assumed to be constant, the length T_miller of the Miller period can be represented by T_miller=Qgc / Ig.

[0059] In addition, in the second structural example (refer to Figure 2 ) When the control unit 2 uses the on-gate resistor 6a to control the on-gate voltage Vg_on applied to the gate electrode 1g, the gate current Ig can be calculated using Ig=(Vg_on-Vm) / Rg_on. Here, Rg_on is the resistance value of the on-gate resistor 6a. Therefore, T_miller can be expressed as the following formula (1).

[0060] [Formula 1]

[0061]

[0062] The gate-collector capacitance Cgc (feedback capacitance) has a dependency on the voltage between the gate electrode 1g and the collector electrode 1c. Therefore, when Cgc (V) is assumed, the charge amount Qgc can be expressed by the following equation (2).

[0063] [Formula 2]

[0064]

[0065] Finally, the determination signal Sj and the delay signal Sd will be described.

[0066] exist Figure 3 , the waveforms of the determination signal Sj and the delayed signal Sd formed by delaying the determination signal Sj are also shown. The solid line is the waveform of the determination signal Sj and the delayed signal Sd in a normal state, and the dotted line is the waveform of the determination signal Sj and the delayed signal Sd in a short circuit. The delayed signal Sd can be a waveform such as the first or second output example according to the internal structure of the filter 4.

[0067] like Figure 3 As shown, when the short-circuit determination unit 3 detects the disappearance of the Miller period in the gate voltage Vg at time t2 during the on operation, it outputs the determination signal Sj at an H level. Figure 3 In the example of , the short-circuit determination unit 3 is configured to output the determination signal Sj of the H level during the predetermined period from the time t2 to the time t5 when the disappearance of the Miller period is detected. However, the short-circuit determination unit 3 may be configured to output the determination signal Sj fixed to the H level after the time t2 when the disappearance of the Miller period is detected.

[0068] In the first output example of the filter 4, the delay signal Sd rises slowly from the time t2 when the determination signal Sj changes from the L level to the H level. The delay signal Sd further falls slowly from the time t5 when the determination signal Sj changes to the L level. In addition, the rise time and fall time of the delay signal Sd are determined by the delay time of the filter 4. The period during which the delay signal Sd becomes the H level is shorter than the period during which the determination signal Sj becomes the H level.

[0069] The second output example of the filter 4 is an example of shaping the delay signal Sd involved in the first output example. Specifically, inside the filter 4, the delay signal Sd involved in the first output example is input to the comparator, and compared with the predetermined reference value REF in the comparator. The comparator is configured to output the delay signal Sd of the H level when the delay signal Sd involved in the first output example is greater than the reference value REF, and output the delay signal Sd of the L level when the delay signal Sd is less than the reference value REF.

[0070] As a result, in the second output example, the delay signal Sd becomes a pulse signal that exhibits an H level for a certain period of time, similarly to the determination signal Sj. However, the timing when the delay signal Sd rises to an H level and the timing when it falls to an L level are later than the timing when the determination signal Sj rises to an H level and the timing when it falls to an L level, respectively.

[0071] The filter 4 outputs the generated delay signal Sd to the control unit 2. The control unit 2 detects that the semiconductor element 1 is in a short-circuit state based on the delay signal Sd of the H level. When the control unit 2 detects that the semiconductor element 1 is in a short-circuit state, it generates an off-gate voltage Vg_off regardless of an instruction from the outside and applies it to the gate electrode 1g of the semiconductor element 1. As a result, the semiconductor element 1 is controlled to be in an off-state at high speed, so that the semiconductor element 1 can be protected at high speed.

[0072] According to the short-circuit determination unit 3 involved in the first embodiment, since the sensing unit of the semiconductor element is not required, it can also be applied to semiconductor elements without additional sensing units and resistors, and the short-circuit state of the semiconductor element can be easily determined. Furthermore, when the semiconductor element 1 is short-circuited, there is no Miller period in the connection operation, so the short-circuit state of the semiconductor element 1 can be quickly determined after the connection operation is started. As described above, the short-circuit determination unit 3 can be applied to a wide range of semiconductor elements, and the short-circuit state of the semiconductor element 1 can be easily and quickly detected.

[0073] Here, during the on-operation, noise may be applied to the gate electrode 1g of the semiconductor element 1. Alternatively, during the on-operation, the control unit 2 may start the off-operation of the semiconductor element 1 in response to a turn-off command received from the outside. In either case, a physical quantity different from that obtained when the semiconductor element 1 is operating normally is obtained in the gate electrode 1g. In such a case, the short-circuit determination unit 3 may determine that the Miller period in the gate voltage Vg has disappeared and may erroneously output the determination signal Sj of the H level.

[0074] Figure 4 1 is a waveform diagram schematically showing time changes of the gate voltage Vg, the gate current Ig, the determination signal Sj, and the delay signal Sd when noise is applied to the gate electrode 1g during the turn-on operation of the semiconductor element 1. Figure 4 The first output example of the delay signal Sd is equivalent to Figure 3 The second output example of the delayed signal Sd is equivalent to the output signal of the filter 4 shown in FIG. Figure 3 The output signal of the filter 4 is the same as the second output example shown.

[0075] exist Figure 4In the example of FIG. 1 , it is assumed that after the semiconductor element 1 starts turning on at time t0 , noise is applied to the gate electrode 1 g during the Miller period from time t1 to t4 .

[0076] In this case, vibration occurs in the waveforms of the gate voltage Vg and the gate current Ig during the Miller period. Since the vibration is input to the short-circuit determination unit 3 as noise, there is a possibility that the short-circuit determination unit 3 may cause malfunction.

[0077] exist Figure 4 In the example of , the short-circuit determination unit 3 detects the vibration of the gate voltage Vg and / or the gate current Ig and determines that the semiconductor element 1 is in a short-circuit state, and outputs the determination signal Sj of the H level. Usually, in such a case, the determination signal Sj output from the short-circuit determination unit 3 becomes a short pulse signal because it is mistaken for a short-circuit state instantaneously. At this time, the pulse width of the determination signal Sj is shorter than the length T_miller of the Miller period.

[0078] In the first output example of the filter 4, the filter 4 delays the short pulse determination signal Sj. As described above, the filter 4 has a delay time longer than the Miller period. Therefore, the delay time of the filter 4 is longer than the pulse width of the determination signal Sj.

[0079] The delay signal Sd rises slowly from time t2 when the determination signal Sj changes from the L level to the H level, and falls slowly from time t3 when the determination signal Sj changes to the L level. However, since the pulse width of the determination signal Sj is shorter than the delay time, the delay signal Sd starts to decay before reaching the H level. Therefore, no pulse is seen in the delay signal Sd.

[0080] In the second output example of the filter 4, the delay signal Sd is generated by comparing the delay signal Sd of the first output example with the reference value REF. Since the delay signal Sd of the first output example is smaller than the reference value REF, the delay signal Sd of the second output example is also kept at the L level after time t2.

[0081] In this way, the determination signal Sj erroneously output due to the noise applied during the Miller period is delayed or cut off by the filter 4. Therefore, the erroneous determination signal Sj is prevented from being input to the control unit 2. Thus, the control unit 2 can prevent erroneous operation such as controlling the semiconductor element 1 to the off state based on the erroneous determination signal Sj.

[0082] Figure 5 1 is a waveform diagram schematically showing time changes of the gate voltage Vg, the gate current Ig, the determination signal Sj, and the delay signal Sd when the semiconductor element 1 starts the turn-off operation during the turn-on operation. Figure 5 The first output example of the delay signal Sd is equivalent to Figure 3 The second output example of the delayed signal Sd is equivalent to the output signal of the filter 4 shown in FIG. Figure 3 The output signal of the filter 4 is the same as the second output example shown.

[0083] exist Figure 5 In the example of FIG. 1 , it is assumed that the semiconductor element 1 starts turning on at time t0 and then starts turning off at time t2 in the Miller period from time t1 to t4 .

[0084] In this case, the gate voltage Vg decreases rapidly from the Miller voltage Vm after time t2 and reaches the off-gate voltage Vg_off. The gate current Ig decreases rapidly after time t2 and converges to zero.

[0085] In the second configuration example (see Figure 2 ), the gate current Ig converges to 0, but when the on-gate resistor 6a and the off-gate resistor 6b are shared, when the shutdown action is started at time t2, the gate current Ig flows in the direction opposite to the direction during the on-action.

[0086] Thus, when the turn-off operation starts during the Miller period, the gate voltage Vg and the gate current Ig change rapidly, so the short-circuit determination unit 3 determines that the semiconductor element 1 is in a short-circuit state and outputs an H-level determination signal Sj. Figure 4 In the example of , the determination signal Sj is output at the moment when the shutoff operation is started (time t2).

[0087] The reason for the determination signal Sj is the rapid change of the physical quantity that occurs during the Miller period when the short-circuit determination is performed. Therefore, even if the shutdown operation is started after the short-circuit determination is completed, that is, after the Miller period ends, the determination signal Sj is not output.

[0088] In addition, the determination signal Sj outputted from the short circuit determination unit 3 is a short pulse signal because it is mistakenly regarded as a short circuit state instantaneously. The pulse width of the determination signal Sj at this time is shorter than the length T_miller of the Miller period.

[0089] In the first output example of the filter 4, the filter 4 delays the short pulse determination signal Sj. The delay signal Sd rises slowly from the time t2 when the determination signal Sj changes from the L level to the H level, and falls slowly from the time t3 when the determination signal Sj changes to the L level. However, since the pulse width of the determination signal Sj is shorter than the delay time, the delay signal Sd starts to attenuate before reaching the H level. Therefore, no pulse is seen in the delay signal Sd.

[0090] In the second output example of the filter 4, the delay signal Sd is generated by comparing the delay signal Sd of the first output example with the reference value REF. Since the delay signal Sd of the first output example is smaller than the reference value REF, the delay signal Sd of the second output example is also kept at the L level after time t2.

[0091] In this way, the determination signal Sj erroneously outputted due to the turn-off operation in the Miller period is delayed or cut off by the filter 4, thereby preventing the erroneous determination signal Sj from being inputted to the control unit 2. Thus, it is possible to prevent the control unit 2 from erroneously operating the semiconductor element 1 to be turned off based on the erroneous determination signal Sj.

[0092] As described above, when noise is applied to the gate electrode 1g during the Miller period at the time of the turn-on operation (see Figure 3 ) or when the shutdown action has started during the Miller period (refer to Figure 4 ), due to the rapid change of the physical quantity in the gate electrode 1g, the short circuit determination unit 3 sometimes erroneously outputs the determination signal Sj of the H level. Usually, the erroneous determination signal Sj becomes a short pulse signal, and the length of the H level period in the determination signal Sj is shorter than the length T_miller of the Miller period.

[0093] In the drive circuit 100 according to the first embodiment, the filter 4 is provided between the short-circuit determination unit 3 and the control unit 2, and the delay time of the filter 4 is configured to be longer than the length T_miller of the Miller period, so that the determination signal Sj erroneously output by the short-circuit determination unit 3 can be delayed or cut off by the filter 4. That is, when the delay time of the filter 4 is τ, the relationship shown in the following formula (3) holds between the delay time τ and the length T_miller of the Miller period shown in the formula (1).

[0094] [Formula 3]

[0095]

[0096] According to the drive circuit 100 according to the first embodiment, a malfunction due to an erroneous determination signal can be suppressed in a drive circuit which is applicable to a wide range of semiconductor elements and can detect a short-circuit state of the semiconductor element 1 simply and quickly.

[0097] In addition, in Embodiment 1, a structural example is described in which the short-circuit determination unit 3 outputs the determination signal Sj of an L level when the semiconductor element 1 is normal, and outputs the determination signal Sj of an H level when a short circuit occurs. However, the short-circuit determination unit 3 may also be configured to output the determination signal Sj of an H level when the semiconductor element 1 is normal, and output the determination signal Sj of an L level when a short circuit occurs.

[0098] Implementation method 2.

[0099] In the second embodiment, the driving circuit 100 (see Figure 1 as well as Figure 2 ) is a first structural example of filter 4.

[0100] Figure 6 4 is a diagram showing a first structural example of the filter 4. Figure 6 As shown, the filter 4 involved in the first structural example is an RC circuit having a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are connected in series between the input terminal 41 and the ground line 11. The connection point between the resistor R1 and the capacitor C1 is connected to the output terminal 42. The input terminal 41 receives the determination signal Sj from the short-circuit determination unit 3. The output terminal 42 outputs a delayed signal Sd of the determination signal Sj.

[0101] In the first configuration example, a delayed signal A′ output from the output terminal 42 with respect to the input signal A received at the input terminal 41 can be expressed by the following equation (4).

[0102] [Formula 4]

[0103]

[0104] Here, R1 is the resistance value of the resistor R1, C1 is the capacitance value of the capacitor C1, and t is the time from the time point when the input signal A is received.

[0105] R1×C1 in the formula (4) corresponds to the time constant of the RC circuit. By setting the time constant (R1×C1) as the delay time τ of the filter 4 and setting the values ​​of R1 and C1 in a manner that satisfies the relationship of the above formula (3), the operation of the filter 4 described in the first embodiment can be realized. In addition, the filter 4 is not limited to Figure 6 The structure shown can also be formed using multiple resistors and multiple capacitors.

[0106] according to Figure 6 The circuit structure can generate Figure 4 as well as Figure 5 The delayed signal Sd shown in the first output example. Figure 6 In the circuit structure of FIG. 4 , by connecting a comparator between the connection point of the resistor 1 and the capacitor C1 and the output terminal 42, the filter 4 can generate Figure 4 as well as Figure 5 The delayed signal Sd shown in the second output example.

[0107] Implementation method 3.

[0108] In Embodiment 3, the driving circuit (see Figure 1 as well as Figure 2 ) is a second structural example of filter 4.

[0109] Fig. 7A as well as Figure 7B 2 is a circuit diagram showing a second configuration example of the filter 4. The filter 4 according to the second configuration example includes at least one RC circuit and a photocoupler 7. Fig. 7A A configuration example of a circuit for driving the photocoupler 7 is shown. Figure 7B Shows the Fig. 7A The circuit shown is a configuration example of a circuit in which at least one RC circuit is added.

[0110] In the filter 4 involved in the second configuration example, the input terminal 41 receiving the determination signal Sj and the output terminal 42 outputting the delayed signal Sd are electrically insulated. Therefore, the filter 4 can transmit the delayed signal Sd of the determination signal Sj to the control unit 2 while electrically isolating the short-circuit determination unit 3 and the control unit 2.

[0111] Thus, for example, when the short-circuit determination unit 3 is connected to the gate electrode 1g of the semiconductor element 1 on the high-side (high-voltage side) of the power converter, the short-circuit determination unit 3 and the control unit 2 are electrically insulated, so that the control unit 2 can be prevented from receiving a high voltage and being destroyed. Usually, when driving the semiconductor element 1 on the high-side, the control unit 2 ensures electrical insulation between the input from the outside and the gate voltage by providing an insulating circuit. Therefore, instead of the present structural example in which the optical coupler 7 is provided inside the filter 4, an insulating circuit may be provided in the control unit 2 for determining the signal, and the insulating circuit may receive the delayed signal Sd from the filter 4.

[0112] like Fig. 7A As shown, on the primary side of the optical coupler 7, the resistors R2, R3 and MOSFET 8 are connected in series in this order between the power supply node 15 supplying the power supply potential VDD and the ground line 12 having the ground line potential GND1. The light emitting element (light emitting diode) of the optical coupler 7 is connected between the first terminal and the second terminal of the resistor R3. The resistor R4 and the resistor R5 are connected in series between the input terminal 41 and the ground line 12. The connection point of the resistor R4 and the resistor R5 is connected to the gate of the MOSFET 8.

[0113] On the secondary side of the photocoupler 7 , the light receiving element is connected between a power supply node 13 to which a power supply potential VCC is supplied and a ground 14 having a ground potential GND2 . An output node 71 of the light receiving element is connected to the output terminal 42 .

[0114] When the input terminal 41 receives the judgment signal Sj of the H level, the MOSFET 8 is turned on, and a current flows through the resistors R2 and R3. When the voltage between the terminals of the resistor R3 becomes equal to or higher than the reference voltage, the photocoupler 7 operates to output the power supply potential VCC of the power supply node 13 to the output node 71. On the other hand, when the input terminal 41 receives the judgment signal Sj of the L level, the MOSFET 8 is turned off, so the photocoupler 7 does not operate. In this case, the photocoupler 7 outputs the ground potential GND of the ground line 14 to the output node 71. That is, the photocoupler 7 outputs a signal of the power supply potential VCC when the judgment signal Sj of the H level is received, and outputs a signal of the ground potential GND2 when the judgment signal Sj of the L level is received.

[0115] exist Figure 7B In the circuit diagram shown, capacitors C2 and C3 are connected to the primary side of the optical coupler 7, and resistor R6 and capacitor C4 are connected to the secondary side of the optical coupler 7. Capacitor C2 is connected in parallel with resistor R3. Capacitor C3 is connected in parallel with resistor R5. Resistor R6 and capacitor C4 are connected in series between the output node 71 and the ground line 14. The connection point of resistor R6 and capacitor C4 is connected to the output terminal 42.

[0116] Capacitor C2 delays the input signal received by the primary side of photocoupler 7. The time constant in the delay of the input signal is C2 / (1 / R2+1 / R3), where C2 is the capacitance of capacitor C2, R2 is the resistance of resistor R2, and R3 is the resistance of resistor R3.

[0117] The capacitor C3 delays the input signal received by the MOSFET 8. The time constant in the delay of the input signal is C3 / (1 / R4+1 / R5), where C3 is the capacitance value of the capacitor C3, R4 is the resistance value of the resistor R4, and R5 is the resistance value of the resistor R5.

[0118] The resistor R6 and the capacitor C4 delay the output signal output from the output node 71 of the photocoupler 7 to the output terminal 42. The time constant of the delay of the output signal is R6×C4, where C4 is the capacitance value of the capacitor C4 and R6 is the resistance value of the resistor R6.

[0119] exist Figure 7B In the circuit structure of , the delay time of the filter 4 can be set using the above three time constants. In addition, the structure for setting the delay time of the filter 4 is not limited to Figure 7B The structure shown in FIG. 1 may also be configured to use at least one of the three time constants to set the delay time of the filter 4. Fig. 7AThe circuit shown can set the delay time of the filter 4 by adding at least one of the capacitors C2 and C3 and / or a series circuit of the resistor R6 and the capacitor C4.

[0120] according to Figure 7B The circuit structure can generate Figure 3 The delayed signal Sd shown in the first output example. Figure 7B In the circuit structure of FIG. 1 , a comparator is connected between the connection point of the resistor 6 and the capacitor C4 and the output terminal 42 to generate Figure 3 The delayed signal Sd shown in the second output example.

[0121] In addition, from Figure 7B In the circuit structure without the resistor 6 and the capacitor C4, the optical coupler 7 itself performs an operation close to that of a comparator, so that Figure 3 However, a comparator may be further connected between the output node 71 of the photocoupler 7 and the output terminal 42.

[0122] Implementation method 4.

[0123] In the fourth embodiment, a first configuration example of the short-circuit determination unit 3 applied to the drive circuit 100 according to the first embodiment will be described.

[0124] Figure 8 It is shown Figure 1 FIG. 2 is a diagram showing a first configuration example of the short-circuit determination unit 3 .

[0125] like Figure 8 As shown, the short-circuit determination unit 3 according to the first configuration example includes a gate electrode physical quantity calculation circuit 31 (hereinafter simply referred to as “calculation circuit 31 ”) and a short-circuit determination circuit 32 .

[0126] The operation circuit 31 is connected to the gate electrode 1g of the semiconductor element 1 to obtain the physical quantity in the gate electrode 1g. The physical quantity obtained by the operation circuit 31 includes, for example, the gate voltage Vg, the gate current Ig, the differential signal of the gate voltage Vg, and the gate charge Qg. The differential signal of the gate voltage Vg can be obtained by time-differentiating the gate voltage Vg. The gate charge Qg can be obtained by time-integrating the gate current Ig. These physical quantities may also be subjected to delay processing, differential processing, or integration processing.

[0127] The short-circuit determination circuit 32 determines whether the semiconductor element 1 is in a short-circuit state based on the physical quantity obtained by the calculation circuit 31 , and outputs a determination signal Sj indicating the determination result to the filter 4 .

[0128] use Fig. 9 Description Figure 8An example of a physical quantity detected by the calculation circuit 31 shown.

[0129] Fig. 9 : is a waveform diagram schematically showing the time variation of the differential signal of the gate voltage Vg and the gate charge amount Qg. Fig. 9 In FIG. 1 , a normal waveform is indicated by a solid line, and a short-circuit waveform is indicated by a dotted line.

[0130] The Miller period can be seen in the gate voltage Vg during normal operation (see Figure 3 ). Therefore, if Fig. 9 As shown, the differential signal in normal state maintains a constant value from time t0 when the conduction command is received to before the start of the Miller period, and then temporarily becomes zero during the Miller period. Thereafter, the differential signal rises again after the Miller period ends and converges to zero.

[0131] On the other hand, the gate voltage Vg during short circuit increases monotonically after time t0 and reaches the on-gate voltage Vg_on. Fig. 9 As shown, the differential signal maintains a constant value from immediately after time t0, and then decreases and converges to zero.

[0132] The gate current Ig in normal conditions rises sharply at time t0 when the on command is received, and then turns to decline. The gate current Ig maintains a constant value during the Miller period, and then decreases again and converges to zero (see Figure 3 ). Therefore, if Fig. 9 As shown, the gate charge amount Qg in a normal state gradually increases after time t0 and converges to a constant value.

[0133] On the other hand, the gate current Ig during short circuit rises sharply at time t0, then turns to decrease and converges to zero (see Figure 3 ). Therefore, if Fig. 9 As shown, the gate charge amount Qg in the short-circuit state increases after time t0 and converges to a constant value, but the converged value becomes smaller than that in the normal state.

[0134] like Fig. 9 As shown, the differential signal of the gate voltage Vg and the gate charge Qg also have waveform differences depending on whether or not the Miller period is present. Therefore, the short-circuit determination circuit 32 can determine that the semiconductor element 1 is in a short-circuit state by detecting the difference in the waveform of the detected physical quantity relative to the waveform in a normal state.

[0135] When noise is applied to the gate electrode 1g during the Miller period, vibration occurs in the gate voltage Vg and the gate current Ig during the Miller period (see Figure 4). In the waveform of the differential signal of the gate voltage Vg and the gate charge amount Qg, vibrations also occur during the Miller period, so the short-circuit determination circuit 32 may erroneously determine that the semiconductor element 1 is in a short-circuit state due to the vibrations. However, as described above, the erroneous determination signal Sj output from the short-circuit determination circuit 32 is delayed or cut off by the filter 4. Therefore, it is possible to prevent the control unit 2 from erroneously operating based on the erroneous determination signal Sj.

[0136] Fig.10 This is a waveform diagram schematically showing the time variation of the differential signal of the gate voltage Vg and the gate charge Qg when the turn-off operation is started during the turn-on operation of the semiconductor element 1. When the turn-off operation is started at time t2 during the Miller period, the gate voltage Vg and the gate current Ig during the Miller period decrease sharply (see Figure 5 ). Therefore, if Fig.10 As shown in FIG. 1 , the waveform of the differential signal of the gate voltage Vg also shows a sharp drop during the Miller period. On the other hand, the gate charge amount Qg stops increasing at time t2 and maintains a constant value.

[0137] The short-circuit determination circuit 32 may erroneously determine that the semiconductor element 1 is in a short-circuit state due to a sudden change in the differential signal and the gate charge amount Qg. However, as described above, the erroneous determination signal Sj output from the short-circuit determination circuit 32 is delayed or cut off by the filter 4. Therefore, malfunction of the control unit 2 based on the erroneous determination signal Sj can be prevented.

[0138] Implementation method 5.

[0139] In the fifth embodiment, the driving circuit 100 (see Figure 1 as well as Figure 2 ) is a second structural example of the short-circuit determination unit 3.

[0140] Fig.11 It is a diagram showing a second configuration example of the short-circuit determination unit 3 .

[0141] like Fig.11 As shown, the short-circuit determination unit 3 involved in the second structural example has a first gate electrode physical quantity operation circuit 31a (hereinafter referred to as "the first operation circuit 31a"), a second gate electrode physical quantity operation circuit 31b (hereinafter referred to as "the second operation circuit 31b"), a first comparator 33a, a second comparator 33b and an AND circuit 34.

[0142] The first operation circuit 31a is connected to the gate electrode 1g of the semiconductor element 1 to obtain a first physical quantity in the gate electrode 1g. The first physical quantity obtained by the first operation circuit 31a is, for example, any physical quantity of the gate voltage Vg, the gate current Ig, the differential signal of the gate voltage Vg, and the gate charge Qg.

[0143] The first comparator 33a compares the first physical quantity obtained by the first operation circuit 31a with the first reference value REF1, and outputs a signal Sc1 indicating the comparison result. For example, when the first physical quantity is a differential signal of the gate voltage Vg, the first comparator 33a outputs an H-level signal Sc1 when the first physical quantity is greater than the first reference value REF1, and outputs an L-level signal Sc1 when the first physical quantity is less than the first reference value REF1.

[0144] The second operation circuit 31b is connected to the gate electrode 1g of the semiconductor element 1, and obtains the second physical quantity in the gate electrode 1g. The second physical quantity obtained by the second operation circuit 31b is a physical quantity different from the first physical quantity, for example, any physical quantity among the gate voltage Vg, the gate current Ig, the differential signal of the gate voltage Vg, and the gate charge Qg.

[0145] The second comparator 33b compares the second physical quantity obtained by the second operation circuit 31b with the second reference value REF2, and outputs a signal Sc2 indicating the comparison result. For example, when the second physical quantity is the gate charge Qg, the second comparator 33b outputs an H-level signal Sc2 when the second physical quantity is less than the second reference value REF2, and outputs an L-level signal Sc2 when the second physical quantity is greater than the second reference value REF2.

[0146] The AND circuit 34 generates a determination signal Sj by calculating the AND of the output signal Sc1 of the first comparator 33a and the output signal Sc2 of the second comparator 33b. When the output signal Sc1 of the first comparator 33a and the output signal Sc2 of the second comparator 33b are both at the H level, the AND circuit 34 determines that the semiconductor element 1 is in a short-circuit state and outputs the determination signal Sj at the H level. In other cases, the AND circuit 34 outputs the determination signal Sj at the L level. In this configuration example, when the differential signal of the gate voltage Vg is greater than the first reference value REF1 and the gate charge amount Qg is less than the second reference value REF2, the AND circuit 34 determines that the semiconductor element 1 is in a short-circuit state and outputs the determination signal Sj at the H level. In addition, the AND circuit 34 can also be configured by a combination of NAND circuits.

[0147] Thus, the short-circuit determination unit 3 according to the second configuration example determines that the semiconductor element 1 is in a short-circuit state when both the first and second physical quantities satisfy a predetermined condition (when both the signals Sc1 and Sc2 are at an H level). That is, the short-circuit determination unit 3 is configured to determine the short-circuit state of the semiconductor element 1 based on the correlation between the first and second physical quantities.

[0148] In addition, in the short-circuit determination unit 3 involved in the second structural example, there is a possibility that an erroneous determination signal Sj is output when the correlation between the above two physical quantities changes sharply due to the addition of noise during the Miller period at the time of the turn-on operation or the start of the turn-off operation. The erroneous determination signal Sj is attenuated or cut off by the subsequent filter 4, so it is prevented from being input to the control unit 2. Thus, it is possible to prevent the control unit 2 from erroneously controlling the semiconductor element 1 to the off state based on the erroneous determination signal Sj.

[0149] Implementation method 6.

[0150] Embodiment 6 is an example in which the semiconductor device according to Embodiment 1 is applied to a power conversion device. Hereinafter, a case in which the present disclosure is applied to a three-phase inverter will be described.

[0151] Fig.12 This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the sixth embodiment is applied.

[0152] like Fig.12 As shown, the power conversion system includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply, and supplies DC power to the power conversion device 2000. The power supply 1000 can be composed of various objects, for example, it can be composed of a DC system, a solar cell, and a storage battery. Alternatively, the power supply 1000 can also be composed of a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 1000 can also be composed of a DC / DC converter that converts the current power supplied from the DC system into power that can be used by the load 3000.

[0153] The power conversion device 2000 is a three-phase inverter connected between the power source 1000 and the load 3000, and converts the DC power supplied from the power source 1000 into three-phase AC power and supplies it to the load 3000. Fig.12 As shown, it includes: a main conversion circuit 2010 that converts DC power into AC power; and a control circuit 2030 that outputs a control signal for controlling the main conversion circuit 2010 to the main conversion circuit 2010.

[0154] The load 3000 is a three-phase electric motor driven by the AC power supplied from the power conversion device 2000 , and is used as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner, for example.

[0155] The power conversion device 2000 is described in detail below. The main conversion circuit 2010 includes a switching element (not shown), and by opening and closing the switching element, the DC power supplied from the power supply 1000 is converted into AC power and supplied to the load 3000. There are various examples of the specific circuit structure of the main conversion circuit 2010, but the main conversion circuit 2010 of this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in anti-parallel with each switching element. The main conversion circuit 2010 includes a semiconductor device 2020 having each switching element and a drive circuit for driving each switching element. Each switching element and each drive circuit provided in the semiconductor device 2020 are the semiconductor element 1 and the drive circuit 100 of the semiconductor device involved in the above-mentioned embodiment 1. With respect to the 6 switching elements, each 2 switching elements are connected in series to form an upper and lower branch, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the output terminals of each upper and lower branch, that is, the three output terminals of the main conversion circuit 2010 are connected to the load 3000.

[0156] The control circuit 2030 controls the switch elements of the main conversion circuit 2010 in such a manner that the desired power is supplied to the load 3000. Specifically, the time (on-time) when each switch element of the main conversion circuit 2010 should be in the on state is calculated according to the power to be supplied to the load 3000. For example, the main conversion circuit 2010 can be controlled by PWM control that modulates the on-time of the switch element according to the voltage to be output. In addition, a control instruction (control signal) is output to the drive circuit of the main conversion circuit 2010 in such a manner that an on signal is output to the switch element to be in the on state and an off signal is output to the switch element to be in the off state at each time point. The drive circuit outputs the on signal or the off signal as a drive signal to the gate electrode of each switch element in accordance with the control signal.

[0157] In the power conversion device according to the sixth embodiment, the semiconductor device according to the first embodiment is applied as the semiconductor device 2020 constituting the main conversion circuit 2010. Therefore, similarly to the first embodiment, the short-circuit state of the semiconductor element can be detected with a simplified circuit.

[0158] In Embodiment 6, an example of applying the present disclosure to a 2-level three-phase inverter is described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In Embodiment 6, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device can also be used. When power is supplied to a single-phase load, the present disclosure can also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0159] In addition, the power conversion device disclosed in the present invention is not limited to the case where the above-mentioned load is an electric motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0160] The embodiments disclosed herein are to be considered in all respects as illustrative and non-restrictive. The scope of the present disclosure is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A driving circuit for a power semiconductor element, driving a power semiconductor element having a gate electrode, a first main electrode, and a second main electrode, the driving circuit for the power semiconductor element comprising: A control unit for controlling the on / off state of the power semiconductor element according to an instruction received from the outside; a short-circuit determination unit for determining whether the power semiconductor element is in a short-circuit state when the power semiconductor element is turned on, and outputting a determination signal indicating the determination result; as well as a filter that receives the determination signal from the short-circuit determination unit, generates a delayed signal of the determination signal, and outputs the delayed signal to the control unit, The delay time in the filter is set to be longer than the length of the Miller period during the on-operation of the power semiconductor element.

2. The driving circuit of the power semiconductor element according to claim 1, wherein: further comprising an on-gate resistor connected between the control unit and the gate electrode, When the delay time of the filter is τ, the on-gate voltage applied from the control unit to the gate electrode is Vg_on, the Miller voltage of the power semiconductor element is Vm, the charge amount accumulated in the parasitic capacitance between the gate electrode and the first main electrode is Qgc, and the resistance value of the on-gate resistor is Rg_on, the delay time satisfies the relationship expressed by the following formula (1):

3. The driving circuit of the power semiconductor element according to claim 1, wherein: The filter comprises an RC circuit having a resistor and a capacitor, The delay time is set using the time constant of the RC circuit.

4. The driving circuit of the power semiconductor element according to claim 2, wherein: The filter comprises an RC circuit having a resistor and a capacitor, The delay time is set using the time constant of the RC circuit.

5. The driving circuit of the power semiconductor element according to claim 3, wherein: The filter further comprises: An input terminal for receiving the determination signal; an output terminal for outputting the delayed signal; and an optical coupler connected between the input terminal and the output terminal, The resistor and the capacitor are connected to at least one of between the input terminal and the photocoupler and between the photocoupler and the output terminal.

6. The driving circuit of a power semiconductor element according to any one of claims 1 to 5, wherein: The short-circuit determination unit is connected to the gate electrode, and determines whether the power semiconductor element is in a short-circuited state based on at least one physical quantity acquired at the gate electrode during the on operation.

7. The driving circuit of the power semiconductor element according to claim 6, wherein: The at least one physical quantity includes a first physical quantity and a second physical quantity, The short-circuit determination unit determines whether the power semiconductor element is in a short-circuited state based on a correlation between the first physical quantity and the second physical quantity.

8. The driving circuit of a power semiconductor element according to any one of claims 1 to 5, wherein: The power semiconductor element is an element made of any of silicon, silicon carbide, gallium nitride and gallium oxide. 9 . A semiconductor device comprising the drive circuit according to claim 1 and a power semiconductor element.

10. A power conversion device comprising: A main conversion circuit, comprising the drive circuit according to any one of claims 1 to 8 and a power semiconductor element, the main conversion circuit converting input power and outputting the converted power; and The control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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