Communication method and apparatus between circuit boards

Abstract

This invention discloses a communication method and apparatus between circuit boards, relating to the field of circuit board communication technology. The method includes: upon receiving a header identifier message, starting a first timer to collect the first interval duration for receiving adjacent messages; when the first interval duration is greater than a first preset duration, clearing the DMA buffer of the current message data and initiating the next DMA receive interrupt; when the first interval duration is not greater than the first preset duration, continuing to receive messages in the current message data; upon receiving a long message indicating the message length in the current message data, determining a second preset duration based on the message length, starting a second timer to collect the second interval duration between receiving the long message and the final message in the current message data; when the second interval duration is greater than the second preset duration, clearing the DMA buffer of the current message data and initiating the next DMA receive interrupt. This invention can improve the accuracy of communication between circuit boards.

Description

Technical Field

[0001] This invention relates to the field of circuit board communication technology, and more particularly to communication methods and devices between circuit boards. Background Technology

[0002] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] Currently, communication between circuit boards relies entirely on the received message length indicator and the actual number of messages received to distinguish different messages. For example, if the received message length indicator is 20, then after receiving 20 messages, these 20 messages are considered as a complete message data. However, in actual communication, due to communication jitter and other factors, some messages may fail to arrive after being sent. This can lead to the circuit board calculating that the messages it receives belong to the same message data according to the message length indicator, but they are not actually the same message data, resulting in errors in message transmission. Consequently, the communication efficiency and accuracy between current circuit boards are low. Summary of the Invention

[0004] This invention provides a communication method between circuit boards to effectively divide the message data transmitted between circuit boards, thereby improving the communication efficiency and accuracy between circuit boards. The method includes:

[0005] When the header identifier message is received from the message sending circuit board, the first timer is started to collect the first interval duration between adjacent messages in the message data.

[0006] When the first interval duration is longer than the first preset duration, disable the Direct Memory Access (DMA) receive interrupt, clear the DMA cache of the current message data, start the next DMA receive interrupt, and wait to receive the next message data.

[0007] If the first interval duration is not greater than the first preset duration, continue to receive messages from the current message data;

[0008] When a length message indicating the message length is received in the current message data, a second preset duration is determined based on the message length, and a second timer is started to collect the second interval duration between receiving the length message in the current message data and the final message.

[0009] When the second interval duration is longer than the second preset duration, the DMA receive interrupt is disabled, the DMA buffer of the current message data is cleared, the next DMA receive interrupt is started, and the message waits to receive the next message data.

[0010] This invention also provides a communication device between circuit boards, used to effectively divide the message data transmitted between circuit boards, thereby improving the communication efficiency and accuracy between circuit boards. The device includes:

[0011] The first processing module is used to start a first timer to collect the first interval duration of adjacent messages in the current message data when it receives the header identifier message in the current message data sent by the message sending circuit board.

[0012] The second processing module is used to disable the Direct Memory Access (DMA) receive interrupt, clear the DMA cache of the current message data, start the next DMA receive interrupt, and wait to receive the next message data when the first interval duration is longer than the first preset duration.

[0013] The third processing module is used to continue receiving messages in the current message data when the first interval duration is not greater than the first preset duration;

[0014] The fourth processing module is used to determine the second preset duration based on the message length when it receives a long message that indicates the message length in the current message data, and to start the second timer to collect the second interval duration between receiving the long message in the current message data and the final message.

[0015] The fifth processing module is used to disable the DMA receive interrupt, clear the DMA buffer of the current message data, start the next DMA receive interrupt, and wait to receive the next message data when the second interval duration is longer than the second preset duration.

[0016] This invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the communication method between the aforementioned circuit boards.

[0017] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the communication method between the circuit boards described above.

[0018] This invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements the communication method between the aforementioned circuit boards.

[0019] In this embodiment of the invention, when a header identifier message is received from the message sending circuit board in the current message data, a first timer is started to collect the first interval duration between adjacent messages in the current message data; when the first interval duration is greater than a first preset duration, the Direct Memory Access (DMA) receive interrupt is disabled, the DMA cache of the current message data is cleared, the next DMA receive interrupt is started, and the system waits to receive the message data of the next message; when the first interval duration is not greater than the first preset duration, the system continues to receive messages in the current message data; when a length message indicating the message length is received in the current message data, a second preset duration is determined according to the message length, and a second timer is started to collect the second interval duration between receiving the length message in the current message data and the final message; when the second interval duration is greater than the second preset duration, the DMA receive interrupt is disabled, the DMA cache of the current message data is cleared, the next DMA receive interrupt is started, and the system waits to receive the message data of the next message. In this way, based on the message transmission time interval and preset duration in the message data, it can determine whether the received messages belong to the same message data and whether the reception of the next message data should begin. This reduces message misalignment caused by communication jitter, effectively divides the message data transmitted between circuit boards, and improves the communication efficiency and accuracy between circuit boards. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0021] Figure 1 This is a flowchart of a communication method between circuit boards provided in an embodiment of the present invention;

[0022] Figure 2 This is an example diagram of message data, a first interval duration, and a second interval duration in a message receiving circuit board provided in an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of a communication device between circuit boards provided in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of another communication device between circuit boards provided in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0027] The acquisition, storage, use, and processing of data in this application all comply with the relevant provisions of national laws and regulations.

[0028] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0029] In the description of this specification, the terms "comprising," "including," "having," and "containing" are open-ended terms, meaning that they include but are not limited to. The terms "an embodiment," "a specific embodiment," "some embodiments," and "for example," etc., refer to specific features, structures, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. The order of steps involved in the various embodiments is used to illustrate the implementation of this application, and the order of steps is not limited and can be adjusted appropriately as needed.

[0030] Research has revealed that when circuit boards communicate, they rely entirely on the received message length indicator and the actual number of messages received to distinguish between different messages. For example, if the received message length indicator is 20, then after receiving 20 messages, these 20 messages are considered as a complete message data. However, in actual communication, due to communication jitter and other factors, some messages may fail to arrive after being sent. This results in the circuit board calculating that the messages it receives belong to the same message data according to the message length indicator, but they do not actually belong to the same message data, causing errors in message transmission. Consequently, the current communication efficiency between circuit boards is low and the accuracy is poor.

[0031] Regarding the above research, such as Figure 1 As shown, this is an embodiment of the communication method between circuit boards provided by the present invention, applied to a message receiving circuit board, including:

[0032] S101: When the header identifier message is received from the message sending circuit board in the current message data, the first timer is started to collect the first interval duration of adjacent messages in the current message data;

[0033] S102: When the first interval duration is longer than the first preset duration, disable the Direct Memory Access (DMA) receive interrupt, clear the DMA cache of the current message data, start the next DMA receive interrupt, and wait to receive the message data of the next message.

[0034] S103: If the first interval duration is not greater than the first preset duration, continue to receive the message in the current message data;

[0035] S104: When a length message indicating the message length is received in the current message data, a second preset duration is determined according to the message length, and a second timer is started to collect the second interval duration between receiving the length message in the current message data and the final message.

[0036] S105: When the second interval duration is longer than the second preset duration, disable the DMA receive interrupt, clear the DMA buffer of the current message data, start the next DMA receive interrupt, and wait to receive the next message data.

[0037] In this embodiment of the invention, when a header identifier message is received from the message sending circuit board in the current message data, a first timer is started to collect the first interval duration between adjacent messages in the current message data; when the first interval duration is greater than a first preset duration, the Direct Memory Access (DMA) receive interrupt is disabled, the DMA cache of the current message data is cleared, the next DMA receive interrupt is started, and the system waits to receive the message data of the next message; when the first interval duration is not greater than the first preset duration, the system continues to receive messages in the current message data; when a length message indicating the message length is received in the current message data, a second preset duration is determined according to the message length, and a second timer is started to collect the second interval duration between receiving the length message in the current message data and the final message; when the second interval duration is greater than the second preset duration, the DMA receive interrupt is disabled, the DMA cache of the current message data is cleared, the next DMA receive interrupt is started, and the system waits to receive the message data of the next message. In this way, based on the message transmission time interval and preset duration in the message data, it can determine whether the received messages belong to the same message data and whether the reception of the next message data should begin. This reduces message misalignment caused by communication jitter, effectively divides the message data transmitted between circuit boards, and improves the communication efficiency and accuracy between circuit boards.

[0038] The communication method between the above circuit boards is described in detail below.

[0039] The message sending circuit board and message receiving circuit board described in this embodiment of the invention can communicate bidirectionally during the communication process. That is, the message sending circuit board can not only send message data, but also receive messages sent by the message receiving circuit board using the communication method between circuit boards described in this embodiment of the invention. For example, if circuit board 1 is a message sending circuit board and circuit board 2 is a message receiving circuit board, when circuit board 1 sends a data message to circuit board 2, circuit board 2 should send a message back to circuit board 1 according to the received message. Circuit board 1 can also act as a message receiver to receive messages sent by circuit board 2.

[0040] To more clearly understand the communication method between circuit boards described in the embodiments of the present invention, the following is combined with... Figure 2 To explain, Figure 2 This is an example diagram of message data, a first interval duration, and a second interval duration in a message receiving circuit board provided in an embodiment of the present invention. H, L, other data, and C1 represent a complete message data set, which is the message data received by circuit board 2, i.e., the message receiving circuit board. dm, h, and c1 represent a complete message data set, which is the message data that circuit board 2 needs to feed back to the message sending circuit board based on the aforementioned message data. Timer1 represents the first interval duration, Timer2 represents the second interval duration, and R1, R2, R13, T1, T2, T13, etc., represent the partial interval duration between two adjacent messages in a complete message data set. This interval duration, plus the pre-configured transmission interval delay duration for adjacent message reception by the message receiving circuit board, equals the first interval duration. For example, R1 + sleep = Timer1.

[0041] Regarding the above S101, such as Figure 2 As shown, each message data includes, for example, the message header identifier (e.g., ...). Figure 2 H in the message), length message that identifies the message length (e.g., Figure 2 L in the message content (e.g., L) Figure 2 Other data in the data), verification code (such as...) Figure 2 In the C1 section, when transmitting message data between circuit boards, the message header identifier is transmitted first, followed by the length message, then the message content of the length identifier, and finally the checksum. When the message receiving circuit board receives the header identifier message in the current message data, it immediately starts DMA data transmission, transferring the received data to memory for buffering. Simultaneously, a timer (i.e., the first timer) is started as a watchdog timer for the current message data transmission, used to collect the first interval between adjacent messages in the current message data reception. For example, the first interval between the message header identifier and the length message indicating the message length, the first interval between the length message and the first message in the message content, ..., the first interval between the last message in the message content and the checksum.

[0042] Regarding S102 above, the first preset duration is the timeout duration of the first timer set in advance. When it is determined that the first interval duration is longer than the first preset duration, it means that the data transmission of this message has been completed by the message sending circuit board due to some circumstances (such as network jitter), but the message receiving circuit board has not received the corresponding message. The message received later should belong to the message in the next message data. Therefore, when the first interval duration is longer than the first preset duration, the direct memory access DMA receive interrupt is disabled, the DMA cache of this message data is cleared, the next DMA receive interrupt is started, and the system waits to receive the message of the next message data.

[0043] In one embodiment of the present invention, the first preset duration is determined using the following formula:

[0044] Timeout 1=A×(Bit / B+sleep)+T_offse1;

[0045] Wherein, Timeout 1 is the first preset duration, T_offset1 is the internal machine clock cycle of the message receiving circuit board, A is a preset coefficient, which is the word data transmission length per baud rate of the Bit / B message sending circuit board, and sleep is the pre-configured transmission interval delay duration for adjacent message reception on the message receiving circuit board.

[0046] For example, each time circuit board 2 receives message data, it immediately initiates DMA data transmission to transfer the received message data to memory for caching. Simultaneously, it starts the first timer, Timer1, as a watchdog timer for this message data transmission T, monitoring whether a timeout occurs during the data communication. The timeout duration Timeout1 (i.e., the first preset duration) of Timer1 is determined based on the baud rate B of circuit board 1, the single data transmission length Bit, the transmission interval delay sleep, and the internal machine clock cycle T_offset1 of circuit board 2 (representing the minimum cycle of single-step operation of the chip inside the circuit board). In one embodiment of the present invention, the preset coefficient A is set to 1.1, the baud rate B of circuit board 1 is 3500000, the single data transmission length Bit is 16, the pre-configured transmission interval delay sleep for adjacent message reception circuit boards is 0.00005 seconds, and T_offset is 0.000001 seconds. Therefore, using the above formula, Timeout1 can be calculated to be 0.000061 seconds, or 61 microseconds.

[0047] Regarding S103 above, the first interval duration not exceeding the first preset duration indicates that the transmission and reception of messages in this message data are normal, and messages in this message data can be received continuously.

[0048] Regarding S104 above, the second preset duration is the timeout duration of the second timer set in advance. The second preset duration is determined according to the message length. Therefore, after receiving the long message in the message data, the second timer is started again to collect the second interval duration between receiving the long message in this message data and the final message.

[0049] In one embodiment of the present invention, the second preset duration is determined using the following formula:

[0050] Timeout 2=Timeout 1×(L+3)-T_offset2;

[0051] Wherein, Timeout 2 is the second preset duration, Timeout 1 is the first preset duration, L is the message length identified in the current message data, and T_offset2 is the time consumed by the message receiving circuit board to read and process the message.

[0052] For example, after receiving the message data length L, circuit board 2 starts the second timer 2. The size of the message length L determines that there are L subsequent valid data transmissions D0 to D(L-1), and 2 C1 data. Taking into account the time of this communication, it includes a total of L+3 data communication messages and L+3 transmission intervals. The timeout time of timer 2 is set according to the baud rate B of circuit board 1, the single data transmission length Bit, and the time T_offset2 consumed by the message receiving circuit board to read and process the message. In one embodiment of the present invention, the data length L is 9, the baud rate B of circuit board 1 is 3500000, the single data transmission length Bit is 16, and T_offset2 is 0.000005 seconds. Therefore, according to the above formula, Timeout2 can be determined to be 0.000727 seconds, or 727 microseconds.

[0053] Regarding S105 above, when it is determined that the second interval duration is greater than the second preset duration, it means that the current message data transmission is completed, and the received message should belong to the message in the next message data. Therefore, when the second interval duration is greater than the second preset duration, the direct memory access DMA receive interrupt is disabled, the DMA cache of the current message data is cleared, the next DMA receive interrupt is started, and the message waits to receive the next message data.

[0054] Furthermore, to avoid switching to receiving the next message data due to slight jitter, in one embodiment of the present invention, when a long message indicating the message length is received in the current message data, a second preset duration is determined based on the message length, and a second timer is started to collect the second interval duration between receiving the long message in the current message data and the final message, including: pre-configuring a reserved duration; when a long message indicating the message length is received in the current message data, the second timer is started to collect the second interval duration from receiving the long message in the current message data to waiting for the reserved duration after receiving the final message, such as... Figure 2 The total time after collecting data from R2 to R13 and then the sleep duration is used as the second interval duration.

[0055] This invention also provides a communication device between circuit boards, as described in the following embodiments. Since the principle by which this device solves the problem is similar to the communication method between circuit boards, the implementation of this device can be referred to the implementation of the communication method between circuit boards, and repeated details will not be elaborated further.

[0056] like Figure 3 The diagram shown is a schematic representation of a communication device between circuit boards provided in an embodiment of the present invention, comprising:

[0057] The first processing module 301 is used to start a first timer to collect the first interval duration of adjacent messages in the current message data when it receives the header identifier message in the current message data sent by the message sending circuit board;

[0058] The second processing module 302 is used to disable the Direct Memory Access (DMA) receive interrupt, clear the DMA cache of the current message data, start the next DMA receive interrupt, and wait to receive the message data of the next message when the first interval duration is longer than the first preset duration.

[0059] The third processing module 303 is used to continue receiving messages in the current message data when the first interval duration is not greater than the first preset duration;

[0060] The fourth processing module 304 is used to determine a second preset duration based on the message length when it receives a length message that indicates the message length in the current message data, and to start a second timer to collect the second interval duration between receiving the length message in the current message data and the final message.

[0061] The fifth processing module 305 is used to disable the DMA receive interrupt, clear the DMA buffer of the current message data, start the next DMA receive interrupt, and wait to receive the next message data when the second interval duration is longer than the second preset duration.

[0062] In one possible implementation, such as Figure 4As shown, the communication device between circuit boards further includes: a first preset duration determination module 401, used to determine the first preset duration using the following formula:

[0063] Timeout 1=A×(Bit / B+sleep)+T_offse1;

[0064] Wherein, Timeout 1 is the first preset duration, T_offset1 is the internal machine clock cycle of the message receiving circuit board, A is a preset coefficient, which is the word data transmission length per baud rate of the Bit / B message sending circuit board, and sleep is the pre-configured transmission interval delay duration for adjacent message reception on the message receiving circuit board.

[0065] In one possible implementation, the fourth processing module 304 is specifically used to determine the second preset duration using the following formula:

[0066] Timeout 2=Timeout 1×(L+3)-T_offset2;

[0067] Wherein, Timeout 2 is the second preset duration, Timeout 1 is the first preset duration, L is the message length identified in the current message data, and T_offset2 is the time consumed by the message receiving circuit board to read and process the message.

[0068] In one possible implementation, the fourth processing module 304 is specifically used to pre-configure a reserved duration; when a length message indicating the message length is received in the current message data, a second timer is started to collect the second interval duration from receiving the length message in the current message data to waiting for the reserved duration after receiving the final message.

[0069] Based on the aforementioned inventive concept, such as Figure 5 As shown, the present invention also proposes a computer device 500, including a memory 510, a processor 520, and a computer program 530 stored in the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 530, it implements the aforementioned communication method between circuit boards.

[0070] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the communication method between the circuit boards described above.

[0071] This invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements the communication method between the aforementioned circuit boards.

[0072] In this embodiment of the invention, when a header identifier message is received from the message sending circuit board in the current message data, a first timer is started to collect the first interval duration between adjacent messages in the current message data; when the first interval duration is greater than a first preset duration, the Direct Memory Access (DMA) receive interrupt is disabled, the DMA cache of the current message data is cleared, the next DMA receive interrupt is started, and the system waits to receive the message data of the next message; when the first interval duration is not greater than the first preset duration, the system continues to receive messages in the current message data; when a length message indicating the message length is received in the current message data, a second preset duration is determined according to the message length, and a second timer is started to collect the second interval duration between receiving the length message in the current message data and the final message; when the second interval duration is greater than the second preset duration, the DMA receive interrupt is disabled, the DMA cache of the current message data is cleared, the next DMA receive interrupt is started, and the system waits to receive the message data of the next message. In this way, based on the message transmission time interval and preset duration in the message data, it can determine whether the received messages belong to the same message data and whether the reception of the next message data should begin. This reduces message misalignment caused by communication jitter, effectively divides the message data transmitted between circuit boards, and improves the communication efficiency and accuracy between circuit boards.

[0073] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0074] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0075] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0076] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0077] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A communication method between circuit boards, characterized in that, Applied to message receiving circuit boards, including: When the header identifier message is received from the message transmission circuit board, the first timer is started to collect the first interval duration between adjacent messages in the message data. The message data includes: message header identifier, length message indicating message length, message content, and checksum. The first interval duration between adjacent messages includes: the first interval duration between the message header identifier and the length message indicating message length, the first interval duration between the length message and the first message in the message content, and the first interval duration between the last message in the message content and the checksum. When the first interval duration is longer than the first preset duration, disable the Direct Memory Access (DMA) receive interrupt, clear the DMA cache of the current message data, start the next DMA receive interrupt, and wait to receive the next message data. If the first interval duration is not greater than the first preset duration, continue to receive messages from the current message data; When a length message indicating the message length is received in the current message data, a second preset duration is determined based on the message length, and a second timer is started to collect the second interval duration between receiving the length message in the current message data and the final message. When the second interval duration is longer than the second preset duration, it indicates that the data transmission of this message is complete. The DMA receive interrupt is disabled, the DMA buffer of this message data is cleared, the next DMA receive interrupt is started, and the message waits to receive the next message data.

2. The communication method between circuit boards as described in claim 1, characterized in that, Also includes: The first preset duration is determined using the following formula: Timeout 1= A (Bit / B + sleep)+ T_offse1; Wherein, Timeout 1 is the first preset duration, T_offset1 is the internal machine clock cycle of the message receiving circuit board, A is a preset coefficient, which is the word data transmission length per baud rate of the Bit / B message sending circuit board, and sleep is the pre-configured transmission interval delay duration for adjacent message reception on the message receiving circuit board.

3. The communication method between circuit boards as described in claim 1, characterized in that, Also includes: The second preset duration is determined using the following formula: Timeout 2= Timeout 1 (L+3) - T_offset2; Wherein, Timeout 2 is the second preset duration, Timeout 1 is the first preset duration, L is the message length identified in the current message data, and T_offset2 is the time consumed by the message receiving circuit board to read and process the message.

4. The communication method between circuit boards as described in claim 1, characterized in that, Upon receiving a length message indicating the message length in the current message data, a second preset duration is determined based on the message length. A second timer is then started to collect the second interval duration between receiving the length message in the current message data and the final message, including: Pre-configure the reserved time; When the length message indicating the message length is received in the current message data, the second timer is started to collect the second interval time after the reserved waiting time from receiving the length message in the current message data to receiving the final message.

5. A communication device between circuit boards, characterized in that, include: The first processing module is used to start a first timer to collect the first interval duration of adjacent messages in the current message data when it receives the header identifier message in the current message data sent by the message sending circuit board. The message data includes: a message header identifier, a length message indicating the message length, the message content, and a checksum; the first interval between adjacent messages includes: the first interval between the message header identifier and the length message indicating the message length, the first interval between the length message and the first message in the message content, and the first interval between the last message in the message content and the checksum; The second processing module is used to indicate that the current message data transmission is completed when the first interval duration is longer than the first preset duration, disable the direct memory access DMA receive interrupt, clear the DMA cache of the current message data, start the next DMA receive interrupt, and wait to receive the next message data. The third processing module is used to continue receiving messages in the current message data when the first interval duration is not greater than the first preset duration; The fourth processing module is used to determine the second preset duration based on the message length when it receives a long message that indicates the message length in the current message data, and to start the second timer to collect the second interval duration between receiving the long message in the current message data and the final message. The fifth processing module is used to disable the DMA receive interrupt, clear the DMA buffer of the current message data, start the next DMA receive interrupt, and wait to receive the next message data when the second interval duration is longer than the second preset duration.

6. The communication device between circuit boards as described in claim 5, characterized in that, Also includes: The first preset duration determination module is used to determine the first preset duration using the following formula: Timeout 1= A (Bit / B + sleep)+ T_offse1; Wherein, Timeout 1 is the first preset duration, T_offset1 is the internal machine clock cycle of the message receiving circuit board, A is a preset coefficient, which is the word data transmission length per baud rate of the Bit / B message sending circuit board, and sleep is the pre-configured transmission interval delay duration for adjacent message reception on the message receiving circuit board.

7. The communication device between circuit boards as described in claim 5, characterized in that, The fourth processing module is specifically used to determine the second preset duration using the following formula: Timeout 2= Timeout 1 (L+3) - T_offset2; Wherein, Timeout 2 is the second preset duration, Timeout 1 is the first preset duration, L is the message length identified in the current message data, and T_offset2 is the time consumed by the message receiving circuit board to read and process the message.

8. The communication device between circuit boards as described in claim 5, characterized in that, The fourth processing module is specifically used to pre-configure the reserved time; when a length message indicating the message length is received in the current message data, the second timer is started to collect the second interval time from the time the length message in the current message data is received to the time after the reserved time after the final message is received.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 4.

11. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 4.

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