Motion vector refinement apparatus and its related motion vector refinement method

Abstract

A motion vector refinement device includes a first storage, a motion vector predictor (MVP) derivation circuit, and a decoder-side motion vector refinement (DMVR) circuit. The MVP derivation circuit derives a first MVP for a current block, stores the first MVP in the first storage, and proceeds with a new task. The DMVR circuit performs a DMVR operation to derive a first motion vector difference (MVD) for the first MVP. The MVP derivation circuit starts the new task before the DMVR circuit finishes deriving the first MVD for the first MVP. The motion vector refinement device and method of the present disclosure allow the MVP derivation circuit to start a new task without waiting for the motion vector difference (MVD) calculation, improving decoding efficiency.

Description

Technical Field

[0001] This disclosure relates to motion vector refinement. In particular, it relates to a motion vector refinement apparatus with motion vector prediction (MVP) derivation circuitry and a related motion vector refinement method, wherein the MVP derivation circuitry can start a new task without waiting for motion vector difference (MVD) calculation. Background Technology

[0002] Traditional video codec standards typically employ block-based coding techniques to utilize spatial and temporal redundancy. For example, the basic approach involves dividing the entire source image into multiple blocks, performing intra-block / inter-block prediction on each block, transforming the residuals of each block, and then performing quantization and entropy coding. Furthermore, a reconstructed image is generated during the coding loop to provide reference pixel data for coding subsequent blocks. For specific video codec standards, loop filters can be used to enhance the image quality of the reconstructed image.

[0003] The video encoding operations performed by a video encoder can be reversed using a video decoder. For example, a video decoder may have multiple processing circuits (e.g., entropy decoding circuits), internal prediction circuits, motion compensation circuits, inverse quantization circuits, inverse conversion circuits, reconstruction circuits, and loop filters. When a merge mode is selected, the motion information of the current block in the current image can be set by the motion information of spatially or temporally adjacent blocks. To refine the merge mode motion vector (MV) without transmitting a signal, a decoder-measured motion vector refinement (DMVR) algorithm can be used. Specifically, to refine the merge mode MV, the DMVR algorithm needs to cross adjacent points to find the minimum sum of absolute differences (SAD) and refer to the position with the minimum SAD to determine the motion vector difference (MVD). For example, the search range is ±2, resulting in a total of 25 points in the search window, and the motion vector prediction (MVP) derived from the motion information of the previously decoded block points to the center point of the search window. By combining the MVP and MVD, the final MV (i.e., the refined MV) for the current block in the current image can be obtained.

[0004] MVD is used to refine the MVP of the current block in the current image. MVD is not sent from the video encoder to the video decoder; instead, it is calculated by the video decoder using the DMVR algorithm. Specifically, to calculate the MVD needed to refine the MVP, reference pixels from the forward and backward reference images are read from Dynamic Random Access Memory (DRAM). The forward reference image (e.g., an image contained in reference image list L0) is in the past in display order relative to the current block, and the backward reference image (e.g., an image contained in reference image list L1) is in the future in display order relative to the current block. The distance between the current image and the forward reference image is equal to the distance between the current image and the backward reference image. As described above, when the MVD calculation for the current block is completed, the final MV (i.e., the refined MV) for the current block is obtained. According to traditional video decoding design, the MVP calculation for the next block will not begin until the final MV (i.e., the refined MV) for the current block is obtained. In other words, the MVP calculation for the next block will not begin until the MVD calculation for the current block is completed. Since calculating the NVD for the current block requires reading reference pixels from DRAM, and reading reference pixels from DRAM takes several DRAM frequency cycles, the calculation of the next MVP block has to wait until the MVD calculation for the current block is completed due to DRAM lag, thus reducing decoder performance. Summary of the Invention

[0005] One object of this disclosure is to provide a motion vector refinement apparatus and a related motion vector refinement method with motion vector prediction (MVP) derivation circuitry, wherein the MVP derivation circuitry can start a new task without waiting for motion vector difference (MVD) calculation.

[0006] According to the first aspect of this disclosure, an example motion vector refinement device has been disclosed. The example motion vector refinement device includes a first storage device, motion vector prediction (MVP) derivation circuitry, and decoder-side motion vector refinement (DMVR) circuitry. The MVP derivation circuitry is configured to derive a first MVP for the current block, store the first MVP in the first storage device, and perform a new task. The DMVR circuitry is configured to perform DMVR operation to derive a first motion vector difference (MVD) for the first MVP. Before the DMVR circuitry completes the derivation of the first MVD for the first MVP, the MVP derivation circuitry begins performing a new task.

[0007] According to a second aspect of this disclosure, an example motion vector refinement method has been disclosed. The example motion vector refinement method includes: deriving a first MVP for the current block; storing the first MVP in a first storage device; performing a DMVR operation to derive a first MVD for the first MVP; and starting a new task before completing the derivation of the first MVD for the first MVP.

[0008] In the motion appropriate refinement device and method disclosed herein, the MVP derivation circuit does not need to wait for the motion vector difference (MVD) calculation before starting a new task, thus improving decoding efficiency. Attached Figure Description

[0009] Referring to the following accompanying drawings, various embodiments of this disclosure presented as examples will be described in detail, wherein:

[0010] Figure 1 A first motion vector refinement device according to an embodiment of the present disclosure is shown.

[0011] Figure 2 The footprint of dynamic random access memory (DRAM) according to an embodiment of the present disclosure is shown.

[0012] Figure 3 Showing the use Figure 2 The example shown is used to store the refined motion vectors of blocks in large coding units (LCUs), each LCU having a size of 32x32.

[0013] Figure 4 Showing the use Figure 2 The example shown is of DRAM usage used to store the refined motion vectors of blocks in LCUs, each LCU having a 64x64 LCU size.

[0014] Figure 5 Showing the use Figure 2 The example shown is of DRAM usage used to store the refined motion vectors of blocks in LCUs, each LCU having an LCU size of 128x128.

[0015] Figure 6 A second motion vector refinement device according to an embodiment of the present disclosure is shown.

[0016] Figure 7 Another DRAM usage is shown according to an embodiment of this disclosure.

[0017] Figure 8 Showing the use Figure 7 The example shown illustrates DRAM usage for storing motion vector predictions and motion vector differences. Detailed Implementation

[0018] Throughout the following description and claims, specific terms refer to particular components. As will be understood by those skilled in the art, electronic device manufacturers may refer to the same component under different names. This document is not intended to distinguish between components with different names but identical functions. In the following description and claims, the terms “comprising” and “including” are used in an open-ended manner and should therefore be interpreted as meaning “including, but not limited to…”. Moreover, the term “coupled” is intended to indicate either indirect or direct electronic connection. Thus, if one device is coupled to another device, the connection may be a direct electronic connection or an indirect electronic connection via other devices and links.

[0019] Figure 1 A first motion vector refinement apparatus according to an embodiment of the present disclosure is shown. The motion vector refinement apparatus 100 may be part of a video decoder used to process the decoding of an input bitstream conforming to the Versatile Video Coding (VVC) standard (also known as the H.266 standard). However, this is for illustrative purposes only, and the present disclosure is not limited to the aforementioned standard. In practice, any video decoder using the architecture proposed in this disclosure falls within the scope of this disclosure. The motion vector refinement apparatus 100 includes a motion vector prediction (MVP) derivation circuit 102, a decoder-measured motion vector refinement (DMVR) circuit 104, an address generation circuit 106, a binding circuit 108, multiple format conversion circuits 110, 112, and multiple independent storage devices, such as a motion vector (MV) buffer 114 (which may be on-chip memory) and dynamic random access memory (DRAM) 116 (which may be external-chip memory).

[0020] MVP derivation circuit 102 is configured to derive the MVP for motion vector prediction of the current block in the current image. FX _1, and predict MVP using motion vectors. FX _1 is stored in MV buffer 114. In this embodiment, motion vector prediction MVP FX _1 represents the first rendering format, such as a fixed-point format. In merge mode, motion vector prediction MVP is derived from the motion vectors of the current block's neighboring blocks. FX Following _1, the MVP derivation circuit 102 is further configured to provide side information INF. MVP To DMVR circuit 104, and provide side information INF ADDR Address generation circuit 106. Responding to the adjacent information INF. ADDR The address generation circuit 106 determines and calculates the motion vector difference (MVD). FXThe read address of the storage location for the reference data D_REF required by _1 (e.g., reference pixels in the forward and backward reference images). That is, the side information INF. ADDR The data is transmitted to address generation circuit 106 to request reference data D_REF stored in DRAM 116.

[0021] Receives side information INF from MVP drive circuit 102 MVP Subsequently, the DMVR circuit 104 is configured to perform DMVR operation to derive the MVP for motion vector prediction. FX Motion Vector Difference (MVD) of _1 FX _1. For example, the DMVR circuit 104 reads reference data D_REF from DRAM 116, calculates 25 SAD values ​​for 25 positions within a search window at the center of the current block, finds the minimum SAD value among the 25 SAD values, and determines the motion vector difference (MVD) based on the position with the minimum SAD value. FX 1. In this embodiment, the motion vector difference (MVD) FX _1 is also the first presentation format, such as fixed-point format.

[0022] Because the motion vector obtained from the MVP derivation circuit 102 predicts the MVP FX _1 is stored in MV buffer 114, and circuit 108 is configured to obtain motion vector prediction MVP from MV buffer 114. FX Instead of obtaining it from MVP derivation circuit 102, _1 is used. With the help of MV buffer 114, an MVP buffer can be provided between MVP derivation circuit 102 and the bonding circuit 108, allowing MVP derivation circuit 102 to complete the derivation of the motion vector prediction MVP for the current block in DMVR circuit 104. FX Motion Vector Difference (MVD) of _1 FX A new task begins before step 1. In some embodiments, the new task includes at least one of the following: deriving the motion vector prediction MVP for the next block. FX _2. Reading data for subsequent calculations from a storage device (e.g., DRAM 116 or SRAM not shown in this document), writing data for subsequent calculations back to the storage device, and any other task independent of deriving the motion vector difference that can effectively utilize idle computing resources. A new task is then performed to derive the motion vector prediction MVP for the next block. FX In the embodiment of _2, when determining the motion vector prediction MVP for the next block... FX After _2, MVP derivation circuit 102 will predict the motion vector of the MVP. FX_2 is stored in MV buffer 114, and the MVP calculation procedure for the next block begins. Reference data D_REF is read to calculate the motion vector difference MVD. FX The DRAM latency of _1 can be completely or partially hidden because during this latency, the MVP propagation circuit 102 can perform motion vector prediction MVP. FX The calculation of _2. Because the next motion vector predicts the MVP. FX The calculation of _2 does not require waiting for the current motion vector difference MVD. FX The calculation of _1 is completed, which can greatly improve the performance of the decoder.

[0023] In the DMVR circuit 104, the motion vector difference (MVD) is determined. FX After _1, the circuit 108 is configured to read the motion vector from the MV buffer 114 to predict the MVP. FX 1. Receive motion vector difference (MVD) from DMVR circuit 104 FX _1 and predicting MVP using motion vectors FX _1 and the difference between motion vectors (MVD) FX _1 is combined to generate the refined motion vector MV for the current block. FX _1(MV FX _1 = MVP FX _1+MVD FX _1), where the refined motion vector MV FX _1 is the first presentation format, such as a fixed-point format. To reduce memory usage, the format conversion circuit 112 is configured to process the refined motion vector MV. FX _1. Format conversion is performed. Specifically, the format conversion circuit 112 is configured to receive the refined motion vector MV output by the combination circuit 108. FX 1. Refine the motion vector MV of the first presentation format. FX The process involves converting _1 into a refined motion vector MVFP_1 in a second rendering format (e.g., floating-point format) and storing the refined motion vector MVFP_1 in DRAM 116 for later use. For example, the refined motion vector MVFP_1 in the first rendering format... FX _1 has a bit length of 18, while the refined motion vector MVFP_1 of the second rendering format has a bit length of 10. It should be noted that the conversion from 18-bit fixed-point rendering to 10-bit floating-point rendering may incur conversion loss, for example, consisting of a 4-bit exponent and a 6-bit mantissa.

[0024] When the motion vector of the current block is selected as a candidate for motion vector prediction of a subsequent decoded block (e.g., a block that is in a future image relative to the current image in terms of display order), the format conversion circuit 110 is configured to read the refined motion vector MVFP_1 from DRAM 116 and perform format conversion on the refined motion vector MVFP_1. Specifically, the format conversion circuit 110 is configured to convert the refined motion vector MVFP_1 in a second rendering format (e.g., floating-point format) to the refined motion vector MVFP_1 in a first rendering format (e.g., fixed-point format). FX _1', and refine the motion vector MV FX _1' is provided to MVP derivation circuit 102. Since converting from fixed-point to floating-point rendering may cause conversion overhead, the refined motion vector MV... FX _1' is not necessarily related to the refined MV FX _1 is the same.

[0025] The format conversion circuit 112 converts the refined motion vector of the first presentation format (e.g., fixed-point format) of each block into the refined motion vector of the second presentation format (e.g., floating-point format), and stores the refined motion vector of the second presentation format (e.g., floating-point format) in DRAM 116. Figure 2 The dynamic random access memory (DRAM) footprint according to embodiments of this disclosure is indicated. The DRAM footprint can define the storage space in which the refined motion vector of a block is to be stored.

[0026] Figure 3 Showing the use Figure 2 The example shown illustrates DRAM usage used to store refined motion vectors of blocks within large coding units (LCUs), each LCU having a 32x32 LCU size. Taking LCU 302 as an example, according to... Figure 2 The DRAM occupancy shown is that the refined motion vector of the block, with indices 0 and 1, is stored at address addr[4:0] = 0, and according to... Figure 2 The DRAM occupancy shown is that the refined motion vector of the block, with indices 2 and 3, is stored at address addr[4:0] = 1.

[0027] Figure 4 Showing the use Figure 2 The example shown illustrates DRAM usage used to store refined motion vectors of blocks within LCUs, each LCU having a 64x64 LCU size. Taking LCU 402 as an example, according to... Figure 2 The DRAM occupancy shown is such that the refined motion vector of the block, with indices 0 and 1, is stored at address addr[4:0] = 0, according to... Figure 2 The DRAM occupancy shown is such that the refined motion vector of the block, with indices 2 and 3, is stored at address addr[4:0] = 1, according to... Figure 2 The DRAM occupancy shown is that the refined motion vector of the block, with indices 4 and 5, is stored at address addr[4:0] = 2, and according to... Figure 2 The DRAM occupancy shown is such that the blocks indexed as 6 and 7 in the refined motion vector are stored at address addr[4:0]=3, and so on.

[0028] Figure 5 Showing the use Figure 2 The example shown illustrates DRAM usage used to store refined motion vectors of blocks within LCUs, each LCU having a 128x128 LCU size. Taking LCU 502 as an example, according to... Figure 2 The DRAM occupancy shown is represented by blocks whose refined motion vectors are indexed from 0 to 63 and stored at addresses addr[4:0] = 0 to addr[4:0] = 31.

[0029] Figure 6 A second motion vector refinement apparatus according to an embodiment of this disclosure is shown. The motion vector refinement apparatus 600 may be part of a video decoder used to process the decoding of an input bitstream conforming to the VVC standard (also known as the H.266 standard). However, this is for illustrative purposes only, and this disclosure is not limited to the aforementioned standard. In practice, any video decoder using the architecture proposed in this disclosure falls within the scope of this disclosure. The motion vector refinement apparatus 600 includes an MVP derivation circuit 602, a DMVR circuit 604, an address generation circuit 606, a binding circuit 608, multiple format conversion circuits 610, 612, and DRAM 614 (which may be external memory). The MVP derivation circuit 602 is configured to derive a motion vector prediction MVP for the current block in the current image. FX _1, and predict MVP using motion vectors. FX _1 is stored in DRAM 614. In this embodiment, motion vector prediction MVP FX _1 represents the first rendering format, such as a fixed-point format. In merge mode, motion vector prediction MVP is derived from the motion vectors of the current block's neighboring blocks. FX Following _1, the MVP derivation circuit 602 is further configured to provide side information INF. MVP To DMVR circuit 604, and provide side information INF ADDR Address generation circuit 606. Responding to the adjacent information INF. ADDR The address generation circuit 606 determines and calculates the motion vector difference (MVD). FXThe read address of the storage location for the reference data D_REF required by _1 (e.g., reference pixels in the forward and backward reference images). That is, the side information INF. ADDR The data is transmitted to address generation circuit 606 to request reference data D_REF stored in DRAM 616.

[0030] Receive side information INF from MVP drive circuit 602 MVP Subsequently, the DMVR circuit 604 is configured to perform DMVR operation to derive the MVP for motion vector prediction. FX Motion Vector Difference (MVD) of _1 FX _1, and the motion vector difference MVD FX _1 is stored in DRAM 614. For example, DMVR circuit 604 reads reference data D_REF from DRAM 614, calculates 25 SAD values ​​for 25 positions within the search window at the center of the current block, finds the minimum SAD value among the 25 SAD values, and determines the motion vector difference (MVD) based on the position with the minimum SAD value. FX 1. In this embodiment, the motion vector difference (MVD) FX _1 is also the first presentation format, such as fixed-point format.

[0031] In this embodiment, motion vector prediction MVP is used for the same block. FX _1 and motion vector difference MVD FX _1 is individually stored in DRAM 614. The motion vector obtained from MVP derivation circuit 602 predicts the MVP. FX _1 is stored in DRAM 614, and circuit 608 is configured to obtain the motion vector prediction MVP from DRAM 614. FX _1, instead of obtaining it from MVP derivation circuit 602. With the help of DRAM 614, the MVP output of MVP derivation circuit 602 can be buffered, allowing MVP derivation circuit 602 to complete the derivation of the motion vector prediction MVP for the current block in DMVR circuit 604. FX Motion Vector Difference (MVD) of _1 FX A new task begins before step 1. In some embodiments, the new task includes at least one of the following: deriving the motion vector prediction MVP for the next block. FX _2. Reading data for subsequent calculations from a storage device (e.g., DRAM 116 or SRAM not shown in this document), writing data for subsequent calculations back to the storage device, and any other task independent of deriving the motion vector difference that can effectively utilize idle computing resources. A new task is then performed to derive the motion vector prediction MVP for the next block. FXIn the embodiment of _2, when determining the motion vector prediction MVP for the next block... FX After _2, the MVP derivation circuit 602 will predict the motion vector of the MVP. FX _2 is stored in DRAM 614, and the MVP calculation program for the next block begins. Therefore, reference data D_REF is read to calculate the motion vector difference MVD. FX The DRAM latency of _1 can be completely or partially hidden because during this latency, the MVP propagation circuit 602 can perform motion vector prediction MVP. FX The calculation of _2. Because the next motion vector predicts the MVP. FX The calculation of _2 does not require waiting for the current motion vector difference MVD. FX The calculation of _1 is completed, which can greatly improve the performance of the decoder.

[0032] When the motion vector of the current block is selected as a candidate for motion vector prediction of a subsequent decoded block (e.g., a block that is in a future image relative to the current image in terms of display order), the combination circuit 608 is configured to read the motion vector prediction MVP from the DRAM 614. FX _1 and motion vector difference MVD FX _1, and predict MVP using motion vectors. FX _1 and the difference between motion vectors (MVD) FX _1 is combined to generate the refined motion vector MV for the current block. FX _1(MV FX _1 = MVP FX _1+MVD FX _1), where the refined motion vector MV FX _1 is the first rendering format, such as fixed-point format.

[0033] exist Figure 1 In the illustrated embodiment, conversion from fixed-point rendering to floating-point rendering may incur conversion overhead. Figure 6 In the illustrated embodiment, conversion loss is taken into account to provide the same motion vector MV. FX _1' is used for motion vector prediction in MVP derivation circuit 602. Specifically, by refining the motion vector MV... FX _1. Conversion loss is introduced through the format conversion circuit 610. The format conversion circuit 610 is configured to convert the refined motion vector MV output by the combination circuit 608. FX _1. Format conversion is performed. Specifically, the format conversion circuit 610 is configured to receive the refined motion vector MV output by the coupling circuit 608. FX _1, and refine the motion vector MV of the first presentation format. FXThe _1 is converted into a refined motion vector MVFP_1 in a second rendering format (e.g., floating-point format). For example, the refined motion vector MV in the first rendering format FX The first motion vector MVFP_1 has a bit length of 18, while the refined motion vector MVFP_1 in the second presentation format has a bit length of 10. Next, the format conversion circuit 612 is configured to perform format conversion on the refined motion vector MVFP_1 output by the format conversion circuit 610. Specifically, the format conversion circuit 612 is configured to receive the refined motion vector MVFP_1 output by the format conversion circuit 610, and convert the refined motion vector MVFP_1 in the second presentation format (e.g., floating-point format) into the refined motion vector MVFP_1 in the first presentation format (e.g., fixed-point format). FX _1', and refine the motion vector MV FX _1' is provided to the MVP derivation circuit 602. (and...) Figure 1 Similar to the motion vector refinement device 100 shown, due to the conversion loss caused by converting from fixed-point to floating-point representation, the motion vector refinement device 600 may not produce the same refined MV. FX The same refined motion vector MV _1 FX _1'.

[0034] For each block to be decoded, the MVP propagation circuit 602 determines the motion vector prediction and stores it in DRAM 614, while the DMVR circuit 604 determines the motion vector difference and stores it in DRAM 614. Since the motion vector prediction and motion vector difference for the same block can be read from DRAM 614 to determine the refined motion vector, DRAM occupancy can be appropriately designed to ensure that, in burst mode of DRAM 614, the motion vector prediction and motion vector difference for the same block can be retrieved by a single burst transfer. Please refer to [reference needed]. Figure 7 and combined Figure 8 . Figure 7 Another DRAM usage is shown according to an embodiment of this disclosure. Figure 8 Showing the use Figure 7 The example shown illustrates DRAM usage for storing motion vector predictions and motion vector differences. DRAM usage defines memory region 702, specified by consecutive addresses Addr_0 to Addr_3, and memory region 704, specified by consecutive addresses Addr_4 to Addr_11. Memory region 702 is used to store... Figure 8 The block shown represents the motion vector difference determined by the data. Storage area 704 is used to store the motion vector difference determined by the data. Figure 8The motion vector prediction for the block shown is determined. Therefore, the address of the block's motion vector prediction is forced to be close to the address of the motion vector difference of the same block. For example, MVP derivation circuit 602 is configured to store the block's MVP at a first address (e.g., Addr_4) in DRAM 614, DMVR circuit 604 is configured to store the same block's MVD at a second address (e.g., Addr_0) in DRAM 614, and address generation circuit 606 is configured to generate the starting read address of the burst mode of DRAM 614, wherein the burst mode of DRAM 614 is configured to read N (N>1) consecutive addresses, and the first address and the second address are part of the N consecutive addresses. In this way, the MVP and MVD of multiple blocks can be sequentially read from DRAM 614 in a single burst transfer, and the refined MV of multiple blocks can be sequentially generated by combination circuit 608. Decoder performance can be further improved by using the DRAM occupancy proposed in this disclosure.

[0035] Throughout this specification, references to "implementation," "some implementations," or similar language indicate that a particular feature, structure, or characteristic described in connection with that implementation may be included in at least one embodiment of the invention. Therefore, the phrases "in an implementation" or "in some implementations" appearing throughout this specification do not necessarily refer to the same implementation, which may be implemented alone or in combination with one or more other implementations. Furthermore, the particular features, structures, or characteristics described may be combined in any suitable manner in one or more implementations. However, those skilled in the art will recognize that the invention may be practiced in the absence of one or more of these specific details or using other methods, components, etc. In other instances, well-known structures or operations have not been shown or described in detail to avoid obscuring aspects of the invention.

[0036] The invention may be embodied in other specific forms without departing from its spirit and essential characteristics. The examples described are to be considered as illustrative rather than limiting in all respects. Therefore, the scope of the invention is indicated by the appended claims rather than the foregoing description. All modifications falling within the meaning and scope of equivalents of the claims will be covered by the scope of these claims.

Claims

1. A motion vector refinement device, the motion vector refinement device comprising: First storage device; Second storage device; The motion vector prediction derivation circuit is configured to derive a first motion vector prediction for the current block, store the first motion vector prediction in the first storage device, and perform a new task. A decoder-side motion vector refinement circuit is configured to perform decoder-side motion vector refinement operations to derive a first motion vector difference for the first motion vector prediction, wherein the motion vector prediction derivation circuit begins the new task before the decoder-side motion vector refinement circuit completes the derivation of the first motion vector difference for the first motion vector prediction. The circuitry is configured to read the first motion vector prediction from the first storage device and combine the first motion vector prediction with the first motion vector difference to generate a first refined motion vector for the current block, wherein the first refined motion vector is in a first rendering format; and A first format conversion circuit is configured to: receive the first refined motion vector output by the combination circuit, convert the first refined motion vector in the first presentation format into a second refined motion vector in a second presentation format, and store the second refined motion vector in a second storage device, wherein the second presentation format is different from the first presentation format.

2. The motion vector refinement device according to claim 1, characterized in that, The new task includes at least one of the following: deriving a second motion vector prediction for the next block, reading first data for a first calculation, and writing second data for a second calculation.

3. The motion vector refinement device according to claim 1, characterized in that, The bit length of the second refined motion vector is shorter than the bit length of the first refined motion vector.

4. The motion vector refinement device according to claim 1, characterized in that, The first presentation format is a fixed-point format, and the second presentation format is a floating-point format.

5. The motion vector refinement device according to claim 1, characterized in that... The motion vector refinement device also includes: The second format conversion circuit is configured to read the second refined motion vector from the second storage device, convert the second refined motion vector in the second presentation format into a third refined motion vector in the first presentation format, and provide the third refined motion vector to the motion vector prediction derivation circuit.

6. A motion vector refinement device, the motion vector refinement device comprising: First storage device; The motion vector prediction derivation circuit is configured to derive a first motion vector prediction for the current block, store the first motion vector prediction in the first storage device, and perform a new task. A decoder-side motion vector refinement circuit is configured to perform decoder-side motion vector refinement operations to derive a first motion vector difference for the first motion vector prediction, wherein the motion vector prediction derivation circuit begins the new task before the decoder-side motion vector refinement circuit completes the derivation of the first motion vector difference for the first motion vector prediction, and the decoder-side motion vector refinement circuit is further configured to store the first motion vector difference in the first storage device. The circuitry is configured to read the first motion vector prediction from the first storage device and combine the first motion vector prediction with the first motion vector difference to generate a first refined motion vector for the current block, wherein the first refined motion vector is in a first presentation format; A first format conversion circuit is configured to receive a first refined motion vector output by the combination circuit and a second refined motion vector that converts the first refined motion vector in the first presentation format into a second presentation format, wherein the second presentation format is different from the first presentation format; and The second format conversion circuit is configured to read the second refined motion vector output by the first format conversion circuit, convert the second refined motion vector in the second presentation format into a third refined motion vector in the first presentation format, and provide the third refined motion vector to the motion vector prediction derivation circuit.

7. The motion vector refinement device according to claim 6, characterized in that, The bit length of the second refined motion vector is shorter than the bit length of the first refined motion vector, and the bit length of the third refined motion vector is equal to the bit length of the first refined motion vector.

8. The motion vector refinement device according to claim 6, characterized in that, The first presentation format is a fixed-point format, and the second presentation format is a floating-point format.

9. A motion vector refinement device, the motion vector refinement device comprising: First storage device; The motion vector prediction derivation circuit is configured to derive a first motion vector prediction for the current block, store the first motion vector prediction in the first storage device, and perform a new task. A decoder-side motion vector refinement circuit is configured to perform decoder-side motion vector refinement operations to derive a first motion vector difference for the first motion vector prediction, wherein the motion vector prediction derivation circuit begins the new task before the decoder-side motion vector refinement circuit completes the derivation of the first motion vector difference for the first motion vector prediction, and the decoder-side motion vector refinement circuit is further configured to store the first motion vector difference in the first storage device. The motion vector prediction derivation circuit is configured to store the first motion vector prediction at a first address of the first storage device, the decoder-side motion vector refinement circuit is configured to store the first motion vector difference at a second address of the first storage device, and the motion vector refinement device further includes: An address generation circuit is configured to generate a starting read address for a burst mode of the first storage device, wherein the burst mode of the first storage device is configured to read a plurality of consecutive addresses, and the first address and the second address are part of the plurality of consecutive addresses.

10. A method for refining motion vectors, the method comprising: Derivation of the first motion vector prediction for the current block; The first motion vector prediction is stored in the first storage device; Perform decoder-side motion vector refinement to derive a first motion vector difference for the prediction of the first motion vector; Before completing the derivation of the first motion vector difference used for the prediction of the first motion vector, a new task begins; Read the first motion vector prediction from the first storage device; The first motion vector prediction is combined with the first motion vector difference to generate a first refined motion vector for the current block, wherein the first refined motion vector is in a first rendering format; Convert the first refined motion vector in the first rendering format to a second refined motion vector in the second rendering format; and The second refined motion vector is stored in a second storage device, wherein the second presentation format is different from the first presentation format.

11. The motion vector refinement method according to claim 10, characterized in that, The new task includes at least one of the following: deriving a second motion vector prediction for the next block, reading first data for a first calculation, and writing second data for a second calculation.

12. The motion vector refinement method according to claim 10, characterized in that, The bit length of the second refined motion vector is shorter than the bit length of the first refined motion vector.

13. The motion vector refinement method according to claim 10, characterized in that... The method further includes: Read the second refined motion vector from the first storage device; Convert the second refined motion vector of the second rendering format into the third refined motion vector of the first rendering format; and The third refined motion vector is provided for motion vector prediction derivation.

14. A motion vector refinement method, the motion vector refinement method comprising: Derivation of the first motion vector prediction for the current block; The first motion vector prediction is stored in the first storage device; Perform decoder-side motion vector refinement to derive a first motion vector difference for the prediction of the first motion vector; Before completing the derivation of the first motion vector difference used for the prediction of the first motion vector, a new task begins; Store the first motion vector difference into the first storage device; Read the first motion vector prediction and the first motion vector difference from the first storage device; The first motion vector prediction is combined with the first motion vector difference to generate a first refined motion vector for the current block, wherein the first refined motion vector is in a first rendering format; The first refined motion vector in the first rendering format is converted into a second refined motion vector in a second rendering format, wherein the second rendering format is different from the first rendering format; Convert the second refined motion vector of the second rendering format into the third refined motion vector of the first rendering format; and The third refined motion vector is provided for motion vector prediction derivation.

15. The motion vector refinement method according to claim 14, characterized in that, The bit length of the second refined motion vector is shorter than the bit length of the first refined motion vector, and the bit length of the third refined motion vector is equal to the bit length of the first refined motion vector.

16. A motion vector refinement method, the motion vector refinement method comprising: Derivation of the first motion vector prediction for the current block; The first motion vector prediction is stored in the first storage device; Perform decoder-side motion vector refinement to derive a first motion vector difference for the prediction of the first motion vector; Before completing the derivation of the first motion vector difference used for the prediction of the first motion vector, a new task begins; Store the first motion vector difference into the first storage device; Storing the first motion vector prediction in the first storage device includes: storing the first motion vector prediction at a first address of the first storage device; Storing the first motion vector difference in the first storage device includes: storing the first motion vector difference at a second address of the first storage device; and the motion vector refinement method further includes: A starting read address is generated for the burst mode of the first storage device, wherein, in response to the starting read address, the burst mode of the first storage device reads a plurality of consecutive addresses, and the first address and the second address are part of the plurality of consecutive addresses.

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