Display substrate, manufacturing method thereof, and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes: a substrate and a shift register unit and a first clock signal line disposed on the substrate, the first clock signal line extending along a first direction on the substrate; the shift register unit includes an input circuit, an output circuit, a first control circuit, a second control point, and an output control circuit; a positive projection of an intermediate transfer electrode on the substrate is located between positive projections of an active layer of a first control transistor and an active layer of a second control transistor on the substrate and positive projections of an active layer of a first noise reduction transistor and an active layer of a second noise reduction transistor on the substrate, and a gate of the first noise reduction transistor is connected to a first pole of the first control transistor and a first pole of the second control transistor through the intermediate transfer electrode. The display substrate optimizes the layout of the circuit structure, which is beneficial to realizing a narrow border design of the display panel.

Description

[0001] Cross-reference

[0002] This application is a divisional application of the invention patent application with the application date of April 10, 2020 and the application number of 202080000513.6. Technical field

[0003] Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device. Background art

[0004] In the field of display technology, for example, the pixel array of a liquid crystal display panel or an organic light-emitting diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interleaved with the gate lines. The driving of the gate lines can be achieved through a bonded integrated driving circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line driving circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including multiple cascaded shift register units can be used to provide a switching state voltage signal (scanning signal) for multiple rows of gate lines of the pixel array, so as to control, for example, multiple rows of gate lines to be sequentially turned on, and at the same time, a data signal is provided to the pixel units of the corresponding rows in the pixel array by the data lines, so as to form the gray-scale voltage required for each gray scale of the display image in each pixel unit, and then display a frame of image. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a display substrate, including: a substrate substrate, and a shift register unit, a first clock signal line, and a second clock signal line disposed on the substrate substrate, wherein

[0006] The first clock signal line extends along a first direction on the substrate, and is configured to provide a first clock signal to the shift register unit; the second clock signal line extends along the first direction on the substrate, and is configured to provide a second clock signal to the shift register unit; the shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and an output control circuit; the input circuit is configured to input an input signal to a first node in response to the first clock signal; the output circuit is configured to output an output signal to an output terminal; the first control circuit is configured to control the level of a second node in response to the level of the first node and the first clock signal; the second control circuit is connected to the first node and the second node, and is configured to control the level of the first node under the control of the level of the second node and the second clock signal; the output control circuit is configured to control the level of the output terminal under the control of the level of the second node; wherein, the first control circuit includes a first control transistor and a second control transistor, the second control circuit includes a first noise reduction transistor and a second noise reduction transistor, the shift register unit further includes an intermediate transfer electrode, the active layers of the first control transistor and the second control transistor and the active layers of the first noise reduction transistor and the second noise reduction transistor are arranged side by side in a second direction different from the first direction, a part of the projection of the intermediate transfer electrode on the substrate includes the projection of the active layer of the first control transistor on the substrate, the projection of the active layer of the second control transistor on the substrate, the projection of the active layer of the first noise reduction transistor on the substrate, and the projection of the active layer of the second noise reduction transistor on the substrate, the gate of the first noise reduction transistor is connected to the first pole of the first control transistor and the first pole of the second control transistor through the intermediate transfer electrode, the input circuit includes an input transistor, and the input transistor and the first noise reduction transistor are sequentially arranged in the first direction, and the imaginary line along which the active layer of the first noise reduction transistor extends in the second direction does not intersect the imaginary line along which the active layer of the input transistor extends in the second direction.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the gate of the first noise reduction transistor is parallel to the gate of the second noise reduction transistor, and the extending direction of the trace where the gate of the first noise reduction transistor is located is not parallel to the extending direction of the trace where the gate of the second noise reduction transistor is located.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, the display substrate further includes a first transfer electrode and a voltage stabilizing transistor, wherein the first transfer electrode includes a broken line located between the first control transistor, the second control transistor, the voltage stabilizing transistor, the first noise reduction transistor, and the second noise reduction transistor and bent and extending along a first direction.

[0009] For example, in the display substrate provided by at least one embodiment of the present disclosure, the extension length of the first transfer electrode in the first direction is greater than the extension length in the second direction.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the length of the first transfer electrode is greater than the width in the second direction.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, the active layer of the second control transistor is located on an imaginary line extending along the second direction of the active layer of the input transistor.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, the active layer of the first control transistor and the active layer of the second control transistor do not overlap in the first direction.

[0013] For example, in the display substrate provided by at least one embodiment of the present disclosure, the arrangement and position of the input transistor, the first noise reduction transistor, and the second noise reduction transistor are structures arranged vertically along the first direction.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, the shift register unit further includes a first insulating layer, a second insulating layer, a third insulating layer, and a second connection trace. The first insulating layer is located between the active layer of the first noise reduction transistor and the gate of the first noise reduction transistor in a direction perpendicular to the substrate; the second insulating layer is located between the gate of the first noise reduction transistor and the intermediate transfer electrode in a direction perpendicular to the substrate; the third insulating layer is located between the intermediate transfer electrode and the second connection trace in a direction perpendicular to the substrate, and the second connection trace includes a first sub-connection trace and a second sub-connection trace; the gate of the first noise reduction transistor is connected to the first sub-connection trace through a via hole penetrating the second insulating layer and the third insulating layer, the first end of the intermediate transfer electrode is connected to the first sub-connection trace through a via hole penetrating the third insulating layer, the first pole of the first control transistor and the first pole of the second control transistor are connected to the second sub-connection trace and are located on the same layer, and the second end of the intermediate transfer electrode is connected to the second sub-connection trace through a via hole penetrating the third insulating layer to connect the gate of the first noise reduction transistor to the first electrode of the first control transistor.

[0015] For example, in the display substrate provided by at least one embodiment of the present disclosure, the display substrate further includes a reference voltage line, a first power supply line, and a second power supply line, wherein the line width of the reference voltage line is greater than the line widths of the first power supply line and the second power supply line.

[0016] At least one embodiment of the present disclosure provides a display substrate, including: a substrate substrate, and a shift register unit, a first clock signal line, and a second clock signal line disposed on the substrate substrate. The first clock signal line extends along a first direction on the substrate substrate and is configured to provide a first clock signal to the shift register unit; the second clock signal line extends along the first direction on the substrate substrate and is configured to provide a second clock signal to the shift register unit; the shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and an output control circuit; the input circuit is configured to input an input signal to a first node in response to the first clock signal; the output circuit is configured to output an output signal to an output terminal; the first control circuit is configured to control the level of a second node in response to the level of the first node and the first clock signal; the second control circuit is connected to the first node and the second node and is configured to control the level of the first node under the control of the level of the second node and the second clock signal; the output control circuit is configured to control the level of the output terminal under the control of the level of the second node. The first control circuit includes a first control transistor and a second control transistor, the second control circuit includes a first noise reduction transistor and a second noise reduction transistor, the shift register unit further includes an intermediate transfer electrode, the active layers of the first control transistor and the second control transistor and the active layers of the first noise reduction transistor and the second noise reduction transistor are arranged side by side in a second direction different from the first direction, a part of the positive projection of the intermediate transfer electrode on the substrate substrate includes the positive projection of the active layer of the first control transistor on the substrate substrate, the positive projection of the active layer of the second control transistor on the substrate substrate, the positive projection of the active layer of the first noise reduction transistor on the substrate substrate, and the positive projection of the active layer of the second noise reduction transistor on the substrate substrate, the gate of the first noise reduction transistor is connected to the first pole of the first control transistor and the first pole of the second control transistor through the intermediate transfer electrode, and the line widths of the first clock signal line and the second clock signal line are 9 microns or more.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, the shift register unit further includes a voltage stabilizing circuit, the voltage stabilizing circuit is connected to the first node and the third node, and is configured to stabilize the level of the third node; the output circuit is connected to the third node, and is configured to output the output signal to the output terminal under the control of the level of the third node. The display substrate further includes a first power supply line and a second power supply line, which are configured to provide a first voltage and a second voltage to the shift register unit. The voltage stabilizing circuit includes a voltage stabilizing transistor. The second power supply line includes a protruding portion protruding in the second direction. The positive projection of the active layer of the voltage stabilizing transistor on the substrate is located between the positive projection of the active layer of the second control transistor on the substrate in the first direction and the positive projection of the active layer of the second noise reduction transistor on the substrate in the first direction. And the second pole of the second control transistor is connected to the protruding portion on the second power supply line to receive the second voltage. The first pole of the voltage stabilizing transistor is connected to the third node, the second pole of the voltage stabilizing transistor is connected to the first node, and the distance between any two of the first clock signal line, the second clock signal line, the first power supply line and the second power supply line is greater than 3 micrometers.

[0018] For example, in the display substrate provided by at least one embodiment of the present disclosure, the output control circuit includes an output control transistor and a first capacitor, the output circuit includes an output transistor and a second capacitor. The active layer of the output control transistor includes the upper part of the first output semiconductor layer and the second output semiconductor layer in the first direction. Notches are respectively provided on the left and right sides of the active layer of the output control transistor in the first direction. The active layer of the output control transistor includes the lower part of the second output semiconductor layer and the second output semiconductor layer in the first direction.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the input circuit includes an input transistor. The first pole of the input transistor is connected through a first connection trace extending in the second direction to receive the input signal. The first pole and the second pole of the first capacitor include notches on the side far from the display area.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the source region or the drain region of the first noise reduction transistor has a curved or bent shape.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the active layers of the first noise reduction transistor and the second noise reduction transistor are formed by a continuous noise reduction semiconductor layer. Description of the Drawings

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present invention and do not limit the present invention.

[0023] Figure 1A It is a schematic diagram of the overall circuit architecture of a display panel;

[0024] Figure 1B It is a circuit diagram of a shift register unit;

[0025] Figure 1C It is Figure 1B The signal timing diagram when the shift register unit shown works;

[0026] Figure 1D It is Figure 1B The layout schematic diagram of the shift register unit shown on the display substrate in ;

[0027] Figure 2A It is a layout schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0028] Figure 2B It is another layout schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0029] Figure 3A and Figure 4A and Figure 5A and Figure 6A respectively show Figure 2A The plan views of the respective layer wirings of the shift register unit of the display substrate shown in ;

[0030] Figure 3B and Figure 4B and Figure 5B and Figure 6B respectively show Figure 2B The plan views of the respective layer wirings of the shift register unit of the display substrate shown in ;

[0031] Figure 5C It is Figure 2A The plan view of the vias between the respective layer wirings of the shift register unit of the display substrate shown;

[0032] Figure 5D It is Figure 2B The plan view of the vias between the respective layer wirings of the shift register unit of the display substrate shown;

[0033] Figure 7A It is Figure 2A The cross-sectional view of an example of the display substrate shown;

[0034] Figure 7B It isFigure 2A Cross-sectional views of some examples of the shown display substrate along the A-A` direction;

[0035] Figure 7C is Figure 2B Cross-sectional views of some examples of the shown display substrate along the B-B` direction;

[0036] Figure 7D is Figure 2A Cross-sectional views of some examples of the shown display substrate along the C-C` direction;

[0037] Figure 7E is Figure 2B Cross-sectional views of some examples of the shown display substrate along the D-D` direction;

[0038] Figure 8 Schematic diagram of a display device provided by at least one embodiment of the present disclosure; and

[0039] Figure 9 Flowchart of a method for manufacturing a display substrate provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0041] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention belongs. The "first", "second", and similar terms used in this disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, terms such as "a", "one", or "the" do not denote a quantity limitation, but mean that there is at least one. The terms "including" or "comprising" and the like mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] The present disclosure will be described below through several specific embodiments. To keep the following description of the embodiments of the present invention clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present invention appears in more than one drawing, the component is denoted by the same reference numeral in each drawing.

[0043] Figure 1A It is a schematic diagram of the overall circuit architecture of a display panel. For example, as Figure 1A shown, 101 represents the overall outer frame line of the display panel; the display panel includes an effective display area (i.e., a pixel array area) 102 and a peripheral area located around the effective display area 102. The effective display area includes pixel units 103 arranged in an array; the peripheral area includes a shift register unit 104, and multiple cascaded shift register units 104 form a gate driving circuit for providing, for example, a gate scanning signal that shifts row by row to the pixel units 103 arranged in an array in the effective display area 102 of the display panel 101; the peripheral area further includes a light emission control unit 105, and multiple cascaded light emission control units 105 form a light emission control array for providing, for example, a light emission control signal that shifts row by row to the pixel units 103 arranged in an array in the effective display area 102 of the display panel 101.

[0044] As Figure 1A shown, data lines D1 - DN (N is an integer greater than 1) connected to a data driving chip IC longitudinally pass through the effective display area 102 to provide data signals for the pixel units 103 arranged in an array; gate lines G1 - GM (M is an integer greater than 1) connected to the shift register unit 104 and the light emission control unit 105 cross the effective display area 102 to provide a gate scanning signal and a light emission control signal for the pixel units arranged in an array. For example, each pixel unit 103 may include a pixel circuit and a light emitting element having a circuit structure such as 7T1C, 8T2C, or 4T1C in the art. The pixel circuit operates under the control of the data signal transmitted through the data line and the gate scanning signal and the light emission control signal transmitted through the gate line to drive the light emitting element to emit light so as to implement operations such as display. The light emitting element may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).

[0045] Figure 1B It is a circuit structure diagram of a shift register unit. Figure 1C It is Figure 1B the signal timing diagram when the shift register unit shown works. The working process of the shift register unit will be briefly introduced below with reference to Figure 1B and Figure 1C

[0046] As Figure 1B ​As shown, the shift register unit 104 includes eight transistors (input transistor T1, first control transistor T2, second control transistor T3, output control transistor T4, output transistor T5, first noise reduction transistor T6, second noise reduction transistor T7, and voltage stabilizing transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). For example, when multiple shift register units 104 are cascaded, the first pole of the input transistor T1 in the first-stage shift register unit 104 is connected to the input terminal IN, and the input terminal IN is configured to be connected to the trigger signal line GSTV to receive a trigger signal as an input signal. The first pole of the input transistor T1 in other stages of the shift register unit 104 is electrically connected to the output terminal of the previous-stage shift register unit 104 to receive the output signal output from the output terminal GOUT of the previous-stage shift register unit 104 as an input signal, thereby realizing a shift output for, for example, performing a line-by-line scan on the pixel unit array in the active display area.

[0047] In addition, as Figure 1B shown, the shift register unit further includes a first clock signal terminal CK and a second clock signal terminal CB. GCK represents the first sub-clock signal line, and GCB represents the second sub-clock signal line. For example, when the first clock signal terminal CK is connected to the first sub-clock signal line GCK to receive the first clock signal, the first sub-clock signal line GCK is the first clock signal line. When the first clock signal terminal CK is connected to the second sub-clock signal line GCB to receive the first clock signal, the second sub-clock signal line GCB is the first clock signal line, which can be determined according to specific circumstances, and the embodiments of the present disclosure do not limit this. The second clock signal terminal CB is connected to the second sub-clock signal line GCB or the first sub-clock signal line GCK to receive the second clock signal. Hereinafter, an example will be introduced in which the first clock signal terminal CK is connected to the first sub-clock signal line GCK to receive the first clock signal, and the second clock signal terminal CB is connected to the second sub-clock signal line GCB to receive the second clock signal, that is, the first sub-clock signal line GCK is used as the first clock signal line and the second sub-clock signal line GCB is used as the second clock signal line. The embodiments of the present disclosure do not limit this. For example, the first clock signal GCK and the second clock signal GCB may adopt pulse signals with a duty cycle greater than 50%, and the two, for example, differ by half a cycle; VGH represents the first power supply line and the first voltage provided by the first power supply line. For example, the first voltage is a DC high level. VGL represents the second power supply line and the second voltage provided by the second power supply line. For example, the second voltage is a DC low level, and the first voltage is greater than the second voltage;

[0048] N1, N2, and N3 respectively represent the first node, the second node, and the third node in the circuit schematic diagram.

[0049] As Figure 1BAs shown, the gate of the input transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first sub-clock signal line GCK) to receive the first clock signal. The second pole of the input transistor T1 is connected to the input terminal IN, and the first pole of the input transistor T1 is connected to the first node N1. For example, when the shift register unit is the first-stage shift register unit, the input terminal IN is connected to the trigger signal line GSTV to receive the trigger signal. When the shift register unit is other than the first-stage shift register unit, the input terminal IN is connected to the output terminal GOUT of its upper-stage shift register unit.

[0050] The gate of the first control transistor T2 is connected to the first node N1. The second pole of the first control transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal. The first pole of the first control transistor T2 is connected to the second node N2.

[0051] The gate of the second control transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal. The second pole of the second control transistor T3 is connected to the second power supply line VGL to receive the second voltage. The first pole of the second control transistor T3 is connected to the second node N2.

[0052] The gate of the output control transistor T4 is connected to the second node N2. The first pole of the output control transistor T4 is connected to the first power supply line VGH to receive the first voltage. The second pole of the output control transistor T4 is connected to the output terminal GOUT.

[0053] The first pole of the first capacitor is connected to the second node N2. The second pole of the first capacitor C1 is connected to the first power supply line VGH.

[0054] The gate of the output transistor T5 is connected to the third node N3. The first pole of the output transistor T5 is connected to the second clock signal terminal CB. The second pole of the output transistor T5 is connected to the output terminal GOUT.

[0055] The first pole of the second capacitor C2 is connected to the third node N3. The second pole of the second capacitor C2 is connected to the output terminal GOUT.

[0056] The gate of the first noise reduction transistor T6 is connected to the second node N2. The first pole of the first noise reduction transistor T6 is connected to the first power supply line VGH to receive the first voltage. The second pole of the first noise reduction transistor T6 is connected to the second pole of the second noise reduction transistor T7.

[0057] The gate of the second noise reduction transistor T7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second sub-clock signal line GCB) to receive the second clock signal. The first pole of the second noise reduction transistor T7 is connected to the first node N1.

[0058] The gate of the voltage stabilizing transistor T8 is connected to the second power supply line VGL to receive the second voltage. The second pole of the voltage stabilizing transistor T8 is connected to the first node N1, and the first pole of the voltage stabilizing transistor T8 is connected to the third node N3.

[0059] Figure 1B The transistors in the shift register unit 104 shown are described by taking P-type transistors as an example. That is, each transistor conducts (conducting level) when a low level is applied to the gate and cuts off (cut-off level) when a high level is applied. At this time, the first pole of the transistor can be the source, and the second pole of the transistor can be the drain.

[0060] The shift register unit includes but is not limited to Figure 1B the configuration method. For example, each transistor in the shift register unit 104 can also use N-type transistors or a combination of P-type transistors and N-type transistors, as long as the port polarities of the selected type of transistors are connected according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0061] It should be noted that the transistors used in the shift register unit can all be thin film transistors, field effect transistors, or other switching devices with the same characteristics. Here, thin film transistors are taken as an example for description. For example, the active layer (channel region) of the transistor uses a semiconductor material, such as polysilicon (such as low-temperature polysilicon or high-temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. use a metal material, such as aluminum or aluminum alloy. The source and drain of the transistors used here can be symmetric in structure, so there is no difference between the source and drain in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other as the second pole. In addition, in the embodiments of the present disclosure, the electrodes of the capacitor can use metal electrodes or one of the electrodes uses a semiconductor material (such as doped polysilicon).

[0062] Figure 1C For Figure 1B the signal timing diagram when the shift register unit 104 shown operates. The following combines Figure 1B and Figure 1C to introduce the working process of the shift register in detail. For example, the working principle of the first-stage shift register unit 104 is described. The working principles of the remaining shift register units 104 are similar and will not be elaborated. As Figure 1C shown, the working process of the shift register unit 104 includes 4 stages, namely the first stage t1, the second stage t2, the third stage t3, and the fourth stage t4, Figure 1C which shows the timing waveforms of each signal in each stage.

[0063] In the first stage t1, as Figure 1C shown, the first clock signal terminal CK receives a first clock signal with a low level, the trigger signal line GSTV provides a trigger signal with a low level, so the input transistor T1 and the second control transistor T3 are turned on. The turned-on input transistor T1 transmits the trigger signal with a low level to the first node N1, thereby making the level of the first node N1 become low. Therefore, the first control transistor T2 and the output transistor T5 are turned on. Since the voltage stabilizing transistor T8 is always turned on in response to the second voltage (low level) provided by the second power supply line VGL, the level of the third node N3 is the same as the level of the first node N1, that is, low level. At the same time, this low level is stored in the second capacitor C2. In addition, the turned-on second control transistor T3 transmits the low-level second voltage VGL to the second node N2, and the turned-on first control transistor T2 transmits the low level of the first clock signal to the second node N2, thereby making the level of the second node N2 become low and stored in the first capacitor C1. Therefore, the output control transistor T4 is turned on in response to the low level of the second node N2, and outputs the first voltage with a high level provided by the first power supply line VGH to the output terminal GOUT. At the same time, the output transistor T5 is turned on in response to the low level of the third node N3, and transmits the second clock signal with a high level received by the second clock signal terminal CB to the output terminal GOUT. Thus, in this stage, the shift register unit outputs a high level.

[0064] In the second stage t2, as Figure 1C shown, the second clock signal terminal CB receives a second clock signal with a low level, so the second noise reduction transistor T7 is turned on. The first clock signal terminal CK receives a first clock signal with a high level, so the input transistor T1 and the second control transistor T3 are cut off. Due to the storage effect of the second capacitor C2, the first node N1 can continue to maintain the low level of the previous stage. Therefore, the first control transistor T2 and the output transistor T5 are turned on. Since the first control transistor T2 is turned on, the first clock signal with a high level received by the first clock signal terminal CK is transmitted to the second node N2. Therefore, the second node N2 becomes high level. Therefore, the first noise reduction transistor T6 and the output control transistor T4 are cut off, thereby preventing the high level provided by the first power supply line VGH from being output to the output terminal GOUT and the first node N1. At the same time, since the output transistor T5 is turned on, in this stage, the output terminal GOUT outputs the low level received by the second clock signal terminal GB. For example, this low level is used to control Figure 1A the pixel unit 103 shown in

[0065] In the third stage t3, as Figure 1CAs shown, the first clock signal terminal CK receives the first clock signal with a low level, so the input transistor T1 and the second control transistor T3 are turned on. At this time, the high level provided by the trigger signal line GSTV is transmitted to the first node N1 and the third node N3, so the output transistor T5 and the first control transistor T2 are turned off. The second clock signal terminal CB receives the second clock signal with a high level, so the second noise reduction transistor T7 is turned off. Since the second control transistor T3 is turned on, the low level provided by the second power supply line VGL is transmitted to the second node N2 and stored in the first capacitor C1. Therefore, the output control transistor T4 and the first noise reduction transistor T6 are turned on. So, at this stage, the output terminal GOUT outputs the high level provided by the first power supply line VGH.

[0066] In the fourth stage t4, as Figure 1C shown, the first clock signal terminal CK receives the first clock signal with a high level, so the input transistor T1 and the second control transistor T3 are turned off. The second clock signal terminal CB receives the second clock signal with a low level, so the second noise reduction transistor T7 is turned on. Due to the storage effect of the second capacitor C2, the level of the first node N1 remains the high level of the previous stage, so that the first control transistor T2 and the output transistor T5 are turned off. Due to the storage effect of the first capacitor C1, the second node N2 continues to maintain the low level of the previous stage, so that the first noise reduction transistor T6 is turned on, so that the high level provided by the first power supply line VGH is transmitted to the first node N1 and the third node N3 through the turned-on first noise reduction transistor T6 and the second noise reduction transistor T7, so that the first node N1 and the third node N3 continue to remain high level, effectively preventing the output transistor T5 from being turned on, thus avoiding misoutput.

[0067] Figure 1D is Figure 1B a schematic layout diagram of the shift register unit 104 shown in the display substrate. As Figure 1D shown, the display substrate includes the input transistor T1 to the voltage stabilizing transistor T8 of the shift register unit 104, the first capacitor C1 to the second capacitor C2, and the first sub-clock signal line GCK, the second sub-clock signal line GCB, the first power supply line VGH, and the second power supply line VGL.

[0068] For example, as Figure 1DAs shown, the input transistor T1 includes an active layer in a "U" shape and a straight (I-shaped) gate. The straight gate overlaps with the two arms of the "U"-shaped active layer to form a double-gate transistor, and is horizontally arranged with the first noise reduction transistor T6 and the second noise reduction transistor T7. Thus, this arrangement occupies a relatively large space both in the horizontal and vertical directions of the display panel; the distance between the gate of the voltage stabilizing transistor T8 and the first pole of the second control transistor T3 is relatively far, and they are respectively connected to different positions of the second power supply line VGL, increasing the complexity of the wiring; the node between the first control transistor T2 and the second control transistor T3 is connected to the gate of the first noise reduction transistor T6 through a very long connecting wire, causing space congestion, etc. Therefore, Figure 1D The arrangement and connection of each transistor on the display substrate shown are likely to cause space congestion, which is not conducive to the realization of the narrow border design of the display panel, and is likely to cause problems such as excessive parasitic capacitance due to unnecessary overlap, resulting in signal crosstalk, etc., affecting the display quality of the display panel.

[0069] At least one embodiment of the present disclosure provides a display substrate, including: a substrate substrate, a shift register unit disposed on the substrate substrate, a first clock signal line, and a second clock signal line. The first clock signal line extends along a first direction on the substrate substrate and is configured to provide a first clock signal to the shift register unit; the second clock signal line extends along the first direction on the substrate substrate and is configured to provide a second clock signal to the shift register unit; the shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and an output control circuit; the input circuit is configured to input an input signal to a first node in response to the first clock signal; the output circuit is configured to output an output signal to an output terminal; the first control circuit is configured to control the level of a second node in response to the level of the first node and the first clock signal; the second control circuit is connected to the first node and the second node and is configured to control the level of the first node under the control of the level of the second node and the second clock signal; the output control circuit is configured to control the level of the output terminal under the control of the level of the second node; the first control circuit includes a first control transistor and a second control transistor, the second control circuit includes a first noise reduction transistor and a second noise reduction transistor, the shift register unit further includes an intermediate transfer electrode, the active layers of the first control transistor and the second control transistor and the active layers of the first noise reduction transistor and the second noise reduction transistor are arranged side by side in a second direction different from the first direction, the orthographic projection of the intermediate transfer electrode on the substrate substrate is located between the orthographic projections of the active layers of the first control transistor and the second control transistor on the substrate substrate and the orthographic projections of the active layers of the first noise reduction transistor and the second noise reduction transistor on the substrate substrate, and the gate of the first noise reduction transistor is connected to the first pole of the first control transistor and the first pole of the second control transistor through the intermediate transfer electrode.

[0070] At least one embodiment of the present disclosure further provides a display device corresponding to the above display substrate and a manufacturing method of the display substrate.

[0071] The display substrate provided by the above embodiments of the present disclosure optimizes the circuit connection and structural layout of the shift register unit, compresses the length of the shift register unit in the second direction to a certain extent, is beneficial to realizing the narrow border design of the display panel, and at the same time ensures the display quality of the display panel.

[0072] The embodiments of the present disclosure and some of their examples will be described in detail below with reference to the accompanying drawings.

[0073] At least one embodiment of the present disclosure provides a display substrate. Figure 2A For Figure 1B a layout schematic diagram of the shift register unit 104 shown in

[0074] For example, asFigure 2A As shown, the display substrate 1 includes: a substrate substrate 10, a shift register unit 104 disposed on the substrate substrate 10, a first power supply line VGH, a second power supply line VGL, and a plurality of clock signal lines (for example, the first sub-clock signal line GCK, the second sub-clock signal line GCB, and the trigger signal line GSTV shown in the figure). For example, the first power supply line VGH, the second power supply line VGL, and the plurality of clock signal lines extend along a first direction (for example, Figure 2A the vertical direction shown in the figure) on the substrate substrate 10, and are configured to respectively provide a first voltage, a second voltage, and a plurality of clock signals (for example, the trigger signal, the first clock signal, or the second clock signal described above, etc.) to the shift register unit 104.

[0075] It should be noted that the first power supply line VGH, the second power supply line VGL, and the plurality of clock signal lines may be arranged in parallel along the first direction, or may intersect at a certain angle (for example, less than or equal to 20°), and the embodiments of the present disclosure do not limit this.

[0076] For example, the first power supply line VGH is configured to provide a first voltage to a plurality of cascaded shift register units 104 included in the scan driving circuit, and the second power supply line VGL is configured to provide a second voltage to a plurality of cascaded shift register units 104 included in the scan driving circuit. For example, the first voltage is greater than the second voltage. For example, the first voltage is a DC high level, and the second voltage is a DC low level.

[0077] For example, the substrate substrate 10 may be made of, for example, glass, plastic, quartz, or other suitable materials, and the embodiments of the present disclosure do not limit this.

[0078] For example, the display substrate 1 includes a pixel array region (i.e., Figure 1A the effective display region 102 shown in the figure, hereinafter referred to as the pixel array region 102) and a peripheral region other than the pixel array region. For example, the above-mentioned first power supply line VGH, second power supply line VGL, plurality of clock signal lines, and shift register unit 104 are located in the peripheral region and on one side of the substrate substrate 10 (as Figure 1A shown in the figure, located between the pixel array region 102 and the side edge of the substrate substrate), for example, as Figure 1A shown in the figure, located on the left side of the substrate substrate. Of course, it may also be located on the right side or both the left and right sides of the substrate substrate 10, and the embodiments of the present disclosure do not limit this.

[0079] For example, the second power supply line VGL and the plurality of clock signal lines are located on the side of the shift register unit 104 away from the pixel array region 102. For example, they are both located on Figure 2AOn the left side of the shift register unit 104 shown, that is, the orthographic projection of the shift register unit 104 on the substrate 10 is located between the second power supply line VGL and the orthographic projections of multiple clock signal lines on the substrate 10 and the pixel array region 102; for example, the first power supply line VGH is located on the side of the shift register unit 104 close to the pixel array region 102, that is, the orthographic projection of the first power supply line VGH on the substrate 10 is located between the orthographic projection of the shift register unit 104 on the substrate 10 and the pixel array region 102.

[0080] It should be noted that the above-mentioned wiring positions are only exemplary, as long as the wiring settings facilitate the connection with the shift register unit, and the embodiments of the present disclosure are not limited thereto.

[0081] For example, the pixel array region 102 includes a plurality of pixel units 103 arranged in an array. For example, each of the plurality of pixel units 103 includes a pixel circuit, and may further include a light-emitting element (not shown in the figure).

[0082] For example, a plurality of cascaded shift register units 104 form a gate driving circuit. For example, the output terminals GOUT of the plurality of shift register units 104 are respectively connected to the gate scan signal terminals of the pixel circuits in each row located in the pixel array region to provide output signals (for example, gate scan signals) to the pixel circuits in each row, so as to realize driving the light-emitting element to emit light. For example, the pixel circuit can be a pixel circuit in the art, such as a pixel circuit including circuit structures such as 7T1C, 2T1C, 4T2C, 8T2C, etc., which will not be elaborated here.

[0083] Figure 2A Only the first-stage shift register unit 104 and the second-stage shift register unit 104 in the gate driving circuit are shown in the figure. For example, as Figure 2A shown, the first clock terminal CK of the first-stage shift register unit 104 (as Figure 1Bis connected to the second sub-clock signal line GCB to receive the first clock signal, the second clock signal terminal CB of the first-stage shift register unit 104 is connected to the first clock signal GCK to receive the second clock signal, the first clock signal terminal CK of the second-stage shift register unit is connected to the first sub-clock signal line GCK to receive the first clock signal, the second clock signal terminal CB of the second-stage shift register unit is connected to the second sub-clock signal line GCB to receive the second clock signal, and so on. The first clock terminal CK of the Xth (X is an odd number greater than 1) stage shift register unit 104 is connected to the second sub-clock signal line GCB to receive the first clock signal, the second clock signal terminal CB of the Xth stage shift register unit 104 is connected to the first clock signal GCK to receive the second clock signal, the first clock signal terminal CK of the (X + 1)th stage shift register unit is connected to the first sub-clock signal line GCK to receive the first clock signal, and the second clock signal terminal CB of the (X + 1)th stage shift register unit is connected to the second sub-clock signal line GCB to receive the second clock signal. It should be noted that the connection manner between each stage of the shift register unit and the clock signal line can also adopt other connection manners in the art, and the embodiments of the present disclosure do not limit this. For example, the input terminal of the first-stage shift register unit 104 is connected to the trigger signal line GSTV to receive the trigger signal as the input signal, the input terminal of the second-stage shift register unit 104 is connected to the output terminal GOUT of the previous stage shift register unit (i.e., the first-stage shift register unit), and the connection manners of the remaining stages of the shift register unit are similar. Hereinafter, the structure of the first-stage shift register unit will be taken as an example for illustration, and the embodiments of the present disclosure do not limit this.

[0084] For example, in Figure 2A the example shown, since the first clock terminal CK of the first-stage shift register unit 104 (as Figure 1B shown) is connected to the second sub-clock signal line GCB to receive the first clock signal, and the second clock signal terminal CB of the first-stage shift register unit 104 is connected to the first clock signal GCK to receive the second clock signal, in this example, the second sub-clock signal line GCB is taken as the first clock signal line and the first sub-clock signal line GCK is taken as the second clock signal line for illustration, and the embodiments of the present disclosure do not limit this.

[0085] For example, as Figure 1B shown, in some examples, the shift register unit 104 includes an input circuit 1041, an output circuit 1043, a first control circuit 1042, and an output control circuit 1044; in other examples, the shift register unit 104 further includes a second control circuit 1045 and a voltage stabilizing circuit 1046.

[0086] The input circuit 1041 is configured to input an input signal to the first node N1 in response to a first clock signal. For example, the input circuit 1041 is connected to the input terminal IN, the first node N1, and the first clock signal terminal CK, and is configured to conduct under the control of the first clock signal received at the first clock signal terminal CK, connecting the input terminal IN to the first node N1, thereby inputting the input signal to the first node N1. For example, the input circuit 1041 is implemented as the input transistor T1 described above, and the connection manner of the input transistor T1 can refer to the above description and will not be elaborated here.

[0087] The output circuit 1043 is configured to output an output signal to the output terminal GOUT. For example, the output circuit 1043 is connected to the third node N3, the output terminal GOUT, and the second clock signal terminal CB, and is configured to conduct under the control of the level of the third node N3, connecting the second clock signal terminal CB to the output terminal GOUT, thereby outputting a second clock signal at the output terminal GOUT, for example, outputting the low level of the second clock signal. For example, the output circuit 1043 is implemented as the output transistor T5 and the second capacitor C2 described above, and the connection manner of the output transistor T5 and the second capacitor C2 can refer to the above description and will not be elaborated here.

[0088] The first control circuit 1042 is configured to control the level of the second node N2 in response to the level of the first node N1 and the first clock signal. For example, the first control circuit is connected to the first node N1, the second node N2, and the first clock signal terminal CK, and is configured to conduct under the control of the level of the first node N1, connecting the second node N2 to the first clock signal terminal CK, thereby providing the first clock signal provided by the first clock signal terminal CK to the second node N2. For example, the first control circuit 1042 is implemented as the first control transistor T2 and the second control transistor T3 described above, and the connection manner of the first control transistor T2 and the second control transistor T3 can refer to the above description and will not be elaborated here. It should be noted that the first control circuit 1042 is not limited to being connected to the first node N1, and can also be connected to other independent voltage terminals (providing the same voltage as the voltage of the first node N1) or a circuit identical to the input circuit provided separately. The embodiments of the present disclosure do not limit this. The connection of other circuits of the shift register unit is similar and will not be elaborated here.

[0089] The output control circuit 1044 is configured to control the level of the output terminal GOUT under the control of the level of the second node N2. For example, the output control circuit 1044 is connected to the second node N2, the first power supply line VGH, and the output terminal GOUT, and is configured to connect the output terminal GOUT to the first power supply line VGH under the control of the level of the second node N2, so as to output the first voltage provided by the first power supply line VGH to the output terminal GOUT, thereby controlling the output terminal GOUT at a high level, so as to avoid misoutput of the shift register unit during the non-output stage. For example, the output control circuit 1044 is implemented as the output control transistor T4 and the first capacitor C1 described above, and the connection manner of the output control transistor T4 and the first capacitor C1 can refer to the above description and will not be elaborated here.

[0090] The second control circuit 1045 is connected to the first node N1 and the second node N2, and is configured to control the level of the first node N1 under the control of the level of the second node N2 and the second clock signal. The second control circuit 1045 is connected to the first node N1, the second node N2, the first power supply line VGH, and the second clock signal terminal CB, and is configured to conduct under the control of the level of the second node N2 and the second clock signal received by the second clock signal terminal CB, so that the first power supply line VGH is connected to the first node N1, thereby charging the potential of the first node N1 to a high level, so as to avoid the output circuit 1042 from conducting during the non-output stage, thereby avoiding misoutput. For example, the second control circuit 1045 is implemented as the first noise reduction transistor T6 and the second noise reduction transistor T7 described above, and the connection manner of the first noise reduction transistor T6 and the second noise reduction transistor T7 can refer to the above description and will not be elaborated here.

[0091] The voltage stabilizing circuit 1046 is connected to the first node N1 and the third node N3, and is configured to stabilize the level of the third node N3. For example, the voltage stabilizing circuit 1046 is connected to the first node N1, the third node N3, and the second power supply line VGL, and is configured to conduct under the control of the second voltage provided by the second power supply line VGL, so that the first node N1 is connected to the third node N3. For example, the voltage stabilizing circuit 1046 is implemented as the voltage stabilizing transistor T8, and the specific introduction can refer to the above Figure 1B description of the voltage stabilizing transistor T8 and will not be elaborated here.

[0092] For example, the voltage-stabilizing transistor T8 is always in the on state under the control of the second voltage provided by the second power line VGL, so that the third node N3 is connected to the first node N1 through the voltage-stabilizing transistor T8, thereby preventing the level of the third node N3 from leaking through the input transistor T1 connected to the first node N1, the first control transistor T2 and the second noise reduction transistor T7, and at the same time, it can also reduce the stress of the level of the third node N3 on the first control transistor T1, which can help maintain the level of the third node N3, so that the output transistor T5 can be fully turned on in the output stage.

[0093] Figure 3A , Figure 4A , Figure 5A and Figure 6A They are shown respectively Figure 2A The plan view of each layer wiring of the shift register unit of the display substrate is shown; Figure 3B , Figure 4B , Figure 5B and Figure 6B They are shown respectively Figure 2B , which shows a plan view of wiring of each layer of a shift register unit of a display substrate. Figure 3A and Figure 3B A plan view of a semiconductor layer of a display substrate is provided for at least one embodiment of the present disclosure. Figure 4A and Figure 4B A plan view of a first conductive layer of a display substrate is provided for at least one embodiment of the present disclosure. Figure 5A and Figure 5B A plan view of a second conductive layer of a display substrate provided in at least one embodiment of the present disclosure, Figure 6A and Figure 6B A plan view of a third conductive layer of a display substrate provided for at least one embodiment of the present disclosure. Figure 7A for Figure 2A A cross-sectional view of an example of a display substrate is shown; Figure 7B for Figure 2A Another example of a cross-sectional view of a display substrate along the AA' direction is shown; Figure 7C for Figure 2B The shown figure is a cross-sectional view of an example of a display substrate along the BB' direction.

[0094] For example, an interlayer insulating layer (eg, including a first insulating layer, a second insulating layer, a third insulating layer, etc.) may be located Figures 3A to 6A or Figures 3B to 6B For example, the first insulating layer 350 (eg Figure 7A shown) is located at Figure 3A The semiconductor layer 310 and Figure 4A The first conductive layer 320 is shown between or located at Figure 3B The semiconductor layer 310 and Figure 4BBetween the first conductive layers 320 shown, the second insulating layer 360 (as Figure 7A shown) is located Figure 4A between the first conductive layer 320 shown and Figure 5A the second conductive layer 330 shown or Figure 4B between the first conductive layer 320 shown and Figure 5B the second conductive layer 330 shown. The third insulating layer 370 (as Figure 7A shown) is located Figure 5A between the second conductive layer 330 shown and Figure 6A the third conductive layer 340 shown or is located between Figure 5B the second conductive layer 330 shown and Figure 6B the third conductive layer 340 shown.

[0095] For example, as shown in Figure 7A , 7B and 7C, the display substrate further includes a fourth insulating layer 380 that is located on the third conductive layer 340 and is used to protect the third conductive layer 340.

[0096] For example, the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, and the fourth insulating layer 380 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, etc., organic insulating materials such as organic resins, or other suitable materials, and the embodiments of the present disclosure do not limit this.

[0097] It should be noted that Figure 2A the display substrate shown is described by taking the layout design of the first two - stage shift registers in the scan - driving circuit and the first power line, the second power line, and the signal line connected thereto as an example. The layout implementation manners of the remaining stages of shift registers can refer to Figure 2A the layout manner shown therein, which will not be elaborated here. Of course, other layout manners can also be adopted, and the embodiments of the present disclosure do not limit this. Of course, the shift registers of each stage of the remaining scan - driving circuits can also refer to Figure 2A the layout manner shown therein, and other layout implementation manners can also be adopted, and the embodiments of the present disclosure do not limit this.

[0098] Next, the display substrate provided by at least one embodiment of the present disclosure will be introduced in detail with reference to Figures 2A - 7C .

[0099] For example, Figure 2A the active layers of the input transistor T1 to the voltage - stabilizing transistor T8 of the shift - register unit 104 shown in Figure 3A can be formed on the semiconductor layer 310 shown. Figure 2BThe active layers of the input transistors T1 to the voltage stabilizing transistors T8 of the shift register unit 104 shown in can be formed on Figure 3B the semiconductor layer 310 shown. The semiconductor layer 310 can be formed by patterning a semiconductor material. For example, as Figure 3A and Figure 3B shown, as required, the semiconductor layer 310 can be in the shape of short rods or have a curved or bent shape, and can be used to fabricate the active layers of the above input transistors T1 to the voltage stabilizing transistors T8. Each active layer can include a source region, a drain region, and a channel region located between the source region and the drain region. For example, the channel region has semiconductor characteristics; the source region and the drain region are on both sides of the channel region and can be doped with impurities and thus have conductivity. For example, the source region is a part of the active layer, and the metal electrode in contact with the source region (for example, located in the third conductive layer 340) corresponds to the source (or called the first pole) of the transistor, and the drain region is a part of the active layer, and the metal electrode in contact with the drain region (for example, located in the third conductive layer 340) corresponds to the drain (or called the second pole) of the transistor. For example, the source region is connected to its corresponding metal electrode (the first pole) through a via hole penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370, and the drain region is connected to its corresponding metal electrode (the second pole) through a via hole penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0100] For example, as Figure 7A shown, taking the first control transistor T2 as an example, the active layer of the first control transistor T2 includes a source region S2, a drain region D2, and a channel region P2. The first control transistor T2 further includes a gate G2, where the gate G2 is located in the first conductive layer 320; taking the first noise reduction transistor T6 as an example, the active layer of the first noise reduction transistor T6 includes a source region S6, a drain region D6, and a channel region P6. The first noise reduction transistor T6 further includes a gate G6, where the gate G6 is located in the first conductive layer 320. The other transistors are similar and will not be described in detail here.

[0101] For example, the material of the semiconductor layer 310 can include oxide semiconductors, organic semiconductors, or amorphous silicon, polysilicon, etc. For example, oxide semiconductors include metal oxide semiconductors (such as indium gallium zinc oxide (IGZO)), and polysilicon includes low-temperature polysilicon or high-temperature polysilicon, etc. The embodiments of the present disclosure do not limit this. It should be noted that the above source region and drain region can be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure do not limit this.

[0102] It should be noted that in other examples, the first electrode and the second electrode of each transistor may also be located in other conductive layers, and connected to the corresponding active layer through vias in the insulating layer between the transistor and the semiconductor layer. The embodiments of the present disclosure are not limited to this.

[0103] Figure 4A and Figure 4B The first conductive layer 320 of the display substrate is shown, and the first conductive layer 320 is disposed on the first insulating layer, thereby being insulated from the semiconductor layer 310. For example, the first conductive layer 320 may include first electrodes CE11 and CE12 of the first capacitor C1 to the second capacitor C2, and gates of the input transistor T1 to the voltage-stabilizing transistor T8 and various wires directly connected to the gates (for example, the first connecting wire L1 and the third connecting wire L2), and connecting electrodes, and the first insulating layer also serves as a gate insulating layer. Figure 4A As shown, the gates of the input transistor T1 to the voltage-stabilizing transistor T8 are the parts enclosed by dashed lines, that is, the parts where the semiconductor layer structures of each transistor overlap with the wiring on the first conductive layer 320 .

[0104] like Figure 4B As shown, the first conductive layer 320 may further include an intermediate transfer electrode 11. For example, in this example, the intermediate transfer electrode 11 is formed integrally with the gate G6 of the first noise reduction transistor T6. For example, in this example, the first connection line L1 may not be located at Figure 4B The first conductive layer 320 shown, for example, is located Figure 6B The third conductive layer 340 shown is not limited in the embodiments of the present disclosure, as long as it can achieve connection between transistors.

[0105] Figure 5A and Figure 5B The second conductive layer 330 of the display substrate is shown, and the second conductive layer 330 includes second electrodes CE21 and CE22 of the first capacitor C1 to the second capacitor C2. The second electrode CE21 at least partially overlaps with the first electrode CE11 to form the first capacitor C1, and the second electrode CE22 at least partially overlaps with the first electrode CE12 to form the second capacitor C2. For example, Figure 5A The second conductive layer 330 shown in FIG. 3 further includes an intermediate switching electrode 11 .

[0106] For example, Figure 5B The example shown is similar to Figure 5A The example shown is similar to the one shown in the figure, except that the second conductive layer 330 does not include the intermediate switching electrode 11, that is, Figure 2B In the display substrate shown in FIG. 1 , the intermediate transfer electrode 11 may not be located on the second conductive layer 330 , for example, it may be located on Figure 4B The first conductive layer 320 is shown, but the embodiments of the present disclosure are not limited thereto.

[0107] Figure 6A and Figure 6B shows the third conductive layer 340 of the first-stage shift register unit and the second-stage shift register unit of the display substrate. The third conductive layer 340 includes a plurality of signal lines (for example, the trigger signal line GSTV connected to the input end of the first-stage shift register unit 104, the first sub-clock signal line GCK, and the second sub-clock signal line GCB), the first power supply line VGH, the second power supply line VGL, and the reference voltage line Vinit, etc. It should be noted that the third conductive layer 340 also includes the first transfer electrode 17, the second transfer electrode 18, the third transfer electrode 16, the signal input electrode 13, the second connection trace (including the first connection sub-trace L3 and the second connection sub-trace L4), and the fourth connection trace L5, etc., which connect between each transistor, capacitor, and signal line.

[0108] As Figures 2A to 6B shown, the plurality of signal lines, the first power supply line VGH, and the second power supply line VGL are connected to the transistors and capacitors that need to be connected to them in the remaining layers through Figure 5C or Figure 5D shown at least one via. The transistors and capacitors are also connected through at least one via or bridged through the transfer electrode, which will not be elaborated here.

[0109] For example, the material of the above-mentioned third conductive layer 340 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, and the embodiments of the present disclosure do not limit this. For example, the materials of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, which will not be elaborated here.

[0110] Figure 2A For the above Figure 3A shown semiconductor layer 310, Figure 4A shown first conductive layer 320, Figure 5A shown second conductive layer 330, and Figure 6A shown third conductive layer 340, it is a schematic diagram of the stacked position relationship. Figure 2B For the above Figure 3B shown semiconductor layer 310, Figure 4B shown first conductive layer 320, Figure 5B shown second conductive layer 330, and Figure 6B shown third conductive layer 340, it is a schematic diagram of the stacked position relationship.

[0111] As Figure 2A , Figure 3A or Figure 2B , Figure 3BAs shown, in at least one example, the active layer of the input transistor T1 is a long strip extending in the second direction, and the second direction is different from the first direction. For example, the included angle between the first direction and the second direction is between 70° and 90°, including 70° and 90°. For example, the included angle between the first direction and the second direction is 70°, 90°, 80°, etc., which can be set according to actual situations, and the embodiments of the present disclosure do not limit this. For example, in some examples, the channel region of the active layer of the input transistor T1 is in an "I" shape on the substrate 10, and the channel length direction of the channel region is the second direction perpendicular to the first direction (for example, the horizontal direction in the figure). Of course, the embodiments of the present disclosure do not limit this, as long as it can shorten the length of the display panel in the first direction. For example, the channel length direction is the direction in which carriers flow from the first pole to the second pole of the input transistor T1; two juxtaposed (and, for example, electrically connected to each other) gates overlap with the long strip-shaped active layer ("I"-shaped active layer) of the input transistor T1 respectively, thereby obtaining an "I"-shaped double-gate transistor. Of course, it can also be a single gate overlapping with the long strip-shaped active layer of the input transistor T1, and the embodiments of the present disclosure do not limit this.

[0112] Since the active layer of the input transistor T1 (it should be noted that here it refers to the overall shape of the active layer of the input transistor T1) is changed from the Figure 1D "U"-shaped structure shown to a long strip extending in the second direction (for example, an "I"-shaped structure along the second direction, for example, a "one"-shaped), the length of the display panel in the first direction, that is, the vertical height of the display panel, can be shortened, which is beneficial for other transistors (for example, the first noise reduction transistor T6 and the second noise reduction transistor T7) to be arranged below the input transistor T1.

[0113] For example, as Figure 3A or Figure 3B shown, the active layer of the first noise reduction transistor T6 and the active layer of the second noise reduction transistor T7 are formed by a continuous noise reduction semiconductor layer A11 (i.e., integrally arranged), and the noise reduction semiconductor layer A11 extends in the first direction and is arranged side by side with the active layer of the input transistor T1 in the first direction, that is, the input transistor T1, the first noise reduction transistor T6, and the second noise reduction transistor T7 are arranged side by side up and down in the first direction. For example, the active layer of the input transistor T1 is located on the imaginary line where the active layers of the first noise reduction transistor T6 and the second noise reduction transistor T7 extend in the first direction.

[0114] For example, as Figure 2A 、 2B and Figure 3A shown, the active layer of the first noise reduction transistor T6 can partially overlap with the active layer of the second noise reduction transistor T7 in the first direction (as Figure 2A andFigure 3A as shown) or completely overlapped (such as Figure 2B and Figure 3B as shown), that is, the active layer of the first noise reduction transistor T6 can be on the imaginary line where the active layer of the second noise reduction transistor T7 extends in the first direction; the active layer of the first noise reduction transistor T6 can also not overlap with the active layer of the second noise reduction transistor T7 in the first direction. For example, as Figure 2A and Figure 3A as shown, the active layer of the first noise reduction transistor T6 can also be offset from the active layer of the second noise reduction transistor T7 by a certain distance in the first direction, as long as it does not affect the arrangement of other structures and does not excessively increase the width of the shift register unit, and as long as the first noise reduction transistor T6 and the second noise reduction transistor T7 are located below the input transistor T1 in the first direction, the embodiments of the present disclosure do not limit this.

[0115] In the embodiments of the present disclosure, the input transistor T1, the first noise reduction transistor T6, and the second noise reduction transistor T7 change from the Figure 1D horizontally juxtaposed structure in Figure 1A to a vertically arranged structure, which can reduce the width of the peripheral area of the display panel in the second direction. For example,

[0116] the horizontal width as shown, which is beneficial to the realization of the narrow border design of the display panel.

[0117] For example, the first pole of the input transistor T1, the gate of the first control transistor T2, the first pole of the second noise reduction transistor T7, and the second pole of the voltage stabilizing transistor T8 described below are all connected to the first node N1. For example, the first pole of the input transistor T1, the gate of the first control transistor T2, and the first pole of the second noise reduction transistor T7 are connected through vias. The second node N2 is connected to the gate of the first noise reduction transistor T6, the gate of the output control transistor T4, the first pole of the first control transistor T2, the first pole of the first capacitor C1, and the first pole of the second control transistor T3. For example, as Figure 2AAs shown, the gate of the first noise reduction transistor T6, the gate of the output control transistor T4, the first pole of the first control transistor T2, the first pole of the first capacitor C1, and the first pole of the second control transistor T3 are connected through vias. The third node N3 is connected to the first pole of the voltage stabilizing transistor T8, the gate of the output transistor T5, and the first pole of the second capacitor C2. For example, the first pole of the voltage stabilizing transistor T8, the gate of the output transistor T5, and the first pole of the second capacitor C2 are connected through vias.

[0118] For example, as Figure 6A shown, the shift register unit further includes a first transfer electrode 17, a second transfer electrode 18, and a third transfer electrode 16.

[0119] For example, the first transfer electrode 17 is connected to the first pole of the input transistor T1, the gate of the first control transistor T2, the second pole of the voltage stabilizing transistor T8, and the first pole of the second noise reduction transistor T7. For example, the first transfer electrode 17 is connected to the gate of the first control transistor T2 through a via penetrating the second insulating layer 360 and the third insulating layer 370. The first transfer electrode 17, the first pole of the input transistor T1, the second pole of the voltage stabilizing transistor T8, and the first pole of the second noise reduction transistor T7 are located on the same layer (for example, all on the third conductive layer 340) and are integrally provided. For example, the first node N1 includes the first transfer electrode 17, that is, the first transfer electrode 17 serves as the first node N1, connecting the corresponding electrodes of the input transistor T1, the first control transistor T2, the voltage stabilizing transistor T8, and the second noise reduction transistor T7.

[0120] For example, the first transfer electrode 17 is a broken line located between the first control transistor T2, the second control transistor T3, the voltage stabilizing transistor T8, the first noise reduction transistor T6, and the second noise reduction transistor T7 and bent and extending along the first direction. Its starting point is the first pole of the input transistor T1, and the end point is the first pole of the second noise reduction transistor T7. Since the first noise reduction transistor T6 and the second noise reduction transistor T7 are arranged side by side with the input transistor T1 along the first direction, and the first control transistor T2 and the second control transistor T3 are also arranged side by side along the first direction, that is, the distance between the first noise reduction transistor T6 and the second noise reduction transistor T7 and the first control transistor T2 and the second control transistor T3 is small, making the extension length of the first transfer electrode 17 in the first direction greater than the extension length in the second direction. Therefore, the length of the first transfer electrode 17 connecting these transistors and the width in the second direction are shortened, which is beneficial to realizing a narrow border.

[0121] For example, the second transfer electrode 18 is connected to the first pole of the voltage stabilizing transistor T8 and the gate of the output transistor T5. For example, the second transfer electrode 18 is connected to the gate of the output transistor T5 through a via hole penetrating the second insulating layer 360 and the third insulating layer 370. The second transfer electrode 18 and the first pole of the voltage stabilizing transistor T8 are located on the same layer (for example, both are located on the third conductive layer 340) and are integrally provided. For example, the third node N3 includes the second transfer electrode 18, that is, the second transfer electrode 18 serves as the third node N3, connecting the voltage stabilizing transistor T8 and the output transistor T5.

[0122] For example, as Figure 4A shown, the input transistor T1 includes a first gate G1, a second gate G1`, and connection electrodes (G11 - G13) connecting the first gate G1 and the second gate G1`. The connection electrodes (G11 - G13) are located on the same layer as the first gate G1 and the second gate G1`, and include a first part G11 extending along a first direction (for example, the vertical direction as Figure 4A shown) and connected to the first gate G1, a second part G12 connected to the second gate G1`, and a third part G13 extending along a second direction (for example, the horizontal direction as Figure 4A shown) and connecting the first part G11 and the second part G12. The first gate G1 and the second gate G1` of the input transistor T1 are connected to the first clock signal line providing the first clock signal through the third part G13 of the connection electrode to receive the first clock signal.

[0123] For example, the first gate G1 and the second gate G1` are first connected together through the connection electrodes (G11 - G13), and then connected to the first clock signal line. For example, it is also possible to connect the gate of the input transistor T1 and the gate of the second control transistor T3 together and then connect them to the first clock signal line as a whole. For example, the connection method shown in Figure 1D is adopted, and the embodiments of the present disclosure are not limited thereto.

[0124] For example, as Figure 2A shown, for the first - stage shift register unit, the first clock signal line providing the first clock signal is the second sub - clock signal line GCB, and for the second - stage shift register unit, the first clock signal line of the first clock signal is the first sub - clock signal line GCK. The embodiments of the present disclosure are not limited thereto.

[0125] For example, in some examples, the second pole of the active layer of the first control transistor T2 can be directly connected to the second sub - clock signal line GCB through a trace. For example, as Figure 6AAs shown, in some other examples, the shift register unit further includes a transfer electrode 15. In this example, the second pole of the first control transistor T2 is not directly connected to the second sub-clock signal line GCB through a trace, but can also be connected to the third part G13 of the connection electrode through the transfer electrode 15, so as to be connected to the second sub-clock signal line GCB simultaneously with the third part G13 of the connection electrode to receive the first clock signal. The embodiments of the present disclosure do not limit this.

[0126] For example, the active layer of the input transistor T1 is connected to the signal input electrode through a first connection trace L1 extending in the second direction to receive an input signal; this signal input electrode serves as the input terminal IN of the shift register unit 104, for example, it is the signal input electrode 13 located in the Figure 6A third conductive layer as shown. For example, the signal input electrode 13 can be a separately provided electrode. For example, as shown in the third conductive layer of the first-stage shift register unit Figure 6A shown, it can also be an extended area of the second pole of the output transistor T5 (the second pole of the output transistor T5 serves as the output terminal GOUT of the output circuit 1043) as the signal input electrode 13. For example, the second pole of the output transistor T5 of the current-stage shift register unit (that is, the metal electrode connected to the drain region of the active layer of the output transistor T5) serves as the output terminal GOUT of the output circuit 1043, and is connected to the signal input electrode of the lower-stage shift register unit (for example, the second-stage shift register unit) adjacent to the shift register unit (for example, the first-stage shift register unit) to serve as the input signal of the lower-stage shift register unit. The embodiments of the present disclosure do not limit this.

[0127] For example, as Figure 2A 、 Figure 4A and Figure 6A shown, the shift register unit further includes a trace transfer electrode 12. For example, the trace transfer electrode 12 is located in the third conductive layer 340. For example, the trace transfer electrode 12 and the active layer of the input transistor T1 are located in different layers. For example, the first pole of the input transistor T1 is electrically connected to the first end 121 of the trace transfer electrode 12. For example, the first pole of the input transistor T1 and the trace transfer electrode 12 are located in the same layer and are integrally formed. For example, the source region of the active layer of the input transistor T1 is connected to the first pole of the input transistor T1 through a via hole penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. The second end 122 of the trace transfer electrode 12 is connected to the first connection trace L1 extending in the second direction that is not in the same layer (located in Figure 4AThe first end L11 of the first conductive layer 320 shown is connected through a via hole penetrating the second insulating layer 360 and the third insulating layer 370. The second end L12 of the first connection trace L1 extending in the second direction is electrically connected to the signal input electrode 13 (located in the third conductive layer 340) that is not on the same layer through a via hole penetrating the second insulating layer 360 and the third insulating layer 370, thereby realizing the connection between the input transistor T1 and the input terminal IN. For example, the trace transfer electrode 12 and the signal input electrode 13 are on the same layer.

[0128] For example, as Figure 2B and 6B shown, the first connection trace L1 can also be formed in the third conductive layer 340 and be directly connected to the trace transfer electrode 12 and the signal input electrode 13 (i.e., not connected through a via hole), that is, integrally formed. The embodiments of the present disclosure do not limit this, as long as the connection between the input transistor T1 and the signal input electrode 13 can be realized.

[0129] For example, in some embodiments of the present disclosure, the active layer of the first control transistor T2 and the active layer of the second control transistor T3 are formed by a continuous control semiconductor layer A12 (i.e., integrally arranged). The control semiconductor layer A12 extends in the first direction. The gate of the first control transistor T2 and the gate of the second control transistor T3 extend parallel to each other in the second direction and overlap each other in the first direction, that is, the gate of the first control transistor T2 and the gate of the second control transistor T3 are arranged one above the other in the first direction on the first conductive layer 320. It should be noted that, for the sake of clear and concise description, A11 and A12 are named as different semiconductor layers, but the noise reduction semiconductor layer A11 and the control semiconductor layer A12 are both located in Figure 3A or Figure 3B the same semiconductor layer 330 shown.

[0130] For example, as Figure 2A and Figure 4A shown, the positive projection of the second control transistor T3 on the substrate 10 and the positive projection of the first control transistor T2 on the substrate 10 are located on both sides of the second sub-connection trace L4 in the first direction. Of course, the extending directions of the gate of the first control transistor T2 and the gate of the second control transistor T3 may not be parallel either, for example, intersecting at a certain angle. For example, the intersection angle is less than or equal to 20°, or the angles of both with the horizontal line are less than or equal to 20°. The embodiments of the present disclosure do not limit this.

[0131] For example, as Figure 2A 、 2B and Figure 3A 、 Figure 3B shown, the active layer of the first control transistor T2 can partially overlap with the active layer of the second control transistor T3 in the first direction (asFigure 2A and Figure 3A shown) or completely overlapped (not shown in the figure), that is, the active layer of the first control transistor T2 can be on the imaginary line where the active layer of the second control transistor T3 extends in the first direction; the active layer of the first control transistor T2 can also not overlap with the active layer of the second control transistor T3 in the first direction. For example, as Figure 2A and Figure 3A shown, the active layer of the first control transistor T2 is offset from the active layer of the second control transistor T3 by a certain distance in the first direction, as long as it does not affect the arrangement of other structures and does not excessively increase the width of the shift register unit, and as long as the active layers of the first control transistor T2 and the second control transistor T3 are located below the input transistor T1 in the first direction, the embodiments of the present disclosure do not limit this.

[0132] For example, the active layers of the first control transistor T2, the second control transistor T2, and the input transistor T1 are arranged side by side in the second direction. For example, in some examples, the active layers of the first control transistor T2 and the second control transistor T3 intersect the imaginary line where the active layer of the input transistor T1 extends in the second direction, that is, the active layers of the first control transistor T2 and the second control transistor T3 are on the imaginary line where the active layer of the input transistor T1 extends in the second direction. For example, in the embodiments of the present disclosure, there is no limitation on other transistors in the shift register unit except the first control transistor T2 and the second control transistor T3, as long as the circuit connection relationship can be satisfied.

[0133] Thus, in the embodiments of the present disclosure, the arrangement of the first control transistor T2 and the second control transistor T3 changes from the Figure 1D structure arranged left and right in the second direction shown in the figure to the structure arranged up and down in the first direction, which can reduce the horizontal width of the peripheral area of the display panel and reduce the distance from the transistor to the signal line and the second power supply line, thereby facilitating the realization of the narrow border design of the display panel.

[0134] For example, in some embodiments of the present disclosure, the active layer of the input transistor T1 is also on the imaginary line where the active layers of the first noise reduction transistor T6 and the second noise reduction transistor T7 extend in the first direction, and the active layers of the first control transistor T2 and the second control transistor T3 are arranged side by side relative to the active layers of the first noise reduction transistor T6 and the second noise reduction transistor T7 in the second direction, so as to reduce the distance between the active layers of the first control transistor T2 and the second control transistor T3 and the active layers of the first noise reduction transistor T6 and the second noise reduction transistor T7.

[0135] For example, in some examples, the shift register unit further includes an intermediate transfer electrode 11. The gate of the first noise reduction transistor T6 is connected to the first pole of the first control transistor T2 and the first pole of the second control transistor T3 through the intermediate transfer electrode 11 located in the second conductive layer 330 as shown in Figure 5A and the second connection sub-wiring L4 in Figure 6A , that is, it is connected to the part between the active layer of the first control transistor T2 and the active layer of the second control transistor T3. And the orthographic projection of the intermediate transfer electrode 11 on the substrate 10 does not overlap with the orthographic projections of the active layer of the first control transistor T2 and the active layer of the second control transistor T3 on the substrate 10 in the first direction. That is, the orthographic projection of the intermediate transfer electrode 11 on the substrate 10 is located between the orthographic projections of the active layer of the first control transistor T2 and the active layer of the second control transistor T3 on the substrate 10 and the orthographic projection of the first noise reduction transistor T6 on the substrate 10.

[0136] Thus, in the embodiments of the present disclosure, the arrangement of the first control transistor T2 and the second control transistor T3 changes from the structure arranged left and right along the second direction as shown in Figure 1D to the structure arranged up and down along the first direction as shown in Figure 2A . The arrangement and positions of the input transistor T1, the first noise reduction transistor T6, and the second noise reduction transistor T7 also change to the structure arranged up and down along the first direction, thereby shortening the distance between the orthographic projection of the first noise reduction transistor T6 on the substrate 10 and the orthographic projections of the first control transistor T2 and the second control transistor T3 on the substrate 10, and thus greatly shortening the length of the wiring (i.e., the intermediate transfer electrode 11) connecting the gate of the first noise reduction transistor T6 and the first control transistor T2 and the second control transistor T3, and largely optimizing the problem of space congestion caused by dense and long wiring.

[0137] For example, in some examples, the connection manner of the intermediate transfer electrode 11 is as shown in Figure 7A or Figure 7B . For example, in this example, the intermediate transfer electrode 11 is located in the second conductive layer 11. For example, as shown in Figure 7A , the first insulating layer 350 is located between the active layer of the first noise reduction transistor T6 (for example, located in the semiconductor layer 310, including the source region S6, the drain region D6, and the channel region P6) and the gate G6 of the first noise reduction transistor T6 in the direction perpendicular to the substrate 10; the second insulating layer 360 is located between the gate G6 of the first noise reduction transistor T6 and the intermediate transfer electrode 11 in the direction perpendicular to the substrate 10.

[0138] For example, as shown in Figure 7AAs shown, in some examples, the gate of the first noise reduction transistor T6 is connected to the first end 111 of the intermediate transfer electrode 11 through a via hole H22 penetrating the second insulating layer 360. The first pole S21 of the first control transistor T2 and the intermediate transfer electrode 11 are on the same layer and are connected to the second end 112 of the intermediate transfer electrode 11, that is, the intermediate transfer electrode 11 and the first pole S21 of the first control transistor T2 are integrally arranged, so as to realize the connection between the gate of the first noise reduction transistor T6 and the first pole of the first control transistor T2. The first pole S21 of the first control transistor T2 and the source region S2 of the active layer of the first control transistor T2 (i.e., the first pole of the first control transistor T2) are connected through a via hole H11 penetrating the first insulating layer 350 and the second insulating layer 360. For example, in some examples, the second node N2 includes the intermediate transfer electrode 11. It should be noted that for the sake of clear and concise expression, Figure 7A only the connection between the first pole S21 of the first control transistor T2 and the second end 112 of the intermediate transfer electrode 11 is shown. Since the first pole of the first control transistor T2 and the first pole of the second control transistor T3 are connected, the first pole of the second control transistor T3 is also connected to the second end 112 of the intermediate transfer electrode 11. The embodiments of the present disclosure do not limit this. The same applies to the following embodiments and will not be repeated.

[0139] For example, as Figure 5C and 7B shown, in other examples, the shift register unit 104 further includes a second connection trace. For example, the second connection trace includes a first connection sub-trace L3 and a second connection sub-trace L4. For example, the third insulating layer 370 is located between the intermediate transfer electrode 11 and the second connection trace L3 / L4 in a direction perpendicular to the substrate 10.

[0140] For example, the gate G6 of the first noise reduction transistor T6 is connected to the first connection sub-trace L3 through a via hole H4 penetrating the second insulating layer 360 and the third insulating layer 370, and the first end 111 of the intermediate transfer electrode 11 is connected to the first connection sub-trace L3 through a via hole H3 penetrating the third insulating layer 370.

[0141] For example, the source region S2 of the active layer of the first control transistor T2 is connected to the first pole S21 of the first control transistor T2 through a via hole H1 penetrating the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370. The first pole S21 of the first control transistor T2 is connected to the second connection sub-trace L4. The first pole S21 of the first control transistor T2 is on the same layer and is integrally arranged. The second end of the intermediate transfer electrode 11 is connected to the second connection sub-trace L4 through a via hole H2 penetrating the third insulating layer 370, so as to realize the connection between the gate of the first noise reduction transistor T6 and the first pole of the first control transistor T2.

[0142] For example, in this example, the second node N2 includes an intermediate transfer electrode 11 and a second connection trace.

[0143] For example, in some other examples, the second connection trace only includes a first connection sub-trace L3 or a second connection sub-trace L4. For example, in Figure 2B and 7C the example shown, taking the second connection trace only including the second connection sub-trace L4 as an example for introduction, of course, the embodiments of the present disclosure are not limited thereto.

[0144] For example, as Figure 5C and 7C shown, in this example, the intermediate transfer electrode 11 may be located in the first conductive layer 320 and is integrally formed with the gate of the first noise reduction transistor T6.

[0145] For example, as Figure 7C shown, the source region S2 of the active layer of the first control transistor T2 is connected to the first pole S21 of the first control transistor T2 through a via H1 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. The first pole S21 of the first control transistor T2 is connected to the second connection sub-trace L4. The first pole S21 of the first control transistor T2 and the second connection sub-trace L4 are located on the same layer and are integrally provided. The second end 112 of the intermediate transfer electrode 11 is connected to the second connection sub-trace L4 through a via H2 that penetrates the third insulating layer 370, thereby realizing the connection between the gate of the first noise reduction transistor T6 and the first pole of the first control transistor T2.

[0146] For example, in this example, the second node N2 includes an intermediate transfer electrode 11 and a second connection sub-trace L4.

[0147] For example, as Figure 6A shown, the second power supply line VGL includes a protrusion 14 that protrudes in the second direction. The active layer of the voltage stabilizing transistor T8 is located between the active layer of the second control transistor T3 and the active layer of the second noise reduction transistor T7 in the second direction. The second pole of the second control transistor T3 and the gate of the voltage stabilizing transistor T8 are both connected to the protrusion 14 on the second power supply line VGL. For example, the second pole of the second control transistor T3 and the protrusion 14 on the second power supply line VGL are located on the same layer and are integrally formed. The gate of the voltage stabilizing transistor T8 and the protrusion 14 on the second power supply line VGL that are not on the same layer are connected through a via that penetrates the second insulating layer 360 and the third insulating layer 370 to receive the second voltage. For example, the via for connecting the second pole of the second control transistor T3 and the drain region of the active layer of the second control transistor T3, and the via for connecting the gate of the voltage stabilizing transistor T8 and the protrusion 14, respectively overlap different sides of the protrusion 14 (for example, as Figure 2Arespectively overlap with the upper side and the lower side of the protrusion 14 along the first direction), for example, are respectively located at different diagonals of the protrusion 14 (such as Figure 2A shown and respectively overlap with the upper left corner and the lower right corner of the protrusion 14 along the first direction).

[0148] In an embodiment of the present disclosure, the first control transistor T2 and the second control transistor T3 are changed from Figure 1D the left - right juxtaposed arrangement along the second direction shown to Figure 2A the up - down arranged structure along the first direction shown in, which can reduce the width of the peripheral area of the display panel in the second direction, thereby shortening the distance between other transistors (for example, the voltage - stabilizing transistor T8) and the second power line VGL. At the same time, since the second pole (for example, the source) of the second control transistor T3 and the gate of the voltage - stabilizing transistor T8 are commonly connected to the protrusion 14 on the second power line VGL, they are closer in space, thus reducing the wiring length, which is beneficial to the realization of the narrow border of the display panel.

[0149] For example, as Figure 2A and Figure 5A shown, the first pole CE11 and the second pole CE12 of the first capacitor C1 include notches, and the signal input electrode 13 connected to the first connection trace L1 extending along the second direction is formed in the notch of the first capacitor C1. For example, the orthographic projection of the signal input electrode 13 on the substrate falls into the notch of the orthographic projection of the first capacitor C1 on the substrate, so that the shapes of the first pole CE11 and the second pole CE12 of the first capacitor C1 are complementary to the signal input electrode 13, making full use of the space on the display substrate, which is beneficial to the realization of the narrow - border design of the display panel.

[0150] It should be noted that although the shape of the capacitance of the first capacitor C1 has changed, the size of the first capacitor C1 generally does not change. For example, the size change can float up and down by 10% - 20%, and its specific shape can be designed according to other structures. The embodiments of the present disclosure do not limit this.

[0151] For example, as Figure 2A and Figure 4A shown, the orthographic projection of the third connection trace L2 (located in the first conductive layer 320) connecting the clock signal line (for example, the first sub - clock signal line GCK) providing the second clock signal and the gate of the second noise - reducing transistor T7 on the substrate 10 overlaps with the orthographic projection of the active layer of the second noise - reducing transistor T7 on the substrate 10 in the first direction and is at least partially parallel to the gate of the second noise - reducing transistor T7, that is, the third connection trace L2 passes through from the side of the active layer of the second noise - reducing transistor T7 far from the signal line (for example, the right side of the active layer of the second noise - reducing transistor T7 shown in Figure 2A ).

[0152] For example, as Figure 2A and Figure 4A shown, the third connection trace L2 includes a third sub - connection trace L21 and a fourth sub - connection trace L22. The third sub - connection trace L21 extends along a first direction, and the orthographic projection of the third sub - connection trace L21 on the substrate 10 and the orthographic projection of the active layer of the second noise reduction transistor T7 on the substrate 10 are arranged side by side relative to each other along a second direction. The fourth sub - connection trace L22 is connected to the third sub - connection trace L21 and extends along the second direction.

[0153] For example, in some examples, as Figure 4A shown, the third connection trace L2 is a gate trace, that is, the third sub - connection trace L21 and the fourth sub - connection trace L22 are directly connected (no via connection is required) and integrally formed. For example, the fourth sub - connection trace L22 is connected to the first sub - clock signal line GCK that provides the second clock signal. For example, in another example, as Figure 4B shown, the third connection trace L2 includes two gate traces connected by vias. One is the third sub - connection trace L21, and the other is the fourth sub - connection trace L22. The connection relationship between the third sub - connection trace L21 and the fourth sub - connection trace L22 will be introduced in detail below.

[0154] For example, the third sub - connection trace L21 connecting the fourth sub - connection trace L22 to the gate of the second noise reduction transistor T7 is also connected to the first pole of the output transistor T5 that is not on the same layer through a via, so as to connect the first pole of the output transistor T5 to the second clock signal terminal CB. For example, the second clock signal terminal CB is connected to the first sub - clock signal line GCK. For example, the first pole of the output transistor T5 is electrically connected to the third sub - connection trace L21, and the third sub - connection trace L21 is located on the side of the active layer of the second noise reduction transistor T7 close to the output transistor T5. For example, the orthographic projection of this via on the substrate 10 is located between the orthographic projection of the active layer of the second noise reduction transistor T7 on the substrate 10 and the orthographic projection of the active layer of the output transistor T5 on the substrate 10. For example, the fourth sub - connection trace L22 is in the first conductive layer 320, and its orthographic projection on the substrate 10 is located between the orthographic projection of the voltage - stabilizing transistor T8 of the X - th stage shift register unit on the substrate 10 and the orthographic projection of the input transistor T1 of the (X + 1) - th stage shift register unit on the substrate 10.

[0155] For example, the gate of the output transistor T5 is electrically connected to the first pole of the voltage - stabilizing transistor T8, and the second pole of the output transistor T5 is connected to the output terminal GOUT.

[0156] For example, in some examples, as Figure 2A , Figure 4A , Figure 5C andFigure 7D As shown, the first pole S51 of the output transistor T5 is connected to the source region S5 of the output transistor T5 through a via H7 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. The first pole S51 of the output transistor T5 is connected to the fourth connection trace L5. For example, the first pole S51 of the output transistor T5 and the fourth connection trace L5 are on the same layer and integrally formed. The fourth connection trace L5 is connected to the third sub-connection trace L21 through vias H5 and H6 that penetrate the second insulating layer 360 and the third insulating layer 370. The third sub-connection trace L21 is connected to the gate of the second noise reduction transistor T7 and to the fourth sub-connection trace L22, thereby connecting the first pole S51 of the output transistor T5 to the gate G7 of the second noise reduction transistor T7 and connecting them together to the first sub-clock signal line GCK to receive the second clock signal.

[0157] For example, in some other examples, such as Figure 2B , Figure 4B , Figure 5D , Figure 6B and Figure 7E As shown, the first pole of the output transistor T5 is connected to the fourth connection trace L5. The first pole S51 of the output transistor T5 is connected to the fourth connection trace L5. The first end L51 of the fourth connection trace L5 is connected to the third sub-connection trace L21 located in the second conductive layer 320 through vias H8 and H9 that penetrate the second insulating layer 360 and the third insulating layer 370. The second end L52 of the fourth connection trace L5 is connected to the fourth sub-connection trace L22 located in the second conductive layer 320 through vias H5 and H6 that penetrate the second insulating layer 360 and the third insulating layer 370. The third sub-connection trace L21 is directly connected to and integrally formed with the gate G7 of the second noise reduction transistor T7, thereby connecting the first pole of the output transistor T5 to the gate G7 of the second noise reduction transistor T7 and connecting them together to the first sub-clock signal line GCK through the fourth connection trace L5 and the fourth sub-connection trace L22 to receive the second clock signal.

[0158] For example, such as Figure 2A , Figure 3A and Figure 4A As shown, the active layer of the output control transistor T4 and the active layer of the output transistor T5 are formed by a first output semiconductor layer A13 and a second output semiconductor layer A14 (i.e., the active layers of the output control transistor T4 and the output transistor T5 are integrally arranged) and extend along the first direction. For example, the active layer of the output control transistor T4 is located on the imaginary line of the active layer of the output transistor T5 in the first direction. l, for example, the active layer of the output control transistor T4 includes A13 of the third semiconductor layer and the upper half of the fourth semiconductor layer A14 along the first direction, and the active layer of the output transistor T5 includes A13 of the third semiconductor layer and the lower half of the fourth semiconductor layer A14 along the first direction. It should be noted that the proportions of the active layers of the output control transistor T4 and the output transistor T5 in the third semiconductor layer A13 and the fourth semiconductor layer A14 respectively can be set according to actual situations, and the embodiments of the present disclosure do not limit this. For example, the gates of the output control transistor T4 and the output transistor T5 extend along the second direction and overlap each other in the first direction, that is, the output control transistor T4 and the output transistor T5 are arranged vertically in the first direction. For example, the gate of the output control transistor T4 is located on the imaginary line of the gate of the output transistor T5 in the first direction. For example, the first pole of the output control transistor T4 is electrically connected to the first power supply line VGH.

[0159] In the embodiments of the present disclosure, relative to Figure 1D the case where connection traces are provided on both sides of the second noise reduction transistor T7 shown, at least one embodiment of the present disclosure provides a setting that changes the connection traces of the second noise reduction transistor T7 (that is, the traces only pass between the output transistor T5 and the second noise reduction transistor T7), which reduces the trace complexity, avoids the problem of space congestion, and is beneficial to realizing the narrow border design of the display panel.

[0160] For example, in some embodiments of the present disclosure, the line width of each layer of traces is generally 3 microns, and the spacing between the traces in the same layer is greater than 3 microns. For example, this trace spacing is related to the accuracy of the exposure machine. The higher the accuracy of the exposure machine, the smaller the spacing can be. Specifically, it can be determined according to actual situations, and the embodiments of the present disclosure do not limit this. In the embodiments of the present disclosure, necessary spacing must be left between the traces in the same layer to avoid trace adhesion and signal short - circuit in the actual process.

[0161] The spacing between the orthographic projections of each trace of the first conductive layer 320 on the substrate 10 and the orthographic projections of each trace of the second conductive layer 330 on the substrate 10 is generally 1.5 microns. For example, the gate of the transistor in the first conductive layer 320 extends beyond its active layer on the semiconductor layer 31 by more than 2 microns. For example, as Figure 2A shown in Figures 3 and 4, the "U" - shaped double - gate of the first transistor T1 extends beyond the strip - shaped active layer of the first transistor T1 by more than 2 microns on both sides in the first direction. For example, the length of the part that does not overlap with the strip - shaped active layer of the first transistor T1 (for example, the first part G11 and the second part G12) in the first direction is more than 2 microns, and the embodiments of the present disclosure do not limit this.

[0162] For example, the distance between the orthographic projection of the active layer of each transistor on the semiconductor layer 310 on the substrate 10 and the orthographic projection of each gate trace on the first conductive layer 320 on the substrate 10 is 1.5 micrometers or more, so as to avoid the channel effect between the gate traces and the active layer of each transistor on the semiconductor layer 310. For example, the distance between the orthographic projection of the semiconductor layer 310 on the substrate 10 and the orthographic projection of the second conductive layer 330 on the substrate 10 is not limited and can be overlapped. For example, in some embodiments of the present disclosure, a certain distance (this distance is smaller than the distance between traces of the same layer) is preferably reserved between traces of different layers, which can reduce unnecessary overlap and avoid crosstalk caused by excessive parasitic capacitance.

[0163] For example, the width of each trace of the third conductive layer 340 should cover its corresponding via. For example, it can exceed the size of the via (for example, the diameter of the via) by more than 1 micrometer. For example, the size of the via is 2.0 - 2.5 micrometers, and the width of each trace of the third conductive layer 340 covering the via is 4 - 5 micrometers. For example, the line width of the traces corresponding to the vias of the output control transistor T4 and the output transistor T5 exceeds the via by 1 micrometer up and down, for example, it is 4.0 - 4.5 micrometers. Since there are more vias corresponding to the output control transistor T4 and the output transistor T5, and the width of the traces of the third conductive layer 340 connecting other transistors only needs to meet the requirement of covering the via by more than 1 micrometer at the via position. For example, the line width between vias can be thinner.

[0164] For example, the distance between traces such as the first sub-clock signal line GCK, the second sub-clock signal line GCB, the first power supply line VGH, and the second power supply line VGL located in the third conductive layer 340 is 3 micrometers or more. The line width of the first sub-clock signal line GCK and the second sub-clock signal line GCB is 9 micrometers or more to meet the driving ability requirements. The line width of the second power supply line VGL can be 6, 9, or 10 micrometers. The line width of the first power supply line VGH is, for example, 10 micrometers, and the line width of the reference voltage line Vinit is, for example, 15 micrometers. The second voltage provided by the second power supply line VGL is generally -7V, and the reference voltage provided by the reference voltage line Vinit is, for example, -3V. Since the reference voltage line Vinit needs to drive the pixel array of the entire display panel, while the first power supply line VGH and the second power supply line VGL only need to drive the gate driving circuit located in the peripheral area of the display panel, the line width of the reference voltage line Vinit is wider than that of the first power supply line VGH and the second power supply line VGL.

[0165] For example, in some examples, the thickness of the first conductive layer 320 and the second conductive layer 330 is 2000 - 300 angstroms, and the thickness of the third conductive layer 340 is 5000 - 8000 angstroms. The embodiments of the present disclosure are not limited thereto.

[0166] For example, in some embodiments of the present disclosure, the second power line VGL is provided with a protrusion in order to shorten the connection line connecting the gate of the voltage stabilizing transistor T8 and the active layer of the second control transistor T3. If the active layer of the second control transistor T3 is too long, the resistance of the doped conductor will be relatively large. For example, in some embodiments of the present disclosure, the shape of the line (i.e., the intermediate transfer electrode 11) of the first node N1 in the third conductive layer 340 is designed to avoid overlapping with the positive projection of the lines and electrodes of other layers on the base substrate 10 as much as possible, and is arranged at the position of the gap, so as to avoid crosstalk caused by overlapping lines.

[0167] It should be noted that, in the embodiment of the present disclosure, for example, the first transfer electrode 17, the second transfer electrode 18, and the third transfer electrode 16 are located in the third conductive layer 340. For example, the first transfer electrode 17 is used to connect, for example Figure 1B The electrodes of the input transistor T1, the first control transistor T2, the second noise reduction transistor T7 and the voltage stabilizing transistor T8 shown in the figure, for example, the first node N1 includes the first switching electrode 17. For example, the second switching electrode 18 is an electrode for connecting the voltage stabilizing transistor T8 and the output transistor T5, and the third node N3 includes the second switching electrode 18. For example, the intermediate switching electrode 11 is an electrode for connecting the first control transistor T2, the second control transistor T3 and the first noise reduction transistor T6, which can be located in the second conductive layer 330 or in the first conductive layer 320. When the intermediate switching electrode 11 is located in the second conductive layer 330 and adopts Figure 7B In the connection mode shown, the second node N2 includes the intermediate transfer electrode 11 and the third sub-connection wire L3 and the fourth sub-connection wire L4 located in the third conductive layer 340 and connected to the intermediate transfer electrode 11. For example, the routing transfer electrode 12 is located in the first conductive layer 320 and is a transfer electrode connected to the first connection wire L1 located in the third conductive layer 340, or the two are located in the same layer, which is not limited in the embodiments of the present disclosure.

[0168] For example, by providing the above-mentioned switching electrodes and connecting wires, problems such as wire adhesion and signal short circuit caused by dense wires on the same layer can be avoided. For example, the above-mentioned switching electrodes and connecting wires play the role of connection or jumper connection.

[0169] The display substrate provided in the above-mentioned embodiments of the present disclosure optimizes the line connection and structural layout of the shift register unit, which compresses the length of the shift register unit to a certain extent, is conducive to realizing the narrow frame design of the display panel, and at the same time ensures the display quality of the display panel.

[0170] At least one embodiment of the present disclosure further provides a display device. Figure 8Schematic diagram of a display device provided by at least one embodiment of the present disclosure. As Figure 8 shown, the display device 2 includes a display substrate 1 provided by any embodiment of the present disclosure. For example, Figure 2A or Figure 2B the display substrate 1 shown in

[0171] It should be noted that the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device 2 may further include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0172] It should be noted that, for the sake of clarity and conciseness, the embodiments of the present disclosure do not give all the constituent units of the display device. To implement the substrate function of the display device, those skilled in the art can provide and set other structures not shown according to specific needs, which are not limited in the embodiments of the present disclosure.

[0173] Regarding the technical effects of the display device 2 provided in the above embodiments, reference can be made to the technical effects of the display substrate 1 provided in the embodiments of the present disclosure, which will not be elaborated here.

[0174] At least one embodiment of the present disclosure also provides a method for manufacturing a display substrate. Figure 9 Flowchart of a method for manufacturing a display substrate provided by at least one embodiment of the present disclosure. For example, this manufacturing method can be used to manufacture the display substrate provided by any embodiment of the present disclosure. For example, it can be used to manufacture Figure 2A the display substrate shown in

[0175] As Figure 9 shown, the method for manufacturing the display substrate includes steps S110 to S120.

[0176] Step S110: Provide a substrate.

[0177] Step S120: Sequentially form a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in a direction perpendicular to the substrate.

[0178] For example, forming the semiconductor layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, and the third conductive layer respectively includes forming corresponding material layers (for example, a semiconductor material layer, an insulating material layer, or a conductive material layer), and then using a patterning process to form corresponding pattern structures (for example, an active layer, an electrode pattern, a trace, a via, etc.) respectively. The patterning process is, for example, a photolithography process, and for example includes: coating a photoresist layer on the material layer to be patterned, exposing the photoresist layer using a mask plate, developing the exposed photoresist layer to obtain a photoresist pattern, etching the structure layer using the photoresist pattern, and then optionally removing the photoresist pattern.

[0179] For step S110, for example, the substrate 10 may be made of, for example, glass, plastic, quartz, or other suitable materials, and the embodiments of the present disclosure are not limited thereto.

[0180] For example, a shift register unit, a first power supply line, a second power supply line, a first clock signal line, and a second clock signal line are formed on the substrate.

[0181] For step S120, for example, forming the shift register unit includes: sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in a direction perpendicular to the substrate.

[0182] For example, the first power supply line VGH, the second power supply line VGL, multiple clock signal lines (for example, a trigger signal line GSTV, a first sub-clock signal line GCK, a second sub-clock signal line GCB, etc.); the first and second poles of each transistor included in the shift register unit 104, the connection traces connecting each transistor and the capacitor, the transfer electrodes, etc. are located in the third conductive layer 340, the active layer of each transistor is located in the semiconductor layer 310, the gates of each transistor and the first poles of each capacitor included in the shift register unit are located in the first conductive layer 320, and the second poles of each capacitor are formed in the second conductive layer 330; each transistor and each capacitor are respectively connected to the first power supply line VGH, the second power supply line VGL, multiple clock signal lines, and the connection traces and transfer electrodes through vias penetrating the first insulating layer 310, the second insulating layer 320, or the third insulating layer 330.

[0183] Regarding the setting of the connection structure between each transistor and capacitor of the shift register unit 104 and the first power supply line VGH, the second power supply line VGL, multiple clock signal lines, and the connection traces and transfer electrodes, reference can be made to Figures 2A - 7E the description, which will not be elaborated here.

[0184] It should be noted that in multiple embodiments of the present disclosure, the process of the manufacturing method of the display substrate may include more or fewer operations, and these operations may be executed sequentially or in parallel. Although the process of the manufacturing method described above includes multiple operations that occur in a specific order, it should be clearly understood that the order of the multiple operations is not limited. The manufacturing method described above may be executed once or multiple times according to predetermined conditions.

[0185] Regarding the technical effects of the manufacturing method of the display substrate provided in the above embodiments, reference may be made to the technical effects of the display substrate provided in the embodiments of the present disclosure, which will not be elaborated here.

[0186] The following points need to be explained:

[0187] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0188] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0189] The above description is only an exemplary implementation manner of the present disclosure and is not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, a shift register unit disposed on the substrate, a first clock signal line, and a second clock signal line, wherein, The first clock signal line extends along a first direction on the substrate and is configured to provide a first clock signal to the shift register unit; The second clock signal line extends along the first direction on the substrate and is configured to provide a second clock signal to the shift register unit; The shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and an output control circuit; The input circuit is configured to input an input signal to a first node in response to the first clock signal; The output circuit is configured to output an output signal to an output terminal; The first control circuit is configured to control the level of a second node in response to the level of the first node and the first clock signal; The second control circuit is connected to the first node and the second node and is configured to control the level of the first node under the control of the level of the second node and the second clock signal; The output control circuit is configured to control the level of the output terminal under the control of the level of the second node; Wherein, the first control circuit includes a first control transistor and a second control transistor, the second control circuit includes a first noise reduction transistor and a second noise reduction transistor, and the shift register unit further includes an intermediate transfer electrode, The active layer of the first control transistor, the active layer of the first noise reduction transistor, and the active layer of the second noise reduction transistor are arranged side by side in a second direction different from the first direction; A part of the positive projection of the intermediate transfer electrode on the substrate includes the positive projection of the active layer of the first control transistor on the substrate, the positive projection of the active layer of the second control transistor on the substrate, the positive projection of the active layer of the first noise reduction transistor on the substrate, and the positive projection of the active layer of the second noise reduction transistor on the substrate; The gate of the first noise reduction transistor is connected to the first pole of the first control transistor and the first pole of the second control transistor through the intermediate transfer electrode; The input circuit includes an input transistor. In the first direction, the input transistor and the first noise reduction transistor are arranged in sequence. The imaginary line along which the channel region of the first noise reduction transistor extends in the second direction does not intersect the imaginary line along which the active layer of the input transistor extends in the second direction.

2. The display substrate according to claim 1, wherein, The gate of the first noise reduction transistor is parallel to the gate of the second noise reduction transistor, and the extending direction of the trace where the gate of the first noise reduction transistor is located is not parallel to the extending direction of the trace where the gate of the second noise reduction transistor is located.

3. The display substrate according to claim 1 further includes a first transfer electrode and a voltage stabilizing transistor, wherein, The first transfer electrode includes a broken line located between the first control transistor, the second control transistor, the voltage stabilizing transistor, the first noise reduction transistor, and the second noise reduction transistor and extending in a bent manner along the first direction.

4. The display substrate according to claim 3, wherein, The extending length of the first transfer electrode in the first direction is greater than the extending length in the second direction.

5. The display substrate according to claim 3, wherein, The length of the first transfer electrode is greater than the width in the second direction.

6. The display substrate according to claim 1, wherein, The active layer of the second control transistor is located on the imaginary line extending in the second direction of the active layer of the input transistor.

7. The display substrate according to claim 1, wherein, The active layer of the first control transistor and the active layer of the second control transistor do not overlap in the first direction.

8. The display substrate according to claim 7, wherein, The arrangement and positions of the input transistor, the first noise reduction transistor, and the second noise reduction transistor are in a structure of being arranged one above the other in sequence along the first direction.

9. The display substrate according to claim 1, wherein, The shift register unit further includes a first insulating layer, a second insulating layer, a third insulating layer, and a second connection trace, wherein the first insulating layer is located between the active layer of the first noise reduction transistor and the gate of the first noise reduction transistor in a direction perpendicular to the substrate; The second insulating layer is located between the gate of the first noise reduction transistor and the intermediate transfer electrode in a direction perpendicular to the substrate; The third insulating layer is located between the intermediate transfer electrode and the second connection trace in a direction perpendicular to the substrate, and the second connection trace includes a first sub-connection trace and a second sub-connection trace; The gate of the first noise reduction transistor is connected to the first sub-connection trace through a via hole penetrating the second insulating layer and the third insulating layer, and the first end of the intermediate transfer electrode is connected to the first sub-connection trace through a via hole penetrating the third insulating layer, The first pole of the first control transistor and the first pole of the second control transistor are connected to the second sub-connection trace and are located on the same layer, and the second end of the intermediate transfer electrode is connected to the second sub-connection trace through a via hole penetrating the third insulating layer to connect the gate of the first noise reduction transistor to the first electrode of the first control transistor.

10. The display substrate according to claim 1 further includes a reference voltage line, a first power supply line, and a second power supply line, wherein, The line width of the reference voltage line is greater than the line widths of the first power supply line and the second power supply line.

11. A display substrate, comprising: A substrate, a shift register unit provided on the substrate, a first clock signal line, and a second clock signal line, wherein, The first clock signal line extends along the first direction on the substrate and is configured to provide a first clock signal to the shift register unit; The second clock signal line extends along the first direction on the substrate and is configured to provide a second clock signal to the shift register unit; The shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and an output control circuit; The input circuit is configured to input an input signal to a first node in response to the first clock signal; The output circuit is configured to output an output signal to an output terminal; The first control circuit is configured to control the level of a second node in response to the level of the first node and the first clock signal; The second control circuit is connected to the first node and the second node and is configured to control the level of the first node under the control of the level of the second node and the second clock signal; The output control circuit is configured to control the level of the output terminal under the control of the level of the second node. Among them, the first control circuit includes a first control transistor and a second control transistor, the second control circuit includes a first noise reduction transistor and a second noise reduction transistor, and the shift register unit further includes an intermediate transfer electrode. The active layers of the first control transistor, the first noise reduction transistor, and the second noise reduction transistor are arranged side by side in a second direction different from the first direction. A part of the positive projection of the intermediate transfer electrode on the substrate includes a region between the positive projections of the active layers of the first control transistor, the second control transistor, the first noise reduction transistor, and the second noise reduction transistor on the substrate. The gate of the first noise reduction transistor is connected to the first pole of the first control transistor and the first pole of the second control transistor through the intermediate transfer electrode. The line widths of the first clock signal line and the second clock signal line are more than 9 microns.

12. The display substrate according to claim 11, wherein, The shift register unit further includes a voltage stabilizing circuit. The voltage stabilizing circuit is connected to the first node and the third node and is configured to stabilize the level of the third node. The output circuit is connected to the third node and is configured to output the output signal to the output terminal under the control of the level of the third node. The display substrate further includes a first power supply line and a second power supply line, which are configured to provide a first voltage and a second voltage to the shift register unit. The voltage stabilizing circuit includes a voltage stabilizing transistor. The second power supply line includes a protruding portion protruding in the second direction. The positive projection of the active layer of the voltage stabilizing transistor on the substrate is located between the positive projections of the active layers of the second control transistor and the second noise reduction transistor on the substrate in the first direction. The second pole of the second control transistor is connected to the protruding portion on the second power supply line to receive the second voltage. Among them, the first pole of the voltage stabilizing transistor is connected to the third node, and the second pole of the voltage stabilizing transistor is connected to the first node. The distance between any two of the first clock signal line, the second clock signal line, the first power supply line, and the second power supply line is greater than 3 microns.

13. The display substrate according to claim 11, wherein, The output control circuit includes an output control transistor and a first capacitor. The output circuit includes an output transistor and a second capacitor. The active layer of the output control transistor includes the upper portions of the first output semiconductor layer and the second output semiconductor layer along the first direction. Notches are respectively provided on the left and right sides of the active layer of the output control transistor in the first direction. The active layer of the output transistor includes the lower portions of the first output semiconductor layer and the second output semiconductor layer along the first direction.

14. The display substrate according to claim 13, wherein, The input circuit includes an input transistor. The first pole of the input transistor is connected through a first connection trace extending along the second direction to receive the input signal. Notches are included on one side away from the display area for the first pole and the second pole of the first capacitor.

15. The display substrate according to claim 11, wherein The source region or drain region of the first noise reduction transistor has a curved or bent shape.

16. The display substrate according to claim 11, wherein, The active layer of the first noise reduction transistor and the active layer of the second noise reduction transistor are formed by a continuous noise reduction semiconductor layer.

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