Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device, the display substrate comprises a gate drive circuit, a first low-level power line and a second low-level power line, the gate drive circuit comprises a plurality of cascaded shift registers, and the second low-level power line is located on the side, close to a display area, of the first low-level power line; the orthographic projection of the first low-level power line on the substrate is at least partially overlapped with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate; the orthographic projection of the second low-level power line on the substrate is located between the orthographic projection of at least one transistor in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate. The line width of the first low-level power line in the first direction is smaller than the line width of the second low-level power line in the first direction.

Description

Technical Field

[0001] The utility model relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Utility Model Content

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate having a display area and a non-display area located on at least one side of the display area, comprising: a substrate; and a gate drive circuit, a first low-level power line, and a second low-level power line disposed on the substrate and located in the non-display area, the gate drive circuit comprising: a plurality of cascaded shift registers, at least one shift register stage comprising: a shift subcircuit and an output subcircuit, the shift subcircuit being electrically connected to a first low-level power terminal and a cascade signal output terminal, respectively; the output subcircuit being electrically connected to a first low-level power terminal, a second low-level power terminal, and a drive signal output terminal, respectively; the shift subcircuit comprising: at least one transistor; and the output subcircuit comprising: at least one output transistor;

[0005] The first low-level power line is electrically connected to the first low-level power terminal of the at least one stage of shift register, the second low-level power line is electrically connected to the second low-level power terminal of the at least one stage of shift register, and the second low-level power line is located on a side of the first low-level power line close to the display area;

[0006] The orthographic projection of the first low-level power line on the substrate at least partially overlaps with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate, and the orthographic projection of the second low-level power line on the substrate is located between the orthographic projection of the at least one transistor in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate;

[0007] A line width of the first low-level power line along the first direction is smaller than a line width of the second low-level power line along the first direction.

[0008] In an exemplary embodiment, at least one signal line of the first low-level power line and the second low-level power line extends at least partially along a second direction, and the first direction and the second direction intersect;

[0009] The signal of at least one of the first low-level power line and the second low-level power line is a negative voltage signal, and the absolute value of the voltage value of the power signal of the first low-level power line is smaller than the absolute value of the voltage value of the power signal of the second low-level power line.

[0010] In an exemplary embodiment, the first low-level power line includes: at least one first power connection line, and the second low-level power line includes: a plurality of second power connection lines arranged in different layers and connected to each other;

[0011] The first power connection line and the second power connection line at least partially extend along the second direction, a plurality of second power connection lines are stacked in sequence in a direction away from the substrate, and orthographic projections of at least two of the plurality of second power connection lines on the substrate at least partially overlap;

[0012] The number of first power connection lines included in the first low-level power line is less than the number of second power connection lines included in the second low-level power line;

[0013] The at least one first power connection line is arranged on the same layer as at least one second power connection line among the multiple second power connection lines, and the film layer where the at least one second power connection line is located is located on the side of the film layer where the at least one first power connection line is located close to the substrate.

[0014] In an exemplary embodiment, the first low-level power line includes: a first power connection line, and the second low-level power line includes: two second power connection lines arranged in different layers and connected to each other, the second second power connection line being located on a side of the first second power connection line away from the substrate;

[0015] The first power connection line and the second power connection line are arranged on the same layer;

[0016] Alternatively, the first low-level power line includes: two first power connection lines arranged in different layers and connected to each other, and the second low-level power line includes: three second power connection lines arranged in different layers and connected to each other, the second first power connection line is located on a side of the first first power connection line away from the substrate, the first second power connection line is located on a side of the second second power connection line close to the substrate, and the third second power connection line is located on a side of the second second power connection line away from the substrate;

[0017] The first first power connection line and the second second power connection line are arranged on the same layer, and the second first power connection line and the third second power connection line are arranged on the same layer.

[0018] In an exemplary embodiment, the present invention further includes: a first clock signal line group disposed on the substrate and located in the non-display area, the at least one stage shift register including: a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal, the shift sub-circuit of the at least one stage shift register being respectively connected to the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, the first clock signal line group including: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line arranged in sequence in a direction close to the display area;

[0019] At least one clock signal line among the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line extends at least partially along the second direction;

[0020] The first clock signal terminal of the 4i-3 stage shift register is electrically connected to the first clock signal line, the second clock signal terminal of the 4i-3 stage shift register is electrically connected to the second clock signal line, the third clock signal terminal of the 4i-3 stage shift register is electrically connected to the third clock signal line, the first clock signal terminal of the 4i-2 stage shift register is electrically connected to the second clock signal line, the second clock signal terminal of the 4i-2 stage shift register is electrically connected to the third clock signal line, the third clock signal terminal of the 4i-2 stage shift register is electrically connected to the fourth clock signal line. connecting, the first clock signal terminal of the 4i-1th stage shift register is electrically connected to the third clock signal line, the second clock signal terminal of the 4i-1th stage shift register is electrically connected to the fourth clock signal line, the third clock signal terminal of the 4i-1th stage shift register is electrically connected to the first clock signal line, the first clock signal terminal of the 4i-th stage shift register is electrically connected to the fourth clock signal line, the second clock signal terminal of the 4i-th stage shift register is electrically connected to the first clock signal line, and the third clock signal terminal of the 4i-th stage shift register is electrically connected to the second clock signal line;

[0021] The orthographic projection of the first low-level power line on the substrate is located between the orthographic projection of the second clock signal line on the substrate and the orthographic projection of the third clock signal line on the substrate, and the orthographic projection of the second low-level power line on the substrate is located on a side of the orthographic projection of at least one clock signal line in the first clock signal line group on the substrate close to the display area.

[0022] In an exemplary embodiment, the shift subcircuit of at least one stage of the shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; wherein the control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode of the first transistor is electrically connected to the first node, the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; the control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the first low-level power supply terminal, and the second electrode of the third transistor is electrically connected to the second node; the control electrode of the fourth transistor is electrically connected to the second node, and the control electrode of the fifth transistor is electrically connected to the second node. The first electrodes of the four transistors are electrically connected to the high-level power supply terminal, and the second electrode of the fourth transistor is electrically connected to the cascade signal output terminal; the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the cascade signal output terminal; the control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the high-level power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fourth node; the control electrode of the seventh transistor is electrically connected to the third clock signal terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first node; the control electrode of the eighth transistor is electrically connected to the first low-level power supply terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node;

[0023] The control electrode of the first transistor and the control electrode of the third transistor are integrally structured and at least partially extend along the first direction, and an orthographic projection of the control electrode of the first transistor on the substrate at least partially overlaps with an orthographic projection of at least one of the first clock signal line, the second clock signal line, the first low-level power line, the third clock signal line, and the fourth clock signal line on the substrate;

[0024] At least a portion of the control electrode of the second transistor extends along the first direction, and an orthographic projection of the control electrode of the second transistor on the substrate at least partially overlaps with an orthographic projection of at least one of the second clock signal line and the first low-level power line on the substrate;

[0025] The control electrode of the fourth transistor and the control electrode of the sixth transistor are integrally structured and at least partially extend along the first direction, and an orthographic projection of the control electrode of the fourth transistor on the substrate at least partially overlaps with an orthographic projection of at least one of the third clock signal line and the fourth clock signal line on the substrate;

[0026] The control electrode of the fifth transistor at least partially extends along the first direction, and an orthographic projection of the control electrode of the fifth transistor on the substrate at least partially overlaps with an orthographic projection of at least one of the second clock signal line, the first low-level power line, the third clock signal line, and the fourth clock signal line on the substrate;

[0027] a control electrode of the seventh transistor at least partially extending along the first direction, and an orthographic projection of the control electrode of the seventh transistor on the substrate at least partially overlapping with an orthographic projection of at least one of the first clock signal line, the second clock signal line, the first low-level power line, the third clock signal line, and the fourth clock signal line on the substrate;

[0028] The control electrode of the eighth transistor extends at least partially along the first direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the first clock signal line, the second clock signal line, the first low-level power line, the third clock signal line and the fourth clock signal line.

[0029] In an exemplary embodiment, the method further includes: exposing a plurality of via holes for exposing the control electrode of the first transistor, wherein two of the plurality of via holes for exposing the control electrode of the first transistor respectively expose two ends of the control electrode of the first transistor;

[0030] A plurality of via holes are exposed to the control electrode of the seventh transistor, and two of the plurality of via holes are exposed to the control electrode of the seventh transistor to expose two ends of the control electrode of the seventh transistor respectively.

[0031] In an exemplary embodiment, the device further includes: a plurality of first connection lines disposed on the substrate and located in the non-display area, wherein one of the plurality of first connection lines is electrically connected to a first electrode of a fifth transistor of at least one stage of the shift register, and the first connection line extends along a first direction.

[0032] An orthographic projection of a first electrode of a fifth transistor of at least one stage of the shift register on the substrate at least partially overlaps with an orthographic projection of the fourth clock signal line and one of the plurality of first connecting lines on the substrate, respectively; an orthographic projection of one of the plurality of first connecting lines on the substrate at least partially overlaps with an orthographic projection of at least one of the first clock signal line, the second clock signal line, the first low-level power supply line, and the third clock signal line on the substrate;

[0033] The film layer where the first connecting line is located is located on a side of the film layer where the first electrode and the second electrode of at least one transistor of the at least one stage shift register are located, close to the substrate.

[0034] In an exemplary embodiment, the method further includes: exposing a plurality of via holes exposing the first connection line, wherein two of the plurality of via holes exposing the first connection line respectively expose an end of the first connection line close to the display area and an end of the first connection line away from the display area.

[0035] In an exemplary embodiment, a line width of one of the first low level power line and the second low level power line along the first direction is smaller than a line width of at least one clock signal line in the first clock signal line group along the first direction.

[0036] In an exemplary embodiment, the present invention further includes: a second clock signal line group disposed on the substrate and located in the non-display area, the second clock signal line group being located on a side of the first clock signal line group close to the display area; the at least one stage shift register includes: a fourth clock signal terminal, the output sub-circuit of the at least one stage shift register being electrically connected to the fourth clock signal terminal; the second clock signal line group includes: a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line sequentially arranged in a direction close to the display area;

[0037] The fifth clock signal line and the seventh clock signal line receive the same clock signal, the sixth clock signal line and the eighth clock signal line receive the same signal, and at least one clock signal line among the fifth clock signal line, the sixth clock signal line, the seventh clock signal line, and the eighth clock signal line extends at least partially along the second direction;

[0038] The fourth clock signal terminal of at least one stage of the shift register is electrically connected to one of the first signal line group and the second signal line group, and the fourth clock signal terminals of adjacent shift registers are connected to different signal line groups, wherein the first signal line group includes: a fifth clock signal line and a seventh clock signal line, and the second signal line group includes: a sixth clock signal line and an eighth clock signal line;

[0039] An orthographic projection of the second low-level power line on the substrate is located between an orthographic projection of the sixth clock signal line on the substrate and an orthographic projection of the seventh clock signal line on the substrate.

[0040] In an exemplary embodiment, the output sub-circuit of at least one stage of the shift register includes: a tenth transistor and a third capacitor, wherein a control electrode of the tenth transistor is electrically connected to the third node, a first electrode of the tenth transistor is electrically connected to the fourth clock signal terminal, a second electrode of the tenth transistor is electrically connected to the drive signal output terminal, a first plate of the third capacitor is electrically connected to the fourth clock signal terminal, and a second plate of the third capacitor is electrically connected to the fifth node;

[0041] When the fourth clock signal terminal of the at least one shift register is electrically connected to the first signal line group, the first electrode of the tenth transistor of the at least one shift register is electrically connected to the seventh clock signal line, and the first plate of the third capacitor of the at least one shift register is electrically connected to the fifth clock signal line;

[0042] When the fourth clock signal end of at least one shift register is electrically connected to the second signal line group, the first electrode of the tenth transistor of at least one shift register is electrically connected to the eighth clock signal line, and the first electrode plate of the third capacitor of at least one shift register is electrically connected to the sixth clock signal line.

[0043] In an exemplary embodiment, the output sub-circuit of the at least one stage shift register further includes: a ninth transistor and an eleventh transistor, wherein a control electrode of the ninth transistor is electrically connected to the fifth node, a first electrode of the ninth transistor is electrically connected to the second low-level power supply terminal, a second electrode of the ninth transistor is electrically connected to the drive signal output terminal, a control electrode of the eleventh transistor is electrically connected to the first low-level power supply terminal, a first electrode of the eleventh transistor is electrically connected to the second node, and a second electrode of the eleventh transistor is electrically connected to the fifth node;

[0044] The orthographic projection of at least one of the fifth clock signal line, the sixth clock signal line and the second low-level power supply line on the substrate is located between the orthographic projection of the transistor in the shift sub-circuit and at least one of the eleventh transistor in the output sub-circuit on the substrate and the orthographic projection of at least one of the ninth transistor and the tenth transistor in the output sub-circuit on the substrate, and the orthographic projection of at least one of the seventh clock signal line and the eighth clock signal line on the substrate is located on a side of the orthographic projection of at least one of the ninth transistor and the tenth transistor in the output sub-circuit on the substrate close to the display area.

[0045] In an exemplary embodiment, a line width of at least one of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the seventh clock signal line, and the eighth clock signal line along the first direction is greater than a line width of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line along the first direction.

[0046] In an exemplary embodiment, at least one of the fifth to eighth clock signal lines includes: a first clock connection line and a second clock connection line that are disposed in different layers and connected to each other, the first clock connection line and the second clock connection line at least partially extending along the second direction, and orthographic projections of the first clock connection line and the second clock connection line of at least one of the fifth to eighth clock signal lines on the substrate at least partially overlap;

[0047] The film layer where the first clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line is located is located on the side of the film layer where the second clock connection line is located close to the substrate, and the second clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line is arranged on the same layer as at least one clock signal line from the first clock signal line to the fourth clock signal line.

[0048] In an exemplary embodiment, the present invention further includes: an initial signal line and a high-level power line disposed on the substrate and located in the non-display area; the at least one shift register includes: a signal input terminal and a high-level power terminal; the high-level power line is electrically connected to the high-level power terminal of the at least one shift register; the initial signal line is electrically connected to the signal input terminal of the at least one shift register; and at least a portion of at least one of the initial signal line and the high-level power line extends along the second direction;

[0049] The orthographic projection of the initial signal line on the substrate is located on a side of the first clock signal line group away from the display area, and the orthographic projection of the high-level power line on the substrate is located between the orthographic projection of the first clock signal line group on the substrate and the orthographic projection of the second clock signal line group on the substrate.

[0050] In an exemplary embodiment, an orthographic projection of the high-level power line on the substrate at least partially overlaps an orthographic projection of a control electrode of at least one of the fourth transistor and the fifth transistor in the at least one stage of the shift register on the substrate.

[0051] In an exemplary embodiment, a line width of the high-level power line along the first direction is greater than a line width of at least one of the first low-level power line and the initial signal line along the first direction, and is smaller than a line width of at least one clock signal line in the first clock signal line group along the first direction.

[0052] In an exemplary embodiment, the shift subcircuit further includes: a first capacitor; the output subcircuit further includes: a second capacitor and a third capacitor; at least one of the first, second, and third capacitors includes: a first plate and a second plate; the second plate of at least one capacitor is located on a side of the first plate of at least one capacitor away from the substrate; the first plate of the first capacitor is electrically connected to the third node; the second plate of the first capacitor is electrically connected to the cascade signal output terminal; the first plate of the second capacitor is electrically connected to the fifth node; the second plate of the second capacitor is electrically connected to the second low-level power supply terminal; the first plate of the third capacitor is electrically connected to the fourth clock signal terminal; and the second plate of the third capacitor is electrically connected to the fifth node.

[0053] The orthographic projection of the first capacitor on the substrate is located between the orthographic projection of the first clock signal line group on the substrate and the orthographic projection of the second clock signal line group on the substrate, and at least partially overlaps with the orthographic projection of the high-level power line on the substrate;

[0054] The orthographic projection of the second capacitor on the substrate is located between the orthographic projection of the second low-level power line on the substrate and the orthographic projection of the seventh clock signal line on the substrate;

[0055] The orthographic projection of the third capacitor on the substrate is located between the orthographic projection of the sixth clock signal line on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate, and at least partially overlaps with the orthographic projection of the second low-level power line on the substrate.

[0056] In an exemplary embodiment, at least one of the first and second plates of the at least one capacitor comprises: a main body portion and a connecting portion, wherein the main body portion and the connecting portion of the at least one plate are connected;

[0057] The orthographic projection of the main body of the first electrode plate of the first capacitor on the substrate covers the orthographic projection of the main body of the second electrode plate of the first capacitor on the substrate, the orthographic projection of the main body of the second electrode plate of the second capacitor on the substrate covers the orthographic projection of the main body of the first electrode plate of the second capacitor on the substrate, and the orthographic projection of the main body of the second electrode plate of the third capacitor on the substrate covers the orthographic projection of the main body of the first electrode plate of the third capacitor on the substrate;

[0058] An orthographic projection of the connection portion of the second plate of the third capacitor on the substrate at least partially overlaps with an orthographic projection of at least one of the fifth clock signal line and the sixth clock signal line on the substrate.

[0059] In an exemplary embodiment, a length of a main portion of the second electrode plate of the third capacitor along the first direction is greater than a line width of the second low-level power line along the first direction, and an orthographic projection of a portion of the second low-level power line close to at least one of a boundary of the display area and a boundary away from the display area on the substrate is located within the range of the orthographic projection of the main portion of the second electrode plate of the third capacitor on the substrate;

[0060] The distance between the orthographic projection of the main portion of the second plate of the third capacitor away from the boundary of the display area on the substrate and the orthographic projection of the sixth clock signal line close to the boundary of the display area on the substrate is greater than 1 micron, and the distance between the main portion of the second plate of the third capacitor and the orthographic projection of the second low-level power line away from the boundary of the display area on the substrate is greater than 1 micron;

[0061] The distance between the orthographic projection of the main portion of the second electrode plate of the third capacitor close to the boundary of the display area on the substrate and the orthographic projection of the second low-level power line close to the boundary of the display area on the substrate is greater than 1 micron.

[0062] In an exemplary embodiment, an area of ​​the first capacitor is larger than an area of ​​at least one of the second capacitor and the third capacitor;

[0063] An area of ​​the third capacitor is greater than an area of ​​the second capacitor.

[0064] In an exemplary embodiment, the active pattern of the first transistor and the active pattern of the third transistor are arranged along a first direction, and a straight line extending along the first direction passes through at least a portion of the control electrode of the first transistor and the active pattern of the second transistor.

[0065] In an exemplary embodiment, the output sub-circuit of at least one stage of the shift register includes: a tenth transistor, which is an output transistor;

[0066] The control electrode of the tenth transistor includes: a first connecting segment, a second connecting segment, and a plurality of first branch segments, the second connecting segment is located on a side of the first connecting segment close to the display area, and the plurality of first branch segments are located on a side of the second connecting segment close to the display area; the second electrode of the tenth transistor includes: a third connecting segment and a plurality of second branch segments, the plurality of second branch segments are located on a side of the third connecting segment close to the display area;

[0067] The first connecting section extends along a first direction, and an orthographic projection thereof on the substrate at least partially overlaps with an orthographic projection of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line on the substrate; the second connecting section extends along a second direction, one of the plurality of first branch sections extends along the first direction, and the plurality of first branch sections are arranged along the second direction; the third connecting section extends along the second direction, one of the plurality of second branch sections extends along the first direction, and the plurality of second branch sections are arranged along the second direction;

[0068] The orthographic projection of the third connecting segment on the base at least partially overlaps with the orthographic projection of the first connecting segment on the base, and does not overlap with the orthographic projection of the second connecting segment on the base. The orthographic projection of at least one branch segment among the multiple first branch segments does not overlap with the orthographic projections of the third connecting segment and at least one branch segment among the multiple second branch segments on the base. The orthographic projection of at least one branch segment among the multiple first branch segments on the base is located between the orthographic projections of at least two second branch segments among the multiple second branch segments on the base.

[0069] In an exemplary embodiment, a width-to-length ratio of a channel region of the active pattern of the tenth transistor is greater than 40.

[0070] In an exemplary embodiment, a line width of the first low-level power line along the first direction is in a range of 4 to 20 micrometers, and a line width of the second low-level power line along the first direction is in a range of 4 to 50 micrometers.

[0071] In an exemplary embodiment, a line width of at least one of the seventh clock signal line and the eighth clock signal line along the first direction is in a range of 10 micrometers to 50 micrometers.

[0072] In an exemplary embodiment, the capacitance of the first capacitor is greater than or equal to 0.3 pF.

[0073] In an exemplary embodiment, the present invention further includes: a circuit structure layer provided on a substrate, the circuit structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate; at least one stage of shift register including: a plurality of transistors and a plurality of capacitors; the gate drive circuit, the first low-level power line, and the second low-level power line are provided on the circuit structure layer;

[0074] The display substrate further includes: a first connection line, an initial signal line, a high-level power line, and first to eighth clock signal lines;

[0075] The semiconductor layer includes at least: an active pattern of at least one transistor among a plurality of transistors in at least one stage of a shift register;

[0076] The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors in at least one stage of the shift register and a first electrode plate of at least one capacitor among a plurality of capacitors;

[0077] The second conductive layer includes: a second plate of at least one capacitor located in a plurality of transistors of at least one stage of the shift register;

[0078] The third conductive layer includes: a first electrode and a second electrode of at least one transistor among a plurality of transistors of at least one stage of the shift register and an initial signal line;

[0079] The fourth conductive layer includes: a high-level power line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line;

[0080] The first connecting line is located in the first conductive layer or the second conductive layer, the first low-level power line is located in the fourth conductive layer, the second low-level power line is located in the third conductive layer and the fourth conductive layer, and at least one clock signal line from the fifth clock signal line to the eighth clock signal line is located in the third conductive layer and the fourth conductive layer.

[0081] In an exemplary embodiment, the present invention further includes: a circuit structure layer provided on a substrate, the circuit structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate; at least one stage of the shift register including: a plurality of transistors and a plurality of capacitors; the gate drive circuit, the first low-level power line, and the second low-level power line are provided on the circuit structure layer;

[0082] The display substrate further includes: a first connection line, an initial signal line, a high-level power line, and first to eighth clock signal lines.

[0083] The semiconductor layer includes at least: an active pattern of at least one transistor among a plurality of transistors in at least one stage of a shift register;

[0084] The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors in at least one stage of the shift register and a first electrode plate of at least one capacitor among a plurality of capacitors;

[0085] The second conductive layer includes: a second plate of at least one capacitor located in a plurality of transistors of at least one stage of the shift register;

[0086] The third conductive layer includes: a first electrode and a second electrode of at least one transistor among a plurality of transistors of at least one stage of the shift register and an initial signal line;

[0087] The fourth conductive layer includes: a high-level power line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line;

[0088] The first connecting line is located in the first conductive layer or the second conductive layer, the first low-level power line is located in at least one film layer among the fourth conductive layer and the fifth conductive layer, the second low-level power line is located in the third conductive layer, the fourth conductive layer and the fifth conductive layer, and at least one clock signal line from the fifth clock signal line to the eighth clock signal line is located in at least two film layers among the third conductive layer, the fourth conductive layer and the fifth conductive layer.

[0089] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0090] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0091] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0092] Figure 1 is a structural schematic diagram of a display device;

[0093] Figure 2A A schematic diagram of the planar structure of a display substrate Figure 1 ;

[0094] Figure 2B Schematic diagram 2 of a planar structure of a display substrate;

[0095] Figure 2C A schematic diagram of the planar structure of a display substrate Figure 3 ;

[0096] Figure 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0097] Figure 4 for Figure 3 The working timing diagram of the pixel driving circuit provided;

[0098] Figure 5 is the equivalent circuit diagram of the shift register;

[0099] Figure 6 for Figure 5 The working timing diagram of the shift register provided;

[0100] Figure 7 A top view of a display substrate provided in an embodiment of the present disclosure;

[0101] Figure 8 A schematic diagram of the cascade connection of multiple shift registers;

[0102] Figure 9 is a top view of a four-stage shift register;

[0103] Figure 10 for Figure 7 Schematic diagram of the middle film layer Figure 1 ;

[0104] Figure 11 for Figure 7 Schematic diagram of the middle membrane layer 2;

[0105] Figure 12 for Figure 7 A magnified view of a local area;

[0106] Figure 13 for Figure 9 Schematic diagram after semiconductor layer patterning is formed;

[0107] Figure 14 for Figure 9 A schematic diagram of a first conductive layer pattern in FIG.

[0108] Figure 15 for Figure 9 A schematic diagram after forming a first conductive layer pattern;

[0109] Figure 16 for Figure 9 Schematic diagram of the second conductive layer pattern;

[0110] Figure 17 for Figure 9 A schematic diagram after forming a second conductive layer pattern;

[0111] Figure 18 for Figure 9 A schematic diagram after forming a third insulating layer pattern;

[0112] Figure 19 for Figure 9 A schematic diagram of a third conductive layer pattern in FIG.

[0113] Figure 20 for Figure 9 Schematic diagram after forming the third conductive layer pattern;

[0114] Figure 21 for Figure 9 Schematic diagram after forming the first planar layer pattern;

[0115] Figure 22 for Figure 9 A schematic diagram of a fourth conductive layer pattern;

[0116] Figure 23 for Figure 9 Schematic diagram after forming the fourth conductive layer pattern. DETAILED DESCRIPTION

[0117] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0118] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the length and spacing of the various signal lines along the first direction can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0119] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0120] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0121] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0122] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0123] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0124] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0125] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0126] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0127] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0128] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0129] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1 As shown, the display device may include a timing controller, a data driver, a gate driver, and a pixel array. The timing controller is respectively connected to the data driver and the gate driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The gate driver is respectively connected to a plurality of gate lines (G1 to Gm). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit. The pixel driving circuit may be respectively connected to the gate lines and the data signal lines.

[0130] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver may sample the grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.

[0131] In an exemplary embodiment, the gate driver may generate a scan signal to be provided to the gate lines G1, G2, G3, ... to Gm by receiving a clock signal, a gate start signal, etc. from a timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the gate lines G1 to Gm. For example, the gate driver may be configured in the form of a shift register and may sequentially transmit a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal to generate a scan signal, and m may be a natural number.

[0132] Figure 2A A schematic diagram of the planar structure of a display substrate Figure 1 , Figure 2B Schematic diagram 2 of a planar structure of a display substrate. Figure 2C A schematic diagram of the planar structure of a display substrate Figure 3 .like Figures 2A to 2C As shown, a display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a gate line and a data signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the gate line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0133] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0134] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0135] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure. Figure 2A and Figure 2B The description is given by taking an example where a pixel unit includes three sub-pixels. Figure 2A The three sub-pixels in the image are arranged horizontally. Figure 2B The three sub-pixels are arranged in a triangular pattern.

[0136] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure. Figure 2C The description is given by taking an example where a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square.

[0137] The pixel drive circuit includes multiple transistors. These transistors include low-temperature polysilicon (LTPS) thin-film transistors and oxide semiconductor (Oxide) transistors. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current.

[0138] When multiple transistors in a pixel driving circuit are low-temperature polysilicon thin-film transistors, the display substrate where the pixel driving circuit is located is called an LTPS display substrate, and the LTPS display substrate has a higher mobility. When some of the multiple transistors in a pixel driving circuit are LTPS thin-film transistors, and some of the multiple transistors in a pixel driving circuit are LTPO thin-film transistors, the display substrate where the pixel driving circuit is located is called a low-temperature polysilicon and oxide semiconductor combined display substrate. A low-temperature polysilicon and oxide semiconductor combined display substrate can integrate low-temperature polysilicon thin-film transistors and oxide thin-film transistors on one display substrate to form an LTPO display substrate, which can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality. When multiple transistors in a pixel driving circuit are oxide semiconductor thin-film transistors, the display substrate where the pixel driving circuit is located is called an oxide semiconductor display substrate. The oxide semiconductor display substrate can achieve high-frequency display and high-resolution display, and can also reduce power consumption.

[0139] The pixel driving circuit in the oxide semiconductor display substrate can have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0140] Figure 3 Figure 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 3As shown, the pixel driving circuit in the oxide semiconductor display substrate may include 7 transistors (a first transistor M1 to a seventh transistor M7) and two storage capacitors (a first storage capacitor Cst1 and a second storage capacitor Cst2). Among them, the gate electrode of the first transistor M1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the gate electrode of the second transistor M2 is electrically connected to the second reset signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first initial signal line INIT1, and the second electrode of the second transistor M2 is electrically connected to the fourth node N4; the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the third node N3; the gate electrode of the fourth transistor M4 is electrically connected to the scan signal line Gate, the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor M4 is electrically connected to the first node N1; the gate electrode of the fifth transistor M5 is electrically connected to the first reset signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first initial signal line INIT1, and the second electrode of the second transistor M2 is electrically connected to the fourth node N4; A light-emitting signal line EM1 is electrically connected, a first electrode of the fifth transistor M5 is electrically connected to the first power supply line VDD, and a second electrode of the fifth transistor M5 is electrically connected to the second node N2; a gate electrode of the sixth transistor M6 is electrically connected to the second light-emitting signal line EM2, a first electrode of the sixth transistor M6 is electrically connected to the third node N3, and a second electrode of the sixth transistor M6 is electrically connected to the fifth node N5; a gate electrode of the seventh transistor M7 is electrically connected to the third reset signal line Reset3, a first electrode of the seventh transistor M7 is electrically connected to the third initial signal line INIT3, and a second electrode of the seventh transistor M7 is electrically connected to the fifth node N5; a first plate of the first storage capacitor Cst1 is electrically connected to the third node N3, and a second plate of the first storage capacitor Cst1 is electrically connected to the fourth node N4; a first plate of the second storage capacitor Cst2 is electrically connected to the first node N1, and a second plate of the second storage capacitor Cst2 is electrically connected to the fourth node N4.

[0141] In an exemplary embodiment, at least one transistor among the first to seventh transistors M1 to M7 is an oxide semiconductor thin film transistor.

[0142] In an exemplary embodiment, at least one transistor among the first to seventh transistors M1 to M7 is an N-type transistor.

[0143] In an exemplary embodiment, the light emitting device L1 may be electrically connected to the fifth node N5 and the second power line VSS, respectively. Exemplarily, a first electrode of the light emitting device L is connected to the fifth node N5, and a second electrode of the light emitting device L is connected to the second power line VSS.

[0144] In an exemplary embodiment, the first power line VDD continuously provides a high level signal, and the second power line VSS continuously provides a low level signal.

[0145] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal of the first initial signal line INIT1 may be -3V.

[0146] In an exemplary embodiment, the voltage value of the signal of at least one of the second initial signal line INIT2 and the third initial signal line INIT3 is constant and is a DC signal, and the voltage value of the signal of at least one of the second initial signal line INIT2 and the third initial signal line INIT3 may be 0V.

[0147] In an exemplary embodiment, the signal received by the second initial signal line INIT2 and the signal received by the third initial signal line INIT3 may be the same signal.

[0148] In an exemplary embodiment, the first initial signal line INIT1 may receive a first initial signal. The first transistor M1 may be referred to as a first initial transistor. The first transistor M1 writes the first initial signal to the first node N1 under the control of a signal of the first reset signal line Reset1 to initialize the first node N1.

[0149] In an exemplary embodiment, the second initial signal line INIT2 may receive a second initial signal. The second transistor M2 may be referred to as a second initial transistor. The second transistor M2 writes the second initial signal into the fourth node N4 under the control of a signal of the second reset signal line Reset2 to initialize the fourth node N4.

[0150] In an exemplary embodiment, the third initial signal line INIT3 may receive a third initial signal. The seventh transistor M7 may be referred to as a second initial transistor. Under the control of the third reset signal line Reset3, the seventh transistor M7 writes the third initial signal into the fifth node N5, thereby initializing the fifth node N5 (which is also the first electrode of the light-emitting device L).

[0151] In an exemplary embodiment, the third transistor M3 may be referred to as a driving transistor. The connection method of the third transistor in the present disclosure may improve the output saturation characteristics of the third transistor M3.

[0152] In an exemplary embodiment, the data signal line Data may receive a data signal, and the fourth transistor M4 may be referred to as a write transistor, which writes the data signal to the first node N1 under the control of a signal of the scan signal line Gate.

[0153] In an exemplary embodiment, the first power line VDD may receive a first power signal, and the fifth transistor M5 may be referred to as a first light-emitting transistor. The fifth transistor M5 may be controlled by a signal from the first light-emitting signal line EM1 to write the first power signal to the second node N2. The sixth transistor M6 may be referred to as a second light-emitting transistor. The sixth transistor M6 may be controlled by a signal from the second light-emitting signal line EM2 to write a driving signal output from the third node N3 to the fifth node N5 (also the first electrode of the light-emitting device L).

[0154] In an exemplary embodiment, the content displayed by the display substrate includes: a plurality of display frames. Figure 4 for Figure 3 The working timing diagram of the pixel driving circuit is provided. Figure 4 for Figure 3 Provided is a working timing diagram of the pixel driving circuit in a display frame.

[0155] Combine Figure 3 and Figure 4 As shown, the working process of the pixel driving circuit may include:

[0156] In the first phase S1, referred to as the initialization phase, the signals on the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the signals on the scan signal line Gate and the first light-emitting signal line EM1 are low-level signals. The first transistor M1, the second transistor M2, the sixth transistor M6, and the seventh transistor M7 are turned on, while the fourth transistor M4 and the fifth transistor M5 are turned off.

[0157] The first transistor M1 is turned on, and the first initial signal of the first initial signal line INIT1 is written into the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The second transistor M2 is turned on, and the second initial signal of the second initial signal line INIT2 is written into the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The sixth transistor T6 and the seventh transistor M7 are turned on, and the third initial signal of the third initial signal line INIT3 is written into the fifth node N5 and the third node N3 in sequence, and the third node N3 and the fifth node N5 (that is, the first electrode of the light-emitting device L) are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed.

[0158] In the second phase S2, referred to as the first buffer phase, the signals on the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, the signals on the scan signal line Gate, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the signal on the third reset signal line Reset3 changes from a high-level signal to a low-level signal. The first transistor M1 and the second transistor M2 are turned on, the seventh transistor M7 changes from an on state to an off state, and the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off.

[0159] The first transistor M1 is turned on, and the first initial signal of the first initial signal line INIT1 is continuously written into the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The second transistor M2 is turned on, and the second initial signal of the second initial signal line INIT2 is continuously written into the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. During the conduction period of the seventh transistor M7, the third initial signal of the third initial signal line INIT3 is written into the fifth node N5, the fifth node N5 (that is, the first electrode of the light-emitting device L) is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0160] In the third stage S3, known as the threshold compensation stage, the signals on the first reset signal line Reset1, the second reset signal line Reset2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the second light-emitting signal line EM2, the third reset signal line Reset3, and the scan signal line Gate are low-level signals. The first transistor M1, the second transistor M2, and the fifth transistor M5 are turned on, while the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are turned off.

[0161] The first transistor M1 is turned on, and the first initial signal of the first initial signal line INIT1 is continuously written into the first node N1. The second transistor M2 is turned on, and the second initial signal of the second initial signal line INIT2 is continuously written into the fourth node N4. The fifth transistor M5 is turned on, and the power signal of the first power line VDD is written into the third node N3 through the turned-on fifth transistor M5 and the third transistor M3, until the voltage value of the signal at the third node N3 reaches Vinit1-Vth, where Vinit1 is the voltage value of the first initial signal and Vth is the threshold voltage of the third transistor M3. The voltage difference stored in the first storage capacitor Cst1 is Vth, and the voltage difference stored in the second storage capacitor Cst2 is 0.

[0162] In the fourth stage S4, referred to as the second buffer stage, the signal on the second reset signal line Reset2 is high, the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the third reset signal line Reset3, and the scan signal line Gate are low, and the signal on the first reset signal line Reset1 changes from a high to a low. The second transistor M2 is turned on, the first transistor M1 changes from an on state to an off state, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off.

[0163] When the first transistor M1 is turned on, the first initial signal of the first initial signal line INIT1 is written into the first node N1, the second transistor M2 is turned on, and the second initial signal of the second initial signal line INIT2 is continuously written into the fourth node N4.

[0164] In the fifth stage S5, known as the data writing stage, the signals on the second reset signal line Reset2 and the scan signal line Gate are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The second transistor M2 and the fourth transistor M4 are turned on, the first transistor M1 and the fifth transistor M5 are turned on, and the sixth transistor M6 and the seventh transistor M7 are turned off.

[0165] The second transistor M2 is turned on, the first initial signal of the first initial signal line INIT1 is continuously written into the fourth node N4, the signal of the third node N3 remains unchanged, the fourth transistor M4 is turned on, and the signal of the data signal line Data is written into the first node N1.

[0166] In the sixth stage S6, also known as the third buffer stage, the signals on the scan signal line Gate, the first reset signal line Reset1, the third reset signal line Reset3, and the first light-emitting signal line EM1 are low-level signals. The signal on the second light-emitting signal line EM2 changes from a low-level signal to a high-level signal, and the second reset signal line Reset2 changes from a high-level signal to a low-level signal. The second transistor M2 changes from an on state to an off state, and the sixth transistor T6 changes from an off state to an on state. The first transistor M1, the fourth transistor T4, the fifth transistor M5, and the seventh transistor M7 are turned off.

[0167] When the second transistor M2 is turned on, the second initial signal of the second initial signal line INIT2 is continuously written into the fourth node N4. When the sixth transistor T6 is turned on, the third node N3 and the fifth node N5 are connected.

[0168] In the seventh stage S7, referred to as the light-emitting stage, the signals on the first and second light-emitting signal lines EM1 and EM2 are high-level signals, while the signals on the first, second, and third reset signal lines Reset1, Reset2, and Reset3, as well as the scan signal line Gate, are low-level signals. The fifth and sixth transistors M5 and M6 are turned on, while the first, second, fourth, and seventh transistors M1, M2, M4, and M7 are turned off.

[0169] The fifth transistor M5 and the sixth transistor M6 are turned on, and the power voltage output from the first power line VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light emitting device L to emit light.

[0170] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage value of the signal at the first node N1 is Vdata and the voltage value of the signal at the third node N3 is Vinit1-Vth, the driving current I of the third transistor M3 is:

[0171] I=K*(Vgs-Vth) 2 =K*[(Vdata-Vinit1+Vth)-Vth] 2 =K*(Vdata-Vinit1) 2

[0172] The driving current is the driving current for driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3.

[0173] In an exemplary embodiment, the light-emitting device may include a current-driven device, and a current-driven light-emitting diode may be used, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED). A typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0174] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0175] In an exemplary embodiment, the gate driver includes at least one gate driving circuit. The number of gate driving circuits depends on the gate line. Figure 3 Taking the display substrate of the provided pixel driving circuit as an example, the gate driving circuit includes: a first scanning driving circuit, wherein the scanning driving circuit can be electrically connected to the scanning signal line.

[0176] In an exemplary embodiment, any gate drive circuit in a gate driver may include a plurality of cascaded shift registers. At least one shift register stage includes a shift subcircuit and an output subcircuit. The shift subcircuit is electrically connected to a signal input terminal, a cascade signal output terminal, a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a first low-level power supply terminal, and a high-level power supply terminal, respectively. The shift subcircuit is configured to provide a signal from the second clock signal terminal or the high-level power supply terminal to the cascade signal output terminal under control of a signal from at least one of the signal input terminal, the first clock signal terminal, the third clock signal terminal, and the second power supply terminal. The output subcircuit is further electrically connected to the shift subcircuit, a fourth clock signal terminal, the first low-level power supply terminal, the second low-level power supply terminal, and the drive signal output terminal, respectively. The output subcircuit is configured to provide a signal from the second low-level power supply terminal or the fourth clock signal terminal to the drive signal output terminal.

[0177] In some embodiments, Figure 5 is the equivalent circuit diagram of the shift register. Figure 5As shown, the shift sub-circuit in at least one stage of the shift register includes an output sub-circuit, for example: the shift sub-circuit in at least one stage of the shift register includes a first node, a second node N2 and a third node N3, and the shift sub-circuit provides a signal from a second clock signal terminal or a high-level power supply terminal to the cascade signal output terminal under the control of the first node, the second node N2 and the third node N3; the output sub-circuit is coupled to the second node N2 and the third node N3, and provides a signal from a second low-level power supply terminal or a fourth clock signal terminal to the drive signal output terminal under the control of the second node N2 and the third node N3.

[0178] like Figure 5As shown, the shift subcircuit in at least one stage of the shift register includes: the first transistor T1 to the eighth transistor T8 and at least part of the first capacitor C1, and the output subcircuit includes: the ninth transistor T9 to the eleventh transistor T11, the second capacitor C2 and the third capacitor C3.Wherein, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the first low-level power supply terminal VGL1, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, and the fourth transistor T5 is electrically connected to the second node N3. A first electrode of the transistor T4 is electrically connected to the high-level power supply terminal VGH, and a second electrode of the fourth transistor T4 is electrically connected to the cascade signal output terminal Carry; a control electrode of the fifth transistor T5 is electrically connected to the third node N3, a first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CK2, and a second electrode of the fifth transistor T5 is electrically connected to the cascade signal output terminal Carry; a control electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the high-level power supply terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, and a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4. A second electrode of the seventh transistor T7 is electrically connected to the first node N1; a control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VGL, a first electrode of the eighth transistor T8 is electrically connected to the first node N1, and a second electrode of the eighth transistor T8 is electrically connected to the third node N3; a control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, a first electrode of the ninth transistor T9 is electrically connected to the second low-level power supply terminal VGL2, and a second electrode of the ninth transistor T9 is electrically connected to the drive signal output terminal GOUT; a control electrode of the tenth transistor T10 is electrically connected to the third node N3, a first electrode of the tenth transistor T10 is electrically connected to the fourth clock signal terminal CK4, and a second electrode of the tenth transistor T10 is electrically connected to the drive signal output terminal GOUT The control electrode of the eleventh transistor T11 is electrically connected to the first low-level power supply terminal VGL1, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, and the second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5; the first plate C11 of the first capacitor C1 is electrically connected to the third node N3, and the second plate of the first capacitor C1 is electrically connected to the cascade signal output terminal Carry; the first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate C22 of the second capacitor C2 is electrically connected to the second low-level power supply terminal VGL2; the first plate C31 of the third capacitor C3 is electrically connected to the fourth clock signal terminal CK4, and the second plate C32 of the third capacitor C3 is electrically connected to the fifth node N5.

[0179] In an exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0180] In example embodiments, at least one of the first to eleventh transistors T1 to T11 may be a P-type transistor.

[0181] In an exemplary embodiment, a duration during which a signal of at least one of the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 of the at least one stage shift register is a first signal within one cycle is greater than a duration during which a signal of at least one of the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 of the at least one stage shift register is a second signal within one cycle, the first signal is a positive voltage signal, and the second signal is a negative voltage signal.

[0182] In an exemplary embodiment, the duration that the signal at the fourth clock signal terminal CK4 of at least one stage of the shift register is the first signal in one cycle is shorter than the duration that the signal at the fourth clock signal terminal CK4 of at least one stage of the shift register is the second signal in one cycle.

[0183] In an exemplary embodiment, the duration of the signal of at least one of the first clock signal terminal CK1, the second clock signal terminal CK2 and the third clock signal terminal CK3 of the at least one stage shift register being the first signal within one cycle is greater than the cycle of the signal of the fourth clock signal terminal CK4 of the at least one stage shift register.

[0184] In an exemplary embodiment, the shift subcircuit outputs a cascade signal provided for other stages of shift registers to a cascade signal output terminal, and the output subcircuit outputs a driving signal provided for a pixel driving circuit to a driving signal output terminal.

[0185] In an exemplary embodiment, the signal input terminal of at least one stage of the shift register is electrically connected to the cascade signal output terminal of at least one stage of the shift register.

[0186] Figure 6 for Figure 5 The working timing diagram of the shift register is provided. Figure 6 Therefore Figure 5All transistors in the figure are P-type transistors. Figure 5 The eighth transistor T8 and the eleventh transistor T11 in the transistor MOSFET are continuously turned on.

[0187] like Figure 5 and Figure 6 As shown, Figure 5 The working process of the shift register may include:

[0188] In the first phase, the signals at P11, the signal input terminal IN, the first clock signal terminal CK1, and the fourth clock signal terminal CK4 are low-level signals, and the signals at the second clock signal terminal CK2 and the third clock signal terminal CK3 are high-level signals. The first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0189] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1. The first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The signals of the first node N1 and the third node N3 are low-level signals. The second transistor T2, the fifth transistor T5, and the tenth transistor T10 are turned on, the low-level signal of the first clock signal terminal CK1 is written into the second node N2, the high-level signal of the second clock signal terminal CK2 is written into the cascade signal output terminal Carry, and the low-level signal of the fourth clock signal terminal CK4 is written into the drive signal output terminal GOUT. The third transistor T3 is turned on, the signal of the first low-level power supply terminal VGL1 is written into the second node N2, the signal of the second node N2 is a low-level signal, and the signal of the second node N2 is written into the fifth node N5 through the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned on, the high-level signal of the high-level power supply terminal VGH is written into the fourth node N4 and the cascade signal output terminal Carry, and the low-level signal of the second low-level power supply terminal VGL2 is written into the drive signal output terminal GOUT.

[0190] In this stage, the signals of the first node N1, the second node N2, the third node N3 and the fifth node N5 are low level signals, the signal of the fourth node N4 is a high level signal, the cascade signal output terminal Carry outputs a high level signal, and the drive signal output terminal GOUT outputs a low level signal.

[0191] In the second phase P12, the signals at the signal input terminal IN and the fourth clock signal terminal CK4 are low level signals, the signals at the first clock signal terminal CK1, the second clock signal terminal CK2 and the third clock signal terminal CK3 are high level signals, and the first transistor T1, the third transistor T3 and the seventh transistor T7 are turned off.

[0192] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 maintain the low-level signals of the previous stage, the second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the high-level signal of the second clock signal terminal CK2 is written into the cascade signal output terminal Carry, the low-level signal of the fourth clock signal terminal CK4 is written into the drive signal output terminal GOUT, the high-level signal of the second node N2 is written into the fifth node N5 through the turned-on eleventh transistor T11, and the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0193] In this stage, the signals of the first node N1 and the third node N3 are low level signals, the signals of the second node N2 and the fifth node N5 are high level signals, the cascade signal output terminal Carry outputs a high level signal, and the drive signal output terminal GOUT outputs a low level signal.

[0194] In the third phase P13, the signals at the signal input terminal IN, the second clock signal terminal CK2, and the fourth clock signal terminal CK4 are low level signals, and the signals at the first clock signal terminal CK1 and the third clock signal terminal CK3 are high level signals. The first transistor T1, the third transistor T3, and the seventh transistor T7 are turned off.

[0195] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 maintain the low-level signals of the previous stage, the second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the low-level signal of the second clock signal terminal CK2 is written into the cascade signal output terminal Carry, the low-level signal of the fourth clock signal terminal CK4 is written into the drive signal output terminal GOUT, the high-level signal of the second node N2 is written into the fifth node N5 through the turned-on eleventh transistor T11, and the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0196] In this stage, the signals of the first node N1 and the third node N3 are low-level signals, the signals of the second node N2, the fourth node N4 and the fifth node N5 are high-level signals, the cascade signal output terminal Carry outputs the cascade signal, which is a low-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0197] In the fourth phase P14, the signals at the signal input terminal IN and the second clock signal terminal CK2 are low level signals, the signals at the first clock signal terminal CK1, the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are high level signals, and the first transistor T1, the third transistor T3 and the seventh transistor T7 are turned off.

[0198] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 still maintain the low-level signals of the previous stage, the second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the low-level signal of the second clock signal terminal CK2 is written into the cascade signal output terminal Carry, the high-level signal of the fourth clock signal terminal CK4 is written into the drive signal output terminal GOUT, the high-level signal of the second node N2 is written into the fifth node N5 through the turned-on eleventh transistor T11, and the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0199] In this stage, the signals of the first node N1 and the third node N3 are low-level signals, the signals of the second node N2, the fourth node N4 and the fifth node N5 are high-level signals, the cascade signal output terminal Carry outputs the cascade signal, the cascade signal is a low-level signal, and the drive signal output terminal GOUT outputs the drive signal, and the drive signal is a high-level signal.

[0200] In the fifth phase P15, the signals at the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 are low-level signals, and the signals at the signal input terminal IN and the first clock signal terminal CK1 are high-level signals. The first transistor T1 and the third transistor T3 are turned off, and the seventh transistor T7 is turned on.

[0201] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 still maintain the low-level signals of the previous stage, the second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the low-level signal of the second clock signal terminal CK2 is written into the cascade signal output terminal Carry, the low-level signal of the fourth clock signal terminal CK4 is written into the drive signal output terminal GOUT, the high-level signal of the second node N2 is written into the fifth node N5 through the turned-on eleventh transistor T11, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off, the seventh transistor T7 is turned on, and the signal of the first node N1 is written into the fourth node N4.

[0202] In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are low-level signals, the signals of the second node N2 and the fifth node N5 are high-level signals, the cascade signal output terminal Carry outputs the cascade signal, the cascade signal is a low-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0203] In the sixth phase P16, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low-level signals, and the signals at the signal input terminal IN, the first clock signal terminal CK1, and the second clock signal terminal CK2 are high-level signals. The first transistor T1 and the third transistor T3 are turned off, and the seventh transistor T7 is turned on.

[0204] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 still maintain the low-level signals of the previous stage, the second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the high-level signal of the second clock signal terminal CK2 is written into the cascade signal output terminal Carry, the low-level signal of the fourth clock signal terminal CK4 is written into the drive signal output terminal GOUT, the high-level signal of the second node N2 is written into the fifth node N5 through the turned-on eleventh transistor T11, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off, the seventh transistor T7 is turned on, and the signal of the first node N1 is written into the fourth node N4.

[0205] In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are low-level signals, the signals of the second node N2 and the fifth node N5 are high-level signals, the cascade signal output terminal Carry outputs the cascade signal, the cascade signal is a high-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0206] In the seventh phase P17, the signal at the first clock signal terminal CK1 is a low-level signal, the signals at the signal input terminal IN and the second clock signal terminal CK2 are high-level signals, the signal at the third clock signal terminal CK3 changes from a low-level signal to a high-level signal, the signal at the fourth clock signal terminal CK4 changes from a low-level signal to a high-level signal, and from a high-level signal to a low-level signal. The first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 changes from on to off.

[0207] The first transistor T1 is turned on, and a high-level signal from the signal input terminal IN is written into the first node N1. The first node N1 is then written into the third node N3 via the turned-on eighth transistor T8. The signals at the first node N1 and the third node N3 are high-level signals. The second transistor T2, the fifth transistor T5, and the tenth transistor T10 are turned off. The third transistor T3 is turned on, and a signal from the second power supply terminal VGL is written into the second node N2. The signal at the second node N2 is a low-level signal. The signal from the second node N2 is written into the fifth node N5 via the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned on, and a high-level signal from the high-level power supply terminal VGH is written into the fourth node N4 and the cascade signal output terminal Carry. The low-level signal from the second low-level power supply terminal VGL2 is written into the drive signal output terminal GOUT.

[0208] In this stage, the signals of the second node N2 and the fifth node N5 are low level signals, the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals, the cascade signal output terminal Carry outputs a low level signal, and the drive signal output terminal GOUT outputs a low level signal.

[0209] In the eighth phase P18, the signal at the fourth clock signal terminal CK4 is a low-level signal, and the signals at the signal input terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 are high-level signals. The first transistor T1, the third transistor T3, and the seventh transistor T7 are turned off.

[0210] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 still maintain the high-level signals of the previous stage, the second transistor T2, the fifth transistor T5 and the tenth transistor T10 are disconnected, and under the joint action of the second capacitor C2 and the third capacitor C3, the second node N2 and the fifth node N5 maintain the low-level signals of the previous stage, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned on, the high-level signal of the high-level power supply terminal VGH is written into the fourth node N4 and the cascade signal output terminal Carry, and the low-level signal of the second power supply terminal VGL is written into the drive signal output terminal GOUT.

[0211] In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals, the signals of the second node N2 and the fifth node N5 are low level signals, the cascade signal output terminal Carry outputs a high level signal, and the drive signal output terminal GOUT outputs a low level signal.

[0212] In the ninth phase P19, the signal at the second clock signal terminal CK2 is a low-level signal, the signals at the signal input terminal IN and the first clock signal terminal CK1 are high-level signals, the signal at the third clock signal terminal CK3 changes from a high-level signal to a low-level signal, and the signal at the fourth clock signal terminal CK4 changes from a low-level signal to a high-level signal and then from a high-level signal to a low-level signal. The first transistor T1 and the third transistor T3 are turned off. The seventh transistor T7 changes from off to on.

[0213] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 still maintain the high-level signals of the previous stage, the second transistor T2, the fifth transistor T5 and the tenth transistor T10 are disconnected, and under the joint action of the second capacitor C2 and the third capacitor C3, the second node N2 and the fifth node N5 maintain the low-level signals of the previous stage, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned on, the high-level signal of the high-level power supply terminal VGH is written into the fourth node N4 and the cascade signal output terminal Carry, and the low-level signal of the second power supply terminal VGL is written into the drive signal output terminal GOUT.

[0214] In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals, the signals of the second node N2 and the fifth node N5 are low level signals, the cascade signal output terminal Carry outputs a high level signal, and the drive signal output terminal GOUT outputs a low level signal.

[0215] In an exemplary embodiment, the fifth node P15 and the sixth phase P16 occur cyclically until the signal of the signal input terminal IN becomes a low-level signal.

[0216] The output stability of the gate driving circuit of the display substrate is poor, which affects the display effect of the display substrate.

[0217] To this end, the present disclosure provides a display substrate having a display area and a non-display area located at at least one side of the display area. Figure 7 This is a top view of a display substrate provided in an embodiment of the present disclosure. Figure 7 As shown, the display substrate provided by the embodiment of the present disclosure includes: a substrate and a gate driving circuit, a first low-level power line VL1 and a second low-level power line VL2 arranged on the substrate and located in a non-display area, the gate driving circuit includes: a plurality of cascaded shift registers, at least one level of shift register includes: a shift sub-circuit and an output sub-circuit, the shift sub-circuit is electrically connected to the first low-level power terminal and the cascade signal output terminal, respectively, and the output sub-circuit is electrically connected to the first low-level power terminal, the second low-level power terminal and the driving signal output terminal, respectively.

[0218] In an exemplary embodiment, the shift subcircuit includes at least one transistor. Exemplarily, the shift subcircuit includes first through eighth transistors T1 through T8. The output subcircuit includes at least one output transistor. Exemplarily, the output subcircuit includes ninth through eleventh transistors T9 through T11, with the ninth and tenth transistors T9 and T10 being output transistors.

[0219] In an exemplary embodiment, the first low-level power line VL1 is electrically connected to the first low-level power terminal of at least one stage of the shift register, the second low-level power line VL2 is electrically connected to the second low-level power terminal of at least one stage of the shift register, and the second low-level power line VL2 is located on a side of the first low-level power line VL1 close to the display area.

[0220] In an exemplary embodiment, Figure 7 As shown, the orthographic projection of the first low-level power line VL1 on the substrate at least partially overlaps with the orthographic projection of at least one transistor (for example, the first transistor T1 to the eighth transistor T8) in the shift sub-circuit on the substrate, and the orthographic projection of the second low-level power line VL2 on the substrate is located between the orthographic projection of at least one transistor (for example, the first transistor T1 to the eighth transistor T8) in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor (for example, the ninth transistor T9 and the tenth transistor T10) in the output sub-circuit on the substrate.

[0221] In an exemplary embodiment, Figure 7 As shown, the line width of the first low-level power line VL1 along the first direction D1 is smaller than the line width of the second low-level power line VL2 along the first direction D1.

[0222] The present disclosure separately arranges a first low-level power line connected to the shift sub-circuit and a second low-level power line connected to the output sub-circuit, and the line width of the first low-level power line along the first direction is smaller than the line width of the second low-level power line along the first direction. The small line width of the first low-level power line along the first direction and the at least partial overlap of the orthographic projection of the first low-level power line on the substrate with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate can achieve a narrow frame, and the large line width of the second low-level power line along the first direction can ensure the output stability of the shift register.

[0223] In an exemplary embodiment, Figure 7 As shown, at least one signal line of the first low level power line VL1 and the second low level power line VL2 extends at least partially along the second direction D2, and the first direction D1 and the second direction D2 intersect.

[0224] In an exemplary embodiment, a signal of at least one of the first low-level power line VL1 and the second low-level power line VL2 is a negative voltage signal, and an absolute value of a voltage value of the power signal of the first low-level power line VL1 is smaller than an absolute value of a voltage value of the power signal of the second low-level power line VL2.

[0225] In the present disclosure, the absolute value of the voltage of the power signal of the first low-level power line VL1 is smaller than the absolute value of the voltage of the power signal of the second low-level power line VL2 , which can ensure the output stability of the shift register.

[0226] In an exemplary embodiment, the voltage value of the power signal of the first low-level power line VL1 may be within a range of -2 volts to -10 volts. The voltage value of the power signal of the first low-level power line VL1 may be -6 volts.

[0227] In an exemplary embodiment, the voltage value of the power signal of the second low level power line VL2 may be within a range of -4 volts to -12 volts. The voltage value of the power signal of the second low level power line VL2 may be -8 volts.

[0228] In an exemplary embodiment, the line width of the first low level power line VL1 along the first direction D1 may be in the range of 4 to 20 micrometers. Exemplarily, the line width of the first low level power line VL1 along the first direction D1 may be 8 micrometers.

[0229] In an exemplary embodiment, the line width of the second low-level power line VL2 along the first direction D1 may be in the range of 4 to 50 micrometers. Exemplarily, the line width of the second low-level power line VL2 along the first direction D1 may be 15 micrometers.

[0230] In an exemplary embodiment, the display substrate further includes a circuit structure layer disposed on a base, the circuit structure layer including: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planar layer, and a fourth conductive layer stacked sequentially on the base, or including: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planar layer, a fourth conductive layer, a second planar layer, and a fifth conductive layer stacked sequentially on the base. At least one stage of the shift register includes: a plurality of transistors and a plurality of capacitors, and a gate drive circuit, a first low-level power line, and a second low-level power line are disposed on the circuit structure layer.

[0231] The semiconductor layer includes at least an active pattern of at least one transistor among a plurality of transistors in at least one stage of the shift register.

[0232] The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors located in at least one stage of the shift register and a first electrode plate of at least one capacitor among a plurality of capacitors.

[0233] The second conductive layer includes: a second plate of at least one capacitor located in a plurality of transistors of at least one stage of the shift register.

[0234] The third conductive layer includes: a first electrode and a second electrode of at least one transistor among a plurality of transistors in at least one stage of the shift register.

[0235] In an exemplary embodiment, the first low-level power line VL1 may have a single-layer structure or a multi-layer structure. The first low-level power line VL1 includes at least one first power connection line. The multi-layer structure may be a two-layer structure, a three-layer structure, or a multi-layer structure, which is not limited in this disclosure.

[0236] In an exemplary embodiment, the second low-level power line VL2 may have a multi-layer structure. The second low-level power line VL2 includes a plurality of second power connection lines arranged in different layers and interconnected with each other. The second power connection lines at least partially extend along the second direction. The plurality of second power connection lines are stacked in a direction away from the substrate, and the orthographic projections of at least two of the plurality of second power connection lines on the substrate at least partially overlap.

[0237] The plurality of second power connection lines in the second low-level power line VL2 in the present disclosure are connected in parallel to each other, and the plurality of second power connection lines connected in parallel to each other can reduce the resistance of the second low-level power line VL2 .

[0238] In an exemplary embodiment, the number of first power connection lines included in the first low-level power line VL1 is less than the number of second power connection lines included in the second low-level power line VL2. For example, the number of first power connection lines included in the first low-level power line VL1 may be 1, and the number of second power connection lines included in the second low-level power line VL2 may be 2, or the number of first power connection lines included in the first low-level power line VL1 may be 2, and the number of second power connection lines included in the second low-level power line VL2 may be 3.

[0239] In an exemplary embodiment, at least one first power connection line is arranged in the same layer as at least one second power connection line among the multiple second power connection lines, and the film layer where at least one second power connection line among the multiple second power connection lines is located is located on the side of the film layer where the at least one first power connection line is located close to the substrate.

[0240] In an exemplary embodiment, when the first low-level power supply line includes a plurality of first power connection lines, the line widths of at least two of the plurality of first power connection lines along the first direction may be the same, or may be different. The line width of the first low-level power supply line along the first direction is the line width of the first power connection line having the largest line width along the first direction among the plurality of first power connection lines. The greater the number of first power connection lines included in the first low-level power supply line, the smaller the line width of the first low-level power supply line along the first direction may be.

[0241] In an exemplary embodiment, the line widths of at least two of the plurality of second power connection lines along the first direction may be the same or different. The line width of the second low-level power line along the first direction is the line width of the second power connection line having the largest line width along the first direction among the plurality of second power connection lines. The greater the number of second power connection lines included in the second low-level power line, the smaller the line width of the second low-level power line along the first direction may be.

[0242] In an exemplary embodiment, the first low-level power line VL1 includes a first power connection line, and the second low-level power line VL2 includes two second power connection lines disposed on different layers and connected to each other, with the second second power connection line being located on a side of the first second power connection line away from the substrate. The first power connection line and the second second power connection line are disposed on the same layer.

[0243] In an exemplary embodiment, the first low-level power line VL1 includes: a first power connection line, and the second low-level power line VL2 includes: two second power connection lines arranged in different layers and connected to each other, the first power connection line can be located in the fourth conductive layer, the first second power connection line can be located in the third conductive layer, and the second second power connection line can be located in the fourth conductive layer.

[0244] In an exemplary embodiment, the first low-level power line VL1 includes two first power connection lines disposed on different layers and interconnected, and the second low-level power line VL2 includes three second power connection lines disposed on different layers and interconnected, wherein the second first power connection line is located on a side of the first first power connection line away from the substrate, the first second power connection line is located on a side of the second second power connection line closer to the substrate, and the third second power connection line is located on a side of the second second power connection line away from the substrate. The first first power connection line and the second second power connection line are disposed on the same layer, and the second first power connection line and the third second power connection line are disposed on the same layer.

[0245] In an exemplary embodiment, the first low-level power line VL1 includes: two first power connection lines arranged in different layers and connected to each other, and the second low-level power line VL2 includes: three second power connection lines arranged in different layers and connected to each other, the first first power connection line is located in the fourth conductive layer, the second first power connection line is located in the fifth conductive layer, the first second power connection line is located in the third conductive layer, the second second power connection line is located in the fourth conductive layer, and the third second power connection line is located in the fifth conductive layer.

[0246] In an exemplary embodiment, Figure 7As shown, the display substrate also includes: a first clock signal line group arranged on the base and located in the non-display area, at least one level of shift register including: a first clock signal terminal, a second clock signal terminal and a third clock signal terminal, a shift sub-circuit of at least one level of shift register respectively connected to the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and the first clock signal line group including: a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3 and a fourth clock signal line CLK4 arranged in sequence along the direction close to the display area.

[0247] In an exemplary embodiment, Figure 7 As shown, at least one clock signal line among the first clock signal line CLK1 , the second clock signal line CLK2 , the third clock signal line CLK3 and the fourth clock signal line CLK4 at least partially extends along the second direction D2 .

[0248] In an exemplary embodiment, Figure 8 This is a schematic diagram of the cascade connection of multiple shift registers. Figure 9 This is a top view of the four-stage shift register. Figure 8 and Figure 9 As shown, the first clock signal end of the 4i-3-stage shift register GOA (4i-3) is electrically connected to the first clock signal line CLK1, the second clock signal end of the 4i-3-stage shift register GOA (4i-3) is electrically connected to the second clock signal line CLK2, the third clock signal end of the 4i-3-stage shift register GOA (4i-3) is electrically connected to the third clock signal line CLK3, the first clock signal end of the 4i-2-stage shift register GOA (4i-2) is electrically connected to the second clock signal line CLK2, the second clock signal end of the 4i-2-stage shift register GOA (4i-2) is electrically connected to the third clock signal line CLK3, the third clock signal end of the 4i-2-stage shift register GOA (4i-2) is electrically connected to the fourth clock signal line CLK4 is electrically connected, the first clock signal end of the 4i-1th stage shift register GOA (4i-1) is electrically connected to the third clock signal line CLK3, the second clock signal end of the 4i-1th stage shift register GOA (4i-1) is electrically connected to the fourth clock signal line CLK4, the third clock signal end of the 4i-1th stage shift register GOA (4i-1) is electrically connected to the first clock signal line CLK1, the first clock signal end of the 4i-stage shift register GOA (4i) is electrically connected to the fourth clock signal line CLK4, the second clock signal end of the 4i-stage shift register GOA (4i) is electrically connected to the first clock signal line CLK1, and the third clock signal end of the 4i-stage shift register GOA (4i) is electrically connected to the second clock signal line CLK2.

[0249] In an exemplary embodiment, Figure 7As shown, the orthographic projection of the first low-level power line VL1 on the substrate is located between the orthographic projection of the second clock signal line CLK2 on the substrate and the orthographic projection of the third clock signal line CLK3 on the substrate, and the orthographic projection of the second low-level power line VL2 on the substrate is located on a side of the orthographic projection of at least one clock signal line in the first clock signal line group on the substrate close to the display area.

[0250] In an exemplary embodiment, Figure 10 for Figure 7 Schematic diagram of the middle film layer Figure 1 . Figure 10 It includes: a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first flat layer and a fourth conductive layer. Figure 10 As shown, the control electrode 12 of the first transistor T1 and the control electrode 32 of the third transistor T3 are integrally structured and extend at least partially along a first direction D1. The orthographic projection of the control electrode 12 of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power line VL1, the third clock signal line CLK3, and the fourth clock signal line CLK4. This at least partially overlaps with the orthographic projection of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power line VL1, the third clock signal line CLK3, and the fourth clock signal line CLK4. This ensures that the control electrode 12 of the first transistor T1 of at least two stages of the multiple cascaded shift registers overlaps with the first clock signal line group in the same area. This, in turn, ensures that the coupling capacitances between the control electrodes 12 of the first transistors T1 of the at least two stages of the shift registers and the first clock signal line group are substantially the same, thereby ensuring the reliability of the shift registers.

[0251] In an exemplary embodiment, Figure 11 for Figure 7 Schematic diagram of the middle membrane layer 2. Figure 11 It includes a semiconductor layer, a first conductive layer, a second insulating layer and a second conductive layer. Figure 11 As shown, the display substrate is further provided with a plurality of via holes H1 exposing the control electrode 12 of the first transistor T1. Two of the plurality of via holes exposing the control electrode 12 of the first transistor T1 expose both ends of the control electrode 12 of the first transistor T1. In the present disclosure, two of the plurality of via holes exposing the control electrode 12 of the first transistor T1 expose both ends of the control electrode 12 of the first transistor T1 to avoid static electricity in the shift register.

[0252] In an exemplary embodiment, the combination Figure 7 and Figure 10At least a portion of the control electrode 22 of the second transistor T2 extends along the first direction D1, and its orthographic projection on the substrate at least partially overlaps with an orthographic projection of at least one of the second clock signal line CLK2 and the first low-level power line VL1 on the substrate.

[0253] In an exemplary embodiment, the combination Figure 7 and Figure 10 The control electrode 42 of the fourth transistor T4 and the control electrode 62 of the sixth transistor T6 are an integral structure and at least partially extend along the first direction D1. The orthographic projection of the control electrode 42 of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of at least one of the third clock signal line CLK3 and the fourth clock signal line CLK4 on the substrate.

[0254] In an exemplary embodiment, the combination Figure 7 and Figure 10 The control electrode 52 of the fifth transistor T5 at least partially extends along the first direction D1, and the orthographic projection of the control electrode 52 on the substrate at least partially overlaps with the orthographic projection of at least one of the second clock signal line CLK2, the first low-level power line VL1, the third clock signal line CLK3 and the fourth clock signal line CLK4 on the substrate.

[0255] In an exemplary embodiment, the combination Figure 7 and Figure 10 The control electrode 72 of the seventh transistor T7 at least partially extends along the first direction D1, and the orthographic projection of the control electrode 72 on the substrate at least partially overlaps with the orthographic projection of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power line VL1, the third clock signal line CLK3 and the fourth clock signal line CLK4 on the substrate.

[0256] In an exemplary embodiment, Figure 11 As shown, the display substrate is further provided with a plurality of via holes H2 exposing the control electrode 72 of the seventh transistor T7. Two of the plurality of via holes exposing the control electrode 72 of the seventh transistor T7 expose both ends of the control electrode 72 of the seventh transistor T7. In the present disclosure, two of the plurality of via holes exposing the control electrode 72 of the seventh transistor T7 expose both ends of the control electrode 72 of the seventh transistor T7 to avoid static electricity in the shift register.

[0257] In an exemplary embodiment, the combination Figure 7 and Figure 10The control electrode 82 of the eighth transistor T8 at least partially extends along the first direction D1, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power line VL1, the third clock signal line CLK3, and the fourth clock signal line CLK4. In at least one stage of the shift register, the control electrode 82 of the eighth transistor T8 and the control electrode 112 of the eleventh transistor T11 are integrally structured.

[0258] In an exemplary embodiment, Figure 10 As shown, the display substrate may further include: a plurality of first connection lines L1 arranged on the base and located in the non-display area, one of the plurality of first connection lines L1 being electrically connected to the first electrode 53 of the fifth transistor T5 of at least one stage of the shift register, and the first connection line L1 extending along the first direction D1.

[0259] In an exemplary embodiment, the combination Figure 7 and Figure 10 The orthographic projections of the first electrode 53 of the fifth transistor of at least one stage of the shift register on the substrate at least partially overlap with the orthographic projections of the fourth clock signal line CLK4 and one of the first connection lines L1 among the multiple first connection lines on the substrate, and the orthographic projection of one of the first connection lines L1 among the multiple first connection lines on the substrate at least partially overlap with the orthographic projections of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power line VL1 and the third clock signal line CLK3 on the substrate.

[0260] In an exemplary embodiment, the film layer where the first connection line L1 is located is located on the side of the film layer where the first and second electrodes of at least one transistor of at least one stage of the shift register are located, close to the substrate. Figure 7 The description is made by taking the first connecting line L1 located in the second conductive layer as an example.

[0261] In an exemplary embodiment, Figure 11 As shown, the display substrate further includes: a plurality of via holes H3 exposing the first connection line L1, wherein two of the plurality of via holes exposing the first connection line respectively expose one end of the first connection line close to the display area and one end of the first connection line away from the display area. In the present disclosure, the two via holes exposing the first connection line respectively expose one end of the first connection line close to the display area and one end of the first connection line away from the display area to prevent static electricity in the shift register.

[0262] In an exemplary embodiment, Figure 7 and Figure 10As shown, the line width of one of the first low level power line VL1 and the second low level power line VL2 along the first direction D1 is smaller than the line width of at least one clock signal line in the first clock signal line group along the first direction D1.

[0263] In an exemplary embodiment, Figure 7 As shown, the display substrate also includes: a second clock signal line group arranged on the base and located in the non-display area, the second clock signal line group is located on the side of the first clock signal line group close to the display area, at least one level of shift register includes: a fourth clock signal terminal, the output sub-circuit of at least one level of shift register is electrically connected to the fourth clock signal terminal, and the second clock signal line group includes: a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7 and an eighth clock signal line CLK8 arranged in sequence along the direction close to the display area.

[0264] In an exemplary embodiment, Figure 7 As shown, the fifth clock signal line CLK5 and the seventh clock signal line CLK7 receive the same clock signal, the sixth clock signal line CLK6 and the eighth clock signal line CLK8 receive the same signal, and at least one clock signal line among the fifth clock signal line CLK5, the sixth clock signal line CLK6, the seventh clock signal line CLK7 and the eighth clock signal line CLK8 extends at least partially along the second direction D2.

[0265] In an exemplary embodiment, Figure 7 As shown, the fourth clock signal terminal of at least one stage of the shift register is electrically connected to one of the first signal line group and the second signal line group, and the fourth clock signal terminals of adjacent shift registers are connected to different signal line groups, wherein the first signal line group includes: the fifth clock signal line CLK5 and the seventh clock signal line CLK7, and the second signal line group includes: the sixth clock signal line CLK6 and the eighth clock signal line CLK8.

[0266] In an exemplary embodiment, Figure 7 As shown, the orthographic projection of the second low-level power line VL2 on the substrate is located between the orthographic projection of the sixth clock signal line CLK6 and the orthographic projection of the seventh clock signal line CLK7 on the substrate.

[0267] In an exemplary embodiment, when the fourth clock signal terminal of at least one shift register is electrically connected to the first signal line group, the first electrode of the tenth transistor T10 of at least one shift register is electrically connected to the seventh clock signal line CLK7, and the first plate of the third capacitor C3 of at least one shift register is electrically connected to the fifth clock signal line CLK5.

[0268] In an exemplary embodiment, when the fourth clock signal terminal of at least one shift register is electrically connected to the second signal line group, the first electrode of the tenth transistor T10 of at least one shift register is electrically connected to the eighth clock signal line CLK8, and the first plate of the third capacitor C3 of at least one shift register is electrically connected to the sixth clock signal line CLK6.

[0269] In an exemplary embodiment, Figure 7 As shown, the orthographic projection of at least one of the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 on the substrate is located between the orthographic projections of at least one of the transistors in the shift sub-circuit and the eleventh transistor T11 in the output sub-circuit, and the orthographic projections of at least one of the ninth transistor T9 and the tenth transistor T10 in the output sub-circuit on the substrate. The arrangement of the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 can reduce crossovers between the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 and other transistors, and can reduce overlap capacitance between the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 and other structures, thereby reducing the impact of noise on the output of the shift register.

[0270] In an exemplary embodiment, Figure 7 As shown, the orthographic projection of at least one of the seventh clock signal line CLK7 and the eighth clock signal line CLK8 on the substrate is located on a side of the orthographic projection of at least one of the ninth transistor T9 and the tenth transistor T10 in the output sub-circuit on the substrate close to the display area.

[0271] In an exemplary embodiment, Figure 7As shown, the line width of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the seventh clock signal line CLK7, and the eighth clock signal line CLK8 along the first direction D1 is greater than the line width of at least one of the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 along the first direction. The larger line width of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the seventh clock signal line CLK7, and the eighth clock signal line CLK8 can reduce the resistance of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the seventh clock signal line CLK7, and the eighth clock signal line CLK8, thereby achieving high-frequency output of the display substrate where the shift register is located.

[0272] In an exemplary embodiment, a line width of at least one of the seventh clock signal line CLK7 and the eighth clock signal line CLK8 along the first direction is in a range of 10 micrometers to 50 micrometers.

[0273] In an exemplary embodiment, at least one clock signal line of the fifth clock signal line CLK5 to the eighth clock signal line CLK8 includes: a first clock connection line and a second clock connection line that are arranged in different layers and are connected to each other, the first clock connection line and the second clock connection line at least partially extending along the second direction D2, and the orthographic projections of the first clock connection line and the second clock connection line of at least one clock signal line of the fifth clock signal line CLK5 to the eighth clock signal line CLK8 on the substrate at least partially overlap.

[0274] In an exemplary embodiment, the film layer where the first clock connection line of at least one of the fifth to eighth clock signal lines CLK5 to CLK8 is located is located on a side of the film layer where the second clock connection line is located that is closer to the substrate, and the second clock connection line of at least one of the fifth to eighth clock signal lines CLK5 to CLK8 is disposed in the same layer as at least one of the first to fourth clock signal lines CLK1 to CLK4. Exemplarily, the film layer where the first clock connection line of at least one of the fifth to eighth clock signal lines CLK5 to CLK8 is located is located on the third conductive layer, and the second clock connection line of at least one of the fifth to eighth clock signal lines CLK5 to CLK8 is located on the fourth conductive layer.

[0275] In an exemplary embodiment, Figure 7As shown, the display substrate further includes: an initial signal line STV and a high-level power line VH arranged on the base and located in the non-display area; at least one shift register includes: a signal input terminal and a high-level power terminal; the high-level power line VH is electrically connected to the high-level power terminal of the at least one shift register; the initial signal line STV is electrically connected to the signal input terminal of the at least one shift register; and at least a portion of at least one of the initial signal line STV and the high-level power line VH extends along the second direction D2.

[0276] In an exemplary embodiment, Figure 7 As shown, the orthographic projection of the initial signal line STV on the substrate is located on the side of the first clock signal line group away from the display area, and the orthographic projection of the high-level power line VH on the substrate is located between the orthographic projection of the first clock signal line group on the substrate and the orthographic projection of the second clock signal line group on the substrate.

[0277] In an exemplary embodiment, Figure 10 As shown, the orthographic projection of the high-level power line VH on the substrate at least partially overlaps with the orthographic projection of the control electrode of at least one of the fourth transistor T4 and the fifth transistor T5 in at least one stage of the shift register on the substrate.

[0278] In an exemplary embodiment, Figure 7 and Figure 10 As shown, the line width of the high-level power line VH along the first direction D1 is greater than the line width of at least one signal line among the first low-level power line VL1 and the initial signal line STV along the first direction D1, and is smaller than the line width of at least one clock signal line in the first clock signal line group along the first direction D1.

[0279] In an exemplary embodiment, Figure 7 As shown, the orthographic projection of the first capacitor C1 on the substrate is located between the orthographic projections of the first clock signal line group and the second clock signal line group on the substrate, and at least partially overlaps with the orthographic projection of the high-level power line VH on the substrate.

[0280] In an exemplary embodiment, Figure 7 As shown, the orthographic projection of the second capacitor C2 on the substrate is located between the orthographic projection of the second low-level power line VL2 on the substrate and the orthographic projection of the seventh clock signal line CLK7 on the substrate.

[0281] In an exemplary embodiment, Figure 7 As shown, the orthographic projection of the third capacitor C3 on the substrate is located between the orthographic projection of the sixth clock signal line CLK6 on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate, and at least partially overlaps with the orthographic projection of the second low-level power line VL2 on the substrate.

[0282] In an exemplary embodiment, at least one of the first plate and the second plate of the at least one capacitor includes a main body portion and a connecting portion, and the main body portion and the connecting portion of the at least one plate are connected.

[0283] In an exemplary embodiment, Figure 11 As shown, the orthographic projection of the main portion of the first electrode plate C11 of the first capacitor C1 on the substrate covers the orthographic projection of the main portion of the second electrode plate C12 of the first capacitor C1 on the substrate.

[0284] In an exemplary embodiment, Figure 11 As shown, the orthographic projection of the main body of the second electrode plate of the second capacitor C2 on the substrate covers the orthographic projection of the main body of the first electrode plate of the second capacitor C2 on the substrate.

[0285] In an exemplary embodiment, Figure 11 As shown, the orthographic projection of the main portion C32A of the second plate C32 of the third capacitor C3 on the substrate covers the orthographic projection of the main portion of the first plate C31 of the third capacitor C3 on the substrate. The first plate C31 of the third capacitor C3 is electrically connected to one of the fifth and sixth clock signal lines. The main portion C32A of the second plate C32 of the third capacitor C3 is the orthographic projection of the main portion of the first plate of the capacitor C3 on the substrate. The second plate C32 of the third capacitor C3 completely isolates the first plate C31 of the third capacitor from the second low-level power line VL2. This can prevent the clock signal of one of the fifth and sixth clock signal lines from affecting the second low-level power line VL2, reduce the coupling capacitance between the fifth and sixth clock signal lines, and further reduce the rising edge time and falling edge time of the output signal when the display substrate outputs high frequency, thereby ensuring the output stability of the shift register.

[0286] In an exemplary embodiment, Figure 11 As shown, the orthographic projection of the connecting portion C32B of the second plate C32 of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of at least one of the fifth clock signal line CLK5 and the sixth clock signal line CLK6 on the substrate.

[0287] In an exemplary embodiment, Figure 12 for Figure 7 A magnified view of a local area. Figure 12As shown, the length L11 of the main portion C32A of the second plate C32 of the third capacitor C3 along the first direction is greater than the line width L12 of the second low-level power line VL2 along the first direction, and the orthographic projection of a portion of at least one of a boundary of the second low-level power line VL2 close to the display area and a boundary away from the display area on the substrate is located within the range of the orthographic projection of the main portion of the second plate of the third capacitor C3 on the substrate.

[0288] In an exemplary embodiment, Figure 12 As shown, the distance W1 between the orthographic projection of the main portion of the second plate C32 of the third capacitor C3 away from the boundary of the display area on the substrate and the orthographic projection of the sixth clock signal line CLK6 close to the boundary of the display area on the substrate is greater than 1 micron, and the distance W1 between the orthographic projection of the main portion of the second plate C32 of the third capacitor C3 away from the boundary of the display area on the substrate is greater than 1 micron.

[0289] In an exemplary embodiment, Figure 12 As shown, the distance W3 between the orthographic projection of the main portion of the second plate of the third capacitor C3 close to the boundary of the display area on the substrate and the orthographic projection of the second low-level power line VL2 close to the boundary of the display area on the substrate is greater than 1 micron.

[0290] In an exemplary embodiment, Figure 7 and Figure 11 As shown, the area of ​​the first capacitor C1 is larger than the area of ​​at least one of the second capacitor C2 and the third capacitor C3.

[0291] In an exemplary embodiment, the capacitance value of the first capacitor C1 is greater than or equal to 0.3 PF. The capacitance value of the first capacitor C1 is relatively large to ensure the stability of the cascade signal output by the shift register.

[0292] In an exemplary embodiment, Figure 7 and Figure 11 As shown, the area of ​​the third capacitor C3 is larger than the area of ​​the second capacitor C2.

[0293] In an exemplary embodiment, Figure 11 As shown, the active pattern 11 of the first transistor T1 and the active pattern 31 of the third transistor T3 are arranged along a first direction, and a straight line extending along the first direction D1 passes through at least a portion of the control electrode 12 of the first transistor T1 and the active pattern 21 of the second transistor T2. The arrangement of the first to third transistors in the present disclosure facilitates connection between the first to third transistors and at least one clock signal line in the first clock signal line group.

[0294] In an exemplary embodiment, Figure 10As shown, the control electrode 102 of the tenth transistor T10 includes: a first connecting segment 102A, a second connecting segment 102B and a plurality of first branch segments 102C, the second connecting segment 102B is located on a side of the first connecting segment 102A close to the display area, and the plurality of first branch segments 102C are located on a side of the second connecting segment 102B close to the display area; the second electrode of the tenth transistor T10 includes: a third connecting segment 104A and a plurality of second branch segments 104B, and the plurality of second branch segments 104B are located on a side of the third connecting segment 104A close to the display area. Among them, the first connecting section 102A extends along the first direction D1, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of at least one signal line among the fifth clock signal line CLK5, the sixth clock signal line CLK6 and the second low-level power line VL2 on the substrate; the second connecting section 102B extends along the second direction D2, one of the multiple first branch sections 102C extends along the first direction D1, and the multiple first branch sections 102C are arranged along the second direction D2; the third connecting section 104A extends along the second direction D2, one of the multiple second branch sections 104B extends along the first direction D1, and the multiple second branch sections 104B are arranged along the second direction D2.

[0295] In an exemplary embodiment, Figure 10 As shown, the orthographic projection of the third connecting segment 104A on the substrate at least partially overlaps with the orthographic projection of the first connecting segment 102A on the substrate, and does not overlap with the orthographic projection of the second connecting segment 102B on the substrate. At least one of the plurality of first branch segments 102C does not overlap with the orthographic projections of the third connecting segment 104A and at least one of the plurality of second branch segments 104B on the substrate. The orthographic projection of at least one of the plurality of first branch segments 102C on the substrate is located between the orthographic projections of at least two of the plurality of second branch segments 104B on the substrate. The arrangement of the control electrode and the second electrode of the tenth transistor in the present disclosure can reduce the overlapping area between the second electrode and the control electrode of the tenth transistor, can improve the impact of noise on the output of the shift register, and can enhance the reliability of the shift register.

[0296] In an exemplary embodiment, the width-to-length ratio of the channel region of the active pattern of the tenth transistor T10 is greater than 40. The width-to-length ratio of the channel region of the active pattern of the tenth transistor T10 being greater than 40 can improve the output performance of the tenth transistor and reduce the rising edge time and falling edge time of the output signal of the shift register when the display substrate outputs at a high frequency.

[0297] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0298] Below Figure 9 The provided process for preparing the display substrate further illustrates the embodiments provided by the present disclosure.

[0299] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. Figure 13 As shown, Figure 13 for Figure 9 Schematic diagram after patterning the semiconductor layer.

[0300] In an exemplary embodiment, Figure 13 As shown, the semiconductor layer pattern may include at least active patterns of transistors located in at least one stage of the shift register, for example, active patterns 11 of the first transistor to 111 of the eleventh transistor.

[0301] In an exemplary embodiment, Figure 13As shown, the active pattern 21 of the second transistor and the active pattern 31 of the third transistor are an integrated structure, the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor are an integrated structure, and the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor are an integrated structure. The active pattern 11 of the first transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 81 of the eighth transistor, and the active pattern 111 of the eleventh transistor are provided separately.

[0302] In an exemplary embodiment, Figure 13 As shown, the active pattern 11 of the first transistor and the active pattern 81 of the eighth transistor are arranged along the second direction D2, and the active pattern 81 of the eighth transistor of the n-th stage shift register is located on the side of the active pattern 11 of the first transistor close to the (n+1)-th stage shift register. The integrated structure of the active pattern 21 of the second transistor and the active pattern 31 of the third transistor is located on the side of the active pattern 11 of the first transistor close to the display area. The integrated structure of the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor is located on the side of the integrated structure of the active pattern 21 of the second transistor and the active pattern 31 of the third transistor close to the display area. The active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, and the active pattern 111 of the eleventh transistor are located on a side of the integrated structure of the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor that is closer to the display area. The active pattern 41 of the fourth transistor of the n-th stage shift register is located on a side of the active pattern 51 of the fifth transistor that is away from the (n+1)-th stage shift register. The active pattern 111 of the eleventh transistor of the n-th stage shift register is located on a side of the active pattern 51 of the fifth transistor that is closer to the (n+1)-th stage shift register. The active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor are located on a side of at least one of the active patterns 41 of the fourth transistor, the active pattern 51 of the fifth transistor, and the active pattern 111 of the eleventh transistor that is closer to the display area. The active pattern 101 of the tenth transistor of the n-th stage shift register is located on a side of the active pattern 91 of the ninth transistor that is closer to the (n+1)-th stage shift register.

[0303] In an exemplary embodiment, any one of the active patterns 11 of the first transistor, 31 of the third transistor, 81 of the eighth transistor, 91 of the ninth transistor, and 101 of the tenth transistor of at least one stage of the shift register has a strip shape and extends along the second direction D2. At least one of the active patterns 21 of the second transistor, 41 of the fourth transistor, 51 of the fifth transistor, 61 of the sixth transistor, 71 of the seventh transistor, and 111 of the eleventh transistor extends at least partially along the first direction D1.

[0304] In an exemplary embodiment, the active pattern 21 of the second transistor and the active pattern 31 of the third transistor are disposed at right angles, and the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor are in a straight line shape.

[0305] In example embodiments, the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0306] like Figure 13 As shown, the second area 31-2 of the active pattern 31 of the third transistor can serve as the second area 21-1 of the active pattern 21 of the second transistor, the second area 61-2 of the active pattern 61 of the sixth transistor can serve as the first area 71-1 of the active pattern 71 of the seventh transistor, and the second area 91-2 of the active pattern 91 of the ninth transistor can serve as the second area 101-2 of the active pattern 101 of the tenth transistor. The first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 21-1 of the active pattern 21 of the second transistor, the first region 31-1 of the active pattern 31 of the third transistor, the first region 41-1 and the second region 41-2 of the active pattern 41 of the fourth transistor, the first region 51-1 and the second region 51-2 of the active pattern 51 of the fifth transistor, the first region 61-1 of the active pattern 61 of the sixth transistor, the second region 71-2 of the active pattern 71 of the seventh transistor, the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor, the first region 91-1 of the active pattern 91 of the ninth transistor, the first region 101-1 of the active pattern 101 of the tenth transistor, and the first region 111-1 and the second region 111-2 of the active pattern 111 of the eleventh transistor are separately provided.

[0307] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, such as Figures 14 and 15 As shown, Figure 14 for Figure 9 Schematic diagram of the first conductive layer pattern in Figure 15 for Figure 9 Schematic diagram after forming a first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0308] In an exemplary embodiment, Figure 14 and Figure 15 As shown, the first conductive layer pattern may include at least the control electrode of at least one transistor and the first plate of a capacitor, for example: the first conductive layer pattern includes: the control electrode 12 of the first transistor to the control electrode 112 of the eleventh transistor located in at least one level of shift register and the first plate C111 of the first capacitor to the first plate C31 of the third capacitor.

[0309] In this exemplary embodiment, the control electrode 12 of the first transistor and the control electrode 32 of the third transistor are integrally formed. The control electrode 12 of the first transistor is shaped like an "n" with its opening facing the display area and includes two branches extending along a first direction D1. The control electrode 32 of the third transistor is strip-shaped and extends along the first direction D1. The control electrode 32 of the third transistor is connected to one of the branches of the control electrode 12 of the first transistor. The control electrode 12 of the first transistor overlaps with the active pattern of the first transistor in two areas, thus, the first transistor has a dual-gate structure.

[0310] In an exemplary embodiment, the control electrode 22 of the second transistor is provided separately. The control electrode 22 of the second transistor is in an inverted "T" shape.

[0311] In an exemplary embodiment, the control electrode 42 of the fourth transistor and the control electrode 62 of the sixth transistor are integrally formed. The control electrode 42 of the fourth transistor is shaped like an "L" rotated 90 degrees to the right, and the control electrode 62 of the sixth transistor is shaped like an "F" rotated 90 degrees to the right.

[0312] In an exemplary embodiment, the control electrode 52 of the fifth transistor, the first plate C11 of the first capacitor, and the control electrode 102 of the tenth transistor are integrally formed. The control electrode 52 of the fifth transistor is located on the side of the first plate C11 of the first capacitor away from the display area, while the control electrode 102 of the tenth transistor is located on the side of the first plate C11 of the first capacitor closer to the display area. The control electrode 52 of the fifth transistor is strip-shaped and extends along the first direction D1. The first plate C11 of the first capacitor is rectangular. The control electrode 102 of the tenth transistor is comb-shaped, with the teeth located on the side of the back of the comb closer to the display area.

[0313] In an exemplary embodiment, the control electrode 72 of the seventh transistor is provided separately, and the control electrode 72 of the seventh transistor is in an inverted "T" shape.

[0314] In an exemplary embodiment, the control electrode 82 of the eighth transistor and the control electrode 112 of the eleventh transistor are integrally formed. The control electrode 82 of the eighth transistor is strip-shaped and extends along a first direction D1, and the control electrode 112 of the eleventh transistor is strip-shaped and extends along a second direction D2. The control electrodes 82 of the eighth transistor and 112 of the eleventh transistor are arranged at a right angle.

[0315] In an exemplary embodiment, the control electrode 92 of the ninth transistor and the first plate C21 of the second capacitor are integrally structured. There are multiple control electrodes 92 of the ninth transistor, each of which is strip-shaped and extends along the first direction D1. The main body of the first plate C21 of the second capacitor is rectangular. The connection portion of the first plate C21 of the second capacitor is located on the side of the main body of the first plate C21 of the second capacitor away from the display area. The control electrode 92 of the ninth transistor is located on the side of the first plate C21 of the second capacitor closer to the display area.

[0316] In an exemplary embodiment, the first plate C31 of the third capacitor is provided separately. The main body of the first plate C31 of the third capacitor is rectangular, and the connecting portion of the first plate C31 of the third capacitor is located on the side of the main body of the first plate C31 of the third capacitor away from the display area.

[0317] In an exemplary embodiment, the control electrode 12 of the first transistor (also the control electrode 32 of the third transistor) is arranged across the active pattern of the first transistor and the active pattern of the third transistor, the control electrode 22 of the second transistor is arranged across the active pattern of the second transistor, the control electrode 42 of the fourth transistor (also the control electrode 62 of the sixth transistor) is arranged across the active pattern of the fourth transistor and the active pattern of the sixth transistor, the control electrode 52 of the fifth transistor (also the first plate C21 of the first capacitor and the control electrode 102 of the tenth transistor) is arranged across the active pattern of the fifth transistor and the active pattern of the tenth transistor, the control electrode 72 of the seventh transistor is arranged across the active pattern of the seventh transistor, the control electrode 82 of the eighth transistor (also the control electrode 112 of the eleventh transistor) is arranged across the active pattern of the eighth transistor, and the control electrode 92 of the ninth transistor (also the first plate C21 of the second capacitor) is arranged across the active pattern of the ninth transistor.

[0318] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductively processed using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor to the twenty-sixth transistor, and the semiconductor layer in the area not shielded by the first conductive layer is conductively processed. That is, the first and second areas of the active pattern of any transistor from the first transistor to the fifteenth transistor are both conductively processed. Figure 15 As shown, the second region of the active pattern of the sixth transistor (also the first region of the active pattern of the seventh transistor) after being conductively connected in the present disclosure serves as the second electrode 64 of the sixth transistor (also the first electrode 73 of the seventh transistor).

[0319] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process to form a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, such as Figure 16 and Figure 17 As shown, Figure 16 for Figure 9 Schematic diagram of the second conductive layer pattern, Figure 17 for Figure 9 Schematic diagram after forming a second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0320] In an exemplary embodiment, Figure 16 and Figure 17 As shown, the second conductive layer pattern may include at least: the second plate of the first capacitor, for example: including: the second plate C12 of the first capacitor to the second plate C32 of the third capacitor located in at least one level of shift register, the first connecting line L1, the second connecting line L2, the third connecting line L3 and the drive signal output line OUTL.

[0321] In an exemplary embodiment, the second electrode plate C12 of the first capacitor is rectangular. The orthographic projection of the main portion of the second electrode plate C12 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the main portion of the first electrode plate of the first capacitor on the substrate. Exemplarily, the orthographic projection of the main portion of the first electrode plate of the first capacitor on the substrate covers the orthographic projection of the main portion of the second electrode plate C12 of the first capacitor on the substrate.

[0322] In an exemplary embodiment, the second plate C22 of the second capacitor is rectangular. The orthographic projection of the main portion of the second plate C22 of the second capacitor on the substrate at least partially overlaps the orthographic projection of the main portion of the first plate of the second capacitor on the substrate. Exemplarily, the orthographic projection of the main portion of the second plate C22 of the second capacitor on the substrate covers the orthographic projection of the main portion of the first plate of the second capacitor on the substrate.

[0323] In an exemplary embodiment, the main portion of the second electrode plate C32 of the third capacitor is rectangular in shape. The orthographic projection of the main portion of the second electrode plate C32 of the third capacitor on the substrate at least partially overlaps with the orthographic projection of the main portion of the first electrode plate of the third capacitor on the substrate. Exemplarily, the orthographic projection of the main portion of the second electrode plate C32 of the third capacitor on the substrate covers the orthographic projection of the main portion of the first electrode plate of the third capacitor on the substrate. The second electrode plate C32 of the third capacitor includes two connecting portions, one of which is located on a side of the main portion of the second electrode plate C32 of the third capacitor away from the display area, and the other connecting portion of the second electrode plate C32 of the third capacitor is located on a side of the main portion of the second electrode plate C32 of the third capacitor closer to the display area.

[0324] In an exemplary embodiment, the first connection line L1 is located on a side of the second plate C12 of the first capacitor away from the display area. The first connection line L1 is linear and at least partially extends along the first direction D1.

[0325] In an exemplary embodiment, the second connection line L2 is located on a side of the second plate C32 of the third capacitor away from the display area. The second connection line L2 is linear and at least partially extends along the first direction D1.

[0326] In an exemplary embodiment, the third connection line L3 is located on a side of the second plate C22 of the second capacitor close to the display area. The third connection line L3 is linear and at least partially extends along the first direction D1.

[0327] In an exemplary embodiment, the driving signal output line OUTL is located on a side of the second plate C12 of the first capacitor close to the display area. The driving signal output line OUTL is linear and at least partially extends along the first direction D1.

[0328] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, such as Figure 18 As shown, Figure 18 for Figure 9Schematic diagram after forming the third insulation layer pattern.

[0329] In an exemplary embodiment, Figure 18 As shown, the third insulation layer pattern may include at least: first to thirty-fourth via holes V1 to V34 located in at least one stage of the shift register.

[0330] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the first insulating layer and the second insulating layer within the first via V1 are etched away to expose the surface of the first area of ​​the active pattern of the first transistor, and the first via V1 is configured to connect the first electrode of the subsequently formed first transistor to the first area of ​​the active pattern of the first transistor through the via.

[0331] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second area of ​​the active pattern of the first transistor, and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor (which is also the first electrode of the eighth transistor) to the second area of ​​the active pattern of the first transistor through the via.

[0332] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second transistor on the substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away, exposing the surface of the first area of ​​the active pattern of the second transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of ​​the active pattern of the second transistor through the via.

[0333] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the third transistor) on the substrate, the first insulating layer and the second insulating layer in the fourth via V4 are etched away to expose the surface of the second area of ​​the active pattern of the second transistor, and the fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the third transistor) through the via.

[0334] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the third transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active pattern of the third transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of ​​the active pattern of the third transistor through the via.

[0335] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the first area of ​​the active pattern of the fourth transistor, and the sixth via V6 is configured to connect the first electrode of the subsequently formed fourth transistor (which is also the first electrode of the sixth transistor) to the first area of ​​the active pattern of the fourth transistor through the via.

[0336] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the second area of ​​the active pattern of the fourth transistor, and the seventh via V7 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second area of ​​the active pattern of the fourth transistor through the via.

[0337] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the first area of ​​the active pattern of the fifth transistor, and the eighth via V8 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active pattern of the fifth transistor through the via.

[0338] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the second area of ​​the active pattern of the fifth transistor, and the ninth via V9 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second area of ​​the active pattern of the fifth transistor through the via.

[0339] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the sixth transistor on the substrate, the first insulating layer and the second insulating layer within the tenth via V10 are etched away, exposing the surface of the first area of ​​the active pattern of the sixth transistor, and the tenth via V10 is configured to connect the first electrode of the subsequently formed fourth transistor (the first electrode of the sixth transistor) to the first area of ​​the active pattern of the sixth transistor through the via.

[0340] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the seventh transistor on the substrate, the first insulating layer and the second insulating layer within the eleventh via V11 are etched away, exposing the surface of the second area of ​​the active pattern of the seventh transistor, and the eleventh via V11 is configured to connect the second electrode of the subsequently formed seventh transistor to the second area of ​​the active pattern of the seventh transistor through the via.

[0341] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the first area of ​​the active pattern of the eighth transistor, and the twelfth via V12 is configured to connect the first electrode of the subsequently formed first transistor (which is also the first electrode of the eighth transistor) to the first area of ​​the active pattern of the eighth transistor through the via.

[0342] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the thirteenth via V13 are etched away, exposing the surface of the second area of ​​the active pattern of the eighth transistor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed eighth transistor to the second area of ​​the active pattern of the eighth transistor through the via.

[0343] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the ninth transistor on the substrate, the first insulating layer and the second insulating layer in the fourteenth via V14 are etched away to expose the surface of the first area of ​​the active pattern of the ninth transistor, and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed ninth transistor to the first area of ​​the active pattern of the ninth transistor through the via.

[0344] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the ninth transistor on the substrate, the first insulating layer and the second insulating layer within the fifteenth via V15 are etched away, exposing the surface of the second area of ​​the active pattern of the ninth transistor, and the fifteenth via V15 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to the second area of ​​the active pattern of the ninth transistor through the via.

[0345] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the tenth transistor on the substrate, the first insulating layer and the second insulating layer in the sixteenth via V16 are etched away to expose the surface of the first area of ​​the active pattern of the tenth transistor, and the sixteenth via V16 is configured to connect the first electrode of the subsequently formed tenth transistor to the first area of ​​the active pattern of the tenth transistor through the via.

[0346] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the tenth transistor on the substrate, the first insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the second area of ​​the active pattern of the tenth transistor, and the seventeenth via V17 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to the second area of ​​the active pattern of the tenth transistor through the via.

[0347] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the first area of ​​the active pattern of the eleventh transistor, and the eighteenth via V18 is configured to connect the first electrode of the subsequently formed eleventh transistor to the first area of ​​the active pattern of the eleventh transistor through the via.

[0348] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the nineteenth via V19 are etched away to expose the surface of the second area of ​​the active pattern of the eleventh transistor, and the nineteenth via V19 is configured to connect the second electrode of the subsequently formed eleventh transistor to the second area of ​​the active pattern of the eleventh transistor through the via.

[0349] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor (also the control electrode of the third transistor) on the substrate, the second insulating layer in the twentieth via V20 is etched away to expose the surface of the control electrode of the first transistor (also the control electrode of the third transistor), and the twentieth via V20 is configured to connect the subsequently formed multiple first connecting electrodes and the first electrode of the second transistor to the control electrode of the first transistor (also the control electrode of the third transistor) through the via.

[0350] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the control electrode of the second transistor on the substrate, the second insulating layer in the twenty-first via V21 is etched away to expose the surface of the control electrode of the second transistor, and the twenty-first via V21 is configured to connect the second electrode of the first transistor (also the first electrode of the eighth transistor) and the second electrode of the seventh transistor formed subsequently to the control electrode of the second transistor through the via.

[0351] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the control electrode of the fourth transistor (also the control electrode of the sixth transistor) on the substrate, the second insulating layer in the twenty-second via V22 is etched away to expose the surface of the control electrode of the fourth transistor (also the control electrode of the sixth transistor), and the twenty-second via V22 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) and the first electrode of the eleventh transistor to the control electrode of the fourth transistor (also the control electrode of the sixth transistor) through the via.

[0352] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the control electrode of the fifth transistor (which is also the control electrode of the tenth transistor and the first plate of the first capacitor) on the substrate, and the second insulating layer in the twenty-third via V23 is etched away to expose the surface of the control electrode of the fifth transistor (which is also the control electrode of the tenth transistor and the first plate of the first capacitor). The twenty-third via V23 is configured to connect the second electrode of the subsequently formed eighth transistor to the control electrode of the fifth transistor (which is also the control electrode of the tenth transistor and the first plate of the first capacitor) through the via.

[0353] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the control electrode of the seventh transistor on the substrate, the second insulating layer in the twenty-fourth via V24 is etched away to expose the surface of the control electrode of the seventh transistor, and the twenty-fourth via V24 is configured to connect multiple third connecting electrodes formed subsequently to the control electrode of the seventh transistor through the via.

[0354] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the control electrode of the eighth transistor (also the control electrode of the eleventh transistor) on the substrate, the second insulating layer in the twenty-fifth via V25 is etched away to expose the surface of the control electrode of the eighth transistor (also the control electrode of the eleventh transistor), and the twenty-fifth via V25 is configured to connect the fourth connecting electrode to the control electrode of the eighth transistor (also the control electrode of the eleventh transistor) through the via.

[0355] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the control electrode of the ninth transistor (also the first plate of the second capacitor) on the substrate, the second insulating layer in the twenty-sixth via V26 is etched away, exposing the surface of the control electrode of the ninth transistor (also the first plate of the second capacitor), and the twenty-sixth via V26 is configured to connect the subsequently formed fifth connecting electrode to the control electrode of the ninth transistor (also the first plate of the second capacitor) through the via.

[0356] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the first plate of the third capacitor on the substrate, the second insulating layer in the twenty-seventh via V27 is etched away to expose the surface of the first plate of the third capacitor, and the twenty-seventh via V27 is configured to connect the first clock connection line of one of the subsequently formed fifth clock signal lines and the sixth clock signal line to the first plate of the third capacitor through the via.

[0357] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate, the twenty-eighth via V28 exposes the surface of the second plate of the first capacitor, and the twenty-eighth via V28 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second plate of the first capacitor through the via.

[0358] In an exemplary embodiment, the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the twenty-ninth via V29 exposes the surface of the second plate of the second capacitor, and the twenty-ninth via V29 is configured to connect the first electrode of the subsequently formed ninth transistor to the second plate of the second capacitor through the via.

[0359] In an exemplary embodiment, the orthographic projection of the thirtieth via V30 on the substrate is located within the range of the orthographic projection of the second plate of the third capacitor on the substrate, the thirtieth via V30 exposes the surface of the second plate of the third capacitor, and the thirtieth via V30 is configured to connect the second electrode of the subsequently formed eleventh transistor to the second plate of the third capacitor through the via.

[0360] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the thirty-first via V31 exposes the surface of the second connecting line, and the thirty-first via V31 is configured to connect the first electrode of the subsequently formed first transistor and the cascade signal output line to the second connecting line through the via.

[0361] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the thirty-second via V32 exposes the surface of the first connecting line, and the thirty-second via V32 is configured to connect the first electrode and multiple second connecting electrodes of the subsequently formed fifth transistor to the first connecting line through the via.

[0362] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the third connecting line on the substrate, the thirty-third via V33 exposes the surface of the third connecting line, and the thirty-third via V33 is configured to connect the first electrode of the subsequently formed tenth transistor and the first clock connecting line of one of the seventh clock signal line and the eighth clock signal line to the third connecting line through the via.

[0363] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the drive signal output line on the substrate, the thirty-fourth via V34 exposes the surface of the drive signal output line, and the thirty-fourth via V34 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to the drive signal output line through the via.

[0364] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fifth insulating layer, Figure 19 and Figure 20 As shown, Figure 19 for Figure 9 Schematic diagram of the third conductive layer pattern in FIG. Figure 20 for Figure 9Schematic diagram after forming the third conductive layer pattern. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0365] In an exemplary embodiment, Figure 19 and Figure 20 As shown, the third conductive layer pattern may include at least: an initial signal line STV, a first clock connection line CLK5A of a fifth clock signal line, a first clock connection line CLK6A of a sixth clock signal line, a first clock connection line CLK7A of a seventh clock signal line, a first clock connection line CLK8A of an eighth clock signal line, a first second power connection line VL21 of a second low-level power line VL2, and a first electrode 13 and a second electrode 14 of a first transistor to a first electrode 113 and a second electrode 114 of an eleventh transistor located in at least one stage of a shift register, a plurality of first connection electrodes E1, a plurality of second connection electrodes E2, a plurality of third connection electrodes E3, a fourth connection electrode E4 and a fifth connection electrode E5.

[0366] In an exemplary embodiment, at least one signal line among the initial signal line STV, the first clock connection line CLK5A of the fifth clock signal line, the first clock connection line CLK6A of the sixth clock signal line, the first clock connection line CLK7A of the seventh clock signal line, the first clock connection line CLK8A of the eighth clock signal line, and the first second power connection line VL21 of the second low-level power line VL2 extends at least partially along the second direction D2, and the initial signal line STV, the first clock connection line CLK5A of the fifth clock signal line, the first clock connection line CLK6A of the sixth clock signal line, the first second power connection line VL21 of the second low-level power line VL2, the first clock connection line CLK7A of the seventh clock signal line, and the first clock connection line CLK8A of the eighth clock signal line are arranged in sequence along a direction close to the display area.

[0367] In an exemplary embodiment, the initial signal line STV is located at a side of the first electrode and the second electrode of at least one transistor in at least one stage of the shift register that is away from the display area.

[0368] In an exemplary embodiment, the first clock connection line CLK5A of the fifth clock signal line, the first clock connection line CLK6A of the sixth clock signal line, and the first second power connection line VL21 of the second low-level power line VL2 are located on a side where the first pole and the second pole of at least one transistor among the first to eighth transistors and the eleventh transistor in at least one stage of the shift register are close to the display area, and are located on a side where the first pole and the second pole of at least one transistor among the ninth transistor and the tenth transistor in at least one stage of the shift register are away from the display area.

[0369] In an exemplary embodiment, the first clock connection line CLK7A of the seventh clock signal line and the first clock connection line CLK8A of the eighth clock signal line are located on a side of the first electrode and the second electrode of at least one of the ninth transistor and the tenth transistor in at least one stage of the shift register close to the display area.

[0370] In an exemplary embodiment, the first electrode 13 of the first transistor is provided separately. The first electrode 13 of the first transistor is strip-shaped and extends at least partially along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through a first via hole and is connected to the second connection line through a thirty-first via hole.

[0371] In an exemplary embodiment, the second electrode 14 of the first transistor and the first electrode 83 of the eighth transistor are integrally formed. The integral structure of the second electrode 14 of the first transistor and the first electrode 83 of the eighth transistor is in the shape of a broken line and extends at least partially along the second direction D2. The second electrode 14 of the first transistor (also the first electrode 83 of the eighth transistor) is connected to the second region of the active pattern of the first transistor via a second via, connected to the first region of the active pattern of the eighth transistor via a twelfth via, and connected to the control electrode of the second transistor via a twenty-first via.

[0372] In the exemplary embodiment, the first electrode 23 of the second transistor is provided separately. The first electrode 23 of the second transistor is strip-shaped and extends along the first direction D1. The first electrode 23 of the second transistor is connected to the first region of the active pattern of the second transistor through a third via hole, and is connected to the control electrode of the first transistor (which is also the control electrode of the third transistor) through a twentieth via hole.

[0373] In the exemplary embodiment, the second electrode 24 of the second transistor and the second electrode 34 of the third transistor are integrally formed. The integral structure of the second electrode 24 of the second transistor and the second electrode 34 of the third transistor is strip-shaped and extends along the first direction D1. The second electrode 24 of the second transistor (also the second electrode 34 of the third transistor) is connected to the second region of the active pattern of the third transistor via a fourth via hole, and is connected to the control electrode of the fourth transistor (also the control electrode of the sixth transistor) via a twenty-second via hole.

[0374] In an exemplary embodiment, the first electrode 33 of the third transistor is separately provided. The first electrode 33 of the third transistor is in a strip shape and extends along the first direction D1. The first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through a fifth via hole.

[0375] In an exemplary embodiment, the first electrode 43 of the fourth transistor and the first electrode 63 of the sixth transistor are integrally formed. The integral structure of the first electrode 43 of the fourth transistor and the first electrode 63 of the sixth transistor is in the shape of a zigzag line and extends at least partially along the first direction D1. The first electrode 43 of the fourth transistor (also the first electrode 63 of the sixth transistor) is connected to the first region of the active pattern of the fourth transistor via a sixth via, and is connected to the first region of the active pattern of the sixth transistor via a tenth via.

[0376] In an exemplary embodiment, the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor are integrally formed. The integral structure of the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor forms an "n" shape with the opening facing away from the display area. The second electrode 44 of the fourth transistor (the second electrode 54 of the fifth transistor) is connected to the second region of the active pattern of the fourth transistor via a seventh via, to the second region of the active pattern of the fifth transistor via a ninth via, and to the second plate of the first capacitor via a twenty-eighth via.

[0377] In the exemplary embodiment, the first electrode 53 of the fifth transistor is separately provided. The first electrode 53 of the fifth transistor is strip-shaped and extends along the first direction D1. The first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor through the eighth via hole and is connected to the first connection line through the thirty-second via hole.

[0378] In the exemplary embodiment, the second electrode 74 of the seventh transistor is separately provided. The second electrode 74 of the seventh transistor is strip-shaped and extends along the first direction D1. The second electrode 74 of the seventh transistor is connected to the second region of the active pattern of the seventh transistor through the eleventh via hole and is connected to the first connection line through the thirty-second via hole.

[0379] In the exemplary embodiment, the second electrode 84 of the eighth transistor is separately provided. The second electrode 84 of the eighth transistor is strip-shaped and extends along the first direction D1. The second electrode 84 of the eighth transistor is connected to the second region of the active pattern of the eighth transistor through a thirteenth via hole, and is connected to the control electrode of the fifth transistor (which is also the control electrode of the tenth transistor and the first plate of the first capacitor) through a twenty-third via hole.

[0380] In an exemplary embodiment, the first electrode 93 of the ninth transistor is integrally formed with the first second power connection line VL21 of the second low-level power line. The first electrode 93 of the ninth transistor is strip-shaped and extends along the first direction D1. The first electrode 93 of the ninth transistor is connected to the first region of the active pattern of the ninth transistor via a fourteenth via and to the second plate of the second capacitor via a twenty-ninth via.

[0381] In an exemplary embodiment, the second electrode 94 of the ninth transistor and the second electrode 104 of the tenth transistor are integrally structured. The second electrode 94 of the ninth transistor is shaped like an "n" with its opening facing away from the display area, while the second electrode 104 of the tenth transistor is shaped like an "m" with its opening facing the display area. A side of the second electrode 94 of the ninth transistor extending along the first direction D1 is the same side as a side of the second electrode 104 of the tenth transistor extending along the first direction D1. The second electrode 94 of the ninth transistor (also the second electrode 104 of the tenth transistor) is connected to the second region of the active pattern of the ninth transistor via a fifteenth via, to the second region of the active pattern of the tenth transistor via a seventeenth via, and to the drive signal output line via a thirty-fourth via.

[0382] In an exemplary embodiment, the first electrode 103 of the tenth transistor is separately provided. The first electrode 103 of the tenth transistor is shaped like an "n" with its opening facing away from the display area. The first electrode 103 of the tenth transistor is connected to the first region of the active pattern of the tenth transistor via a sixteenth via hole and to the third connection line via a thirty-third via hole.

[0383] In an exemplary embodiment, the first electrode 113 of the eleventh transistor is separately provided. The first electrode 113 of the eleventh transistor is strip-shaped and extends along the second direction. The first electrode 113 of the eleventh transistor is connected to the first region of the active pattern of the eleventh transistor through an eighteenth via hole, and is connected to the control electrode of the fourth transistor (also the control electrode of the sixth transistor) through a twenty-second via hole.

[0384] In an exemplary embodiment, the second electrode 114 of the eleventh transistor is separately provided. The second electrode 114 of the eleventh transistor is strip-shaped and extends along the second direction D2. The second electrode 114 of the eleventh transistor is connected to the second region of the active pattern of the eleventh transistor via a nineteenth via and to the second plate of the third capacitor via a thirtieth via.

[0385] In an exemplary embodiment, there are four first connection electrodes E1. The first to fourth first connection electrodes E1 are sequentially arranged in a direction close to the display area. The first, third, and fourth first connection electrodes are arranged along a first direction. The first electrode 23 of the second transistor is reused as a second first connection electrode. At least one of the plurality of first connection electrodes is connected to the control electrode of the first transistor (which is also the control electrode of the third transistor) through a twentieth via.

[0386] In an exemplary embodiment, there are four second connection electrodes E2. The first through fourth second connection electrodes E2 are sequentially arranged in a direction approaching the display area. The first electrode 53 of the fifth transistor is multiplexed as the fourth second connection electrode. At least one of the plurality of second connection electrodes is connected to the first connection line via a thirty-second via.

[0387] In an exemplary embodiment, there are four third connection electrodes E3, and the first third connection electrode E3 to the fourth second connection electrode E3 are sequentially arranged in a direction close to the display area. At least one of the plurality of third connection electrodes is connected to the control electrode of the seventh transistor through the twenty-fourth via hole.

[0388] In an exemplary embodiment, the fourth connection electrode E4 is in a strip shape and extends along the second direction D2. The fourth connection electrode E4 is connected to the control electrode of the eighth transistor (also the control electrode of the eleventh transistor) through the twenty-fifth via hole.

[0389] In an exemplary embodiment, the fifth connection electrode E5 is strip-shaped and extends along the first direction D1. The fifth connection electrode E5 is connected to the control electrode of the ninth transistor (also the first plate of the second capacitor) through a twenty-sixth via hole.

[0390] In an exemplary embodiment, the clock signal line (ie, one of the fifth and sixth clock signal lines) connected to the first plate of the third capacitor of the shift register is connected to the first plate of the third capacitor through the twenty-seventh via.

[0391] In an exemplary embodiment, the clock signal line (ie, one of the seventh and eighth clock signal lines) to which the first electrode of the tenth transistor of the shift register is connected is connected to the third connection line through a thirty-third via.

[0392] In an exemplary embodiment, the nth cascade signal output line OUTCL(n) is integrally formed with the second electrode 54 of the fourth transistor and the second electrode 54 of the fifth transistor in the nth stage shift register, and is connected to the second connection line in the n+1th stage shift register via a thirty-first via. The second electrode 54 of the fourth transistor and the second electrode 54 of the fifth transistor in the nth stage shift register are sequentially connected to the first electrode 13 of the first transistor in the n+1th stage shift register via the nth cascade signal output line OUTCL(n) and the second connection line in the n+1th stage shift register.

[0393] In an exemplary embodiment, the provision of the first to fifth connection electrodes can reduce the depth of the via hole in the display substrate, thereby improving the reliability of the display substrate.

[0394] (6) Forming a first planar layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: first depositing a fourth insulating film on a substrate having the aforementioned pattern, then coating a first planar film, patterning the fourth insulating film and the first planar film through a patterning process to form a fourth insulating layer covering the aforementioned structure and a first planar layer disposed on the fourth insulating layer, wherein the first planar layer is provided with a plurality of via patterns, such as Figure 21 As shown, Figure 21 for Figure 9 Schematic diagram after forming the first planar layer pattern.

[0395] In an exemplary embodiment, Figure 21 As shown, the planar layer pattern may include at least: a thirty-fifth via hole V35 to a forty-fourth via hole V44 located in at least one stage of the shift register.

[0396] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the orthographic projection of one of the plurality of first connection electrodes on the substrate. The fourth insulating layer within the thirty-fifth via V35 is etched away, exposing the surface of one of the plurality of first connection electrodes. The thirty-fifth via V35 is configured to connect one of the subsequently formed clock signal lines of the first clock signal line group to the one of the plurality of first connection electrodes through the via. Exemplarily, the thirty-fifth via in the 4i-3 stage shift register exposes the orthographic projection of the first first connection electrode on the substrate, the thirty-fifth via in the 4i-2 stage shift register exposes the orthographic projection of the second first connection electrode on the substrate, the thirty-fifth via in the 4i-1 stage shift register exposes the orthographic projection of the third first connection electrode on the substrate, and the thirty-fifth via in the 4i stage shift register exposes the orthographic projection of the fourth first connection electrode on the substrate.

[0397] In an exemplary embodiment, the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the first electrode of the third transistor on the substrate, the fourth insulating layer in the thirty-sixth via V36 is etched away to expose the surface of the first electrode of the third transistor, and the thirty-sixth via V36 is configured to connect the subsequently formed first low-level power line to the first electrode of the third transistor through the via.

[0398] In an exemplary embodiment, the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor (the first electrode of the sixth transistor) on the substrate, the fourth insulating layer in the thirty-seventh via V37 is etched away to expose the surface of the first electrode of the second transistor, and the thirty-seventh via V37 is configured to connect a subsequently formed high-level power line to the first electrode of the fourth transistor (the first electrode of the sixth transistor) through the via.

[0399] In an exemplary embodiment, the orthographic projection of the thirty-eighth via V38 on the substrate is within the range of the orthographic projection of one of the plurality of second connection electrodes on the substrate. The fourth insulating layer within the thirty-eighth via V38 is etched away, exposing the surface of one of the plurality of second connection electrodes. The thirty-eighth via V38 is configured to connect one of the clock signal lines in a subsequently formed clock signal line group to one of the plurality of second connection electrodes through the via. Exemplarily, the thirty-eighth via in the 4i-3 stage shift register exposes the range of the orthographic projection of the third second connection electrode on the substrate, the thirty-eighth via in the 4i-2 stage shift register exposes the range of the orthographic projection of the fourth second connection electrode on the substrate, the thirty-eighth via in the 4i-1 stage shift register exposes the range of the orthographic projection of the first second connection electrode on the substrate, and the thirty-eighth via in the 4i stage shift register exposes the range of the orthographic projection of the second first connection electrode on the substrate.

[0400] In an exemplary embodiment, the orthographic projection of the thirty-ninth via V39 on the substrate is within the range of the orthographic projection of one of the plurality of third connection electrodes on the substrate. The fourth insulating layer within the thirty-ninth via V39 is etched away, exposing the surface of one of the plurality of third connection electrodes. The thirty-ninth via V39 is configured to connect one of the clock signal lines in the subsequently formed first clock signal line group to one of the plurality of third connection electrodes through the via. Exemplarily, the thirty-ninth via in the 4i-3 stage shift register exposes the range of the orthographic projection of the fourth third connection electrode on the substrate, the thirty-ninth via in the 4i-2 stage shift register exposes the range of the orthographic projection of the first third connection electrode on the substrate, the thirty-ninth via in the 4i-1 stage shift register exposes the range of the orthographic projection of the second third connection electrode on the substrate, and the thirty-ninth via in the 4i stage shift register exposes the range of the orthographic projection of the third first connection electrode on the substrate.

[0401] In an exemplary embodiment, the orthographic projection of the 40th via hole V40 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode on the substrate, the fourth insulating layer in the 40th via hole V40 is etched away to expose the surface of the fourth connecting electrode, and the 40th via hole V40 is configured to electrically connect a subsequently formed first low-level power line to the fourth connecting electrode through the via hole.

[0402] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the first clock connection line of the fifth clock signal line on the substrate, the fourth insulating layer in the forty-first via V41 is etched away to expose the surface of the first clock connection line of the fifth clock signal line, and the forty-first via V41 is configured to connect the subsequently formed second clock connection line of the fifth clock signal line to the first clock connection line of the fifth clock signal line through the via.

[0403] In an exemplary embodiment, the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the first clock connection line of the sixth clock signal line on the substrate, the fourth insulating layer in the forty-second via V42 is etched away to expose the surface of the first clock connection line of the sixth clock signal line, and the forty-second via V42 is configured to connect the second clock connection line of the sixth clock signal line formed subsequently to the first clock connection line of the sixth clock signal line through the via.

[0404] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the first clock connection line of the seventh clock signal line on the substrate, the fourth insulating layer in the forty-third via V43 is etched away to expose the surface of the first clock connection line of the seventh clock signal line, and the forty-third via V43 is configured to connect the second clock connection line of the seventh clock signal line formed subsequently to the first clock connection line of the seventh clock signal line through the via.

[0405] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the first clock connection line of the eighth clock signal line on the substrate, the fourth insulating layer in the forty-fourth via V44 is etched away to expose the surface of the first clock connection line of the eighth clock signal line, and the forty-fourth via V44 is configured to connect the subsequently formed second clock connection line of the eighth clock signal line to the first clock connection line of the eighth clock signal line through the via.

[0406] In an exemplary embodiment, the orthographic projection of the forty-fifth via V45 on the substrate is located within the range of the orthographic projection of the first second power connection line of the second low-level power line on the substrate, the fourth insulating layer in the forty-fifth via V45 is etched away to expose the surface of the first second power connection line of the second low-level power line, and the forty-fifth via V45 is configured to connect the second second power connection line of the second low-level power line formed subsequently to the first second power connection line of the second low-level power line through the via.

[0407] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fourth insulating layer, such as Figure 22 and Figure 23 shown. Figure 22 for Figure 9 A schematic diagram of a fourth conductive layer pattern, Figure 23 for Figure 9 Schematic diagram after forming the fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0408] In an exemplary embodiment, Figure 22 and Figure 23 As shown, the fourth conductive layer pattern may include at least: a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a first low-level power line VL, a high-level power line VH, a second second power connection line VL22 of the second low-level power line, a second clock connection line CLK5B of the fifth clock signal line, a second clock connection line CLK6B of the sixth clock signal line, a second clock connection line CLK7B of the seventh clock signal line and a second clock connection line CLK8B of the eighth clock signal line.

[0409] In an exemplary embodiment, at least one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the first low-level power line VL, the high-level power line VH, the second second power connection line VL22 of the second low-level power line, the second clock connection line CLK5B of the fifth clock signal line, the second clock connection line CLK6B of the sixth clock signal line, the second clock connection line CLK7B of the seventh clock signal line, and the second clock connection line CLK8B of the eighth clock signal line extends at least partially along the second direction D2.

[0410] In an exemplary embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power line VL, the third clock signal line CLK3, the fourth clock signal line CLK4, the high-level power line VH, the second clock connection line CLK5B of the fifth clock signal line, the second clock connection line CLK6B of the sixth clock signal line, the second second power connection line VL22 of the second low-level power line, the second clock connection line CLK7B of the seventh clock signal line, and the second clock connection line CLK8B of the eighth clock signal line are arranged in sequence along a direction close to the display area.

[0411] In an exemplary embodiment, the first clock signal line CLK1 is connected to the first first connection electrode through the thirty-fifth via in the 4i-3 stage shift register, is connected to the first second connection electrode through the thirty-eighth via in the 4i-1 stage shift register, and is connected to the first third connection electrode through the thirty-ninth via in the 4i-2 stage shift register.

[0412] In an exemplary embodiment, the second clock signal line CLK2 is connected to the second connection electrode through the thirty-fifth via in the 4i-2 stage shift register, is connected to the second first connection electrode through the thirty-eighth via in the 4i stage shift register, and is connected to the second third connection electrode through the thirty-ninth via in the 4i-1 stage shift register.

[0413] In an exemplary embodiment, the third clock signal line CLK3 is connected to the third first connection electrode through the thirty-fifth via in the 4i-1th level shift register, is connected to the third second connection electrode through the thirty-eighth via in the 4i-3th level shift register, and is connected to the third first connection electrode through the thirty-ninth via in the 4i-level shift register.

[0414] In an exemplary embodiment, the fourth clock signal line CLK4 is connected to the fourth first connection electrode through the thirty-fifth via in the 4i-stage shift register, is connected to the fourth second connection electrode through the thirty-eighth via in the 4i-2-stage shift register, and is connected to the fourth third connection electrode through the thirty-ninth via in the 4i-3-stage shift register.

[0415] In an exemplary embodiment, the first low-level power line VL1 is connected to the first electrode of the third transistor through a thirty-sixth via hole, and is electrically connected to the fourth connection electrode through a fortieth via hole.

[0416] In the exemplary embodiment, the high-level power line VH is connected to the first electrode of the fourth transistor (the first electrode of the sixth transistor) through the thirty-seventh via.

[0417] In an exemplary embodiment, an orthographic projection of the second clock connection line CLK5B of the fifth clock signal line on the substrate at least partially overlaps with an orthographic projection of the first clock connection line of the fifth clock signal line on the substrate, and is connected to the first clock connection line of the fifth clock signal line through a forty-first via.

[0418] In an exemplary embodiment, an orthographic projection of the second clock connection line CLK6B of the sixth clock signal line on the substrate at least partially overlaps with an orthographic projection of the first clock connection line of the sixth clock signal line on the substrate, and is connected to the first clock connection line of the sixth clock signal line through a forty-second via.

[0419] In an exemplary embodiment, the orthographic projection of the second clock connection line CLK7B of the seventh clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock connection line of the seventh clock signal line on the substrate, and is connected to the first clock connection line of the seventh clock signal line through a forty-third via.

[0420] In an exemplary embodiment, an orthographic projection of the second clock connection line CLK8B of the eighth clock signal line on the substrate at least partially overlaps with an orthographic projection of the first clock connection line of the eighth clock signal line on the substrate, and is connected to the first clock connection line of the eighth clock signal line through a forty-fourth via.

[0421] In an exemplary embodiment, the second second power connection line VL22 of the second low-level power line at least partially overlaps with the positive projection of the first second power connection line of the second low-level power line on the substrate, and is connected to the first second power connection line of the second low-level power line through the forty-fifth via.

[0422] At this point, the circuit structure layer is prepared on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple shift registers. In a plane perpendicular to the display substrate, the circuit structure layer may be arranged on the substrate.

[0423] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0424] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0425] In exemplary embodiments, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0426] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0427] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0428] In an exemplary embodiment, after the circuit structure layer is prepared, a light emitting structure layer is prepared on the circuit structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0429] An anode conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the anode conductive film is patterned using a patterning process to form an anode conductive layer pattern arranged on the second flat layer. A pixel definition film is deposited on the substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern. An organic light-emitting material is coated on the substrate on which the pixel definition layer pattern is formed, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. A cathode conductive film is deposited on the substrate on which the organic material layer pattern is formed, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0430] At this point, the light-emitting structure layer is prepared on the substrate.

[0431] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns. The plurality of anode patterns may include an anode of a first light-emitting device, an anode of a second light-emitting device, an anode of a third light-emitting device, and an anode of a fourth light-emitting device, wherein the anode of the first light-emitting device is located in a red sub-pixel emitting red light, the anode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the anode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the anode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0432] In an exemplary embodiment, the anode of the first light-emitting device and the anode of the second light-emitting device may be alternately arranged along the first direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device may be alternately arranged along the first direction. Alternatively, the anode of the first light-emitting device and the anode of the second light-emitting device may be alternately arranged along the second direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device may be alternately arranged along the second direction.

[0433] In an exemplary embodiment, the shapes and areas of the anode electrodes of the four sub-pixels in one pixel unit may be the same, or may be different.

[0434] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0435] In an exemplary embodiment, the organic structure layer may include at least an organic light emitting layer of a light emitting device.

[0436] In an exemplary embodiment, the cathode conductive layer may include at least cathodes of a plurality of light emitting devices.

[0437] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0438] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0439] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0440] The present disclosure also provides a method for preparing a display substrate, which is configured to prepare the display substrate provided by any of the aforementioned embodiments. The method for preparing the display substrate may include the following steps:

[0441] A substrate is provided.

[0442] A gate driving circuit, a first low-level power line and a second low-level power line are formed on a substrate in a non-display area.

[0443] In an exemplary embodiment, the gate drive circuit includes: a plurality of cascaded shift registers, at least one stage of the shift register includes: a shift subcircuit and an output subcircuit, the shift subcircuit includes: at least one transistor, and the output subcircuit includes: at least one output transistor; the orthographic projection of the first low-level power line on the substrate at least partially overlaps with the orthographic projection of at least one transistor in the shift subcircuit on the substrate, and the orthographic projection of the second low-level power line on the substrate is located between the orthographic projection of at least one transistor in the shift subcircuit on the substrate and the orthographic projection of at least one output transistor in the output subcircuit on the substrate.

[0444] In an exemplary embodiment, a line width of the first low-level power line along the first direction is smaller than a line width of the second low-level power line along the first direction.

[0445] In an exemplary embodiment, the method for preparing a display substrate may further include:

[0446] A first clock signal line group, a second clock signal line group, an initial signal line and a high-level power line are formed on a substrate and located in a non-display area.

[0447] An embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0448] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0449] In an exemplary embodiment, the display device may be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0450] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0451] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0452] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate comprising a display area and a non-display area located at least on one side of the display area, characterized in that: include: A substrate and a gate drive circuit, a first low-level power line, and a second low-level power line disposed on the substrate and located in the non-display area, the gate drive circuit comprising: a plurality of cascaded shift registers, at least one shift register comprising: a shift subcircuit and an output subcircuit, the shift subcircuit being electrically connected to the first low-level power terminal and the cascade signal output terminal, respectively; the output subcircuit being electrically connected to the first low-level power terminal, the second low-level power terminal, and the drive signal output terminal, respectively; the shift subcircuit comprising: at least one transistor; and the output subcircuit comprising: at least one output transistor; The first low-level power line is electrically connected to the first low-level power terminal of the at least one stage of shift register, the second low-level power line is electrically connected to the second low-level power terminal of the at least one stage of shift register, and the second low-level power line is located on a side of the first low-level power line close to the display area; The orthographic projection of the first low-level power line on the substrate at least partially overlaps with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate, and the orthographic projection of the second low-level power line on the substrate is located between the orthographic projection of the at least one transistor in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate; A line width of the first low-level power line along the first direction is smaller than a line width of the second low-level power line along the first direction.

2. The display substrate according to claim 1, wherein: At least one signal line of the first low-level power line and the second low-level power line extends at least partially along a second direction, and the first direction and the second direction intersect; The signal of at least one of the first low-level power line and the second low-level power line is a negative voltage signal, and the absolute value of the voltage value of the power signal of the first low-level power line is smaller than the absolute value of the voltage value of the power signal of the second low-level power line.

3. The display substrate according to claim 1, wherein The first low-level power line includes: at least one first power connection line; the second low-level power line includes: a plurality of second power connection lines arranged in different layers and connected to each other; The first power connection line and the second power connection line at least partially extend along the second direction, a plurality of second power connection lines are stacked in sequence in a direction away from the substrate, and orthographic projections of at least two of the plurality of second power connection lines on the substrate at least partially overlap; The number of first power connection lines included in the first low-level power line is less than the number of second power connection lines included in the second low-level power line; The at least one first power connection line is arranged on the same layer as at least one second power connection line among the multiple second power connection lines, and the film layer where the at least one second power connection line is located is located on the side of the film layer where the at least one first power connection line is located close to the substrate.

4. The display substrate according to claim 3, wherein: The first low-level power line includes: a first power connection line; the second low-level power line includes: two second power connection lines arranged in different layers and connected to each other, the second second power connection line being located on a side of the first second power connection line away from the substrate; The first power connection line and the second power connection line are arranged on the same layer; Alternatively, the first low-level power line includes: two first power connection lines arranged in different layers and connected to each other, and the second low-level power line includes: three second power connection lines arranged in different layers and connected to each other, the second first power connection line is located on a side of the first first power connection line away from the substrate, the first second power connection line is located on a side of the second second power connection line close to the substrate, and the third second power connection line is located on a side of the second second power connection line away from the substrate; The first first power connection line and the second second power connection line are arranged on the same layer, and the second first power connection line and the third second power connection line are arranged on the same layer.

5. The display substrate according to claim 1, wherein Also includes: A first clock signal line group is provided on the substrate and located in the non-display area, the at least one stage of shift register includes: a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal, the shift sub-circuit of the at least one stage of shift register is respectively connected to the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, the first clock signal line group includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line arranged in sequence along a direction close to the display area; At least one clock signal line among the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line extends at least partially along the second direction; The first clock signal terminal of the 4i-3 stage shift register is electrically connected to the first clock signal line, the second clock signal terminal of the 4i-3 stage shift register is electrically connected to the second clock signal line, the third clock signal terminal of the 4i-3 stage shift register is electrically connected to the third clock signal line, the first clock signal terminal of the 4i-2 stage shift register is electrically connected to the second clock signal line, the second clock signal terminal of the 4i-2 stage shift register is electrically connected to the third clock signal line, the third clock signal terminal of the 4i-2 stage shift register is electrically connected to the fourth clock signal line. connecting, the first clock signal terminal of the 4i-1th stage shift register is electrically connected to the third clock signal line, the second clock signal terminal of the 4i-1th stage shift register is electrically connected to the fourth clock signal line, the third clock signal terminal of the 4i-1th stage shift register is electrically connected to the first clock signal line, the first clock signal terminal of the 4i-th stage shift register is electrically connected to the fourth clock signal line, the second clock signal terminal of the 4i-th stage shift register is electrically connected to the first clock signal line, and the third clock signal terminal of the 4i-th stage shift register is electrically connected to the second clock signal line; The orthographic projection of the first low-level power line on the substrate is located between the orthographic projection of the second clock signal line on the substrate and the orthographic projection of the third clock signal line on the substrate, and the orthographic projection of the second low-level power line on the substrate is located on a side of the orthographic projection of at least one clock signal line in the first clock signal line group on the substrate close to the display area.

6. The display substrate according to claim 5, wherein: The shift subcircuit of at least one stage of the shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; wherein the control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode of the first transistor is electrically connected to the first node, the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; the control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the first low-level power supply terminal, and the second electrode of the third transistor is electrically connected to the second node; the control electrode of the fourth transistor is electrically connected to the second node, and the control electrode of the fourth transistor is electrically connected to the first node. the first electrode is electrically connected to the high-level power supply terminal, and the second electrode of the fourth transistor is electrically connected to the cascade signal output terminal; the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the cascade signal output terminal; the control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the high-level power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fourth node; the control electrode of the seventh transistor is electrically connected to the third clock signal terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first node; the control electrode of the eighth transistor is electrically connected to the first low-level power supply terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node; The control electrode of the first transistor and the control electrode of the third transistor are integrally structured and at least partially extend along the first direction, and an orthographic projection of the control electrode of the first transistor on the substrate at least partially overlaps with an orthographic projection of at least one of the first clock signal line, the second clock signal line, the first low-level power line, the third clock signal line, and the fourth clock signal line on the substrate; At least a portion of the control electrode of the second transistor extends along the first direction, and an orthographic projection of the control electrode of the second transistor on the substrate at least partially overlaps with an orthographic projection of at least one of the second clock signal line and the first low-level power line on the substrate; The control electrode of the fourth transistor and the control electrode of the sixth transistor are an integrated structure, and at least a portion thereof extends along the first direction. An orthographic projection of the control electrode of the fourth transistor on the substrate at least partially overlaps with an orthographic projection of at least one of the third clock signal line and the fourth clock signal line on the substrate; The control electrode of the fifth transistor at least partially extends along the first direction, and an orthographic projection of the control electrode of the fifth transistor on the substrate at least partially overlaps with an orthographic projection of at least one of the second clock signal line, the first low-level power line, the third clock signal line, and the fourth clock signal line on the substrate; a control electrode of the seventh transistor at least partially extending along the first direction, and an orthographic projection of the control electrode of the seventh transistor on the substrate at least partially overlapping with an orthographic projection of at least one of the first clock signal line, the second clock signal line, the first low-level power line, the third clock signal line, and the fourth clock signal line on the substrate; The control electrode of the eighth transistor extends at least partially along the first direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the first clock signal line, the second clock signal line, the first low-level power line, the third clock signal line and the fourth clock signal line.

7. The display substrate according to claim 6, wherein: Also includes: exposing a plurality of via holes that expose the control electrode of the first transistor, wherein two of the plurality of via holes that expose the control electrode of the first transistor respectively expose two ends of the control electrode of the first transistor; A plurality of via holes are exposed to the control electrode of the seventh transistor, and two of the plurality of via holes are exposed to the control electrode of the seventh transistor to expose two ends of the control electrode of the seventh transistor respectively.

8. The display substrate according to claim 6, wherein: Also includes: A plurality of first connection lines are provided on the substrate and located in the non-display area, wherein one of the plurality of first connection lines is electrically connected to a first electrode of a fifth transistor of at least one stage of the shift register, and the first connection line extends along a first direction. An orthographic projection of a first electrode of a fifth transistor of at least one stage of the shift register on the substrate at least partially overlaps with an orthographic projection of the fourth clock signal line and one of the plurality of first connecting lines on the substrate, respectively; an orthographic projection of one of the plurality of first connecting lines on the substrate at least partially overlaps with an orthographic projection of at least one of the first clock signal line, the second clock signal line, the first low-level power supply line, and the third clock signal line on the substrate; The film layer where the first connecting line is located is located on a side of the film layer where the first electrode and the second electrode of at least one transistor of the at least one stage shift register are located, close to the substrate.

9. The display substrate according to claim 8, wherein: Also includes: A plurality of via holes are exposed for the first connection line, and two of the via holes expose an end of the first connection line close to the display area and an end away from the display area, respectively.

10. The display substrate according to claim 5, wherein: A line width of one of the first low-level power line and the second low-level power line along the first direction is smaller than a line width of at least one clock signal line in the first clock signal line group along the first direction.

11. The display substrate according to claim 5, wherein Also includes: a second clock signal line group disposed on the substrate and located in the non-display area, the second clock signal line group being located on a side of the first clock signal line group close to the display area, the at least one stage shift register comprising: a fourth clock signal terminal, an output subcircuit of the at least one stage shift register being electrically connected to the fourth clock signal terminal, the second clock signal line group comprising: a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line arranged in sequence along a direction close to the display area; The fifth clock signal line and the seventh clock signal line receive the same clock signal, the sixth clock signal line and the eighth clock signal line receive the same signal, and at least one clock signal line among the fifth clock signal line, the sixth clock signal line, the seventh clock signal line, and the eighth clock signal line extends at least partially along the second direction; The fourth clock signal terminal of at least one stage of the shift register is electrically connected to one of the first signal line group and the second signal line group, and the fourth clock signal terminals of adjacent shift registers are connected to different signal line groups, wherein the first signal line group includes: a fifth clock signal line and a seventh clock signal line, and the second signal line group includes: a sixth clock signal line and an eighth clock signal line; An orthographic projection of the second low-level power line on the substrate is located between an orthographic projection of the sixth clock signal line on the substrate and an orthographic projection of the seventh clock signal line on the substrate.

12. The display substrate according to claim 11, wherein: The output subcircuit of the at least one stage shift register includes: a tenth transistor and a third capacitor, wherein a control electrode of the tenth transistor is electrically connected to the third node, a first electrode of the tenth transistor is electrically connected to the fourth clock signal terminal, a second electrode of the tenth transistor is electrically connected to the drive signal output terminal, a first plate of the third capacitor is electrically connected to the fourth clock signal terminal, and a second plate of the third capacitor is electrically connected to the fifth node; When the fourth clock signal terminal of the at least one shift register is electrically connected to the first signal line group, the first electrode of the tenth transistor of the at least one shift register is electrically connected to the seventh clock signal line, and the first plate of the third capacitor of the at least one shift register is electrically connected to the fifth clock signal line; When the fourth clock signal end of at least one shift register is electrically connected to the second signal line group, the first electrode of the tenth transistor of at least one shift register is electrically connected to the eighth clock signal line, and the first electrode plate of the third capacitor of at least one shift register is electrically connected to the sixth clock signal line.

13. The display substrate according to claim 12, wherein: The output sub-circuit of the at least one stage shift register further includes: a ninth transistor and an eleventh transistor, wherein the control electrode of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the second low-level power supply terminal, the second electrode of the ninth transistor is electrically connected to the drive signal output terminal, the control electrode of the eleventh transistor is electrically connected to the first low-level power supply terminal, the first electrode of the eleventh transistor is electrically connected to the second node, and the second electrode of the eleventh transistor is electrically connected to the fifth node; The orthographic projection of at least one of the fifth clock signal line, the sixth clock signal line and the second low-level power supply line on the substrate is located between the orthographic projection of the transistor in the shift sub-circuit and at least one of the eleventh transistor in the output sub-circuit on the substrate and the orthographic projection of at least one of the ninth transistor and the tenth transistor in the output sub-circuit on the substrate, and the orthographic projection of at least one of the seventh clock signal line and the eighth clock signal line on the substrate is located on a side of the orthographic projection of at least one of the ninth transistor and the tenth transistor in the output sub-circuit on the substrate close to the display area.

14. The display substrate according to claim 11, wherein The line width of at least one clock signal line among the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the seventh clock signal line and the eighth clock signal line along the first direction is greater than the line width of at least one signal line among the fifth clock signal line, the sixth clock signal line and the second low-level power line along the first direction.

15. The display substrate according to claim 11, wherein At least one of the fifth to eighth clock signal lines comprises: a first clock connection line and a second clock connection line that are arranged in different layers and connected to each other, wherein the first clock connection line and the second clock connection line at least partially extend along the second direction, and orthographic projections of the first clock connection line and the second clock connection line of at least one of the fifth to eighth clock signal lines on the substrate at least partially overlap; The film layer where the first clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line is located is located on the side of the film layer where the second clock connection line is located close to the substrate, and the second clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line is arranged on the same layer as at least one clock signal line from the first clock signal line to the fourth clock signal line.

16. The display substrate according to claim 11, wherein: Also includes: An initial signal line and a high-level power line are provided on the substrate and located in the non-display area, wherein the at least one shift register comprises: a signal input terminal and a high-level power terminal, the high-level power line is electrically connected to the high-level power terminal of the at least one shift register, the initial signal line is electrically connected to the signal input terminal of the at least one shift register, and at least a portion of at least one of the initial signal line and the high-level power line extends along the second direction; The orthographic projection of the initial signal line on the substrate is located on a side of the first clock signal line group away from the display area, and the orthographic projection of the high-level power line on the substrate is located between the orthographic projection of the first clock signal line group on the substrate and the orthographic projection of the second clock signal line group on the substrate.

17. The display substrate according to claim 16, wherein: The orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the control electrode of at least one of the fourth transistor and the fifth transistor in the at least one stage of the shift register on the substrate.

18. The display substrate according to claim 16, wherein: The line width of the high level power line along the first direction is greater than the line width of at least one signal line among the first low level power line and the initial signal line along the first direction, and is smaller than the line width of at least one clock signal line in the first clock signal line group along the first direction.

19. The display substrate according to claim 11, wherein The shift subcircuit further includes: a first capacitor; the output subcircuit further includes: a second capacitor and a third capacitor; at least one of the first capacitor, the second capacitor, and the third capacitor includes: a first plate and a second plate; the second plate of at least one capacitor is located on a side of the first plate of at least one capacitor away from the substrate; the first plate of the first capacitor is electrically connected to the third node; the second plate of the first capacitor is electrically connected to the cascade signal output terminal; the first plate of the second capacitor is electrically connected to the fifth node; the second plate of the second capacitor is electrically connected to the second low-level power supply terminal; the first plate of the third capacitor is electrically connected to the fourth clock signal terminal; and the second plate of the third capacitor is electrically connected to the fifth node; The orthographic projection of the first capacitor on the substrate is located between the orthographic projection of the first clock signal line group on the substrate and the orthographic projection of the second clock signal line group on the substrate, and at least partially overlaps with the orthographic projection of the high-level power line on the substrate; The orthographic projection of the second capacitor on the substrate is located between the orthographic projection of the second low-level power line on the substrate and the orthographic projection of the seventh clock signal line on the substrate; The orthographic projection of the third capacitor on the substrate is located between the orthographic projection of the sixth clock signal line on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate, and at least partially overlaps with the orthographic projection of the second low-level power line on the substrate.

20. The display substrate according to claim 19, wherein At least one of the first and second plates of the at least one capacitor comprises: a main body and a connecting portion, wherein the main body and the connecting portion of the at least one plate are connected; The orthographic projection of the main body of the first electrode plate of the first capacitor on the substrate covers the orthographic projection of the main body of the second electrode plate of the first capacitor on the substrate, the orthographic projection of the main body of the second electrode plate of the second capacitor on the substrate covers the orthographic projection of the main body of the first electrode plate of the second capacitor on the substrate, and the orthographic projection of the main body of the second electrode plate of the third capacitor on the substrate covers the orthographic projection of the main body of the first electrode plate of the third capacitor on the substrate; An orthographic projection of the connection portion of the second plate of the third capacitor on the substrate at least partially overlaps with an orthographic projection of at least one of the fifth clock signal line and the sixth clock signal line on the substrate.

21. The display substrate according to claim 19, wherein The length of the main portion of the second electrode plate of the third capacitor along the first direction is greater than the line width of the second low-level power line along the first direction, and the orthographic projection of a portion of the second low-level power line close to or away from a boundary of the display area on the substrate is located within the range of the orthographic projection of the main portion of the second electrode plate of the third capacitor on the substrate; The distance between the orthographic projection of the main portion of the second plate of the third capacitor away from the boundary of the display area on the substrate and the orthographic projection of the sixth clock signal line close to the boundary of the display area on the substrate is greater than 1 micron, and the distance between the main portion of the second plate of the third capacitor and the orthographic projection of the second low-level power line away from the boundary of the display area on the substrate is greater than 1 micron; The distance between the orthographic projection of the main portion of the second electrode plate of the third capacitor close to the boundary of the display area on the substrate and the orthographic projection of the second low-level power line close to the boundary of the display area on the substrate is greater than 1 micron.

22. The display substrate according to claim 19, wherein The area of ​​the first capacitor is larger than the area of ​​at least one of the second capacitor and the third capacitor; An area of ​​the third capacitor is greater than an area of ​​the second capacitor.

23. The display substrate according to claim 6, wherein: The active pattern of the first transistor and the active pattern of the third transistor are arranged along a first direction, and a straight line extending along the first direction passes through at least a portion of the control electrode of the first transistor and the active pattern of the second transistor.

24. The display substrate according to claim 11, wherein The output sub-circuit of at least one stage of the shift register includes: a tenth transistor, which is an output transistor; The control electrode of the tenth transistor includes: a first connecting segment, a second connecting segment, and a plurality of first branch segments, the second connecting segment is located on a side of the first connecting segment close to the display area, and the plurality of first branch segments are located on a side of the second connecting segment close to the display area; the second electrode of the tenth transistor includes: a third connecting segment and a plurality of second branch segments, the plurality of second branch segments are located on a side of the third connecting segment close to the display area; The first connecting section extends along a first direction, and an orthographic projection thereof on the substrate at least partially overlaps with an orthographic projection of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line on the substrate; the second connecting section extends along a second direction, one of the plurality of first branch sections extends along the first direction, and the plurality of first branch sections are arranged along the second direction; the third connecting section extends along the second direction, one of the plurality of second branch sections extends along the first direction, and the plurality of second branch sections are arranged along the second direction; The orthographic projection of the third connecting segment on the base at least partially overlaps with the orthographic projection of the first connecting segment on the base, and does not overlap with the orthographic projection of the second connecting segment on the base. The orthographic projection of at least one branch segment among the multiple first branch segments does not overlap with the orthographic projections of the third connecting segment and at least one branch segment among the multiple second branch segments on the base. The orthographic projection of at least one branch segment among the multiple first branch segments on the base is located between the orthographic projections of at least two second branch segments among the multiple second branch segments on the base.

25. The display substrate according to claim 24, wherein: The width-to-length ratio of the channel region of the active pattern of the tenth transistor is greater than 40.

26. The display substrate according to claim 2, wherein: A line width of the first low-level power line along the first direction is in a range of 4 micrometers to 20 micrometers, and a line width of the second low-level power line along the first direction is in a range of 4 micrometers to 50 micrometers.

27. The display substrate according to claim 11, wherein A line width of at least one of the seventh clock signal line and the eighth clock signal line along the first direction is in a range of 10 micrometers to 50 micrometers.

28. The display substrate according to claim 20, wherein: The capacitance of the first capacitor is greater than or equal to 0.3PF.

29. The display substrate according to claim 1, wherein Also includes: A circuit structure layer is provided on a substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked sequentially on the substrate, at least one stage of a shift register comprising: a plurality of transistors and a plurality of capacitors, the gate drive circuit, the first low-level power line, and the second low-level power line being provided on the circuit structure layer; The display substrate further includes: a first connection line, an initial signal line, a high-level power line, and first to eighth clock signal lines; The semiconductor layer includes at least: an active pattern of at least one transistor among a plurality of transistors in at least one stage of a shift register; The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors in at least one stage of the shift register and a first electrode plate of at least one capacitor among a plurality of capacitors; The second conductive layer includes: a second plate of at least one capacitor located in a plurality of transistors of at least one stage of the shift register; The third conductive layer includes: a first electrode and a second electrode of at least one transistor among a plurality of transistors of at least one stage of the shift register and an initial signal line; The fourth conductive layer includes: a high-level power line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; The first connecting line is located in the first conductive layer or the second conductive layer, the first low-level power line is located in the fourth conductive layer, the second low-level power line is located in the third conductive layer and the fourth conductive layer, and at least one clock signal line from the fifth clock signal line to the eighth clock signal line is located in the third conductive layer and the fourth conductive layer.

30. The display substrate according to claim 1, wherein Also includes: A circuit structure layer is provided on a substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked sequentially on the substrate, at least one stage of a shift register comprising: a plurality of transistors and a plurality of capacitors, the gate drive circuit, the first low-level power line, and the second low-level power line being provided on the circuit structure layer; The display substrate further includes: a first connection line, an initial signal line, a high-level power line, and first to eighth clock signal lines. The semiconductor layer includes at least: an active pattern of at least one transistor among a plurality of transistors in at least one stage of a shift register; The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors in at least one stage of the shift register and a first electrode plate of at least one capacitor among a plurality of capacitors; The second conductive layer includes: a second plate of at least one capacitor located in a plurality of transistors of at least one stage of the shift register; The third conductive layer includes: a first electrode and a second electrode of at least one transistor among a plurality of transistors of at least one stage of the shift register and an initial signal line; The fourth conductive layer includes: a high-level power line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; The first connecting line is located in the first conductive layer or the second conductive layer, the first low-level power line is located in at least one film layer among the fourth conductive layer and the fifth conductive layer, the second low-level power line is located in the third conductive layer, the fourth conductive layer and the fifth conductive layer, and at least one clock signal line from the fifth clock signal line to the eighth clock signal line is located in at least two film layers among the third conductive layer, the fourth conductive layer and the fifth conductive layer.

31. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 30.

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