Shift register, gate driving circuit and display device

Abstract

A shift register comprises: an input circuit (1) configured to write a signal provided by a signal input terminal (INPUT) to a third node (N3) in response to a signal provided by a first clock signal terminal (CK); a first control circuit (2) configured to write a voltage provided by a first power supply terminal to a first node (N1) in response to a signal provided by a preset control signal terminal (CS) and a signal provided by a preset clock signal terminal; a second control circuit (3) configured to write a voltage provided by a second power supply terminal to the first node (N1) in response to a signal provided by the signal input terminal (INPUT); and an output circuit (4) configured to write the voltage provided by the second power supply terminal to a signal output terminal (OUT) in response to a voltage at the first node (N1) and write the voltage provided by the first power supply terminal to the signal output terminal (OUT) in response to a voltage at a fourth node (N4), the third node (N3) being coupled to the fourth node (N4). The disclosure also provides a gate drive circuit (DC) and a display device.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to PCT International Patent Application No. PCT / CN2022 / 082794 filed on March 24, 2022, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the field of display, in particular to a shift register, a gate driving circuit and a display device. BACKGROUND

[0004] With the development of display technology, a light emitting control transistor for controlling whether a driving transistor outputs a driving current is generally arranged in a pixel driving circuit. The light emitting control transistor is generally controlled by a light emitting control signal line. For the light emitting control signal line, a corresponding light emitting control gate driving circuit needs to be configured.

[0005] In the prior art, the transistors in the light emitting control gate driving circuit are integrated on an array substrate by using a Gate Driver on Array (GOA) technology, so as to scan and drive the light emitting control signal line in the display panel, thereby part of the gate driving IC can be saved, which is conducive to the realization of narrow frame.

[0006] However, it is found in actual application that the circuit structure of the shift register in the existing light emitting control gate driving circuit is complex and occupies a large space. SUMMARY

[0007] The present application aims to at least solve one of the technical problems existing in the prior art, and proposes a shift register, a gate driving circuit and a display device.

[0008] In a first aspect, the present application provides a shift register, comprising:

[0009] An input circuit is coupled to a signal input end, a first clock signal end and a third node, and is configured to write a signal provided by the signal input end to the third node in response to a signal provided by the first clock signal end.

[0010] A first control circuit is coupled to a first power supply end, a preset control signal end, a preset clock signal end and a first node, and is configured to write a voltage provided by the first power supply end to the first node in response to a signal provided by the preset control signal end and a signal provided by the preset clock signal end.

[0011] The second control circuit is coupled to the second power supply end, the signal input end and the first node, and is configured to control writing of a voltage provided by the second power supply end to the first node in response to a signal provided by the signal input end.

[0012] The output circuit is coupled to the signal output end, the first power supply end, the second power supply end, the first node and the fourth node, and is configured to write the voltage provided by the second power supply end to the signal output end in response to the voltage at the first node, and write the voltage provided by the first power supply end to the signal output end in response to the voltage at the fourth node, the third node being coupled to the fourth node.

[0013] In some embodiments, the first control circuit includes a first transistor and a second transistor.

[0014] The control electrode of the first transistor is coupled to the preset control signal end, the first electrode of the first transistor is coupled to the first power supply end, and the second electrode of the first transistor is coupled to the first electrode of the second transistor.

[0015] The control electrode of the second transistor is coupled to a preset clock signal end, and the second electrode of the second transistor is coupled to the first node.

[0016] In some embodiments, the first control circuit includes a first transistor and a second transistor.

[0017] The control electrode of the first transistor is coupled to the preset control signal end, the first electrode of the first transistor is coupled to the second electrode of the second transistor, and the second electrode of the first transistor is coupled to the first node.

[0018] The control electrode of the second transistor is coupled to a preset clock signal end, and the first electrode of the second transistor is coupled to the first power supply end.

[0019] In some embodiments, the preset control signal end is the third node.

[0020] In some embodiments, the preset control signal end is the signal input end.

[0021] In some embodiments, the first transistor is an N-type transistor, and other transistors in the shift register except the first transistor are P-type transistors.

[0022] In some embodiments, the first transistor is a metal oxide transistor, and other transistors in the shift register except the first transistor are low-temperature polysilicon transistors.

[0023] In some embodiments, the second control circuit includes a third transistor;

[0024] a control electrode of the third transistor is coupled with the signal input terminal, a first electrode of the third transistor is coupled with the second power terminal, and a second electrode of the third transistor is coupled with the first node.

[0025] In some embodiments, the input circuit includes a fourth transistor;

[0026] a control electrode of the fourth transistor is coupled with the first clock signal terminal, a first electrode of the fourth transistor is coupled with the signal input terminal, and a second electrode of the fourth transistor is coupled with the third node.

[0027] In some embodiments, the output circuit includes a seventh transistor and an eighth transistor;

[0028] a control electrode of the seventh transistor is coupled with the fourth node, a first electrode of the seventh transistor is coupled with the first power terminal, and a second electrode of the seventh transistor is coupled with the signal output terminal;

[0029] a control electrode of the eighth transistor is coupled with the first node, a first electrode of the eighth transistor is coupled with the signal output terminal, and a second electrode of the eighth transistor is coupled with the second power terminal.

[0030] In some embodiments, the shift register further includes a noise reduction circuit coupled with the second power terminal, the first node, and the third node, and configured to write a voltage provided by the second power terminal to the third node in response to a control of a voltage at the first node.

[0031] In some embodiments, the noise reduction circuit includes a fifth transistor;

[0032] a control electrode of the fifth transistor is coupled with the first node, a first electrode of the fifth transistor is coupled with the third node, and a second electrode of the fifth transistor is coupled with the second power terminal.

[0033] In some embodiments, the shift register further includes a first capacitor;

[0034] a first terminal of the first capacitor is coupled with a second clock signal terminal, and a second terminal of the first capacitor is coupled with the fourth node.

[0035] In some embodiments, the shift register further includes a sixth transistor, the sixth transistor being located between the third node and the fourth node, and the third node being coupled with the fourth node through the sixth transistor;

[0036] The control electrode of the sixth transistor is coupled with a first power supply end, the first electrode of the sixth transistor is coupled with the third node, and the second electrode of the sixth transistor is coupled with the fourth node.

[0037] In some embodiments, the preset clock signal end is a first clock signal end or a second clock signal end.

[0038] In some embodiments, the shift register further comprises a second capacitor.

[0039] The first end of the second capacitor is coupled with the first node, and the second end of the second capacitor is coupled with the first power supply end or the second power supply end.

[0040] In a second aspect, the embodiments of the present disclosure further provide a gate drive circuit, comprising: a plurality of shift registers connected in cascade, wherein each shift register is the shift register provided in the first aspect.

[0041] The signal input end of the shift register located at the first stage is coupled with a frame start signal end.

[0042] For any shift register located at a stage other than the first stage, the signal input end of the shift register is coupled with the signal output end of the shift register located at the previous stage.

[0043] In a third aspect, the embodiments of the present disclosure further provide a display device, comprising: the gate drive circuit provided in the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1A A circuit structure schematic diagram of a shift register provided in the embodiments of the present disclosure;

[0045] Figure 1B Another circuit structure schematic diagram of a shift register provided in the embodiments of the present disclosure;

[0046] Figure 2A Still another specific circuit structure schematic diagram of a shift register provided in the embodiments of the present disclosure;

[0047] Figure 2B Still another specific circuit structure schematic diagram of a shift register provided in the embodiments of the present disclosure;

[0048] Figure 3A Still another specific circuit structure schematic diagram of a shift register provided in the embodiments of the present disclosure;

[0049] Figure 3B Still another specific circuit structure schematic diagram of a shift register provided in the embodiments of the present disclosure;

[0050] Figure 4A A timing diagram of the operation of the shift register shown in Figure 3A A timing diagram of the operation of the shift register shown in

[0051] Figure 4B A timing diagram of the operation of the shift register shown in Figure 3B A timing diagram of the operation of the shift register shown in

[0052] Figure 5A A timing diagram of the operation of the shift register shown in

[0053] Figure 5B A timing diagram of the operation of the shift register shown in

[0054] Figure 6A A timing diagram of the operation of the shift register shown in

[0055] Figure 6B A timing diagram of the operation of the shift register shown in

[0056] Figure 7A A timing diagram of the operation of the shift register shown in

[0057] Figure 7B A timing diagram of the operation of the shift register shown in

[0058] Figure 8A A timing diagram of the operation of the shift register shown in

[0059] Figure 8B A timing diagram of the operation of the shift register shown in

[0060] Figure 9A A timing diagram of the operation of the shift register shown in Figure 8A A timing diagram of the operation of the shift register shown in

[0061] Figure 9B A timing diagram of the operation of the shift register shown in Figure 8B A timing diagram of the operation of the shift register shown in

[0062] Figure 10A A timing diagram of the operation of the shift register shown in

[0063] Figure 10B A timing diagram of the operation of the shift register shown in

[0064] Figure 11A A timing diagram of the operation of the shift register shown in Figure 10A A timing diagram of the operation of the shift register shown in

[0065] Figure 11B For Figure 10B a working timing diagram of the shift register shown in FIG. 1;

[0066] Figure 12A a circuit structure schematic diagram of another shift register provided by an embodiment of the present disclosure;

[0067] Figure 12B a circuit structure schematic diagram of another shift register provided by an embodiment of the present disclosure;

[0068] Figure 12C a circuit structure schematic diagram of another shift register provided by an embodiment of the present disclosure;

[0069] Figure 12D a circuit structure schematic diagram of another shift register provided by an embodiment of the present disclosure;

[0070] Figure 13 a circuit structure schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] In order for those skilled in the art to better understand the technical solutions of the present application, a shift register, a gate drive circuit and a display device provided by the present application are described in detail below with reference to the drawings.

[0072] It should be noted that the transistor in the present application can be a thin film transistor or a field effect transistor or other switching devices with the same characteristics. The transistor generally includes three poles: gate, source and drain, and the source and drain of the transistor are symmetrical in structure and can be interchangeable according to the need. In the present application, the control pole is the gate of the transistor, one of the first pole and the second pole is the source, and the other is the drain.

[0073] In addition, according to the characteristics of the transistor, the transistor can be divided into N-type transistor and P-type transistor; when the transistor is an N-type transistor, the on voltage is a high-level voltage and the off voltage is a low-level voltage; when the transistor is a P-type transistor, the on voltage is a low-level voltage and the off voltage is a high-level voltage.

[0074] Figure 1A a circuit structure schematic diagram of a shift register provided by an embodiment of the present disclosure, Figure 1B a circuit structure schematic diagram of another shift register provided by an embodiment of the present disclosure, as shown in FIG. 4; Figure 1A and Figure 1BAs shown, the shift register in the gate driving circuit for light emitting control in the shift register provided by the embodiment of the present disclosure is coupled with the corresponding row light emitting control signal line in the display device to provide the corresponding light emitting control signal to the coupled light emitting control signal line, and the shift register comprises an input circuit 1, a first control circuit 2, a second control circuit 3 and an output circuit 4.

[0075] The input circuit 1 is coupled with the signal input end INPUT, the first clock signal end CK and the third node N3, and the input circuit 1 is configured to write the signal provided by the signal input end INPUT to the third node N3 in response to the signal provided by the first clock signal end CK.

[0076] The first control circuit 2 is coupled with the first power supply end, the preset control signal end CS, the second clock signal end CKB and the first node N1, and is configured to write the voltage provided by the first power supply end to the first node N1 in response to the signal provided by the preset control signal end CS and the signal provided by the preset clock signal end.

[0077] The second control circuit 3 is coupled with the second power supply end, the signal input end INPUT and the first node N1, and the second control circuit 3 is configured to write the voltage provided by the second power supply end to the first node N1 in response to the signal provided by the signal input end INPUT.

[0078] The output circuit 4 is coupled with the signal output end OUT, the first power supply end, the second power supply end, the first node N1 and the fourth node N4, and the output circuit 4 is configured to write the voltage provided by the second power supply end to the signal output end OUT in response to the voltage at the first node N1, and write the voltage provided by the first power supply end to the signal output end OUT in response to the voltage at the fourth node N4, and the third node N3 is coupled with the fourth node N4.

[0079] In some embodiments, the preset clock signal end is the first clock signal end CK or the second clock signal end CKB. Figure 1A In the case where the preset clock signal end is the second clock signal end CKB, Figure 1B In the case where the preset clock signal end is the first clock signal end CK.

[0080] The shift register provided by the embodiment of the present disclosure has the advantages of simple circuit structure and small space occupation, which is beneficial to the narrow frame design of the display device.

[0081] Figure 2A Another specific circuit structure diagram of the shift register provided by the embodiment of the present disclosure is shown, Figure 2B Another specific circuit structure diagram of the shift register provided by the embodiment of the present disclosure is shown, Figure 2A andFigure 2B As shown in some embodiments, the shift register further comprises: a noise reduction circuit 5 coupled with the second power supply end, the first node N1 and the third node N3, and the noise reduction circuit 5 is configured to write the voltage provided by the second power supply end to the third node N3 in response to the control of the voltage at the first node N1.

[0082] In the embodiments of the present disclosure, the noise reduction circuit 5 can be used to perform noise reduction processing on the third node N3 during the operation of the shift register.

[0083] Figure 3A Another specific circuit structure diagram of the shift register provided by the embodiments of the present disclosure is shown in Figure 3B Another specific circuit structure diagram of the shift register provided by the embodiments of the present disclosure is shown in Figure 3A and Figure 3B As shown, Figure 3A The shift register shown is based on Figure 2A A specific implementation scheme of the shift register shown; Figure 3B The shift register shown is based on Figure 2B A specific implementation scheme of the shift register shown.

[0084] In some embodiments, the first control circuit 2 includes a first transistor T1 and a second transistor T2, the second control circuit 3 includes a third transistor T3, the input circuit 1 includes a fourth transistor T4, the noise reduction circuit 5 includes a fifth transistor T5, and the output circuit 4 includes a seventh transistor T7 and an eighth transistor T8.

[0085] The control electrode of the first transistor T1 is coupled with a preset control signal end CS, the first electrode of the first transistor T1 is coupled with a first power supply end, and the second electrode of the first transistor T1 is coupled with the first electrode of the second transistor T2.

[0086] The control electrode of the second transistor T2 is coupled with a second clock signal end CKB (shown in Figure 3A ) or a first clock signal end CK (shown in Figure 3B ), and the second electrode of the second transistor T2 is coupled with the first node N1.

[0087] The control electrode of the third transistor T3 is coupled with a signal input end INPUT, the first electrode of the third transistor T3 is coupled with a second power supply end, and the second electrode of the third transistor T3 is coupled with the first node N1.

[0088] The control electrode of the fourth transistor T4 is coupled with the first clock signal end CK, the first electrode of the fourth transistor T4 is coupled with the signal input end INPUT, and the second electrode of the fourth transistor T4 is coupled with the third node N3.

[0089] The control electrode of the fifth transistor T5 is coupled with the first node N1, the first electrode of the fifth transistor T5 is coupled with the third node N3, and the second electrode of the fifth transistor T5 is coupled with the second power supply end.

[0090] The control electrode of the seventh transistor T7 is coupled with the fourth node N4, the first electrode of the seventh transistor T7 is coupled with the first power supply end, and the second electrode of the seventh transistor T7 is coupled with the signal output end OUT.

[0091] The control electrode of the eighth transistor T8 is coupled with the first node N1, the first electrode of the eighth transistor T8 is coupled with the signal output end OUT, and the second electrode of the eighth transistor T8 is coupled with the second power supply end.

[0092] In some embodiments, the preset control signal end CS is the signal input end INPUT. In the embodiments of the present disclosure, the signal input end INPUT is used as the preset control signal end CS, so that it is not necessary to additionally configure a new control signal end, thereby effectively reducing the number of signal ends configured in the shift register and facilitating reduction of the control difficulty of the shift register.

[0093] In some embodiments, the first transistor T1 is an N-type transistor, and the other transistors in the shift register except the first transistor T1 are P-type transistors.

[0094] Currently, the pixel driving circuit in the display device starts to develop in the direction of Low Temperature Polycrystalline Oxide (LTPO) technology, that is, the pixel driving circuit includes two types of transistors: low-temperature polycrystalline silicon type transistors and metal oxide type transistors. Since the GOA circuit is prepared synchronously with the pixel driving circuit based on the same process, in order to adapt to the preparation process of the LTPO type pixel driving circuit, the transistors in the shift register are also designed to include two types of low-temperature polycrystalline silicon type transistors and metal oxide type transistors. In some embodiments, the N-type transistor described above adopts a metal oxide type transistor, and the P-type transistor described above adopts a low-temperature polycrystalline silicon type transistor. That is, the first transistor T1 is a metal oxide type transistor, and the other transistors in the shift register except the first transistor T1 are low-temperature polycrystalline silicon type transistors.

[0095] The working process of the shift register shown in FIGS. 1 to 3 will be described in detail below with reference to the accompanying drawings. Figure 2A and Figure 2B In the embodiments of the present disclosure, the signal input end INPUT is used as the preset control signal end CS, so that it is not necessary to additionally configure a new control signal end, thereby effectively reducing the number of signal ends configured in the shift register and facilitating reduction of the control difficulty of the shift register.

[0096] Figure 4A As Figure 3A shown in FIG. 2, the working process of the shift register includes the following stages: Figure 4A

[0097] In the first stage t1, the signal provided by the signal input terminal INPUT is at a low level, the signal provided by the first clock signal terminal CK is at a high level, and the signal provided by the second clock signal terminal CKB is at a low level.

[0098] Since the signal provided by the second clock signal terminal CKB is at a low level, the second transistor T2 is turned on.

[0099] Since the signal provided by the signal input terminal INPUT is at a low level, the first transistor T1 is turned off, the third transistor T3 is turned on, the high-level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3, the voltage at the first node N1 is at a high level, and the fifth transistor T5 and the eighth transistor T8 are both turned off.

[0100] Since the signal provided by the first clock signal terminal CK is at a high level, the fourth transistor T4 is turned off, the third node N3 and the fourth node N4 are both in a floating state, the voltage at the third node N3 and the fourth node N4 maintains the low level of the previous stage, the seventh transistor T7 maintains the turned-on state, and the low-level signal provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so that the signal output terminal OUT outputs a low-level signal.

[0101] In the second stage t2, the signal provided by the signal input terminal INPUT is at a high level, the signal provided by the first clock signal terminal CK is at a low level, and the signal provided by the second clock signal terminal CKB is at a high level.

[0102] Since the signal provided by the second clock signal terminal CKB is at a high level, the second transistor T2 is turned off.

[0103] Since the signal provided by the signal input terminal INPUT is at a high level, the first transistor T1 is turned on, and the third transistor T3 is turned off. At this time, the first node N1 is in a floating state and maintains the high level of the previous stage. At this time, the fifth transistor T5 and the eighth transistor T8 are both maintained to be turned off.

[0104] ​Since the signal provided by the first clock signal terminal CK is at the low level, the fourth transistor T4 is turned on, and the high level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4, and the voltage at the third node N3 and the fourth node N4 is at the high level. At this time, the seventh transistor T7 is in the off state. The signal output terminal OUT is in the floating state, maintaining the low level state of the previous stage, that is, the signal output terminal OUT outputs the low level signal.

[0105] In the third stage t3, the signal provided by the signal input terminal INPUT is at the high level, the signal provided by the first clock signal terminal CK is at the high level, and the signal provided by the second clock signal terminal CKB is at the low level.

[0106] Since the signal provided by the second clock signal terminal CKB is at the low level, the second transistor T2 is turned on.

[0107] Since the signal provided by the signal input terminal INPUT is at the high level, the first transistor T1 is turned on, and the third transistor T3 is turned off. At this time, the low level voltage VGL provided by the first power supply terminal is written to the first node N1 through the first transistor T1 and the second transistor T2, the voltage at the first node N1 is at the low level, and the fifth transistor T5 and the eighth transistor T8 are both turned on.

[0108] Since the signal provided by the first clock signal terminal CK is at the high level, the fourth transistor T4 is turned off. However, since the fifth transistor T5 is in the on state, the high level voltage VGH provided by the second power supply terminal is written to the third node N3 through the fifth transistor T5, so as to realize the purpose of noise reduction of the voltage at the third node N3. At this time, the seventh transistor T7 is maintained in the off state.

[0109] Since the eighth transistor T8 is turned on, the high level voltage VGH provided by the second power supply terminal can be written to the signal output terminal OUT through the eighth transistor T8, so that the signal output terminal OUT outputs the high level signal.

[0110] Based on the foregoing, it can be seen that the noise reduction circuit 5 (the fifth transistor T5) can play a role in noise reduction of the voltage at the third node N3 in the third stage t3. The noise reduction circuit 5 (the fifth transistor T5) is not a necessary circuit structure provided in the shift register in the embodiments of the present disclosure, so in some embodiments, the noise reduction circuit 5 can be removed according to actual needs (for example, simplifying the circuit structure, reducing the size occupied by the shift register).

[0111] In the fourth stage t4, the signal provided by the signal input terminal INPUT is at the high level, the signal provided by the first clock signal terminal CK is at the low level, and the signal provided by the second clock signal terminal CKB is at the high level.

[0112] Since the signal provided by the second clock signal terminal CKB is at high level, the second transistor T2 is cut off.

[0113] Since the signal provided by the signal input terminal INPUT is at high level, the first transistor T1 is turned on and the third transistor T3 is cut off. At this time, the first node N1 is in floating state and maintains the low level state of the previous stage, and the fifth transistor T5 and the eighth transistor T8 are both maintained in conduction.

[0114] Since the signal provided by the first clock signal terminal CK is at low level, the fourth transistor T4 is turned on, and the high level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4. The voltages at the third node N3 and the fourth node N4 are at high level. At this time, the seventh transistor T7 is in cut-off state. The signal output terminal OUT is in floating state and maintains the high level state of the previous stage, that is, the signal output terminal OUT outputs a high level signal.

[0115] It should be noted that according to the pulse width of the input signal, there may be multiple third stages t3 and multiple fourth stages t4 in one period, and the third stage t3 and the fourth stage t4 are alternately performed.

[0116] In the fifth stage t5, the signal provided by the signal input terminal INPUT is at low level, the signal provided by the first clock signal terminal CK is at low level, and the signal provided by the second clock signal terminal CKB is at high level.

[0117] Since the signal provided by the second clock signal terminal CKB is at high level, the second transistor T2 is cut off.

[0118] Since the signal provided by the signal input terminal INPUT is at low level, the first transistor T1 is cut off and the third transistor T3 is turned on. At this time, the high level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3, and the voltage at the first node N1 is at high level. The fifth transistor T5 and the eighth transistor T8 are both cut off.

[0119] Since the signal provided by the first clock signal terminal CK is at low level, the fourth transistor T4 is turned on. The low level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4, and the voltages at the third node N3 and the fourth node N4 are at low level. At this time, the seventh transistor T7 is turned on.

[0120] The low voltage VGL provided by the first power supply end is written to the signal output end OUT through the seventh transistor T7 due to the conduction of the seventh transistor T7, and thus the signal output end OUT outputs a low level signal. It should be noted that during the fifth stage, the voltages of the third node N3 and the fourth node N4 slowly decrease, and the seventh transistor T7 slowly switches from the off state to the on state, so that the signal output by the signal output end OUT slowly switches from the high level state to the low level state. That is, during the fifth stage, the signal output end OUT actually outputs a high level signal first and then outputs a low level signal. The time when the signal output end OUT outputs the low level signal is related to the discharging speed of the fourth node N4 (the working state of the seventh transistor T7).

[0121] During the sixth stage t6, the signal provided by the signal input end INPUT is in a low level state, the signal provided by the first clock signal end CK is in a high level state, and the signal provided by the second clock signal end CKB is in a low level state.

[0122] The second transistor T2 is turned on due to the low level signal provided by the second clock signal end CKB.

[0123] The first transistor T1 is turned off and the third transistor T3 is turned on due to the low level signal provided by the signal input end INPUT, and at this time, the high level voltage VGH provided by the second power supply end is written to the first node N1, the voltage at the first node N1 is in a high level state, and the fifth transistor T5 and the eighth transistor T8 are both turned off.

[0124] The fourth transistor T4 is turned off due to the high level signal provided by the first clock signal end CK. At this time, the third node N3 and the fourth node N4 are in a floating state and maintain the low level of the previous stage. The seventh transistor T7 is maintained in conduction.

[0125] The low level voltage VGL provided by the first power supply end is written to the signal output end OUT through the seventh transistor T7 due to the conduction of the seventh transistor T7, and thus the signal output end OUT outputs a low level signal.

[0126] During the seventh stage t7, the signal provided by the signal input end INPUT is in a low level state, the signal provided by the first clock signal end CK is in a low level state, and the signal provided by the second clock signal end CKB is in a high level state.

[0127] The second transistor T2 is turned off due to the high level signal provided by the second clock signal end CKB.

[0128] Since the signal provided by the signal input terminal INPUT is at a low level, the first transistor T1 is cut off, and the third transistor T3 is turned on. At this time, the high-level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3, and the voltage at the first node N1 is at a high level. The fifth transistor T5 and the eighth transistor T8 are both cut off.

[0129] Since the signal provided by the first clock signal terminal CK is at a low level, the fourth transistor T4 is turned on. The low-level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4 to perform noise reduction processing on the third node N3. The voltages at the third node N3 and the fourth node N4 are at a low level. At this time, the seventh transistor T7 is turned on.

[0130] Since the seventh transistor T7 is turned on, the low-level voltage VGL provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so that the signal output terminal OUT outputs a low-level signal.

[0131] It should be noted that according to the design of one frame length, there will be multiple sixth stages t6 and multiple seventh stages t7 in one period. The sixth stage t6 and the seventh stage t7 are alternately performed until the first stage of the next period begins.

[0132] Figure 4B For Figure 3B As shown in FIG. 8, the working process of the shift register includes the following stages: Figure 4B

[0133] The first stage t1', the signal provided by the signal input terminal INPUT is at a low level, the signal provided by the first clock signal terminal CK is at a low level, and the signal provided by the second clock signal terminal CKB is at a high level.

[0134] Since the signal provided by the signal input terminal INPUT is at a low level, the first transistor T1 is cut off, and the third transistor T3 is turned on. At this time, the high-level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3, and the voltage at the first node N1 is at a high level. The fifth transistor T5 and the eighth transistor T8 are both cut off.

[0135] ​Since the signal provided by the first clock signal terminal CK is at low level, the second transistor and the fourth transistor T4 are both turned on, at this moment, the low level signal provided by the signal input terminal INPUT can be written to the third node N3 and the fourth node N4 through the fourth transistor, the voltage at the third node N3 and the fourth node N4 is at low level, at this moment, the seventh transistor T7 maintains the conductive state, the low level signal provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so the signal output terminal OUT outputs the low level signal.

[0136] The second stage t2', the signal provided by the signal input terminal INPUT is at high level, the signal provided by the first clock signal terminal CK is at high level, and the signal provided by the second clock signal terminal CKB is at low level.

[0137] Since the signal provided by the signal input terminal INPUT is at high level, the first transistor T1 is turned on, and the third transistor T3 is cut off. At this moment, the first node N1 is in a floating state and maintains the high level state of the previous stage. At this moment, the fifth transistor T5 and the eighth transistor T8 are both maintained to be cut off.

[0138] Since the signal provided by the first clock signal terminal CK is at high level, the second transistor T2 and the fourth transistor T4 are cut off, and the third node N3 and the fourth node N4 are in a floating state, that is, the voltage at the third node N3 and the fourth node N4 maintains the low level state of the previous stage, at this moment, the seventh transistor T7 maintains the conductive state, and the low level signal provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so the signal output terminal OUT outputs the low level signal.

[0139] The third stage t3', the signal provided by the signal input terminal INPUT is at high level, the signal provided by the first clock signal terminal CK is at low level, and the signal provided by the second clock signal terminal CKB is at high level.

[0140] Since the signal provided by the first clock signal terminal CK is at low level, the second transistor T2 and the fourth transistor are both turned on.

[0141] Since the fourth transistor T4 is turned on, the high level signal provided by the signal input terminal INPUT is written to the third node N3 and the fourth node N4 through the fourth transistor, the voltage at the third node N3 and the fourth node N4 is at high level, and the seventh transistor is cut off.

[0142] Meanwhile, since the signal provided by the signal input terminal INPUT is at a high level, the first transistor T1 is turned on, and the third transistor T3 is turned off. At this time, the low-level voltage VGL provided by the first power supply terminal is written to the first node N1 through the first transistor T1 and the second transistor T2, and the voltage at the first node N1 is at a low level, and the fifth transistor T5 and the eighth transistor T8 are both turned on.

[0143] Since the fifth transistor T5 is in a turned-on state, the high-level voltage VGH provided by the second power supply terminal is written to the third node N3 through the fifth transistor T5, so as to achieve the purpose of noise reduction of the voltage at the third node N3.

[0144] Since the eighth transistor T8 is turned on, the high-level voltage VGH provided by the second power supply terminal can be written to the signal output terminal OUT through the eighth transistor T8, so that the signal output terminal OUT outputs a high-level signal.

[0145] Based on the foregoing, it can be seen that the noise reduction circuit 5 (fifth transistor T5) can play a role in noise reduction of the voltage at the third node N3 from the third stage t3'. The noise reduction circuit 5 (fifth transistor T5) is not a necessary circuit structure provided in the shift register in the embodiments of the present disclosure, so in some embodiments, the noise reduction circuit 5 can be removed according to actual needs (for example, simplifying the circuit structure, reducing the size occupied by the shift register).

[0146] In the fourth stage t4', the signal provided by the signal input terminal INPUT is at a high level, the signal provided by the first clock signal terminal CK is at a high level, and the signal provided by the second clock signal terminal CKB is at a low level.

[0147] Since the signal provided by the first clock signal terminal CK is at a high level, the second transistor T2 and the fourth transistor are both turned off.

[0148] Since the signal provided by the signal input terminal INPUT is at a high level, the first transistor T1 is turned on, and the third transistor T3 is turned off. At this time, the first node N1 is in a floating state and maintains the low-level state of the previous stage, and the fifth transistor T5 and the eighth transistor T8 are both maintained in a turned-on state.

[0149] Since the fifth transistor T5 is maintained in a turned-on state, the voltage at the third node N3 can be maintained for noise reduction.

[0150] Since the eighth transistor T8 is turned on, the high-level voltage VGH provided by the second power supply terminal can be written to the signal output terminal OUT through the eighth transistor T8, so that the signal output terminal OUT continuously outputs a high-level signal.

[0151] It should be noted that according to the pulse width of the input signal, there can be multiple third stages t3' and multiple fourth stages t4' in one period, and the third stage t3' and the fourth stage t4' are alternately performed.

[0152] The fifth stage t5', the signal provided by the signal input terminal INPUT is in a low level state, the signal provided by the first clock signal terminal CK is in a low level state, and the signal provided by the second clock signal terminal CKB is in a high level state.

[0153] Since the signal provided by the first clock signal terminal CK is in a low level state, the second transistor T2 and the fourth transistor T4 are turned on. The low level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4, and the voltages at the third node N3 and the fourth node N4 are in a low level state. At this time, the seventh transistor T7 is turned on.

[0154] Since the signal provided by the signal input terminal INPUT is in a low level state, the first transistor T1 is turned off, and the third transistor T3 is turned on. At this time, the high level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3, the voltage at the first node N1 is in a high level state, and the fifth transistor T5 and the eighth transistor T8 are both turned off.

[0155] Since the seventh transistor T7 is turned on, the low level voltage VGL provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so that the signal output terminal OUT outputs a low level signal. It should be noted that during the fifth stage, the voltages at the third node N3 and the fourth node N4 will slowly decrease, and the seventh transistor T7 will slowly switch from the off state to the on state, so that the signal output terminal OUT outputs a high level signal first and then outputs a low level signal during the fifth stage. The time when the signal output terminal OUT outputs a low level signal is related to the discharge speed of the fourth node N4 (the working state of the seventh transistor T7).

[0156] The sixth stage t6', the signal provided by the signal input terminal INPUT is in a low level state, the signal provided by the first clock signal terminal CK is in a high level state, and the signal provided by the second clock signal terminal CKB is in a low level state.

[0157] Since the signal provided by the signal input terminal INPUT is in a low level state, the first transistor T1 is turned off, and the third transistor T3 is turned on. At this time, the high level voltage VGH provided by the second power supply terminal is written to the first node N1, the voltage at the first node N1 is in a high level state, and the fifth transistor T5 and the eighth transistor T8 are both turned off.

[0158] Since the signal provided by the first clock signal terminal CK is at a high level, the second transistor T2 and the fourth transistor T4 are both turned off. At this moment, the third node N3 and the fourth node N4 are in a floating state and maintain the low level of the previous stage. The seventh transistor T7 is maintained in a conductive state.

[0159] Since the seventh transistor T7 is turned on, the low-level voltage VGL provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so that the signal output terminal OUT outputs a low-level signal.

[0160] In the seventh stage t7', the signal provided by the signal input terminal INPUT is at a low level, the signal provided by the first clock signal terminal CK is at a low level, and the signal provided by the second clock signal terminal CKB is at a high level.

[0161] Since the signal provided by the signal input terminal INPUT is at a low level, the first transistor T1 is turned off and the third transistor T3 is turned on. At this moment, the high-level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3, the voltage at the first node N1 is at a high level, and the fifth transistor T5 and the eighth transistor T8 are both turned off.

[0162] Since the signal provided by the first clock signal terminal CK is at a low level, the second transistor T3 and the fourth transistor T4 are both turned on. The low-level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4 to perform noise reduction on the third node N3, and the voltages at the third node N3 and the fourth node N4 are at a low level. At this moment, the seventh transistor T7 is turned on.

[0163] Since the seventh transistor T7 is turned on, the low-level voltage VGL provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so that the signal output terminal OUT outputs a low-level signal.

[0164] It should be noted that according to the design of one frame length, there will be multiple sixth stages t6' and multiple seventh stages t7' in one period, the sixth stage t6' and the seventh stage t7' are alternately performed until the first stage of the next period begins.

[0165] Based on the above content, it can be seen that, Figure 3A and Figure 3B The shift register shown in FIGS. 7 and 8 only includes seven transistors: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8, compared with the traditional 12T2C circuit (including 12 transistors and 2 capacitors), Figure 3A and Figure 3BThe circuit structure of the shift register shown is simpler and occupies less size, and is more conducive to narrow frame design.

[0166] Figure 5A Another circuit structure of the shift register provided by the embodiments of the present disclosure is shown in Figure 5B Another circuit structure of the shift register provided by the embodiments of the present disclosure is shown in Figure 5A and Figure 5B Unlike the previous embodiments in which the preset control signal end CS is the signal input end INPUT, in the embodiments of the present disclosure, the preset control signal end CS is the third node N3. Specifically, Figure 5A and Figure 5B The control electrode of the first transistor T1 in

[0167] Figure 5A and Figure 5B The working timing of the shift register shown in Figure 4A and Figure 4B The specific working process can be referred to the related descriptions of Figure 4A and Figure 4B above, which will not be described here again. It should be noted that based on Figure 4A and Figure 4B , the signal waveform at the third node N3 is similar to the signal waveform at the signal input end INPUT, so when the control electrode of the first transistor T1 is connected to the third node N3, the working state of the first transistor T1 in each stage is the same as when the control electrode of the first transistor T1 is connected to the signal input end INPUT.

[0168] Figure 6A Another circuit structure of the shift register provided by the embodiments of the present disclosure is shown in Figure 6B Another circuit structure of the shift register provided by the embodiments of the present disclosure is shown in Figure 7A Another circuit structure of the shift register provided by the embodiments of the present disclosure is shown in Figure 7B Another circuit structure of the shift register provided by the embodiments of the present disclosure is shown in Figure 6A , 6B , 7A and 7B, unlike the previous embodiments, Figure 6A , 6B , in the embodiments shown in 7A and 7B, the control electrode of the first transistor T1 is connected to the preset control signal end CS Figure 6A and Figure 6B , the preset control signal end CS is the signal input end INPUT, Figure 7A and Figure 7BThe preset control signal terminal CS is coupled to the third node N3. The first terminal of the first transistor T1 is coupled to the second terminal of the second transistor T2. The second terminal of the first transistor T1 is coupled to the first node N1. The control terminal of the second transistor T2 is coupled to the second clock signal terminal CKB or the first clock signal terminal CK. The first terminal of the second transistor T2 is coupled to the first power supply terminal.

[0169] Figure 6A and Figure 7A The timing diagram of the shift register shown can be found in [reference needed]. Figure 4A As shown, Figure 6B and Figure 7B The timing diagram of the shift register shown can be found in [reference needed]. Figure 4B As shown, the specific details will not be repeated here.

[0170] exist Figure 3A , Figure 3B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A and Figure 7B In the illustrated embodiment, the third node N3 and the fourth node N4 are directly connected. During the first and sixth stages, the seventh transistor T7 is controlled by a low-level voltage at the fourth node N4 to output. Generally, to ensure that the seventh transistor T7 can be fully turned on in the first and fifth stages (the gate-source voltage of the seventh transistor T7 needs to be less than or equal to Vth_T7, where Vth_T7 is the threshold voltage of the seventh transistor T7, and Vth_T7≤0V), the voltage at the fourth node N4 needs to be less than or equal to VGL (VGL is generally a negative voltage, such as -9V) to ensure that the signal output terminal OUT can output a low-level voltage VGL. This also requires that the low-level voltage provided by the signal input terminal INPUT is less than or equal to VGL.

[0171] Generally, in the gate driving circuit, the signal input end INPUT of the shift register at the first stage is coupled with the frame start signal end, and the signal input end INPUT of any shift register at other stages is coupled with the signal output end OUT of the shift register at the previous stage. That is, the low voltage at the signal output end OUT of the current shift register is input as the low voltage at the signal input end INPUT of the next shift register. Based on this, it can be seen that the low voltage provided by the frame start signal end needs to be VGL to ensure that the voltage at the fourth node N4 of each shift register at the first stage, the fifth stage and the seventh stage is VGL. However, in actual application, considering the IR Drop and other factors, it is found that the actual voltage VN4 loaded by each shift register at the first stage, the fifth stage and the seventh stage is greater than VGL, and the voltage output by the signal output end OUT is VN4-Vth_T7 (the seventh transistor T7 is turned on first, and the seventh transistor T7 is turned off when the voltage at the signal output end OUT is discharged to VN4-Vth_T7). Since Vth_T7≤0, VN4-Vth_T7>VGL, that is, the signal output end OUT cannot completely output VGL. Once VN4 is too large, the low voltage output by the signal output end OUT will also be too large, which will easily lead to the fact that the low voltage output by the signal output end OUT cannot effectively control the light-emitting control transistor in the pixel driving circuit.

[0172] To effectively improve the above technical problems, the embodiment of the present disclosure further provides a new shift register. Figure 8A A circuit structure diagram of another shift register provided by the embodiment of the present disclosure is shown in Figure 8B A circuit structure diagram of another shift register provided by the embodiment of the present disclosure is shown in Figures 8A to 9B As shown in the above embodiment, Figure 8A and Figure 9B The shift register unit shown in the above embodiment not only includes the circuit structure in the above shift register, but also includes a first capacitor C1; wherein the first end of the first capacitor C1 is coupled with the second clock signal end CKB, and the second end of the first capacitor C1 is coupled with the fourth node N4.

[0173] Figure 9A A working timing diagram of the shift register shown in Figure 8A A working timing diagram of the shift register shown in Figure 9B A working timing diagram of the shift register shown in Figure 8A B. As shown in the above embodiment, Figure 9A and Figure 9B As shown in the above embodiment, Figure 8A The working process of the shift register shown in the above embodiment also includes the first stage t1 to the seventh stage t7 as described above, Figure 9AThe working process of the shift register shown also includes the first stage t1' to the seventh stage t7' as described above. In the first stage t1 and the fifth stage t5, because the third node N3 and the fourth node N4 are in a floating state, when the signal provided by the second clock signal end CKB is switched from a high level state to a low level state, the third node N3 and the fourth node N4 are also pulled down by the bootstrap action of the first capacitor C1.

[0174] Exemplarily, it is assumed that the voltage at the fourth node N4 is VN4 after the end of the fifth stage t5 and before the start of the sixth stage t6, and the voltage output by the signal output end OUT is VN4-Vth_T7. After the start of the sixth stage, when the voltage provided by the second clock signal end CKB is switched from a high level voltage Vgh_C to a low level voltage Vgl_C, the voltage at the third node N3 and the fourth node N4 is pulled down to VN4-(Vgh_C-Vgl_C) by the first capacitor C1. By pre-designing the value of Vgh_C-Vgl_C, VN4-(Vgh_C-Vgl_C) is less than VGL, so the seventh transistor T7 is in a fully open state in the sixth stage, and at this time the signal output end OUT can fully output a low level voltage VGL.

[0175] It should be noted that in the seventh stage t7 and t7' that follows, although the voltage at the fourth node N4 is also pulled up to VN4 by the first capacitor C1, at this time because the gate-source voltage of the seventh transistor T7 is greater than Vth_T7, the seventh transistor T7 is in a cut-off state in the seventh stage t7 and t7', and the signal output end OUT is in a floating state, maintaining the output of a low level voltage VGL.

[0176] Similarly, in the first stage t1 and t1', the voltage at the fourth node N4 is pulled down to VN4-(Vgh_C-Vgl_C) by the first capacitor C1, and the signal output end OUT outputs a low level voltage VGL.

[0177] Based on the above, it can be seen that by setting the first capacitor C1, the signal output end OUT can stably output a low level voltage VGL in the first stage, the sixth stage and the seventh stage.

[0178] Figure 10A Another circuit structure schematic diagram of a shift register provided by the embodiment of the present disclosure, Figure 10B Another circuit structure schematic diagram of a shift register provided by the embodiment of the present disclosure, Figure 11A For Figure 10A A working timing diagram of the shift register shown, Figure 11B For Figure 10B A working timing diagram of the shift register shown, as Figure 10AHezhi Figure 11B As shown, in some embodiments, the shift register includes not only Figure 8A and Figure 8B The first capacitor C1 in the circuit also includes a sixth transistor T6. The sixth transistor T6 is located between the third node N3 and the fourth node N4. The third node N3 is coupled to the fourth node N4 through the sixth transistor T6. The control terminal of the sixth transistor T6 is coupled to the first power supply terminal. The first terminal of the sixth transistor T6 is coupled to the third node N3, and the second terminal of the sixth transistor T6 is coupled to the fourth node N4.

[0179] pass Figure 9A and Figure 9B As can be seen from the timing diagram, due to Figure 8A , Figure 8B The third node N3 and the fourth node N4 are directly connected, so the signals applied to them are always consistent. During the first stage t1, t1' and the sixth stage t6, t6', the voltage at the third node N3 is in an extremely low state (extremely low negative voltage). At this time, the fourth transistor T4 and the fifth transistor T5 will be in a high voltage state (there is a large voltage difference between the first and second terminals of the transistors), which will affect the lifespan of the fourth transistor T4 and the fifth transistor T5.

[0180] To effectively improve the above-mentioned technical problems, in Figure 10A and Figure 10B In the illustrated embodiment, a sixth transistor T6 is disposed between the third node N3 and the fourth node N4. The control electrode of the sixth transistor T6 is coupled to the first power supply terminal to receive a low-level voltage VGL.

[0181] See Figure 11A and Figure 11B As shown, during the first stage t1, t1' and the sixth stage t6, t6', when the voltage at the fourth node N4 is pulled down to VN4-(Vgh_C-Vgl_C) by the first capacitor C1, the gate-source voltage of the sixth transistor T6 will be greater than its own threshold voltage. At this time, the sixth transistor T6 switches to the off state. Therefore, the extremely low negative voltage at the fourth node N4 cannot be written to the third node N3. At this time, the voltage at the third node N3 will maintain the state of the fifth stage (at this time, the third node N3 is in the floating state). Thus, it can effectively prevent the fourth transistor T4 and the fifth transistor T5 from being in a high-voltage state, so as to ensure the service life of the fourth transistor T4 and the fifth transistor T5.

[0182] Figure 12A This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present disclosure. Figure 12B This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present disclosure. Figure 12CAnother circuit structure schematic diagram of a shift register provided by an embodiment of the present disclosure is shown in FIG. 6. Figure 12D Another circuit structure schematic diagram of a shift register provided by an embodiment of the present disclosure is shown in FIG. 6. Figures 12A to 12D As shown in FIG. 6, different from the previous embodiments, the shift register further includes a second capacitor C2. Figures 12A to 12D As shown in FIG. 6, the first end of the second capacitor C2 is coupled to the first node N1, and the second end of the second capacitor C2 is coupled to the first power supply end (not shown in the corresponding figure) or the second power supply end (shown in FIG. 5). Figures 12A to 12D

[0183] In the present embodiment of the present disclosure, the first node N1 is in a floating state during the second stage and the fourth stage. In order to maintain the stability of the voltage of the first node N1 during the second stage and the fourth stage, the second capacitor C2 that plays a voltage stabilizing role is arranged at the first node N1.

[0184] Figures 12A to 12D The shift register shown in FIG. 6 is an 8T2C circuit (including 8 transistors and 2 capacitors), which is simpler in circuit structure and smaller in size than the conventional 12T2C circuit. Figure 13 The circuit structure of the shift register shown in FIG. 6 is simpler and occupies a smaller size, which is more conducive to narrow-frame design.

[0185] Based on the same inventive concept, an embodiment of the present disclosure further provides a gate drive circuit. Figure 13 A circuit structure schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure is shown in FIG. 7. ​ As shown in FIG. 7, the gate drive circuit DC includes a plurality of shift registers SR1-SRm connected in cascade, and the shift registers SR1-SRm adopt the shift register provided by the previous embodiment.

[0186] The signal input end INPUT of the shift register SR1 at the first stage is coupled to the frame start signal end STV. The signal input end INPUT of any shift register SR2-SRm at a stage other than the first stage is coupled to the signal output end OUT of the shift register at the previous stage. The signal output end OUT of each shift register SR1-SRm is further coupled to the light-emitting control signal line EM1-EMm configured for the corresponding pixel unit in the display device.

[0187] ​In some embodiments, the gate driving circuit DC is further configured with two clock signal lines CLK, CLKB: a first clock signal line CLK and a second clock signal line CLKB; wherein the first clock signal end CK of the shift register at the odd stage is coupled with the first clock signal line CLK, and the second clock signal end CKB of the shift register at the odd stage is coupled with the second clock signal line CLKB; the first clock signal end CK of the shift register at the even stage is coupled with the second clock signal line CLKB, and the second clock signal end CKB of the shift register at the even stage is coupled with the first clock signal line CLK.

[0188] The display device provided in the embodiment of the present disclosure can be an OLED panel, an OLED television, a QLED panel, a QLED television, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function; the display device can further include other components, such as a data driving circuit, a timing controller, and the like, and the embodiment of the present disclosure does not limit the display device.

[0189] It should be noted that the display device provided in the embodiment of the present disclosure can be an OLED panel, an OLED television, a QLED panel, a QLED television, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function; the display device can further include other components, such as a data driving circuit, a timing controller, and the like, and the embodiment of the present disclosure does not limit the display device.

[0190] It can be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A shift register, wherein, The application relates to a shift register, comprising: an input circuit, coupled with a signal input end, a first clock signal end and a third node, configured to write a signal provided by the signal input end to the third node in response to a signal provided by the first clock signal end; a first control circuit, coupled with a first power supply end, a preset control signal end, a preset clock signal end and a first node, configured to write a voltage provided by the first power supply end to the first node in response to a signal provided by the preset control signal end and a signal provided by the preset clock signal end; a second control circuit, coupled with a second power supply end, the signal input end and the first node, configured to write a voltage provided by the second power supply end to the first node in response to a signal provided by the signal input end; an output circuit, coupled with a signal output end, the first power supply end, the second power supply end, the first node and a fourth node, configured to write a voltage provided by the second power supply end to the signal output end in response to a voltage at the first node, and write a voltage provided by the first power supply end to the signal output end in response to a voltage at the fourth node, wherein the third node is coupled with the fourth node; the preset control signal end is the third node; or the preset control signal end is the signal input end.

2. The shift register of claim 1, wherein, The first control circuit comprises a first transistor and a second transistor; a control electrode of the first transistor is coupled with the preset control signal end, a first electrode of the first transistor is coupled with the first power supply end, and a second electrode of the first transistor is coupled with a first electrode of the second transistor; a control electrode of the second transistor is coupled with the preset clock signal end, and a second electrode of the second transistor is coupled with the first node.

3. The shift register of claim 1, wherein, The first control circuit comprises a first transistor and a second transistor; a control electrode of the first transistor is coupled with the preset control signal end, a first electrode of the first transistor is coupled with a second electrode of the second transistor, and a second electrode of the first transistor is coupled with the first node; a control electrode of the second transistor is coupled with the preset clock signal end, and a first electrode of the second transistor is coupled with the first power supply end.

4. The shift register of claim 2 or 3, wherein, The first transistor is an N-type transistor, and other transistors in the shift register except the first transistor are P-type transistors.

5. The shift register of claim 4, wherein, The first transistor is a metal oxide transistor, and other transistors in the shift register except the first transistor are low-temperature polysilicon transistors.

6. The shift register of claim 1, wherein, The second control circuit comprises a third transistor; a control electrode of the third transistor is coupled with the signal input end, a first electrode of the third transistor is coupled with the second power supply end, and a second electrode of the third transistor is coupled with the first node.

7. The shift register of claim 1, wherein, The input circuit comprises a fourth transistor; a control electrode of the fourth transistor is coupled with the first clock signal end, a first electrode of the fourth transistor is coupled with the signal input end, and a second electrode of the fourth transistor is coupled with the third node.

8. The shift register of claim 1, wherein, The output circuit comprises a seventh transistor and an eighth transistor; A control electrode of the seventh transistor is coupled with the fourth node, a first electrode of the seventh transistor is coupled with the first power supply end, and a second electrode of the seventh transistor is coupled with the signal output end. A control electrode of the eighth transistor is coupled with the first node, a first electrode of the eighth transistor is coupled with the signal output end, and a second electrode of the eighth transistor is coupled with the second power supply end.

9. The shift register of claim 1, wherein, The shift register further comprises a noise reduction circuit coupled with the second power supply end, the first node and the third node, and configured to write a voltage provided by the second power supply end to the third node in response to a control of a voltage at the first node.

10. The shift register of claim 9, wherein, The noise reduction circuit comprises a fifth transistor. A control electrode of the fifth transistor is coupled with the first node, a first electrode of the fifth transistor is coupled with the third node, and a second electrode of the fifth transistor is coupled with the second power supply end.

11. The shift register of claim 1, wherein, Further comprising a first capacitor. A first end of the first capacitor is coupled with a second clock signal end, and a second end of the first capacitor is coupled with the fourth node.

12. The shift register of claim 11, wherein, Further comprising a sixth transistor, the sixth transistor being located between the third node and the fourth node, and the third node being coupled with the fourth node through the sixth transistor. A control electrode of the sixth transistor is coupled with the first power supply end, a first electrode of the sixth transistor is coupled with the third node, and a second electrode of the sixth transistor is coupled with the fourth node.

13. The shift register of claim 1, wherein, The preset clock signal end is a first clock signal end or a second clock signal end.

14. The shift register of claim 1, wherein, Further comprising a second capacitor. A first end of the second capacitor is coupled with the first node, and a second end of the second capacitor is coupled with the first power supply end or the second power supply end.

15. A gate drive circuit, wherein, Comprising: A plurality of shift registers in cascade, the shift registers being any one of the shift registers in claims 1 to 14. A signal input end of the shift register located at the first stage is coupled with a frame start signal end. For any stage other than the first stage, a signal input end of the shift register is coupled with the signal output end of the shift register of the previous stage.

16. A display device comprising: Comprising: The gate drive circuit as claimed in claim 15.

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