Display panel and display device

Abstract

Provided in the present disclosure are a display panel and a display device. The display panel comprises: a display area and a peripheral area located at the periphery of the display area. The display panel further comprises: a plurality of sub-pixels, a gate driving circuit, and a power signal transmission layer, wherein the plurality of sub-pixels are located in the display area; the gate driving circuit comprises a plurality of shift register units, and the shift register units are coupled to the corresponding sub-pixels; and the power signal transmission layer comprises a portion located in the display area and a portion located in the peripheral area, and the shift register units are coupled to the power signal transmission layer.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, the application range of display products has gradually expanded from small and medium-sized watches, mobile phones, tablets and other fields to PC, Monitor and other fields. In order to achieve better display effect, such as reducing the ghosting effect and improving the response speed of the screen, the refresh rate of the display product is gradually increased, and the gradually increased refresh rate also increases the power consumption of the whole machine processor and chip.

[0003] In specific use scenarios, only part of the display area of the display product is usually changing, such as video playing, game window and the like; the rest of the display area is usually static and does not need to be refreshed at a high refresh rate, such as comment area, advertisement area and the like. In order to reduce power consumption, the display product develops a local refresh function, which controls the frequency of the scanning signal transmitted by the gate drive circuit to the display area through a local refresh module to realize the partition refresh function, so that different display areas in the display panel can realize different refresh rates, thereby reducing the power consumption of the display product.

[0004] SUMMARY

[0005] The purpose of the present disclosure is to provide a display panel and a display device.

[0006] In order to achieve the above purpose, the present disclosure provides the following technical solutions:

[0007] The first aspect of the present disclosure provides a display panel, comprising: a display area and a peripheral area located at the periphery of the display area; the display panel further comprises:

[0008] a plurality of sub-pixels, the plurality of sub-pixels being located in the display area;

[0009] a gate drive circuit, the gate drive circuit comprising a plurality of shift register units, the shift register units being coupled with corresponding sub-pixels;

[0010] a power signal transmission layer, the power signal transmission layer comprising a part located in the display area and a part located in the peripheral area, the shift register units being coupled with the power signal transmission layer.

[0011] Optionally, the power signal transmission layer comprises: a power bus part and a power compensation part.

[0012] The power bus portion is located in the peripheral region, and is coupled with the shift register unit and a power signal input end.

[0013] The power compensation portion is coupled with the power bus portion, and at least part of the power compensation portion is located in the display region.

[0014] Optionally, the power compensation portion includes a plurality of first power compensation lines, each of which is coupled with the power bus portion, and at least part of the first power compensation lines is located in the display region.

[0015] Optionally, the power compensation portion includes a plurality of second power compensation lines, the extension direction of each of the second power compensation lines intersects with the extension direction of each of the first power compensation lines, and each of the second power compensation lines is coupled with at least one of the first power compensation lines.

[0016] Optionally, the first power compensation lines and the second power compensation lines are arranged in the same layer.

[0017] Optionally, the first power compensation lines and the second power compensation lines are arranged in different layers, and at least part of the first power compensation lines is located between the second power compensation lines and a substrate of the display panel.

[0018] Optionally, the sub-pixel includes a sub-pixel driving circuit, and the plurality of sub-pixels include a plurality of sub-pixel driving circuit rows.

[0019] The orthogonal projection of the first power compensation lines on the substrate of the display panel at least partially overlaps with the orthogonal projection of the corresponding sub-pixel driving circuit row on the substrate.

[0020] Between two corresponding sub-pixel driving circuit rows of two adjacent first power compensation lines, there are n sub-pixel driving circuit rows, and n is greater than or equal to 0.

[0021] Optionally, the sub-pixel driving circuit includes a driving transistor, a local refresh control transistor, and a second reset transistor, the gate of the driving transistor is coupled with the second electrode of the local refresh control transistor, and the second electrode of the driving transistor is coupled with the second electrode of the second reset transistor.

[0022] The display panel further includes a second initialization signal line and a local refresh control line, the first electrode of the second reset transistor included in each sub-pixel driving circuit in the corresponding sub-pixel driving circuit row is coupled with the second initialization signal line, and the gate of the local refresh control transistor included in each sub-pixel driving circuit in the corresponding sub-pixel driving circuit row is coupled with the local refresh control line.

[0023] At least a portion of the orthographic projection of the first power compensation line onto the substrate is located between the orthographic projection of the second initialization signal line onto the substrate and the orthographic projection of the local refresh control line onto the substrate.

[0024] Optionally, the display panel further includes data lines, which are coupled to each sub-pixel driving circuit in the corresponding sub-pixel driving circuit column; or,

[0025] The display panel further includes multiple first data lines and multiple second data lines. The first data lines are coupled to the odd-numbered sub-pixel driving circuits in the corresponding sub-pixel driving circuit columns, and the second data lines are coupled to the even-numbered sub-pixel driving circuits in the corresponding sub-pixel driving circuit columns. The orthographic projection of the first data line on the substrate is located on the first side of the orthographic projection of the sub-pixel driving circuit column coupled to it on the substrate, and the orthographic projection of the second data line on the substrate is located on the second side of the orthographic projection of the sub-pixel driving circuit column coupled to it on the substrate, with the second side opposite to the first side.

[0026] Optionally, the plurality of sub-pixels, including the plurality of sub-pixel driving circuits, are divided into multiple columns of sub-pixel driving circuits;

[0027] Between the orthographic projections of two adjacent second power compensation lines on the substrate, there are m columns of sub-pixel driving circuits projected onto the substrate, where m is greater than or equal to 1.

[0028] Optionally, the sub-pixel driving circuit includes a driving transistor and a compensation transistor, wherein the second terminal of the driving transistor is coupled to the first terminal of the compensation transistor;

[0029] The display panel also includes a data line, which is coupled to each sub-pixel driving circuit in the corresponding sub-pixel driving circuit column.

[0030] At least a portion of the orthographic projection of the second power compensation line onto the substrate lies between the orthographic projection of the active layer of the compensation transistor onto the substrate and the orthographic projection of the data line coupled to the sub-pixel driving circuit adjacent to the compensation transistor onto the substrate.

[0031] Optionally, the sub-pixel driving circuit includes a driving transistor and a light-emitting control transistor, wherein the second terminal of the driving transistor is coupled to the first terminal of the light-emitting control transistor;

[0032] The display panel also includes a data line, which is coupled to each sub-pixel driving circuit in the corresponding sub-pixel driving circuit column.

[0033] At least part of the projection of the second power compensation line on the substrate substrate is located between the projection of the active layer of the light emitting control transistor on the substrate substrate and the projection of the data line coupled with the sub-pixel drive circuit adjacent to the compensation transistor on the substrate substrate.

[0034] Optionally, the display panel further comprises a plurality of first data lines and a plurality of second data lines, the first data lines are respectively coupled with odd-numbered sub-pixel drive circuits in the corresponding sub-pixel drive circuit column, and the second data lines are respectively coupled with even-numbered sub-pixel drive circuits in the corresponding sub-pixel drive circuit column.

[0035] The projection of the first data line on the substrate substrate is located on a first side of the projection of the sub-pixel drive circuit column coupled therewith on the substrate substrate, and the projection of the second data line on the substrate substrate is located on a second side of the projection of the sub-pixel drive circuit column coupled therewith on the substrate substrate, the second side being opposite to the first side.

[0036] At least part of the projection of the second power compensation line on the substrate substrate is located between the projection of the first data line on the substrate substrate and the projection of the second data line on the substrate substrate.

[0037] Optionally, the display panel comprises a first power signal transmission layer and a second power signal transmission layer; the first power compensation lines included in the first power signal transmission layer and the first power compensation lines included in the second power signal transmission layer are arranged alternately along a first direction.

[0038] Optionally, the projection of the first power compensation line included in the first power signal transmission layer on the substrate substrate at least partially overlaps with the projection of the odd-numbered row of sub-pixel drive circuits on the substrate substrate, and the projection of the first power compensation line included in the second power signal transmission layer on the substrate substrate at least partially overlaps with the projection of the even-numbered row of sub-pixel drive circuits on the substrate substrate; or, the projection of the first power compensation line included in the first power signal transmission layer on the substrate substrate at least partially overlaps with the projection of the even-numbered row of sub-pixel drive circuits on the substrate substrate, and the projection of the first power compensation line included in the second power signal transmission layer on the substrate substrate at least partially overlaps with the projection of the odd-numbered row of sub-pixel drive circuits on the substrate substrate.

[0039] Optionally, the second power compensation lines included in the first power signal transmission layer and the second power compensation lines included in the second power signal transmission layer are arranged alternately along a second direction, and the second direction intersects the first direction.

[0040] Optionally, the sub-pixel driving circuit comprises a first reset transistor, a second electrode of the first reset transistor being coupled with a gate electrode of the driving transistor;

[0041] The display panel further comprises a first initialization signal transmission layer structure, the first initialization signal transmission layer structure comprising a plurality of first initialization signal lines and a plurality of first initialization compensation lines; the first initialization compensation lines intersect with the extension direction of the first initialization signal lines; the first initialization signal lines are respectively coupled with the first electrodes of the first reset transistors comprised by each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; and the first initialization compensation lines are respectively coupled with at least part of the first initialization signal lines.

[0042] The orthogonal projection of the first initialization compensation lines on the substrate substrate is alternately arranged with the orthogonal projection of the second power compensation lines comprised by the first power signal transmission layer on the substrate substrate along the second direction; and / or, the orthogonal projection of the first initialization compensation lines on the substrate substrate is alternately arranged with the orthogonal projection of the second power compensation lines comprised by the second power signal transmission layer on the substrate substrate along the second direction.

[0043] Optionally, the sub-pixel driving circuit comprises a second reset transistor, a second electrode of the second reset transistor being coupled with a second electrode of the driving transistor;

[0044] The display panel further comprises a second initialization signal transmission layer structure, the second initialization signal transmission layer structure comprising a plurality of second initialization signal lines and a plurality of second initialization compensation lines, the second initialization compensation lines intersect with the extension direction of the second initialization signal lines; the second initialization signal lines are respectively coupled with the first electrodes of the second reset transistors comprised by each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; and the second initialization compensation lines are respectively coupled with at least part of the second initialization signal lines.

[0045] The orthogonal projection of the second initialization compensation lines on the substrate substrate is alternately arranged with the orthogonal projection of the second power compensation lines comprised by the first power signal transmission layer on the substrate substrate along the second direction; and / or, the orthogonal projection of the second initialization compensation lines on the substrate substrate is alternately arranged with the orthogonal projection of the second power compensation lines comprised by the second power signal transmission layer on the substrate substrate along the second direction.

[0046] Optionally, the sub-pixel driving circuit comprises a third reset transistor, a second electrode of the third reset transistor being coupled with a first electrode of the driving transistor;

[0047] The display panel further comprises a third initialization signal transmission layer structure, the third initialization signal transmission layer structure comprises a plurality of third initialization signal lines and a plurality of third initialization compensation lines, the third initialization compensation lines intersect with the extension direction of the third initialization signal lines; the first poles of the third reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits are respectively coupled with the third initialization signal lines; and the third initialization compensation lines are respectively coupled with at least part of the third initialization signal lines;

[0048] The orthogonal projection of the third initialization compensation lines on the substrate substrate is alternately arranged with the orthogonal projection of the second power compensation lines included in the first power signal transmission layer on the substrate substrate along the second direction; and / or, the orthogonal projection of the third initialization compensation lines on the substrate substrate is alternately arranged with the orthogonal projection of the second power compensation lines included in the second power signal transmission layer on the substrate substrate along the second direction.

[0049] Optionally, the sub-pixel drive circuit comprises a first reset transistor, a second reset transistor and a third reset transistor; the second pole of the first reset transistor is coupled with the gate of the drive transistor, the second pole of the second reset transistor is coupled with the second pole of the drive transistor, and the second pole of the third reset transistor is coupled with the first pole of the drive transistor.

[0050] The display panel further comprises a first initialization signal transmission layer structure, a second initialization signal transmission layer structure and a third initialization signal transmission layer structure.

[0051] The first initialization signal transmission layer structure comprises a plurality of first initialization signal lines and a plurality of first initialization compensation lines; the first initialization compensation lines intersect with the extension direction of the first initialization signal lines; the first poles of the first reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits are respectively coupled with the first initialization signal lines; and the first initialization compensation lines are respectively coupled with at least part of the first initialization signal lines.

[0052] The second initialization signal transmission layer structure comprises a plurality of second initialization signal lines and a plurality of second initialization compensation lines, the second initialization compensation lines intersect with the extension direction of the second initialization signal lines; the first poles of the second reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits are respectively coupled with the second initialization signal lines; and the second initialization compensation lines are respectively coupled with at least part of the second initialization signal lines.

[0053] The third initialization signal transmission layer structure includes a plurality of third initialization signal lines and a plurality of third initialization compensation lines, the third initialization compensation lines intersect with the extension direction of the third initialization signal lines; the third initialization signal lines are respectively coupled with the first poles of the third reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the third initialization compensation lines are respectively coupled with at least part of the third initialization signal lines;

[0054] The second initialization compensation lines, the third initialization compensation lines and the first initialization compensation lines are arranged in the second direction in sequence and cyclically; and the second initialization compensation lines, the third initialization compensation lines and the first initialization compensation lines are arranged in the same layer and of the same material.

[0055] The second power supply compensation lines included in the first power supply signal transmission layer and the second power supply compensation lines included in the second power supply signal transmission layer are arranged in the same layer and of the same material, and are arranged in different layers from the first initialization compensation lines.

[0056] Optionally, the display panel includes a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged in the direction away from the substrate substrate in sequence.

[0057] The first power supply compensation lines included in the first power supply signal transmission layer and the first power supply compensation lines included in the second power supply signal transmission layer are arranged in the same layer and of the same material as the first source-drain metal layer.

[0058] The second power supply compensation lines included in the first power supply signal transmission layer and the second power supply compensation lines included in the second power supply signal transmission layer are arranged in the same layer and of the same material as the second source-drain metal layer.

[0059] The second initialization compensation lines, the third initialization compensation lines and the first initialization compensation lines are arranged in the same layer and of the same material as the third source-drain metal layer.

[0060] Optionally, the sub-pixel drive circuit includes a first reset transistor, a second reset transistor and a third reset transistor; the second pole of the first reset transistor is coupled with the gate of the drive transistor, the second pole of the second reset transistor is coupled with the second pole of the drive transistor, and the second pole of the third reset transistor is coupled with the first pole of the drive transistor.

[0061] The display panel further includes a first initialization signal transmission layer structure, a second initialization signal transmission layer structure and a third initialization signal transmission layer structure.

[0062] The first initialization signal transmission layer structure includes a plurality of first initialization signal lines and a plurality of first initialization compensation lines; the first initialization compensation lines intersect the extension direction of the first initialization signal lines; the first initialization signal lines are respectively coupled to the first poles of the first reset transistors included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; and the first initialization compensation lines are respectively coupled to at least part of the first initialization signal lines.

[0063] The second initialization signal transmission layer structure includes a plurality of second initialization signal lines and a plurality of second initialization compensation lines, the second initialization compensation lines intersect the extension direction of the second initialization signal lines; the second initialization signal lines are respectively coupled to the first poles of the second reset transistors included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; and the second initialization compensation lines are respectively coupled to at least part of the second initialization signal lines.

[0064] The third initialization signal transmission layer structure includes a plurality of third initialization signal lines and a plurality of third initialization compensation lines, the third initialization compensation lines intersect the extension direction of the third initialization signal lines; the third initialization signal lines are respectively coupled to the first poles of the third reset transistors included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; and the third initialization compensation lines are respectively coupled to at least part of the third initialization signal lines.

[0065] The plurality of first initialization compensation lines, the plurality of second initialization compensation lines, the plurality of third initialization compensation lines, the plurality of second power supply compensation lines included in the first power supply signal transmission layer, and the plurality of second power supply compensation lines included in the second power supply signal transmission layer are divided into a plurality of first compensation groups, a plurality of second compensation groups, and a plurality of third compensation groups; the first compensation groups, the second compensation groups, and the third compensation groups are arranged in a second direction in cycles.

[0066] The first compensation group includes the second initialization compensation line, the first initialization compensation line, and the third initialization compensation line arranged in sequence.

[0067] The second compensation group includes the second initialization compensation line, the first initialization compensation line, and the second power supply compensation line included in the first power supply signal transmission layer arranged in sequence.

[0068] The second compensation group includes the second initialization compensation line, the first initialization compensation line, and the second power supply compensation line included in the second power supply signal transmission layer arranged in sequence.

[0069] Optionally, the display panel includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer which are sequentially stacked in a direction away from the substrate substrate.

[0070] The first power supply compensation line included in the first power supply signal transmission layer and the first power supply compensation line included in the second power supply signal transmission layer are arranged in the same layer and of the same material as the first source-drain metal layer;

[0071] The second power supply compensation line included in the first power supply signal transmission layer, the second power supply compensation line included in the second power supply signal transmission layer, the second initialization compensation line, the third initialization compensation line and the first initialization compensation line are arranged in the same layer and of the same material as the third source-drain metal layer.

[0072] Optionally, the line width d of the power bus portion satisfies: 50 μm≤d≤150 μm.

[0073] Optionally, the power bus portion includes a first bus layer, a second bus layer and a third bus layer which are sequentially stacked in a direction away from the substrate of the display panel, and the third bus layer is coupled to the first bus layer and the second bus layer respectively.

[0074] Optionally, the display panel further includes a first gate metal layer, a second gate metal layer and a first source-drain metal layer which are sequentially stacked in a direction away from the substrate.

[0075] The first bus layer is arranged in the same layer and of the same material as the first gate metal layer, the second bus layer is arranged in the same layer and of the same material as the second gate metal layer, and the third bus layer is arranged in the same layer and of the same material as the first source-drain metal layer.

[0076] Based on the technical solution of the display panel, the second aspect of the present disclosure provides a display device including the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0077] The accompanying drawings, which are included to provide a further understanding of the present disclosure, constitute a part of the present disclosure, and the illustrative embodiments of the present disclosure and their description serve to explain the present disclosure, and do not constitute improper limitations on the present disclosure. In the drawings:

[0078] FIG. 1 is a circuit schematic diagram of a sub-pixel driving circuit according to an embodiment of the present disclosure;

[0079] FIG. 2 is a schematic diagram of a film layer cross-section of a display panel according to an embodiment of the present disclosure;

[0080] FIG. 3 is a layout schematic diagram of a display area and a peripheral area of a display panel according to an embodiment of the present disclosure;

[0081] FIG. 4 is a layout schematic diagram of various shift register units of a display panel according to an embodiment of the present disclosure;

[0082] FIG. 5 is a first layout diagram of some sub-pixels in a display panel according to an embodiment of the present disclosure;

[0083] FIG. 6 is a layout diagram of a driving circuit of a sub-pixel in FIG. 5;

[0084] FIG. 7 is a layout diagram of a light shielding layer in FIG. 5;

[0085] FIG. 8 is a layout diagram of a first active layer in FIG. 5;

[0086] FIG. 9 is a layout diagram of a first gate metal layer in FIG. 5;

[0087] FIG. 10 is a layout diagram of a second gate metal layer in FIG. 5;

[0088] FIG. 11 is a layout diagram of a second active layer in FIG. 5;

[0089] FIG. 12 is a layout diagram of a third gate metal layer in FIG. 5;

[0090] FIG. 13 is a layout diagram of a deep hole and a blind hole in FIG. 5;

[0091] FIG. 14 is a layout diagram of a blind hole in FIG. 5;

[0092] FIG. 15 is a layout diagram of a first source-drain metal layer in FIG. 5;

[0093] FIG. 16 is a layout diagram of a via in a passivation layer and a first planarization layer in FIG. 5;

[0094] FIG. 17 is a layout diagram of a second source-drain metal layer in FIG. 5;

[0095] FIG. 18 is a layout diagram of a via in a second planarization layer in FIG. 5;

[0096] FIG. 19 is a layout diagram of a light shielding layer and a first active layer in FIG. 5;

[0097] FIG. 20 is a layout diagram of a first active layer and a first gate metal layer in FIG. 5;

[0098] FIG. 21 is a layout diagram of a first gate metal layer and a second gate metal layer in FIG. 5;

[0099] FIG. 22 is a layout diagram of a second gate metal layer and a second active layer in FIG. 5;

[0100] FIG. 23 is a layout diagram of a second active layer and a third gate metal layer in FIG. 5;

[0101] FIG. 24 is a layout diagram of a third gate metal layer, a deep hole and a blind hole in FIG. 5;

[0102] FIG. 25 is a layout schematic diagram of the first source-drain metal layer and the deep hole and the blind hole penetrating through the interlayer insulating layer in FIG. 5;

[0103] FIG. 26 is a layout schematic diagram of the first source-drain metal layer and the second source-drain metal layer in FIG. 5;

[0104] FIG. 27 is a layout schematic diagram of the second source-drain metal layer and the third source-drain metal layer in FIG. 5;

[0105] FIG. 28 is a layout schematic diagram of the third source-drain metal layer and the via included in the third planar layer in FIG. 5;

[0106] FIG. 29 is a layout schematic diagram of the third source-drain metal layer and the anode layer in FIG. 5;

[0107] FIG. 30 is a second layout schematic diagram of a part of the sub-pixel driving circuit in the display panel provided by the embodiment of the present disclosure;

[0108] FIG. 31 is a cross-sectional schematic diagram of FIG. 30 along the horizontal dotted line direction;

[0109] FIG. 32 is a cross-sectional schematic diagram of FIG. 30 along the vertical dotted line direction;

[0110] FIG. 33 is a second layout schematic diagram of the power signal transmission layer in the display panel provided by the embodiment of the present disclosure;

[0111] FIG. 34 is an enlarged schematic diagram of the X1 part in FIG. 33;

[0112] FIG. 35 is a layout schematic diagram of the first source-drain metal layer in the two-row three-column sub-pixel driving circuit under the layout condition of FIG. 30;

[0113] FIG. 36 is a layout schematic diagram of the via included in the passivation layer and the first planar layer in the two-row three-column sub-pixel driving circuit under the layout condition of FIG. 30;

[0114] FIG. 37 is a layout schematic diagram of the second source-drain metal layer in the two-row three-column sub-pixel driving circuit under the layout condition of FIG. 30;

[0115] FIG. 38 is a layout schematic diagram of the via included in the second planar layer in the two-row three-column sub-pixel driving circuit under the layout condition of FIG. 30;

[0116] FIG. 39 is a layout schematic diagram of the first source-drain metal layer and the second source-drain metal layer in the two-row three-column sub-pixel driving circuit under the layout condition of FIG. 30;

[0117] FIG. 40 is a layout schematic diagram of the second source-drain metal layer and the third source-drain metal layer in the two-row three-column sub-pixel driving circuit under the layout condition of FIG. 30;

[0118] FIG. 41 is a layout diagram of the third source-drain metal layer and the via included in the third planarization layer in a two-row three-column sub-pixel driving circuit in the layout of FIG. 30;

[0119] FIG. 42 is a third layout diagram of a power signal transmission layer in a display panel according to an embodiment of the present disclosure;

[0120] FIG. 43 is an enlarged diagram of the X2 portion in FIG. 42;

[0121] FIG. 44 is a cross-sectional view along the horizontal dashed line direction in FIG. 43;

[0122] FIG. 45 is a cross-sectional view along the vertical dashed line direction in FIG. 43;

[0123] FIG. 46 is a layout diagram of the first source-drain metal layer in a two-row nine-column sub-pixel driving circuit in the layout of FIG. 42;

[0124] FIG. 47 is a layout diagram of the via included in the passivation layer and the first planarization layer in a two-row nine-column sub-pixel driving circuit in the layout of FIG. 42;

[0125] FIG. 48 is a layout diagram of the second source-drain metal layer in a two-row nine-column sub-pixel driving circuit in the layout of FIG. 42;

[0126] FIG. 49 is a layout diagram of the via included in the second planarization layer in a two-row nine-column sub-pixel driving circuit in the layout of FIG. 42;

[0127] FIG. 50 is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in a two-row nine-column sub-pixel driving circuit in the layout of FIG. 42;

[0128] FIG. 51 is a layout diagram of the second source-drain metal layer and the third source-drain metal layer in a two-row nine-column sub-pixel driving circuit in the layout of FIG. 42;

[0129] FIG. 52 is a layout diagram of the third source-drain metal layer and the via included in the third planarization layer in a two-row nine-column sub-pixel driving circuit in the layout of FIG. 42;

[0130] FIG. 53 is a fourth layout diagram of a sub-pixel driving circuit in a display panel according to an embodiment of the present disclosure;

[0131] FIG. 54 is a layout diagram of the first source-drain metal layer in a two-row three-column sub-pixel driving circuit in the layout of FIG. 53;

[0132] FIG. 55 is a layout diagram of the via included in the passivation layer and the first planarization layer in a two-row three-column sub-pixel driving circuit in the layout of FIG. 53;

[0133] FIG. 56 is a layout diagram of the second source-drain metal layer in the two-row three-column sub-pixel driving circuit in the layout of FIG. 53;

[0134] FIG. 57 is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in the two-row three-column sub-pixel driving circuit in the layout of FIG. 53;

[0135] FIG. 58 is a layout diagram of the second source-drain metal layer and the third source-drain metal layer in the two-row three-column sub-pixel driving circuit in the layout of FIG. 53;

[0136] FIG. 59 is a fifth layout diagram of the power signal transmission layer in the display panel provided by the embodiment of the present disclosure;

[0137] FIG. 60 is an enlarged diagram of the X3 part in FIG. 59;

[0138] FIG. 61 is a layout diagram of the first source-drain metal layer in the two-row nine-column sub-pixel driving circuit in the layout of FIG. 59;

[0139] FIG. 62 is a layout diagram of the passivation layer and the via included in the first planarization layer in the two-row nine-column sub-pixel driving circuit in the layout of FIG. 59;

[0140] FIG. 63 is a layout diagram of the second source-drain metal layer in the two-row nine-column sub-pixel driving circuit in the layout of FIG. 59;

[0141] FIG. 64 is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in the two-row nine-column sub-pixel driving circuit in the layout of FIG. 59;

[0142] FIG. 65 is a layout diagram of the second source-drain metal layer and the third source-drain metal layer in the two-row nine-column sub-pixel driving circuit in the layout of FIG. 59;

[0143] FIG. 66 is a layout diagram of the power bus part of the display panel provided by the embodiment of the present disclosure on the side close to the power signal output end;

[0144] FIG. 67 is an enlarged diagram of the X4 part in FIG. 66. DETAILED DESCRIPTION

[0145] To further illustrate the display panel and the display device provided by the embodiment of the present disclosure, the following will be described in detail in combination with the drawings of the specification.

[0146] When a display panel adopts a local refresh technology, a part of the display area is a high refresh area, and another part of the display area is a low refresh area. The gate drive circuit is affected by the different refresh rate display areas, and there is a load difference, which causes a bright band problem in the boundary area, especially at the boundary line position where the high refresh area enters the low refresh area. Because the load of the high refresh area is larger than that of the low refresh area, the voltage of the power signal (such as VGH and VGL) connected to the gate drive circuit jumps, which increases the voltage jump when the local refresh control signal on the high frequency side of the boundary line decreases, and lowers the gate voltage of the driving transistor in the sub-pixel drive circuit, thereby generating a bright band at the boundary line.

[0147] Referring to FIG. 3, the display panel provided by the embodiment of the present disclosure includes a display area 10 and a peripheral area 11 located at the periphery of the display area 10. The display panel further includes:

[0148] a plurality of sub-pixels 101 located in the display area 10;

[0149] a gate drive circuit including a plurality of shift register units GOA, the shift register unit GOA being coupled with a corresponding sub-pixel 101;

[0150] a power signal transmission layer (such as a first power signal transmission layer 21 and a second power signal transmission layer 22), the power signal transmission layer including a part located in the display area 10 and a part located in the peripheral area 11, the shift register unit GOA being coupled with the power signal transmission layer.

[0151] For example, the display panel includes the display area 10 and the peripheral area 11, and the peripheral area 11 surrounds the display area 10, but is not limited thereto.

[0152] For example, the display panel includes a plurality of sub-pixels located in the display area 10, and the plurality of sub-pixels are arranged in an array in the display area 10. The sub-pixel includes a sub-pixel drive circuit and a light emitting element. The sub-pixel drive circuit is coupled with the anode of the light emitting element, and is configured to provide a driving signal for the light emitting element to drive the light emitting element to emit light.

[0153] For example, the gate drive circuit includes a plurality of shift register units connected in cascade, and the plurality of shift register units can be located in the peripheral area 11, or at least part of the plurality of shift register units can be arranged in the display area 10 as needed. The shift register unit is coupled with a corresponding sub-pixel, and is configured to provide a corresponding scanning signal for the corresponding sub-pixel.

[0154] It is worth noting that the specific types of the sub-pixel driving circuit and the gate driving circuit are various, and the specific structure of the sub-pixel driving circuit and the specific type of the gate driving circuit will be described below by taking the sub-pixel driving circuit adopting a 9T1C (i.e., including 9 transistors and 1 capacitor) circuit structure as an example.

[0155] As shown in FIG. 1, the sub-pixel driving circuit includes first to ninth transistors T1-T9 and a storage capacitor. The display panel includes a power supply line VDD, a data line DA, a light-emitting control signal line EM, a first scan line PG, a second scan line NG, a third scan line Scan, a first initialization signal transmission layer structure Vinit1, a second initialization signal transmission layer structure Vinit2, and a third initialization signal transmission layer structure Vinit3.

[0156] The gate of the first transistor T1 is coupled with the corresponding third scan line Scan, the first electrode of the first transistor T1 is coupled with the first initialization signal transmission layer structure Vinit1, the second electrode of the first transistor T1 is coupled with the first electrode of the eighth transistor T8, the gate of the eighth transistor T8 is coupled with the corresponding second scan line NG, and the second electrode of the eighth transistor T8 is coupled with the gate T3-g of the third transistor T3.

[0157] The gate of the second transistor T2 is coupled with the corresponding first scan line PG, the first electrode of the second transistor T2 is coupled with the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is coupled with the first electrode of the eighth transistor T8.

[0158] The gate of the fourth transistor T4 is coupled with the corresponding first scan line PG, the first electrode of the fourth transistor T4 is coupled with the corresponding data line DA, and the second electrode of the fourth transistor T4 is coupled with the first electrode of the third transistor T3.

[0159] The gate of the fifth transistor T5 is coupled with the corresponding light-emitting control signal line EM, the first electrode of the fifth transistor T5 is coupled with the corresponding power supply line VDD, and the second electrode of the fifth transistor T5 is coupled with the first electrode of the third transistor T3.

[0160] The gate of the sixth transistor T6 is coupled with the corresponding light-emitting control signal line EM, the first electrode of the sixth transistor T6 is coupled with the second electrode of the third transistor T3, the second electrode of the sixth transistor T6 is coupled with the anode of the light-emitting element, and the cathode of the light-emitting element is connected to a negative power supply signal VSS.

[0161] The gate of the seventh transistor T7 is coupled with the corresponding third scan line Scan', the first electrode of the seventh transistor T7 is coupled with the second initialization signal transmission layer structure Vinit2, and the second electrode of the seventh transistor T7 is coupled with the anode of the light emitting element.

[0162] The gate of the ninth transistor T9 is coupled with the corresponding third scan line Scan', the first electrode of the ninth transistor T9 is coupled with the third initialization signal transmission layer structure Vinit3, and the second electrode of the ninth transistor T9 is coupled with the first electrode of the third transistor T3.

[0163] The first plate Cst1 of the storage capacitor Cst is coupled with the gate of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled with the power supply line VDD. Exemplarily, the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate T3-g of the third transistor T3, but is not limited thereto.

[0164] Exemplarily, the third scan line Scan' to which the seventh transistor T7 and the ninth transistor T9 are coupled corresponds to the third scan line Scan coupled with the first transistor T1 in the next sub-pixel driving circuit adjacent to the sub-pixel driving circuit in the first direction of the display panel, but is not limited thereto.

[0165] As shown in FIG. 4, when the sub-pixel driving circuit adopts the above structure, the gate driving circuit includes a first scan gate driving circuit, a second scan gate driving circuit, a third scan gate driving circuit, and an emission control gate driving circuit. The first scan gate driving circuit includes a plurality of cascaded first scan shift register units (PG GOA). The second scan gate driving circuit includes a plurality of cascaded second scan shift register units (NG GOA). The third scan gate driving circuit includes a plurality of cascaded third shift register units (Scan GOA). The emission control gate driving circuit includes a plurality of cascaded emission control shift register units (EM GOA).

[0166] As shown in FIG. 2, the display panel includes, in sequence from the substrate 70, a buffer layer BF, a first active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, a third gate insulating layer GI3, a second active layer ACT, a fourth gate insulating layer GI4, a third gate metal layer gate3, an interlayer insulating layer ILD, a first source-drain metal layer SD1, a passivation layer PVX, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, a third source-drain metal layer SD3, a third planarization layer PLN3, an anode layer ANO, a pixel definition layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2. As shown in FIG. 7, the display panel further includes a light shielding layer LS.

[0167] In an example, when the display panel is controlled to perform local refresh, the output of the NG GOA is specially controlled, the output of the Scan GOA and the EM GOA is not specially controlled, i.e., the Scan GOA and the EM GOA remain in normal output, and the output of the PG GOA is optionally controlled, i.e., the output of the PG GOA can be specially controlled or the PG GOA remains in normal output.

[0168] In an example, the display panel includes at least one power signal transmission layer, which is coupled to each of the shift register units and configured to provide corresponding power signals to the shift register units. For example, the power signals include a direct current power signal used in the shift register unit with the local refresh module. The local refresh module is added to the shift register unit, so that the shift register unit can perform local refresh on the display area 10.

[0169] In an example, the power signal transmission layer includes a portion located in the display area 10 and a portion located in the peripheral area 11, and the portion located in the display area 10 is coupled to the portion located in the peripheral area 11.

[0170] According to the specific structure of the display panel, the display panel provided by the embodiment of the present disclosure can realize the power signal transmission layer with smaller resistance value by using larger layout space in the display panel, so that the power signal transmitted by the power signal transmission layer is more stable, and the problem of power signal voltage jump caused by the load difference of the shift register units for controlling different refresh rate areas can be effectively prevented, so as to avoid the display difference between different refresh rate display areas 10. Therefore, the display panel provided by the embodiment of the present disclosure can prevent the problem of bright band at the display boundary caused by the load difference between different refresh frequencies during local brushing.

[0171] As shown in FIG. 3, in some embodiments, the power signal transmission layer includes a power bus portion 200 and a power compensation portion 201; the power bus portion 200 is located in the peripheral area 11, the power bus portion 200 is coupled with the shift register unit, and the power bus portion 200 is further coupled with the power signal input end 30; the power compensation portion 201 is coupled with the power bus portion 200, and the power compensation portion 201 includes at least part located in the display area 10.

[0172] For example, the power bus portion 200 is coupled with the power signal input end 30, the power bus portion 200 receives the power signal from the power signal input end 30, and transmits the power signal to the power compensation portion 201 and the shift register unit.

[0173] As shown in FIG. 3, FIG. 5, FIG. 6, FIG. 15, FIG. 30, FIG. 33, FIG. 35, FIG. 39, FIG. 42, FIG. 46, FIG. 53, FIG. 54, FIG. 57, FIG. 59-FIG. 61, and FIG. 64, in some embodiments, the power compensation portion 201 includes a plurality of first power compensation lines 201a, the plurality of first power compensation lines 201a are respectively coupled with the power bus portion 200, and at least part of the first power compensation lines 201a is located in the display area 10.

[0174] For example, the plurality of first power compensation lines 201a are arranged along a first direction, the first power compensation lines 201a include at least part extending along a second direction, and the second direction intersects the first direction. For example, the first direction includes a longitudinal direction, and the second direction includes a transverse direction, but is not limited thereto.

[0175] For example, the first power compensation line 201a can extend from the peripheral area 11 to the inside of the display area 10, for example, the first power compensation line 201a can pass through the display area 10, but not limited thereto.

[0176] The above arrangement mode enables the power signal transmission layer to be arranged in the display area 10 and the peripheral area 11 of the display panel at the same time, so that a larger layout space can be used inside the display panel to realize a power signal transmission layer with smaller resistance, thereby making the power signal transmitted by the power signal transmission layer more stable, effectively preventing the power signal voltage jump problem caused by the load difference of the shift register units controlling different refresh rate areas, thereby avoiding the display difference between different refresh rate display areas 10, and preventing the display of a bright band at the display boundary line caused by the load difference between different refresh frequencies during local brushing.

[0177] More specifically, referring to FIGS. 5-29, the specific arrangement mode of the power compensation part 201 including a plurality of first power compensation lines 201a is shown.

[0178] As shown in FIG. 7, the light shielding layer LS is shown.

[0179] As shown in FIGS. 8 and 11, the first active layer pattern 41 included in the first transistor T1, the second active layer pattern 42 included in the second transistor T2, the third active layer pattern 43 included in the third transistor T3, the fourth active layer pattern 44 included in the fourth transistor T4, the fifth active layer pattern 45 included in the fifth transistor T5, the sixth active layer pattern 46 included in the sixth transistor T6, the seventh active layer pattern 47 included in the seventh transistor T7, the eighth active layer pattern 48 included in the eighth transistor T8, and the ninth active layer pattern 49 included in the ninth transistor T9 are shown. It should be noted that the eighth transistor T8 is an oxide transistor. As shown in FIGS. 10-12 and 21-23, the second scan line NG connected to the gate of the eighth transistor T8 includes a first scan layer NG1 and a second scan layer NG2.

[0180] As shown in FIGS. 6-29, the first conductive connection part 51 is coupled to the first initialization signal line Vinit11 through a first via Via1, and the first conductive connection part 51 is coupled to the first electrode of the first transistor T1 through a second via Via2.

[0181] The second conductive connection part 52 is coupled to the second electrode of the ninth transistor T9 through a third via Via3, and the second conductive connection part 52 is coupled to the second electrode of the fifth transistor T5 through a thirteenth via Via13.

[0182] The third scan line Scan is coupled with the gate of the first transistor T1, the gate of the seventh transistor T7 and the gate of the ninth transistor T9 through the fourth via Via4 respectively.

[0183] The third conductive connection part 53 is coupled with the first electrode of the ninth transistor T9 through the fifth via Via5, and coupled with the third initialization signal line Vinit31 through the sixteenth via Via16.

[0184] The fourth conductive connection part 54 is coupled with the first electrode of the seventh transistor T7 through the sixth via Via6, and coupled with the second initialization signal line Vinit21 through the seventh via Via7.

[0185] The fifth conductive connection part 55 is coupled with the first electrode of the fourth transistor T4 through the eighth via Via8, and coupled with the data line DA through the nineteenth via Via19.

[0186] The sixth conductive connection part 56 is coupled with the first electrode of the eighth transistor T8 through the seventeenth via Via17, and coupled with the second electrode of the second transistor T2 through the ninth via Via9.

[0187] The seventh conductive connection part 57 is coupled with the second electrode of the eighth transistor T8 through the eighteenth via Via18, and coupled with the gate T3-g of the third transistor T3 through the eleventh via Via11.

[0188] The first scan line PG is coupled with the gate of the second transistor T2 and the gate of the fourth transistor T4 through the tenth via Via10.

[0189] The eighth conductive connection part 58 is formed in an integral structure with the first compensation line VDD', and coupled with the first electrode of the fifth transistor T5 through the fourteenth via Via14.

[0190] The first compensation line VDD' is coupled with the second plate Cst2 of the storage capacitor Cst through the twelfth via Via12, and coupled with the power line VDD through the twentieth via Via20, and the power line VDD is coupled with the second compensation line VDD" through the twenty-sixth via Via26.

[0191] The ninth conductive connection 59 is coupled with the second electrode of the sixth transistor T6 through the fifteenth via Via15, coupled with the tenth conductive connection 510 through the twenty-first via Via21, coupled with the fourteenth conductive connection 514 through the twenty-fifth via Via25, and coupled with the anode pattern Anode through the thirtieth via Via30.

[0192] In the embodiment shown in FIGS. 5-29, the power compensation part 201 in the power signal transmission layer only includes the first power compensation line 201a and does not include the second power compensation line 201b. In this case, the first initialization compensation line Vinit12, the second initialization compensation line Vinit22, and the third initialization compensation line Vinit32 can be arranged in the third source-drain metal layer. In this embodiment, each column of sub-pixel drive circuits corresponds to a data line DA.

[0193] As shown in FIGS. 15-18 and 25-28, in the layout area of the first column of sub-pixel drive circuits in the figure, the fourth conductive connection 54 is coupled with the eleventh conductive connection 511 through the twenty-second via Via22, and the eleventh conductive connection 511 is coupled with the second initialization compensation line Vinit22 through the twenty-seventh via Via27.

[0194] In the layout area of the second column of sub-pixel drive circuits in the figure, the first conductive connection 51 is coupled with the twelfth conductive connection 512 through the twenty-third via Via23, and the twelfth conductive connection 512 is coupled with the first initialization compensation line Vinit12 through the twenty-eighth via Via28.

[0195] In the layout area of the third column of sub-pixel drive circuits in the figure, the third conductive connection 53 is coupled with the thirteenth conductive connection 513 through the twenty-fourth via Via24, and the thirteenth conductive connection 513 is coupled with the third initialization compensation line Vinit32 through the twenty-ninth via Via29.

[0196] It is worth noting that in the embodiment shown in FIGS. 5-29, the second initialization compensation line Vinit22, the first initialization compensation line Vinit12, and the third initialization compensation line Vinit32 are arranged in the second direction in sequence.

[0197] In the embodiments shown in FIGS. 53-58, the power compensation portion 201 in the power signal transmission layer includes only the first power compensation lines 201a, but does not include the second power compensation lines 201b. In this case, the first initialization compensation line Vinit12, the second initialization compensation line Vinit22, and the third initialization compensation line Vinit32 can be arranged in the third source-drain metal layer. In this embodiment, each column of sub-pixel drive circuits corresponds to two data lines, such as the first data line DA1 and the second data line DA2.

[0198] It should be noted that the first initialization compensation line Vinit12 can be coupled to the first initialization signal line Vinit11 to form a grid-like structure, which is conducive to reducing the voltage drop generated when the first initialization signal line Vinit11 transmits the first initialization signal. The second initialization compensation line Vinit22 can be coupled to the second initialization signal line Vinit21 to form a grid-like structure, which is conducive to reducing the voltage drop generated when the second initialization signal line Vinit21 transmits the second initialization signal. The third initialization compensation line Vinit32 can be coupled to the third initialization signal line Vinit31 to form a grid-like structure, which is conducive to reducing the voltage drop generated when the third initialization signal line Vinit32 transmits the third initialization signal.

[0199] As shown in FIGS. 30-52 and 59-65, in some embodiments, the power compensation portion 201 includes a plurality of second power compensation lines 201b, the extension direction of the second power compensation lines 201b intersects the extension direction of the first power compensation lines 201a, and the second power compensation lines 201b are respectively coupled to at least part of the first power compensation lines 201a.

[0200] For example, the first power compensation lines 201a and the second power compensation lines 201b are arranged in the same layer. It should be noted that the first power compensation lines 201a and the second power compensation lines 201b in the same power signal transmission layer are arranged in the same layer.

[0201] For example, the first power compensation lines 201a and the second power compensation lines 201b are arranged in different layers, and at least part of the first power compensation lines 201a is located between the second power compensation lines 201b and the substrate of the display panel.

[0202] For example, the plurality of second power compensation lines 201b are arranged along the second direction, and the second power compensation lines 201b include at least part extending along the first direction.

[0203] For example, the second power compensation lines 201b are respectively coupled to the plurality of first power compensation lines 201a.

[0204] The above arrangement mode makes the power signal transmission layer form a mesh structure crossed by the first power compensation line 201a and the second power compensation line 201b, thereby further reducing the resistance of the power signal transmission layer and further improving the stability of the power signal transmitted by the power signal transmission layer.

[0205] More specifically, in the embodiment shown in FIGS. 30-41, the power compensation part 201 in the power signal transmission layer includes both the first power compensation line 201a and the second power compensation line 201b. In this embodiment, the second power compensation line 201b is arranged in the second source-drain metal layer, and the first initialization compensation line Vinit12, the second initialization compensation line Vinit22, and the third initialization compensation line Vinit32 can be arranged in the third source-drain metal layer. In this embodiment, each column of sub-pixel drive circuit columns corresponds to a data line DA.

[0206] In the embodiment shown in FIGS. 30-41, the second initialization compensation line Vinit22, the third initialization compensation line Vinit32, and the first initialization compensation line Vinit12 are arranged in the second direction in sequence.

[0207] Notably, as shown in FIGS. 30-41, in the layout area of the first column of sub-pixel drive circuits in the figure, the fourth conductive connection part 54 is coupled to the eleventh conductive connection part 511 through the twenty-second via Via22, and the eleventh conductive connection part 511 is coupled to the second initialization compensation line Vinit22 through the twenty-seventh via Via27.

[0208] As shown in FIGS. 30-41, in the layout area of the second column of sub-pixel drive circuits in the figure, the third conductive connection part 53 is coupled to the thirteenth conductive connection part 513 through the twenty-fourth via Via24, and the thirteenth conductive connection part 513 is coupled to the third initialization compensation line Vinit32 through the twenty-ninth via Via29.

[0209] As shown in FIGS. 30-41, in the layout area of the third column of sub-pixel drive circuits in the figure, the first conductive connection part 51 is coupled to the twelfth conductive connection part 512 through the twenty-third via Via23, and the twelfth conductive connection part 512 is coupled to the first initialization compensation line Vinit12 through the twenty-eighth via Via28.

[0210] As shown in FIGS. 30-41, in the layout area of the first and third column sub-pixel driving circuit in the figure, the first power compensation line 201a in the first power signal transmission layer 21 is coupled with the second power compensation line 201b in the first power signal transmission layer 21 through the thirty-first via Via31. In the layout area of the second column sub-pixel driving circuit in the figure, the first power compensation line 201a in the second power signal transmission layer 22 is coupled with the second power compensation line 201b in the second power signal transmission layer 22 through the thirty-second via Via32.

[0211] As shown in the embodiment of FIGS. 42-52, the power compensation part 201 in the power signal transmission layer comprises the first power compensation line 201a and the second power compensation line 201b at the same time. In this embodiment, the second power compensation line 201b, the first initialization compensation line Vinit12, the second initialization compensation line Vinit22, and the third initialization compensation line Vinit32 are all arranged in the third source-drain metal layer. In this embodiment, each column of sub-pixel driving circuit column corresponds to a data line DA.

[0212] In the embodiment shown in FIGS. 42-52, the second initialization compensation line Vinit22, the first initialization compensation line Vinit12, the third initialization compensation line Vinit32, the second initialization compensation line Vinit22, the first initialization compensation line Vinit12, the second power compensation line 201b in the first power signal transmission layer 21, the second initialization compensation line Vinit22, the first initialization compensation line Vinit12, and the second power compensation line 201b in the second power signal transmission layer 22 are sequentially arranged in the second direction.

[0213] As shown in FIGS. 42-52, in the layout area of the sixth column sub-pixel driving circuit in the figure, the first power compensation line 201a in the first power signal transmission layer 21 is coupled with the fifteenth conductive connection part 515 through the thirty-fifth via Via35, and the fifteenth conductive connection part 515 is coupled with the second power compensation line 201b in the first power signal transmission layer 21 through the thirty-seventh via Via37.

[0214] As shown in FIGS. 42-52, in the layout area of the ninth column sub-pixel driving circuit in the figure, the first power compensation line 201a in the second power signal transmission layer 22 is coupled with the sixteenth conductive connection part 516 through the thirty-sixth via Via36, and the sixteenth conductive connection part 516 is coupled with the second power compensation line 201b in the second power signal transmission layer 22 through the thirty-eighth via Via38.

[0215] In the embodiment shown in FIGS. 59-65, the power supply compensation part 201 in the power supply signal transmission layer includes the first power supply compensation line 201a and the second power supply compensation line 201b. In this embodiment, the second power supply compensation line 201b, the first initialization compensation line Vinit12, the second initialization compensation line Vinit22, and the third initialization compensation line Vinit32 are arranged in the third source-drain metal layer. In this embodiment, each column of sub-pixel drive circuit columns corresponds to two data lines, such as the first data line DA1 and the second data line DA2.

[0216] In the embodiment shown in FIGS. 59-65, the second initialization compensation line Vinit22, the first initialization compensation line Vinit12, the third initialization compensation line Vinit32, the second initialization compensation line Vinit22, the first initialization compensation line Vinit12, the second power supply compensation line 201b in the first power supply signal transmission layer 21, the second initialization compensation line Vinit22, the first initialization compensation line Vinit12, and the second power supply compensation line 201b in the second power supply signal transmission layer 22 are arranged in the second direction in a cyclic manner.

[0217] As shown in FIGS. 6, 30, and 53, in some embodiments, the sub-pixel includes a sub-pixel drive circuit, and the plurality of sub-pixels includes a plurality of sub-pixel drive circuits that are divided into a plurality of rows of sub-pixel drive circuit rows;

[0218] The normal projection of the first power supply compensation line 201a on the substrate of the display panel at least partially overlaps the normal projection of a corresponding row of sub-pixel drive circuit rows on the substrate.

[0219] Between two rows of sub-pixel drive circuit rows corresponding to two adjacent first power supply compensation lines 201a, there are n rows of sub-pixel drive circuit rows, where n is greater than or equal to 0.

[0220] For example, the plurality of sub-pixel drive circuits included in the plurality of sub-pixels are arranged in an array. The plurality of sub-pixel drive circuits can be divided into a plurality of rows of sub-pixel drive circuit rows and a plurality of columns of sub-pixel drive circuit columns. The plurality of rows of sub-pixel drive circuit rows are arranged in a first direction, and each row of sub-pixel drive circuit rows includes a plurality of sub-pixel drive circuits arranged in a second direction. The plurality of columns of sub-pixel drive circuit columns are arranged in the second direction, and each column of sub-pixel drive circuit columns includes a plurality of sub-pixel drive circuits arranged in the first direction.

[0221] Exemplarily, a projection of the first power supply compensation line 201a on the substrate of the display panel at least partially overlaps with a projection of each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

[0222] Exemplarily, between two rows of sub-pixel driving circuits corresponding to two adjacent first power supply compensation lines 201a, there are n rows of sub-pixel driving circuits, where n is an integer greater than or equal to 0; for example, n is 1, 2, 3, 4, 5, etc., but is not limited thereto.

[0223] The above arrangement enables the first power supply compensation line 201a to have a suitable density in the display area 10, which is conducive to reducing the resistance of the power signal transmission layer and better balancing the layout complexity of the display panel in the display area 10, thereby reducing the overall layout difficulty of the display panel.

[0224] As shown in FIGS. 6, 30 and 53, in some embodiments, the sub-pixel driving circuit includes a driving transistor (such as the third transistor T3), a local refresh control transistor (such as the eighth transistor T8) and a second reset transistor (such as the seventh transistor T7), a gate of the driving transistor is coupled with a second electrode of the local refresh control transistor, and a second electrode of the driving transistor is coupled with a second electrode of the second reset transistor.

[0225] The display panel further includes a second initialization signal line Vinit21 and a local refresh control line (such as the second scan line NG), a first electrode of a second reset transistor included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits is respectively coupled with the second initialization signal line Vinit21, and a gate of a local refresh control transistor included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits is respectively coupled with the local refresh control line.

[0226] At least part of the projection of the first power supply compensation line 201a on the substrate is located between the projection of the second initialization signal line Vinit21 on the substrate and the projection of the local refresh control line on the substrate.

[0227] Exemplarily, the display panel comprises a plurality of second initialization signal lines Vinit21 arranged in sequence along the first direction, the second initialization signal line Vinit21 comprises at least a portion extending along the second direction, and the plurality of second initialization signal lines Vinit21 correspond to the plurality of rows of sub-pixel drive circuit rows one by one, but are not limited thereto.

[0228] Exemplarily, the display panel comprises a plurality of local refresh control lines arranged in sequence along the first direction, the local refresh control line comprises at least a portion extending along the second direction, and the plurality of local refresh control lines correspond to the plurality of rows of sub-pixel drive circuit rows one by one, but are not limited thereto.

[0229] Exemplarily, the orthographic projection of the first power supply compensation line 201a on the substrate substrate is located between the orthographic projection of the second initialization signal line Vinit21 on the substrate substrate and the orthographic projection of the local refresh control line on the substrate substrate.

[0230] The above arrangement mode enables the first power supply compensation line 201a to be arranged in a larger layout space between the second initialization signal line Vinit21 and the local refresh control line, which is beneficial to reduce the layout difficulty of the display panel and improve the yield of the layout.

[0231] As shown in FIGS. 1-52, in some embodiments, the display panel further comprises a data line DA, which is respectively coupled with each sub-pixel drive circuit in the corresponding sub-pixel drive circuit column.

[0232] Exemplarily, the display panel comprises a plurality of data lines DA arranged along the second direction, the data line DA comprises at least a portion extending along the first direction, and the plurality of data lines DA correspond to the plurality of sub-pixel drive circuit columns one by one, but are not limited thereto.

[0233] Exemplarily, the sub-pixel drive circuit comprises a drive transistor and a data writing transistor (such as the fourth transistor), the second electrode of the data writing transistor is coupled with the first electrode of the drive transistor. The data line DA is respectively coupled with the first electrode of the data writing transistor included in each sub-pixel drive circuit in the corresponding sub-pixel drive circuit column.

[0234] As shown in FIGS. 53-65, in some embodiments, the display panel further includes a plurality of first data lines DA1 and a plurality of second data lines DA2, the first data lines DA1 are respectively coupled with odd-numbered sub-pixel drive circuits in a corresponding column of sub-pixel drive circuits, and the second data lines DA2 are respectively coupled with even-numbered sub-pixel drive circuits in a corresponding column of sub-pixel drive circuits; a projection of the first data line DA1 on the substrate is located on a first side of a projection of the column of sub-pixel drive circuits coupled therewith on the substrate, and a projection of the second data line DA2 on the substrate is located on a second side of a projection of the column of sub-pixel drive circuits coupled therewith on the substrate, the second side being opposite to the first side.

[0235] For example, the first data lines DA1 include at least a portion extending along the first direction, the second data lines DA2 include at least a portion extending along the first direction, and the first data lines DA1 and the second data lines DA2 are alternately arranged along the second direction.

[0236] For example, the plurality of first data lines DA1 and the plurality of second data lines DA2 are divided into a plurality of groups of data lines DA groups, the plurality of groups of data lines DA groups are arranged along the second direction, each group of data lines DA group includes adjacent first data lines DA1 and second data lines DA2, and the plurality of groups of data lines DA groups correspond one-to-one to the plurality of columns of sub-pixel drive circuits. In the same group of data lines DA group, the first data lines DA1 are respectively coupled with odd-numbered sub-pixel drive circuits in a corresponding column of sub-pixel drive circuits, and the second data lines DA2 are respectively coupled with even-numbered sub-pixel drive circuits in a corresponding column of sub-pixel drive circuits.

[0237] As shown in FIGS. 6-65, in some embodiments, the plurality of sub-pixels includes a plurality of sub-pixel drive circuits divided into a plurality of columns of sub-pixel drive circuits; between projections of two adjacent second power compensation lines 201b on the substrate, there are projections of m columns of sub-pixel drive circuits on the substrate, m being greater than or equal to 1.

[0238] For example, at least a portion of a projection of the second power compensation line 201b on the substrate is located between projections of adjacent columns of sub-pixel drive circuits on the substrate.

[0239] For example, a projection of the second power compensation line 201b on the substrate is located on one side of a column of sub-pixel drive circuits along the second direction.

[0240] For example, the orthogonal projection of the two adjacent second power supply compensation lines 201b on the substrate has the orthogonal projection of m columns of sub-pixel driving circuit columns on the substrate, where m is an integer greater than or equal to 1; for example, m is 1, 2, 3, 4, 5, etc., but is not limited thereto.

[0241] The above arrangement enables the second power supply compensation line 201b to have a suitable density in the display area 10, which is conducive to reducing the resistance of the power signal transmission layer and better balancing the layout complexity of the display panel in the display area 10, thereby reducing the overall layout difficulty of the display panel.

[0242] As shown in FIG. 30, in some embodiments, the sub-pixel driving circuit includes a driving transistor and a compensation transistor (e.g., the second transistor T2), and the second electrode of the driving transistor is coupled to the first electrode of the compensation transistor.

[0243] The display panel further includes a data line DA, and the data line DA is coupled to each sub-pixel driving circuit in the corresponding column of sub-pixel driving circuits.

[0244] At least part of the orthogonal projection of the second power supply compensation line 201b on the substrate is located between the orthogonal projection of the active layer (e.g., the second active layer pattern 42) of the compensation transistor on the substrate and the orthogonal projection of the data line DA coupled to the sub-pixel driving circuit adjacent to the compensation transistor on the substrate.

[0245] The above arrangement enables the second power supply compensation line 201b to be arranged in a larger layout space between the compensation transistor and the data line DA, which is conducive to reducing the layout difficulty of the display panel and improving the yield of the layout.

[0246] As shown in FIG. 30, in some embodiments, the sub-pixel driving circuit includes a driving transistor and a light-emitting control transistor (e.g., the sixth transistor T6), and the second electrode of the driving transistor is coupled to the first electrode of the light-emitting control transistor.

[0247] The display panel further includes a data line DA, and the data line DA is coupled to each sub-pixel driving circuit in the corresponding column of sub-pixel driving circuits.

[0248] At least part of the orthogonal projection of the second power supply compensation line 201b on the substrate is located between the orthogonal projection of the active layer (e.g., the sixth active layer pattern 46) of the light-emitting control transistor on the substrate and the orthogonal projection of the data line DA coupled to the sub-pixel driving circuit adjacent to the compensation transistor on the substrate.

[0249] The second power compensation line 201b can be arranged in a larger layout space between the light-emitting control transistor and the data line DA, which is conducive to reducing the layout difficulty of the display panel and improving the yield of the layout.

[0250] As shown in FIG. 65, in some embodiments, the display panel further includes a plurality of first data lines DA1 and a plurality of second data lines DA2, the first data lines DA1 are respectively coupled with odd-numbered sub-pixel drive circuits in the corresponding sub-pixel drive circuit column, and the second data lines DA2 are respectively coupled with even-numbered sub-pixel drive circuits in the corresponding sub-pixel drive circuit column; the orthogonal projection of the first data line DA1 on the substrate substrate is located on the first side of the orthogonal projection of the sub-pixel drive circuit column coupled therewith on the substrate substrate, and the orthogonal projection of the second data line DA2 on the substrate substrate is located on the second side of the orthogonal projection of the sub-pixel drive circuit column coupled therewith on the substrate substrate, the second side being opposite to the first side.

[0251] At least part of the orthogonal projection of the second power compensation line 201b on the substrate substrate is located between the orthogonal projection of the first data line DA1 on the substrate substrate and the orthogonal projection of the second data line DA2 on the substrate substrate.

[0252] For example, the plurality of first data lines DA1 and the plurality of second data lines DA2 are divided into the plurality of groups of data lines DA groups, and at least part of the orthogonal projection of the second power compensation line 201b on the substrate substrate is located between the orthogonal projection of the adjacent data line DA group on the substrate substrate.

[0253] The second power compensation line 201b can be arranged in a larger layout space between adjacent data line DA groups, which is conducive to reducing the layout difficulty of the display panel and improving the yield of the layout.

[0254] As shown in FIGS. 6-65, in some embodiments, the display panel includes a first power signal transmission layer 21 and a second power signal transmission layer 22; the first power compensation line 201a included in the first power signal transmission layer 21 and the first power compensation line 201a included in the second power signal transmission layer 22 are arranged alternately along a first direction.

[0255] For example, the first power signal transmitted by the first power signal transmission layer 21 includes a high-level power signal, and the second power signal transmitted by the second power signal transmission layer 22 includes a low-level power signal, but not limited thereto.

[0256] Exemplarily, the first power signal transmission layer 21 is coupled with each of the shift register units, for providing a first power signal for the shift register unit coupled therewith. The second power signal transmission layer 22 is coupled with each of the shift register units, for providing a second power signal for the shift register unit coupled therewith.

[0257] Exemplarily, the first power signal transmission layer 21 comprises a portion located in the display region 10 and a portion located in the peripheral region 11, and the portion located in the display region 10 is coupled with the portion located in the peripheral region 11. The second power signal transmission layer 22 comprises a portion located in the display region 10 and a portion located in the peripheral region 11, and the portion located in the display region 10 is coupled with the portion located in the peripheral region 11.

[0258] Exemplarily, a projection of the first power compensation line 201a included in the first power signal transmission layer 21 on the substrate overlaps at least partially with a projection of the first odd row of sub-pixel driving circuit rows on the substrate, and a projection of the first power compensation line 201a included in the second power signal transmission layer 22 on the substrate overlaps at least partially with a projection of the first even row of sub-pixel driving circuit rows on the substrate; or, a projection of the first power compensation line 201a included in the first power signal transmission layer 21 on the substrate overlaps at least partially with a projection of the first even row of sub-pixel driving circuit rows on the substrate, and a projection of the first power compensation line 201a included in the second power signal transmission layer 22 on the substrate overlaps at least partially with a projection of the first odd row of sub-pixel driving circuit rows on the substrate.

[0259] The above-mentioned arrangement of the first power compensation line 201a included in the first power signal transmission layer 21 and the first power compensation line 201a included in the second power signal transmission layer 22 in the first direction can better ensure the uniformity of the layout of the first power compensation line 201a included in each power signal transmission layer in the display region 10, and can better utilize the layout space in the display region 10 to realize the first power signal transmission layer 21 and the second power signal transmission layer 22 with low resistance.

[0260] As shown in FIGS. 30-52 and 59-65, in some embodiments, the second power compensation line 201b included in the first power signal transmission layer 21 and the second power compensation line 201b included in the second power signal transmission layer 22 are arranged alternately in a second direction intersecting the first direction.

[0261] Exemplarily, the second power compensation lines 201b included in the first power signal transmission layer 21 are located on one side of the corresponding first odd column of sub-pixel drive circuit columns, and the second power compensation lines 201b included in the second power signal transmission layer 22 are located on one side of the corresponding first even column of sub-pixel drive circuit columns; or, the second power compensation lines 201b included in the first power signal transmission layer 21 are located on one side of the corresponding first even column of sub-pixel drive circuit columns, and the second power compensation lines 201b included in the second power signal transmission layer 22 are located on one side of the corresponding first odd column of sub-pixel drive circuit columns.

[0262] The above-mentioned arrangement of the second power compensation lines 201b included in the first power signal transmission layer 21 and the second power compensation lines 201b included in the second power signal transmission layer 22 alternately along the second direction can better ensure the uniformity of the layout of the second power compensation lines 201b included in each power signal transmission layer within the display area 10; at the same time, the layout space within the display area 10 can be better utilized to realize the first power signal transmission layer 21 and the second power signal transmission layer 22 with low resistance.

[0263] In some embodiments, the sub-pixel drive circuit includes a first reset transistor (such as the first transistor T1), and a second electrode of the first reset transistor is coupled with a gate electrode of the drive transistor.

[0264] The display panel further includes a first initialization signal transmission layer structure Vinit1, and the first initialization signal transmission layer structure Vinit1 includes a plurality of first initialization signal lines Vinit11 and a plurality of first initialization compensation lines Vinit12; the first initialization compensation lines Vinit12 intersect with the extension direction of the first initialization signal lines Vinit11; the first initialization signal lines Vinit11 are respectively coupled with the first electrodes of the first reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; the first initialization compensation lines Vinit12 are respectively coupled with at least part of the first initialization signal lines Vinit11; as shown in FIGS. 10 to 28, it should be noted that the first conductive connection part 51 is coupled with the first initialization signal line Vinit11 through the first via Via1, the first conductive connection part 51 is coupled with the twelfth conductive connection part 512 through the twenty-third via Via23, and the twelfth conductive connection part 512 is coupled with the first initialization compensation line Vinit12 through the twenty-eighth via Via28.

[0265] The orthogonal projection of the first initialization compensation line Vinit12 on the substrate substrate is arranged alternately along a second direction with the orthogonal projection of the second power compensation line 201b included in the first power signal transmission layer 21 on the substrate substrate; and / or, the orthogonal projection of the first initialization compensation line Vinit12 on the substrate substrate is arranged alternately along a second direction with the orthogonal projection of the second power compensation line 201b included in the second power signal transmission layer 22 on the substrate substrate.

[0266] In some embodiments, the sub-pixel driving circuit includes a second reset transistor (for example, the seventh transistor T7), a second electrode of the second reset transistor is coupled with a second electrode of the driving transistor;

[0267] The display panel further includes a second initialization signal transmission layer structure Vinit2, the second initialization signal transmission layer structure Vinit2 includes a plurality of second initialization signal lines Vinit21 and a plurality of second initialization compensation lines Vinit22, the second initialization compensation lines Vinit22 intersect with the extension direction of the second initialization signal lines Vinit21; the second initialization signal lines Vinit21 are respectively coupled with the first electrode of the second reset transistor included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; the second initialization compensation lines Vinit22 are respectively coupled with at least part of the second initialization signal lines Vinit21; as shown in FIGS. 10 to 28, it should be noted that the fourth conductive connection part 54 is coupled with the first electrode of the seventh transistor T7 through the sixth via Via6, the fourth conductive connection part 54 is coupled with the second initialization signal line Vinit21 through the seventh via Via7, the fourth conductive connection part 54 is coupled with the eleventh conductive connection part 511 through the twenty-second via Via22, and the eleventh conductive connection part 511 is coupled with the second initialization compensation line Vinit22 through the twenty-seventh via Via27.

[0268] The orthogonal projection of the second initialization compensation line Vinit22 on the substrate substrate is arranged alternately along a second direction with the orthogonal projection of the second power compensation line 201b included in the first power signal transmission layer 21 on the substrate substrate; and / or, the orthogonal projection of the second initialization compensation line Vinit22 on the substrate substrate is arranged alternately along a second direction with the orthogonal projection of the second power compensation line 201b included in the second power signal transmission layer 22 on the substrate substrate.

[0269] In some embodiments, the sub-pixel driving circuit includes a third reset transistor (for example, the ninth transistor T9), a second electrode of the third reset transistor is coupled with a first electrode of the driving transistor;

[0270] The display panel further comprises a third initialization signal transmission layer structure Vinit3, the third initialization signal transmission layer structure Vinit3 comprises a plurality of third initialization signal lines Vinit31 and a plurality of third initialization compensation lines Vinit32, the third initialization compensation lines Vinit32 intersect with the extension direction of the third initialization signal lines Vinit31; the third initialization signal lines Vinit31 are respectively coupled with the first electrode of the third reset transistor included in each sub-pixel driving circuit in the corresponding sub-pixel driving circuit row; the third initialization compensation lines Vinit32 are respectively coupled with at least part of the third initialization signal lines Vinit31; as shown in FIGS. 10-28 and 35-41, it should be noted that the third conductive connection part 53 is coupled with the first electrode of the ninth transistor T9 through the fifth via Via5, the third conductive connection part 53 is coupled with the third initialization signal line Vinit31 through the sixteenth via Via16, the third conductive connection part 53 is coupled with the thirteenth conductive connection part 513 through the twenty-fourth via Via24, and the thirteenth conductive connection part 513 is coupled with the third initialization compensation line Vinit32 through the twenty-ninth via Via29.

[0271] The orthogonal projection of the third initialization compensation line Vinit32 on the substrate substrate is alternately arranged along the second direction with the orthogonal projection of the second power compensation line 201b included in the first power signal transmission layer 21 on the substrate substrate; and / or, the orthogonal projection of the third initialization compensation line Vinit32 on the substrate substrate is alternately arranged along the second direction with the orthogonal projection of the second power compensation line 201b included in the second power signal transmission layer 22 on the substrate substrate.

[0272] Exemplarily, the second power compensation line 201b included in the first power signal transmission layer 21 and the second power compensation line 201b included in the second power signal transmission layer 22 are laid out in the same layer as the first initialization compensation line Vinit12, the second initialization compensation line Vinit22 or the third initialization compensation line Vinit32, but are not limited thereto.

[0273] The above-mentioned alternately arranging the second power compensation line 201b included in each power signal transmission layer and the first initialization compensation line Vinit12, the second initialization compensation line Vinit22 and / or the third initialization compensation line Vinit32 is not only beneficial to improving the uniformity of the layout of the second power compensation line 201b included in each power signal transmission layer and each initialization compensation line in the display area 10; but also can better utilize the layout space in the display area 10 to realize the first power signal transmission layer 21 and the second power signal transmission layer 22 with low resistance.

[0274] As shown in FIGS. 30-41, in some embodiments, the sub-pixel driving circuit includes a first reset transistor, a second reset transistor and a third reset transistor; a second electrode of the first reset transistor is coupled with a gate electrode of the driving transistor, a second electrode of the second reset transistor is coupled with a second electrode of the driving transistor, and a second electrode of the third reset transistor is coupled with a first electrode of the driving transistor;

[0275] The display panel further includes a first initialization signal transmission layer structure Vinit1, a second initialization signal transmission layer structure Vinit2 and a third initialization signal transmission layer structure Vinit3;

[0276] The first initialization signal transmission layer structure Vinit1 includes a plurality of first initialization signal lines Vinit11 and a plurality of first initialization compensation lines Vinit12; the first initialization compensation lines Vinit12 intersect the extension direction of the first initialization signal lines Vinit11; the first initialization signal lines Vinit11 are respectively coupled with the first electrodes of the first reset transistors included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; and the first initialization compensation lines Vinit12 are respectively coupled with at least part of the first initialization signal lines Vinit11;

[0277] The second initialization signal transmission layer structure Vinit2 includes a plurality of second initialization signal lines Vinit21 and a plurality of second initialization compensation lines Vinit22; the second initialization compensation lines Vinit22 intersect the extension direction of the second initialization signal lines Vinit21; the second initialization signal lines Vinit21 are respectively coupled with the first electrodes of the second reset transistors included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; and the second initialization compensation lines Vinit22 are respectively coupled with at least part of the second initialization signal lines Vinit21;

[0278] The third initialization signal transmission layer structure Vinit3 includes a plurality of third initialization signal lines Vinit31 and a plurality of third initialization compensation lines Vinit32; the third initialization compensation lines Vinit32 intersect the extension direction of the third initialization signal lines Vinit31; the third initialization signal lines Vinit31 are respectively coupled with the first electrodes of the third reset transistors included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits; and the third initialization compensation lines Vinit32 are respectively coupled with at least part of the third initialization signal lines Vinit31;

[0279] The second initialization compensation line Vinit22, the third initialization compensation line Vinit32 and the first initialization compensation line Vinit12 are arranged in sequence along a second direction and are arranged in the same layer and of the same material.

[0280] The second power compensation line 201b included in the first power signal transmission layer 21 and the second power compensation line 201b included in the second power signal transmission layer 22 are arranged in the same layer and of the same material, and are arranged in different layers from the first initialization compensation line Vinit12.

[0281] For example, the display panel includes a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged in sequence in a direction away from the substrate substrate; the first power compensation line 201a included in the first power signal transmission layer 21 and the first power compensation line 201a included in the second power signal transmission layer 22 are arranged in the same layer and of the same material as the first source-drain metal layer; the second power compensation line 201b included in the first power signal transmission layer 21 and the second power compensation line 201b included in the second power signal transmission layer 22 are arranged in the same layer and of the same material as the second source-drain metal layer; the second initialization compensation line Vinit22, the third initialization compensation line Vinit32 and the first initialization compensation line Vinit12 are arranged in the same layer and of the same material as the third source-drain metal layer.

[0282] The above arrangement not only helps to improve the uniformity of the layout of the second power compensation line 201b included in each power signal transmission layer and each initialization compensation line in the display area 10; at the same time, it can better utilize the layout space in the display area 10 to realize low-resistance first power signal transmission layer 21 and second power signal transmission layer 22. Moreover, the above arrangement not only ensures that each power signal transmission layer and each initialization signal transmission layer has a low resistance and stable transmission signal, but also appropriately reduces the wiring density of the second power compensation line 201b in each power signal transmission layer and each initialization compensation line, simplifies the layout complexity of the display panel, and reduces the layout difficulty of the display panel.

[0283] As shown in FIGS. 42-52, 59-65, in some embodiments, the sub-pixel drive circuit includes a first reset transistor, a second reset transistor and a third reset transistor; the second electrode of the first reset transistor is coupled to the gate electrode of the drive transistor, the second electrode of the second reset transistor is coupled to the second electrode of the drive transistor, and the second electrode of the third reset transistor is coupled to the first electrode of the drive transistor.

[0284] The display panel further comprises a first initialization signal transmission layer structure Vinit1, a second initialization signal transmission layer structure Vinit2 and a third initialization signal transmission layer structure Vinit3.

[0285] The first initialization signal transmission layer structure Vinit1 comprises a plurality of first initialization signal lines Vinit11 and a plurality of first initialization compensation lines Vinit12; the first initialization compensation lines Vinit12 intersect the extension direction of the first initialization signal lines Vinit11; the first initialization signal lines Vinit11 are respectively coupled with the first poles of the first reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the first initialization compensation lines Vinit12 are respectively coupled with at least part of the first initialization signal lines Vinit11.

[0286] The second initialization signal transmission layer structure Vinit2 comprises a plurality of second initialization signal lines Vinit21 and a plurality of second initialization compensation lines Vinit22, and the second initialization compensation lines Vinit22 intersect the extension direction of the second initialization signal lines Vinit21; the second initialization signal lines Vinit21 are respectively coupled with the first poles of the second reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the second initialization compensation lines Vinit22 are respectively coupled with at least part of the second initialization signal lines Vinit21.

[0287] The third initialization signal transmission layer structure Vinit3 comprises a plurality of third initialization signal lines Vinit31 and a plurality of third initialization compensation lines Vinit32, and the third initialization compensation lines Vinit32 intersect the extension direction of the third initialization signal lines Vinit31; the third initialization signal lines Vinit31 are respectively coupled with the first poles of the third reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the third initialization compensation lines Vinit32 are respectively coupled with at least part of the third initialization signal lines Vinit31.

[0288] The plurality of first initialization compensation lines Vinit12, the plurality of second initialization compensation lines Vinit22, the plurality of third initialization compensation lines Vinit32, the plurality of second power compensation lines 201b included in the first power signal transmission layer 21, and the plurality of second power compensation lines 201b included in the second power signal transmission layer 22 are divided into a plurality of first compensation groups, a plurality of second compensation groups and a plurality of third compensation groups; the first compensation groups, the second compensation groups and the third compensation groups are arranged in a cycle along the second direction.

[0289] The first compensation group comprises the second initialization compensation line Vinit22, the first initialization compensation line Vinit12 and the third initialization compensation line Vinit32 arranged in sequence; the second compensation group comprises the second initialization compensation line Vinit22, the first initialization compensation line Vinit12 and the second power compensation line 201b included in the second power signal transmission layer 22 arranged in sequence; and the third compensation group comprises the second initialization compensation line Vinit22, the first initialization compensation line Vinit12 and the second power compensation line 201b included in the second power signal transmission layer 22 arranged in sequence.

[0290] For example, the display panel comprises a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged in sequence in a direction away from the substrate; the first power compensation line 201a included in the first power signal transmission layer 21 and the first power compensation line 201a included in the second power signal transmission layer 22 are arranged in the same layer and of the same material as the first source-drain metal layer; the second power compensation line 201b included in the first power signal transmission layer 21, the second power compensation line 201b included in the second power signal transmission layer 22, the second initialization compensation line Vinit22, the third initialization compensation line Vinit32 and the first initialization compensation line Vinit12 are arranged in the same layer and of the same material as the third source-drain metal layer.

[0291] The above arrangement not only facilitates the uniformity of the layout of the second power compensation line 201b included in each power signal transmission layer and each initialization compensation line in the display area 10, but also better utilizes the layout space in the display area 10 to realize the low-resistance first power signal transmission layer 21 and the second power signal transmission layer 22. Moreover, the above arrangement appropriately reduces the wiring density of the second power compensation line 201b in each power signal transmission layer and each initialization compensation line while ensuring that each power signal transmission layer and each initialization signal transmission layer has a low resistance and stable signal transmission, simplifies the layout complexity of the display panel and reduces the layout difficulty of the display panel.

[0292] As shown in FIGS. 66 and 67, in some embodiments, the line width d of the power bus portion 200 satisfies 50 μm≤d≤150 μm.

[0293] For example, the line width d of the power bus portion 200 in the first power signal transmission layer 21 and the second power signal transmission layer 22 satisfies the above range.

[0294] Exemplarily, the line width d of the power bus portion 200 can be 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, but is not limited to this.

[0295] Exemplarily, the line width of the power bus portion 200 in the orthographic projection on the substrate substrate is between 50 μm and 150 μm, and can include the end point value.

[0296] The line width of the power bus portion 200 is set in the above range, which further reduces the resistance of the power signal transmission layer and improves the stability of the power signal transmission layer in signal transmission.

[0297] As shown in FIGS. 66 and 67, in some embodiments, the power bus portion 200 includes a first bus layer 2001, a second bus layer 2002 and a third bus layer 2003 which are sequentially stacked in a direction away from the substrate substrate of the display panel, and the third bus layer 2003 is coupled with the first bus layer 2001 and the second bus layer 2002, respectively.

[0298] Exemplarily, the third bus layer 2003 is coupled with the first bus layer 2001 through a forty-first via Via40, and the third bus layer 2003 is coupled with the second bus layer 2002 through a forty-first via Via41.

[0299] Exemplarily, the power bus portion 200 in the first power signal transmission layer 21 and the second power signal transmission layer 22 all adopts the structure including three bus layers.

[0300] Exemplarily, the display panel further includes a first gate metal layer, a second gate metal layer and a first source-drain metal layer which are sequentially stacked in a direction away from the substrate substrate; the first bus layer 2001 is provided in the same layer and the same material as the first gate metal layer, the second bus layer 2002 is provided in the same layer and the same material as the second gate metal layer, and the third bus layer 2003 is provided in the same layer and the same material as the first source-drain metal layer. This setting mode enables each bus layer to be formed in the same patterning process as the existing film layer in the display panel, thereby simplifying the manufacturing process flow of the display panel.

[0301] The power bus portion 200 adopts the above structure, which further reduces the resistance of the power signal transmission layer and improves the stability of the power signal transmission layer in signal transmission.

[0302] The display device provided by the embodiments of the present disclosure also includes the display panel provided by the above embodiments.

[0303] Exemplarily, the display device includes an organic light emitting diode display device, but is not limited thereto.

[0304] It should be noted that the display device can be any product or component with display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, and the like, which further includes a flexible circuit board, a printed circuit board, a back plate, and the like.

[0305] In the display panel provided by the above embodiment, the power signal transmission layer coupled with the shift register unit includes a part located in the display area 10 and a part located in the peripheral area 11, so that the power signal transmission layer can be arranged in the display area 10 and the peripheral area 11 of the display panel at the same time. In this way, a larger layout space can be utilized inside the display panel to realize a power signal transmission layer with a smaller resistance value, so that the power signal transmitted by the power signal transmission layer is more stable, and the problem of power signal voltage jump caused by the load difference of the shift register units for controlling different refresh rate areas can be effectively prevented, thereby avoiding the display difference between different refresh rate display areas 10. Therefore, the display panel provided by the above embodiment can prevent the adverse problem of bright band at the display boundary caused by the load difference between different refresh frequencies during local refresh.

[0306] The display device provided by the embodiments of the present disclosure also has the beneficial effects described above when including the above display panel, which will not be described here again.

[0307] It should be noted that the signal line extending in a certain direction refers to that the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0308] It should be noted that the "same layer" of the embodiments of the present disclosure can refer to a film layer on the same structure layer. Or for example, the film layers on the same layer can be layers formed by using the same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by using the same mask plate through a one-time patterning process. According to different specific patterns, the one-time patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous. These specific patterns can also be at different heights or have different thicknesses.

[0309] In the method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the sequence of the steps, and for those skilled in the art, the changes in the sequence of the steps without creative labor are also within the protection scope of the present disclosure.

[0310] It should be noted that each of the embodiments described in the specification of the present disclosure adopts a progressive description manner, and the same or similar parts between the embodiments can be mutually referred to. Each of the embodiments focuses on the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the product embodiments.

[0311] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure pertains. The terms “first”, “second”, and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms “include”, “contain”, and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect”, “couple”, or “link” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right”, and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0312] It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being “on” or “under” another element, it can be “directly” on or under the other element, or an intervening element can also be present.

[0313] In the description of the above-described embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0314] The above description is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: A display region and a peripheral region located at a periphery of the display region; The display panel further comprises: A plurality of sub-pixels located in the display region; A gate driving circuit comprising a plurality of shift register units coupled with corresponding sub-pixels; A power signal transmission layer comprising a part located in the display region and a part located in the peripheral region, the shift register units being coupled with the power signal transmission layer.

2. The display panel of claim 1, wherein The power signal transmission layer comprises a power bus part and a power compensation part; The power bus part is located in the peripheral region, coupled with the shift register units, and further coupled with a power signal input end; The power compensation part is coupled with the power bus part and comprises at least a part located in the display region.

3. The display panel of claim 2, wherein, The power compensation part comprises a plurality of first power compensation lines, each coupled with the power bus part, at least a part of the first power compensation lines being located in the display region.

4. The display panel of claim 3, wherein, The power compensation part comprises a plurality of second power compensation lines, the extension direction of the second power compensation lines intersecting the extension direction of the first power compensation lines, each of the second power compensation lines being coupled with at least one of the first power compensation lines.

5. The display panel of claim 4, wherein, The first power compensation lines and the second power compensation lines are arranged in the same layer.

6. The display panel of claim 4, wherein, The first power compensation lines and the second power compensation lines are arranged in different layers, at least a part of the first power compensation lines being located between the second power compensation lines and a substrate of the display panel.

7. The display panel of claim 3, wherein, The sub-pixels comprise sub-pixel driving circuits, the plurality of sub-pixels comprising a plurality of sub-pixel driving circuit rows; The orthogonal projection of the first power compensation lines on the substrate at least partially overlaps the orthogonal projection of the corresponding sub-pixel driving circuit row on the substrate; Between two corresponding sub-pixel driving circuit rows of two adjacent first power compensation lines, there are n sub-pixel driving circuit rows, n being greater than or equal to 0.

8. The display panel of claim 7, wherein, The sub-pixel driving circuit comprises a driving transistor, a local refresh control transistor, and a second reset transistor, the gate of the driving transistor being coupled with the second electrode of the local refresh control transistor, and the second electrode of the driving transistor being coupled with the second electrode of the second reset transistor; The display panel further comprises a second initialization signal line and a local refresh control line, the second initialization signal line being coupled with the first electrode of the second reset transistor of each sub-pixel driving circuit in the corresponding sub-pixel driving circuit row, and the local refresh control line being coupled with the gate of the local refresh control transistor of each sub-pixel driving circuit in the corresponding sub-pixel driving circuit row; At least a part of the orthogonal projection of the first power compensation lines on the substrate is located between the orthogonal projection of the second initialization signal line on the substrate and the orthogonal projection of the local refresh control line on the substrate.

9. The display panel of claim 7, wherein, the display panel further comprises a data line coupled to each of the sub-pixel drive circuit columns, respectively; or, the display panel further comprises a plurality of first data lines and a plurality of second data lines, the first data lines are coupled to odd-numbered sub-pixel drive circuits in the corresponding sub-pixel drive circuit columns, respectively, and the second data lines are coupled to even-numbered sub-pixel drive circuits in the corresponding sub-pixel drive circuit columns, respectively; a projection of the first data line on the substrate is located at a first side of a projection of the sub-pixel drive circuit column coupled to the first data line on the substrate, and a projection of the second data line on the substrate is located at a second side of a projection of the sub-pixel drive circuit column coupled to the second data line on the substrate, the second side is opposite to the first side.

10. The display panel of claim 4, wherein, the plurality of sub-pixel drive circuits are divided into a plurality of sub-pixel drive circuit columns; a projection of any two adjacent second power compensation lines on the substrate has a projection of the m sub-pixel drive circuit columns on the substrate, m is greater than or equal to 1.

11. The display panel of claim 10, wherein, the sub-pixel drive circuit comprises a drive transistor and a compensation transistor, a second electrode of the drive transistor is coupled to a first electrode of the compensation transistor; the display panel further comprises a data line coupled to each of the sub-pixel drive circuit columns, respectively; at least part of the projection of the second power compensation line on the substrate is located between a projection of an active layer of the compensation transistor on the substrate and a projection of a data line coupled to the sub-pixel drive circuit adjacent to the compensation transistor on the substrate.

12. The display panel of claim 10, wherein, the sub-pixel drive circuit comprises a drive transistor and a light-emitting control transistor, a second electrode of the drive transistor is coupled to a first electrode of the light-emitting control transistor; the display panel further comprises a data line coupled to each of the sub-pixel drive circuit columns, respectively; at least part of the projection of the second power compensation line on the substrate is located between a projection of an active layer of the light-emitting control transistor on the substrate and a projection of a data line coupled to the sub-pixel drive circuit adjacent to the compensation transistor on the substrate.

13. The display panel of claim 10, wherein, the display panel further comprises a plurality of first data lines and a plurality of second data lines, the first data lines are coupled to odd-numbered sub-pixel drive circuits in the corresponding sub-pixel drive circuit columns, respectively, and the second data lines are coupled to even-numbered sub-pixel drive circuits in the corresponding sub-pixel drive circuit columns, respectively; a projection of the first data line on the substrate is located at a first side of a projection of the sub-pixel drive circuit column coupled to the first data line on the substrate, and a projection of the second data line on the substrate is located at a second side of a projection of the sub-pixel drive circuit column coupled to the second data line on the substrate, the second side is opposite to the first side. At least part of the orthographic projection of the second power supply compensation line on the substrate substrate is located between the orthographic projection of the adjacent first data line on the substrate substrate and the orthographic projection of the second data line on the substrate substrate.

14. The display panel according to any one of claims 7 to 13, wherein, The display panel comprises a first power supply signal transmission layer and a second power supply signal transmission layer; the first power supply compensation line included in the first power supply signal transmission layer and the first power supply compensation line included in the second power supply signal transmission layer are arranged alternately along a first direction.

15. The display panel of claim 14, wherein, The orthographic projection of the first power supply compensation line included in the first power supply signal transmission layer on the substrate substrate at least partially overlaps with the orthographic projection of the first odd row of sub-pixel drive circuit rows on the substrate substrate, and the orthographic projection of the first power supply compensation line included in the second power supply signal transmission layer on the substrate substrate at least partially overlaps with the orthographic projection of the first even row of sub-pixel drive circuit rows on the substrate substrate. Alternatively, The orthographic projection of the first power supply compensation line included in the first power supply signal transmission layer on the substrate substrate at least partially overlaps with the orthographic projection of the first even row of sub-pixel drive circuit rows on the substrate substrate, and the orthographic projection of the first power supply compensation line included in the second power supply signal transmission layer on the substrate substrate at least partially overlaps with the orthographic projection of the first odd row of sub-pixel drive circuit rows on the substrate substrate.

16. The display panel of claim 14, wherein, The second power supply compensation line included in the first power supply signal transmission layer and the second power supply compensation line included in the second power supply signal transmission layer are arranged alternately along a second direction, and the second direction intersects the first direction.

17. The display panel of claim 16, wherein, The sub-pixel drive circuit comprises a first reset transistor, and a second electrode of the first reset transistor is coupled to a gate electrode of the drive transistor. The display panel further comprises a first initialization signal transmission layer structure, the first initialization signal transmission layer structure comprises a plurality of first initialization signal lines and a plurality of first initialization compensation lines; the first initialization compensation lines intersect the extension direction of the first initialization signal lines; the first initialization signal lines are respectively coupled to the first electrodes of the first reset transistors included in the respective sub-pixel drive circuit rows of the corresponding sub-pixel drive circuit; and the first initialization compensation lines are respectively coupled to at least part of the first initialization signal lines. The orthographic projection of the first initialization compensation line on the substrate substrate and the orthographic projection of the second power supply compensation line included in the first power supply signal transmission layer on the substrate substrate are arranged alternately along a second direction; and / or the orthographic projection of the first initialization compensation line on the substrate substrate and the orthographic projection of the second power supply compensation line included in the second power supply signal transmission layer on the substrate substrate are arranged alternately along a second direction. The sub-pixel drive circuit comprises a second reset transistor, and a second electrode of the second reset transistor is coupled to a second electrode of the drive transistor.

18. The display panel of claim 16, wherein, ​ The display panel further comprises a second initialization signal transmission layer structure, the second initialization signal transmission layer structure comprises a plurality of second initialization signal lines and a plurality of second initialization compensation lines, the second initialization compensation lines intersect with the extension direction of the second initialization signal lines; the first poles of the second reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits are respectively coupled with the second initialization signal lines; and the second initialization compensation lines are respectively coupled with at least part of the second initialization signal lines; The normal projection of the second initialization compensation lines on the substrate substrate is alternately arranged with the normal projection of the second power compensation lines included in the first power signal transmission layer on the substrate substrate along the second direction; and / or, the normal projection of the second initialization compensation lines on the substrate substrate is alternately arranged with the normal projection of the second power compensation lines included in the second power signal transmission layer on the substrate substrate along the second direction.

19. The display panel of claim 16, wherein, The sub-pixel drive circuit comprises a third reset transistor, the second pole of the third reset transistor is coupled with the first pole of the drive transistor; The display panel further comprises a third initialization signal transmission layer structure, the third initialization signal transmission layer structure comprises a plurality of third initialization signal lines and a plurality of third initialization compensation lines, the third initialization compensation lines intersect with the extension direction of the third initialization signal lines; the first poles of the third reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits are respectively coupled with the third initialization signal lines; and the third initialization compensation lines are respectively coupled with at least part of the third initialization signal lines; The normal projection of the third initialization compensation lines on the substrate substrate is alternately arranged with the normal projection of the second power compensation lines included in the first power signal transmission layer on the substrate substrate along the second direction; and / or, the normal projection of the third initialization compensation lines on the substrate substrate is alternately arranged with the normal projection of the second power compensation lines included in the second power signal transmission layer on the substrate substrate along the second direction.

20. The display panel of claim 16, wherein, The sub-pixel drive circuit comprises a first reset transistor, a second reset transistor and a third reset transistor; the second pole of the first reset transistor is coupled with the gate of the drive transistor, the second pole of the second reset transistor is coupled with the second pole of the drive transistor, and the second pole of the third reset transistor is coupled with the first pole of the drive transistor; The display panel further comprises a first initialization signal transmission layer structure, a second initialization signal transmission layer structure and a third initialization signal transmission layer structure; The first initialization signal transmission layer structure comprises a plurality of first initialization signal lines and a plurality of first initialization compensation lines; the first initialization compensation lines intersect with the extension direction of the first initialization signal lines; the first poles of the first reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits are respectively coupled with the first initialization signal lines; and the first initialization compensation lines are respectively coupled with at least part of the first initialization signal lines; The second initialization signal transmission layer structure includes a plurality of second initialization signal lines and a plurality of second initialization compensation lines, the second initialization compensation lines intersect the extension direction of the second initialization signal lines; the second initialization signal lines are respectively coupled with the first electrodes of the second reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the second initialization compensation lines are respectively coupled with at least part of the second initialization signal lines; The third initialization signal transmission layer structure includes a plurality of third initialization signal lines and a plurality of third initialization compensation lines, the third initialization compensation lines intersect the extension direction of the third initialization signal lines; the third initialization signal lines are respectively coupled with the first electrodes of the third reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the third initialization compensation lines are respectively coupled with at least part of the third initialization signal lines; The second initialization compensation lines, the third initialization compensation lines and the first initialization compensation lines are arranged in the second direction in turn and cyclically; the second initialization compensation lines, the third initialization compensation lines and the first initialization compensation lines are arranged in the same layer and of the same material; The second power supply compensation line included in the first power supply signal transmission layer and the second power supply compensation line included in the second power supply signal transmission layer are arranged in the same layer and of the same material, and are arranged in different layers from the first initialization compensation line.

21. The display panel of claim 20, wherein, The display panel includes a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged in the direction away from the substrate in turn; The first power supply compensation line included in the first power supply signal transmission layer and the first power supply compensation line included in the second power supply signal transmission layer are arranged in the same layer and of the same material as the first source-drain metal layer; The second power supply compensation line included in the first power supply signal transmission layer and the second power supply compensation line included in the second power supply signal transmission layer are arranged in the same layer and of the same material as the second source-drain metal layer; The second initialization compensation lines, the third initialization compensation lines and the first initialization compensation lines are arranged in the same layer and of the same material as the third source-drain metal layer.

22. The display panel of claim 16, wherein, The sub-pixel drive circuit includes a first reset transistor, a second reset transistor and a third reset transistor; the second electrode of the first reset transistor is coupled with the gate electrode of the drive transistor, the second electrode of the second reset transistor is coupled with the second electrode of the drive transistor, and the second electrode of the third reset transistor is coupled with the first electrode of the drive transistor; The display panel further includes a first initialization signal transmission layer structure, a second initialization signal transmission layer structure and a third initialization signal transmission layer structure; The first initialization signal transmission layer structure includes a plurality of first initialization signal lines and a plurality of first initialization compensation lines; the first initialization compensation lines intersect the extension direction of the first initialization signal lines; the first initialization signal lines are respectively coupled with the first electrodes of the first reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the first initialization compensation lines are respectively coupled with at least part of the first initialization signal lines; The second initialization signal transmission layer structure includes a plurality of second initialization signal lines and a plurality of second initialization compensation lines, the second initialization compensation lines intersect the extension direction of the second initialization signal lines; the second initialization signal lines are respectively coupled with the first electrodes of the second reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the second initialization compensation lines are respectively coupled with at least part of the second initialization signal lines; The third initialization signal transmission layer structure includes a plurality of third initialization signal lines and a plurality of third initialization compensation lines, the third initialization compensation lines intersect the extension direction of the third initialization signal lines; the third initialization signal lines are respectively coupled with the first electrodes of the third reset transistors included in each sub-pixel drive circuit in the corresponding row of sub-pixel drive circuits; and the third initialization compensation lines are respectively coupled with at least part of the third initialization signal lines; The plurality of first initialization compensation lines, the plurality of second initialization compensation lines, the plurality of third initialization compensation lines, the plurality of second power supply compensation lines included in the first power supply signal transmission layer, and the plurality of second power supply compensation lines included in the second power supply signal transmission layer are divided into a plurality of first compensation groups, a plurality of second compensation groups, and a plurality of third compensation groups; the first compensation groups, the second compensation groups, and the third compensation groups are arranged in cycles along a second direction; The first compensation group includes the second initialization compensation lines, the first initialization compensation lines, and the third initialization compensation lines arranged in sequence; The second compensation group includes the second initialization compensation lines, the first initialization compensation lines, and the second power supply compensation lines included in the first power supply signal transmission layer arranged in sequence; The second compensation group includes the second initialization compensation lines, the first initialization compensation lines, and the second power supply compensation lines included in the second power supply signal transmission layer arranged in sequence.

23. The display panel of claim 22, wherein The display panel includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in sequence in a direction away from the substrate substrate; The first power supply compensation lines included in the first power supply signal transmission layer and the first power supply compensation lines included in the second power supply signal transmission layer are both arranged in the same layer and of the same material as the first source-drain metal layer; The second power supply compensation lines included in the first power supply signal transmission layer, the second power supply compensation lines included in the second power supply signal transmission layer, the second initialization compensation lines, the third initialization compensation lines, and the first initialization compensation lines are all arranged in the same layer and of the same material as the third source-drain metal layer.

24. The display panel according to any one of claims 2 to 13, wherein, The line width d of the power bus portion satisfies: 50 μm ≤ d ≤ 150 μm.

25. The display panel according to any one of claims 2 to 13, wherein, The power bus portion includes a first bus layer, a second bus layer, and a third bus layer arranged in sequence in a direction away from the substrate substrate of the display panel, and the third bus layer is respectively coupled with the first bus layer and the second bus layer.

26. The display panel of claim 25, wherein, The display panel further includes a first gate metal layer, a second gate metal layer, and a first source-drain metal layer arranged in sequence in a direction away from the substrate substrate; The first bus layer is arranged in the same layer and material as the first gate metal layer, the second bus layer is arranged in the same layer and material as the second gate metal layer, and the third bus layer is arranged in the same layer and material as the first source-drain metal layer.

27. A display device comprising the display panel according to any one of claims 1 to 26. ​

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