Random number generator quality analyzer

Abstract

FIELD: computing technology.SUBSTANCE: invention can be used for hardware implementation of the evaluation of random number generators (RNG) based on repeating codes in the output sequence from the RNG. A random number generator quality analyser includes a shift register, a decoder, a comparison unit, a counter, a logarithm calculator, a divider, and a square root calculator, wherein the first input of the device is connected to the input of the shift register, the output of which is connected to the first input of the comparison unit, the second input of the device is connected to the input of the decoder, the output of which is connected to the second input of the comparison unit, the output of which is connected to the input of the counter, the output of which is connected to the input of the logarithm calculator and to the input of the divider, built on the basis of the CORDIC algorithm, the output of which is connected to the input of the square root calculator, the output of which is connected to the output of the device, wherein the output of the logarithm calculator is connected to the input of the divider.EFFECT: expanding the information field for assessing the quality of the RNG operation during hardware implementation.2 cl, 5 dwg

Description

[0001] The invention relates to computing technology and can be used for hardware implementation of the evaluation of random number generators (hereinafter referred to as RNG) based on repeating codes in the output sequence from the RNG.

[0002] Technology Level

[0003] Various solutions are known from the prior art relating to the control of a random number generator, for example, inventions under USSR Author's Certificates 1087993, 1088011, 1302274, 333551, 1038942, 1674118, 744608, 1084813, 1020837, 1022169 relating to the design of devices for controlling random number generators, for example:

[0004] Decision according to the USSR AS 1087993 a device for monitoring a random number generator containing an AND element, a control unit, wherein in order to increase the speed and simplify the device, it contains a decoder, a group of triggers, two counters, a clock pulse generator, a trigger and a time interval generation unit, the control unit contains an INHIBITION element and an AND element, the output of which is connected to the "Start" input of the time interval generation unit, with the zero inputs of the group triggers and with the zero input of the trigger, the single output of which is the "Fault" output of the device, the output of the clock pulse generator is connected to the counting input of the first counter, with the first inputs of the INHIBITION element and the AND element and with the input of the controlled random number generator, the outputs of the bits of which are connected to the inputs of the corresponding bits of the decoder, the outputs of which are connected to the single inputs of the corresponding group triggers, the outputs of which are connected to the inputs of the AND element, respectively,the output of which is connected to the counting input of the second counter, to the "Reset" input of the time interval generation unit, to the second inputs of the AND element and the INHIBITION element, the output of which is connected to the synchronizing input of the decoder, the output of the time interval generation unit is connected to the single input of the trigger, the carry output of the first counter is connected to the "Reset" input of the second counter, the information outputs of the first and second counters are respectively the first and second information outputs of the device,

[0005] Or

[0006] A DEVICE FOR CONTROLLING A RANDOM NUMBER GENERATOR according to AS USSR No. 1088011 comprising a clock pulse generator, the output of which is connected to the input of a controlled random number generator, a first AND element, a second AND element, the first input of which is connected to the output of the first AND element, an RS trigger, the direct output of which is connected to the second input of the second AND element, a counter, while the device contains two OR elements, a third AND element, a fourth AND element, the first input of which is connected to the inverse output of the trigger, the first input of the first OR element is connected to the output of the first AND element, and its second input to the second input of the fourth AND element and to the output of the third AND element, the output of the first OR element to the counting input of the counter, the first input of the second OR element to the R-input of the trigger and to the output of the second AND element, the second input of the second OR element to the S-input of the trigger and the output of the fourth AND element, and the output of the second OR element to R-input of the counter.

[0007] The disadvantages of the given and similar known solutions are the limited scope of research (analysis), since the RNG in these cases operates only on the single-bit width of the output word.

[0008] There are also publications concerning the use of RNGs using various approaches, including those related to control, for example:

[0009] Implementation Guidance for FIPS PUB 140-1 and the Cryptographic Module Validation Program, US Department of Commerce / National Institute of Standards and Technology, updated January 10, 2002.

[0010] Implementation Guidance for FIPS PUB 140-2 and the Cryptographic Module Validation Program, US Department of Commerce / National Institute of Standards and Technology, updated September 22, 2004.

[0011] Annex C: Approved Random Number Generators for FIPS PUB 140-2, Security Requirements for Cryptographic Modules, U.S. Department Of Commerce / National Institute of Standards and Technology, 19 March 2007, (pdf, 129 kB).

[0012] Federal Information Processing Standard, FIPS PUB 180-4 Secure Hash Standard (SHS), U.S. Department of Commerce / National Institute of Standards and Technology, August 2015. (NIST.FIPS. 180-4).

[0013] стандарт обработки информации Federal Information Processing Standard, FIPS PUB 198-1 The Keyed-Hash Message Authentication Code (HMAC), U.S. Department of Commerce / National Institute of Standards and Technology, July 2008. (NIST.FIPS. 198-1).

[0014] Программная генерация практически стойких случайных чисел Peter Gutmann, Software Generation of Practically Strong Random Numbers presented at the 1998 Usenix Security Symposium, and the updated version dated June 2000, both available from

[0015] <http: / / www. cs. auckland. ac.nz / ~pgut001 / >.

[0016] Intel Corporation, Intel Digital Random Number Generator (DRNG) Software Implmentation Guide, ID 658356, Revision 2.1, October 17, 2018 (link accessed December 2023).

[0017] John Kelsey, Bruce Schneier, David Wagner, Chris Hall, Cryptanalytic Attacks on Pseudorandom Number Generators, March 1998, available from <http: / / www.schneier.com / paper-prngs.html>.

[0018] LavaRnd, Terms & Definitions: pseudo-random number generator, <http: / / www.lavarnd.org / faq / prng.html>, (accessed September 2007).

[0019] NIST Special Publication 800-90A, Recommendation for Random Number Generation Using Deterministic Random Bit Generators, Elaine Barker and John Kelsey, National Institute of Standards and Technology, June 2015. NIST.SP.800-90Arl.

[0020] At the same time, the cited sources of information mainly disclose information about the designs of RNGs and the principles of their operation, without disclosing the devices related to the analysis of the results of the operation and control of random number generators.

[0021] Disclosure of invention

[0022] The technical problem that the present invention is aimed at solving is the creation of a device that makes it possible to evaluate the quality (stochasticity) of a number of repeating sequences of output bit data, which is important information for the developer of the RNG.

[0023] The technical result of the claimed invention is the expansion of the information field for assessing the quality of the RNG operation during hardware implementation.

[0024] The technical result is achieved in that a random number generator quality analyzer is proposed, which includes a shift register, a decoder, a comparison unit, a counter, a logarithm calculator, a divider, and a square root calculator, wherein the first input of the device is connected to the input of the shift register, the output of which is connected to the first input of the comparison unit, the second input of the device is connected to the input of the decoder, the output of which is connected to the second input of the comparison unit, the output of which is connected to the input of the counter, the output of which is connected to the input of the logarithm calculator and to the input of the divider, the output of which is connected to the input of the square root calculator, the output of which is connected to the output of the device, wherein the output of the logarithm calculator is connected to the input of the divider;

[0025] The logarithm calculation unit of which includes a first register with two inputs that are also the inputs of the logarithm calculation unit, a constant unit, a counter, a first comparison unit, a second comparison unit, a counter, a third comparison unit, a shift register, a multiplication unit, a negation unit, a register, a fourth comparison unit, a register, wherein the output of the first comparison unit is connected to the input of the first register and the input of the counter, the input of which is connected to the output of the first register, and the input of the counter is connected to the output of the shift register, the input of which is connected to the output of the multiplication unit, the input of which is connected to the output of the counter and the input of the third comparison unit, the output of which is connected to the input of the register, the second input of which is connected to the input of the multiplication unit and the output of the negation unit, the input of which is connected to the input of the counter and the output of the second comparison unit, the input of which is connected to the input of the first comparison unit, with the output of the counter and the input of the fourth comparison unit,whose output is connected to the input of a register, whose input is connected to the output of a register, and the output of the logarithm calculation unit is the output of the register unit. The combination of the above essential features results in the following:

[0026] The result of analysis of repeating sequences of bit combinations, this characteristic supplements the information capacity for the RNG developer, since the bit depth of the bit sequence for analysis can be more than 4 digits;

[0027] Despite the complexity of the device in comparison with known ones, the proposed solution is an option for additional analysis that requires large hardware costs, but at the same time increases the information field of view of the RNG developer.

[0028] Brief description of drawings

[0029] The proposed invention is explained by the figures: Figure 1 shows a functional diagram of the claimed device for monitoring the RNG, where the positions indicate:

[0030] 1 - shift register, 2 - decoder, 3 - comparison unit, 4 - counter, 5 - logarithm calculator, 6 - divider, 7 - square root calculator, 8 - device input to the shift register, 9 - device input to the decoder input, 10 - device output, 11 - output of shift register 1, 12 - input of comparison unit 3, 13 - output of decoder 2, 14 - input of comparison unit 3, 15 - output of comparison unit 3, 16 - input of counter 4, 17 - output of counter 4, 18 - input of logarithm calculator 5, 19- input of divider 6, 20- output of logarithm calculator 5, 21 - input of divider 6, 22 - output of divider 6, 23 - input of square root calculator 7.

[0031] Figure 2 shows the block for calculating the logarithm 5, where the positions indicate:

[0032] 24 - first register, 25 - constant block, 26 - counter, 27 - first comparison block, 28 - second comparison block, 29 - counter, 30 - third comparison block, 31 - shift register, 32 - multiplication block, 33 - negation block, 34 - register, 35 - fourth comparison block, 36 - register, 37 - first input of calculation block 5, 38 - second input of calculation block 5, 39 - output of logarithm calculation block 5, 40 - output of first comparison block 27, 41 - input of first register 24, 42 - input of counter 29, 43 - input of counter 29, 44 - output of first register 24, 45 - input of counter 29, 46 - output of shift register 31, 47 - input of shift register 31, 48 - output of block multiplication 32, 49 - input of multiplication block 32, 50 - output of counter 29, 51 - input of third comparison block 30, 52 - output of third comparison block 30, 53 - input of register 34, 54 - second input of register 34, 55 - input of multiplication block 32, 56 - output of negation block 33, 57 - input of negation block 33, 58 - input of counter 26,59 - output of the second comparison block 28, 60 - input of the comparison block 28, 61 - input of the first comparison block 27, 62 - output of the counter 26, 63 - input of the fourth comparison block 35, 64 output of the fourth comparison block 35, 65 - input of register 36, 66 input of register 36, 67 - output of register 34.,

[0033] Figure 3 shows the result of calculating the logarithm

[0034] Figure 4 shows the structure of the simulation system

[0035] Figure 5 shows the RNG testing result

[0036] Implementation of the invention

[0037] The most important characteristic of the RNG is the parameter - entropy -

[0038]

[0039] This value should be as close to 1 as possible. However, there are a number of other characteristics used to evaluate the quality of a RNG. The proposed device is a hardware implementation of RNG evaluation based on repeating codes in the RNG output sequence. The feasibility of this approach enhances the information available to the RNG developer.

[0040] The device includes a shift register 1, a decoder 2, a comparison unit 3, a counter 4, a logarithm calculator 5, a divider 6 and a square root calculator 7. Input 8 is connected to the input of shift register 1, input 9 is connected to the input of decoder 2, output 10 is connected to the square root calculator 7. Output 11 of shift register 1 is connected to input 12 of comparison unit 3, and output 13 of decoder 2 is connected to input 14 of comparison unit 3, output 15 of which is connected to input 16 of counter 4. Output 17 of counter 4 is connected to input 18 of logarithm calculator 5 and to input 19 of divider 6, and output 20 of logarithm calculator 5 is connected to input 21 of divider 6, output 22 of which is connected to input 23 of square root calculator 7. The divisor 6 and the square root calculator 7 are built on the basis of the KOR DIK algorithm.Shift register 1 can be of any bit capacity, in this variant a four-bit register is considered, accordingly the combinations “0”, “1”, “00”, “01”, “10”, “11”, “000”, “001”, “010”, “011”, “100”, “101”, “110”, “111”, “0000”, “0001”, “0010”, “0011”, “0100”, “0101”, “0110”, “0111”, “0100”, “0101”, “0110”, “0111”, “1000”, “1001”, “1010”, “1011”, “1100”, “1101”, “1110”, “1111”.

[0041] The 5 logarithm calculation unit (integer part) is shown in Figure 2. The unit includes the first register 24, the constant unit 25, the counter 26, the first comparison unit 27, the second comparison unit 28, the counter 29, the third comparison unit 30, the shift register 31, the multiplication unit 32, the negation unit 33, the register 34, the fourth comparison unit 35, the register 36. The 5 calculation unit includes the first input 37 and the second input 38, respectively, which are the inputs of the first register 24, the output 39 of the 5 logarithm calculation unit is the output of the register unit 36.The output 40 of the first comparison block 27 is connected to the input 41 of the first register 24 and the input 42 of the counter 29, the input 43 of which is connected to the output 44 of the first register 24, and the input 45 of the counter 29 is connected to the output 46 of the shift register 31, the input 47 of which is connected to the output 48 of the multiplication block 32, the input 49 of which is connected to the output 50 of the counter 29 and the input 51 of the third comparison block 30, the output 52 of which is connected to the input 53 of the register 34, the second input 54 of which is connected to the input 55 of the multiplication block 32 and the output 56 of the negation block 33, the input 57 of which is connected to the input 58 of the counter 26 and the output 59 of the second comparison block 28, the input 60 of which is connected to the input 61 of the first comparison block 27, with the output 62 of the counter 26 and the input 63 of the fourth comparison block 35, the output 64 of which is connected to the input 65 of register 36, the input 66 of which is connected to the output 67 of register 34.

[0042] Examples of implementation

[0043] The following example illustrates a variant of the claimed invention, but does not limit it.

[0044] The device operates as follows. A signal from a random number generator is fed to input 8 of shift register 1. One of the following codes can be generated in shift register 1: "0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111". The code for determining which signal (code) will be analyzed in the device is sent to input 9 of decoder 2. It is one of the following - "0", "1", "00", "01", "10", "11", "000", "001", "010", "011", "100", "101", "110", "111", "0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111" - the bit depth (in this case 4 bits) is not important, in particular for the analysis of a smaller bit depth (<4).From the output 11 of the shift register 1 to the input 12 of the comparison unit 3, the corresponding code is sent during the operation of the random number generator, while the code for analysis is sent from the output 13 of the decoder 2 to the input 14 of the comparison unit 3. In the comparison unit 3, these codes are compared and the output 15 of this unit will result in "0" or "1" depending on the equality, then the signal is sent to the input 16 of the counter 4, from the output 17 of which the corresponding value is sent to the input 18 of the logarithm calculation unit 5 (Fig. 2) and to the input 19 of the divider 6. The logarithm calculation unit 5 is shown in Fig. 2, in which, in this case, the integer part of the logarithm is calculated, which is sufficient for assessing the quality of the RNG. In the divider 6, the logarithm is divided by the value of the data from the input 19 (the signal from the output 20 to the input 21). Divisor 6 is built on the basis of the KORDIK algorithm, which is a well-known calculator, in particular, described in Russian patent No. 2691854 dated June 18, 2019.The division result is fed to output 22 and then to input 23 of square root calculator 7, which is also based on the KORDIK algorithm. Output 10 of the device generates a signal, which is the characteristic of the RNG being evaluated.

[0045] Logarithm calculation block 5 (in Fig. 2) operates as follows.

[0046] Data from output 17 (Fig. 1) is fed to input 37 (input 18 in Fig. 1) in register 24. At the beginning of operation, register 24 is set to the initial state ("0") upon receipt of a reset signal at input 38. This result is fed from output 44 of register 24 to input 43 of counter 29 in accordance with the synchronization signal. At the same time, a signal is fed from output 40 of the first comparison block 27 to input 42 of counter 29. This signal determines from which input the writing to counter 29 is carried out - either from input 43 or from input 45. The result from output 46 of shift register (shift to the right) 31 is fed to input 45, which ensures that each synchronization signal at input 42 evaluates "0" or "1" at the next digit of the multi-bit word. In this case, the enabling signal is the level from the output 56 of the negation block 33, to the input 57 of which the corresponding signal from the output 59 of the second comparison block 28 is fed, to the input 60 of which the generated signal 62 is fed from the counter 26.During the operation of the RNG (which is being tested), at output 17 (Fig. 1) of counter 4, which determines the moment of the next shift of the number in shift register 31, in particular, it is determined by comparison block 28. A signal is sent from output 50 to input 51, and if the level is > "1" (third comparison block 30), and accordingly, from output 52 of comparison block 30, the signal is sent to input 53 of register 34, with an enabling signal 54, the data is written into register 34. The next step in the calculation process is writing the result from output 67 to input 66 of register 36 with a clock signal at input 65 from output 64 of the fourth comparison block 35. The result of the logarithm calculation is formed at output 39 of the logarithm calculation block (output 20 in Fig. 1); an example of result processing is shown in Fig. 3.

[0047] The general structure of the simulation system is shown in Figure 4 (various code combinations at the analysis system inputs) – 15 different combinations at the decoder inputs. The RNG developed within this study is used as an example, but any RNG can be used for the proposed device. The generalized test result output is shown in Figure 5. The curves from the device outputs (there are 15 of them in the model) are smoothed and decrease in value. This is precisely what satisfies the requirements of this methodology (and, accordingly, this device) and the RNG itself, according to the analysis results. A non-declining curve(s) characterizes the poor quality of the RNG.

Claims

1. A random number generator quality analyzer characterized by the fact that it includes a shift register, a decoder, a comparison unit, a counter, a logarithm calculator, a divider, and a square root calculator, wherein the first input of the device, to which a signal with random numbers is received, is connected to the input of the shift register, the output of which is connected to the first input of the comparison unit, the second input of the device, to which a detection code is received from an external device, is connected to the input of the decoder, the output of which is connected to the second input of the comparison unit, the output of which is connected to the input of the counter, the output of which is connected to the input of the logarithm calculator and to the input of the divider, built on the basis of the CORDIC algorithm, the output of which is connected to the input of the square root calculator, the output of which is connected to the output of the device, wherein the output of the logarithm calculator is connected to the input of the divider.

2. The random number generator quality analyzer according to claim 1, characterized in that the logarithm calculation unit includes a first register with two inputs that are also inputs of the logarithm calculation unit, a constant unit, a counter, a first comparison unit, a second comparison unit, a counter, a third comparison unit, a shift register, a multiplication unit, a negation unit, a register, a fourth comparison unit, a register, wherein the output of the first comparison unit is connected to the input of the first register and the input of the counter, the input of which is connected to the output of the first register, and the input of the counter is connected to the output of the shift register, the input of which is connected to the output of the multiplication unit, the input of which is connected to the output of the counter and the input of the third comparison unit, the output of which is connected to the input of the register, the second input of which is connected to the input of the multiplication unit and the output of the negation unit, the input of which is connected to the input of the counter and the output of the second comparison unit, the input of which is connected to the input of the first comparison unit,with the output of the counter and the input of the fourth comparison block, the output of which is connected to the input of the register, the input of which is connected to the output of the register, and the output of the logarithm calculation block is the output of the register block.,

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