Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a pixel circuit and a driving circuit connected with the pixel circuit. The pixel circuit comprises a driving transistor whose gate is connected with a first node, a first pole is connected with a second node, and a second pole is connected with a third node; a first electrode of the first light-emitting control transistor accesses a first power supply signal, a second electrode is connected with the second node, and a grid is connected with the first port; the first electrode of the second light-emitting control transistor is connected with the third node, the second electrode is connected with the fourth node, and the grid is connected with the second port; the first electrode of the communication transistor is connected with the first node, the second electrode is connected with the second node and the grid is connected with the third port; the first electrode of the data write-in transistor is connected with the third node, the second electrode is connected with data voltage, and the grid is connected with the fourth port; a first electrode of the first reset transistor is connected with a first reference voltage and connected with the fourth node, and a grid electrode is connected with the fifth port; and the at least two ports are respectively connected with different shift registers in the same driving circuit.

Description

Technical Field

[0001] This application relates to the field of display device technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of science and technology, more and more electronic devices with display functions are being widely used in people's daily lives and work, bringing great convenience and becoming an indispensable tool for people today. The main component of electronic devices that realizes the display function is the display panel. The display panel needs to control the light-emitting elements to emit light through pixel circuits so that the display panel can display images based on the light-emitting elements.

[0003] The pixel circuits of existing display panels require a large number of driving circuits to provide gate control signals to the transistors in the pixel circuits. Summary of the Invention

[0004] In view of the above problems, this application provides a display panel and a display device to reduce the number of driving circuits in the display device. The specific solution is as follows:

[0005] The first aspect of this application provides a display panel, including: a pixel circuit and a driving circuit connected to the pixel circuit;

[0006] The pixel circuit includes:

[0007] The driving transistor has its gate connected to the first node, its first terminal connected to the second node, and its second terminal connected to the third node.

[0008] The first light-emitting control transistor has a first electrode for receiving a first power supply signal, a second electrode for connecting to a second node, and a gate for receiving a first port for receiving the first light-emitting control signal.

[0009] The second light-emitting control transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the second port for receiving the second light-emitting control signal; the fourth node is used to connect the light-emitting element.

[0010] A connecting transistor is connected to a first node, a second node, and a gate connected to a third port for receiving a first gate control signal.

[0011] The data writing transistor has its first terminal connected to the third node, its second terminal used to receive the data voltage, and its gate connected to the fourth port used to receive the second gate control signal.

[0012] The first reset transistor has a first terminal for connecting to a first reference voltage, a first terminal connected to a fourth node, and a gate connected to a fifth port for connecting to a third gate control signal.

[0013] Among them, two or three of the first to fifth ports are respectively connected to different shift registers in the same driving circuit.

[0014] As can be seen from the above description, in the pixel circuit of the display panel provided in the embodiments of this application, at least two or three of the ports connected to the gate of the first light-emitting control transistor, the gate of the second light-emitting control transistor, the gate of the connecting transistor, the gate of the first reset transistor, and the gate of the data writing transistor are connected to the same driving circuit, so that two or three of these five transistors can use the same driving circuit to provide gate input signals, which can reduce the number of driving circuits required to drive the pixel circuit.

[0015] A second aspect of this application provides a display device, comprising: a display panel;

[0016] The display panel includes:

[0017] Light-emitting elements;

[0018] Pixel circuit connected to the light-emitting element;

[0019] The driving circuit connected to the pixel circuit;

[0020] The pixel circuit includes:

[0021] The driving transistor has its gate connected to the first node, its first terminal connected to the second node, and its second terminal connected to the third node.

[0022] The first light-emitting control transistor has a first electrode for receiving a first power supply signal, a second electrode for connecting to a second node, and a gate for receiving a first port for receiving the first light-emitting control signal.

[0023] The second light-emitting control transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the second port for receiving the second light-emitting control signal; the fourth node is connected to the light-emitting element.

[0024] A connecting transistor is connected to a first node, a second node, and a gate connected to a third port for receiving a first gate control signal.

[0025] The data writing transistor has its first terminal connected to the third node, its second terminal used to receive the data voltage, and its gate connected to the fourth port used to receive the second gate control signal.

[0026] The first reset transistor has a first terminal for connecting to a first reference voltage, a first terminal connected to a fourth node, and a gate connected to a fifth port for connecting to a third gate control signal.

[0027] Among them, two or three of the first to fifth ports are respectively connected to different shift registers in the same driving circuit.

[0028] Based on the above description, in the pixel circuit of the display panel proposed in the embodiments of this application, since at least two or three of the first light-emitting control transistor, the second light-emitting control transistor, the connecting transistor, the gate of the first reset transistor, and the data writing transistor are connected to the same driving circuit, two or three of these five transistors can use the same driving circuit to provide gate input signals, which can reduce the number of driving circuits required to drive the pixel circuit, reduce the number of driving circuits in the display panel, and facilitate the display panel to achieve a narrow bezel or even a bezel-less design. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

[0031] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0032] Figure 2 for Figure 1 The image shown is a cross-sectional view of the display panel in the display area.

[0033] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0034] Figure 4 This application provides a schematic diagram of the structure of a pixel circuit in a display panel.

[0035] Figure 5A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in another display panel provided in this application embodiment;

[0036] Figure 6 for Figure 5 The diagram shows a control timing diagram of the pixel circuit in the display panel.

[0037] Figure 7 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0038] Figure 8 for Figure 7 The diagram shows a control timing diagram of the pixel circuit in the display panel.

[0039] Figure 9 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0040] Figure 10 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0041] Figure 11 for Figure 10 The diagram shows a control timing diagram of the pixel circuit in the display panel.

[0042] Figure 12 for Figure 10 Another control timing diagram of the pixel circuit in the display panel is shown;

[0043] Figure 13 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0044] Figure 14 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0045] Figure 15 for Figure 14 The control timing diagram of the pixel circuit in the display panel is shown.

[0046] Figure 16 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0047] Figure 17 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0048] Figure 18 for Figure 17 The control timing diagram of the pixel circuit in the display panel is shown.

[0049] Figure 19 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0050] Figure 20 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0051] Figure 21 for Figure 20 The control timing diagram of the pixel circuit in the display panel is shown.

[0052] Figure 22 A schematic diagram illustrating the connection relationship between pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0053] Figure 23 for Figure 22 The control timing diagram of the pixel circuit in the display panel is shown.

[0054] Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0055] Figure label:

[0056] 100 - Light-emitting element; 101 - First driving circuit; 102 - Second driving circuit; 103 - Third driving circuit; 104 - Pixel circuit; 105 - Driving circuit; 106 - Display panel; 107 - Substrate; 108 - Circuit layer; 109 - Anode; 110 - Light-emitting layer; 111 - Cathode; T1 - First light-emitting control transistor; T2 - Connecting transistor; T4 - Data writing transistor; T3 - Driving transistor; T5 - Second light-emitting control transistor; T6 - First reset transistor; T7 - ​​Second reset transistor; T8 - Bias adjustment transistor; Cst - Storage capacitor; N1 - First node; N2 - Second node; N3 - Third node; N4 - Fourth node; PVDD - First power signal; PVEE - Second power signal; EM - First power signal Wave signals; EM1 - First light emission control signal; EM2 - Second light emission control signal; SP - Second square wave signal; SN - Third square wave signal; DATA - Data voltage; VREF1 - First reference voltage; VREF2 - Second reference voltage; D1 - First port; D2 - Second port; D3 - Third port; D4 - Fourth port; D5 - Fifth port; D6 - Sixth port; D7 - Seventh port; S1 - First gate control signal; S2 - Second gate control signal; S3 - Third gate control signal; S4 - Fourth gate control signal; S5 - Fifth gate control signal; VSR - Shift register; VSR1 - First shift register; VSR2 - Second shift register; VSR3 - Third shift register; DVH - Bias adjustment signal; AA - Display area; BB - Border area. Detailed Implementation

[0057] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0058] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] refer to Figure 1 , Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application. The display panel includes a display area AA and a border area BB located on at least one side of the display area AA. Figure 1 As shown, the display panel includes: a light-emitting element 100, a pixel circuit 104 connected to the light-emitting element 100, and a driving circuit 105 connected to the pixel circuit 104. The light-emitting element 100 and the pixel circuit 104 are located within the display area AA.

[0060] refer to Figure 2 , Figure 2 for Figure 1 The image shown is a cross-sectional view of the display panel in the display area. Figure 2 The illustration uses an OLED panel as an example. Figure 1 and Figure 2 As shown, the display panel includes: a substrate 107; a circuit layer 108 is disposed on the surface of the substrate 107, the circuit layer 108 including pixel circuits 104 and driving circuits 105. A display array is disposed on the side of the circuit layer 108 opposite to the substrate 107, the display array including multiple light-emitting elements 100, the light-emitting elements can be OLEDs, including an anode 109, a light-emitting layer 110 and a cathode 111 disposed sequentially.

[0061] The circuit layer 108 may include a first metal layer M1, a second metal layer M2, a capacitor metal layer Mc, and a third metal layer M3 sequentially formed on the surface of the substrate 107. The first metal layer M1 can be used to fabricate the gate of a transistor, the second metal layer M2 can be used to fabricate the source and drain of a transistor, the capacitor metal layer Mc can be used to fabricate capacitor plates, and the third metal layer M3 can be used to fabricate the electrical connection between the anode 109 and the pixel circuit 104. An insulating layer is provided between adjacent metal layers. Furthermore, each metal layer in the circuit layer 108 can also be used as various signal lines and connections between circuits.

[0062] In this embodiment, the light-emitting element 100 is not limited to an OLED, but can also be a micro LED. The micro LED can be a MINI LED or a Micro LED. This embodiment does not limit the specific type of micro LED.

[0063] One implementation method is, as follows: Figure 1 As shown, the driving circuit 105 can be located in the border area BB on one side of the display area AA.

[0064] refer to Figure 3 , Figure 3 This is a schematic diagram of another display panel provided in an embodiment of this application. Based on the above embodiments, Figure 3 In the display panel shown, driving circuits 105 are respectively arranged on both sides of the display area AA.

[0065] In other ways, to reduce the bezel width, at least part of the driving circuit 105 can be placed within the display area AA.

[0066] refer to Figure 4 , Figure 4 This application provides a schematic diagram of the structure of a pixel circuit in a display panel, showing the pixel circuit including:

[0067] Drive transistor T3, the gate of the drive transistor is connected to the first node N1, the first terminal of the drive transistor T3 is connected to the second node N2, and the second terminal is connected to the third node N3;

[0068] The first light-emitting control transistor T1 has a first terminal for receiving the first power supply signal PVDD, a second terminal for connecting to the second node N2, and a gate for connecting to the first port D1 for receiving the first light-emitting control signal EM1.

[0069] The second light-emitting control transistor T5 has its first terminal connected to the third node N3, its second terminal connected to the fourth node N4, and its gate connected to the second port D2 for receiving the second light-emitting control signal EM2; the fourth node N4 is used to connect the light-emitting element 100.

[0070] Connect transistor T2, with its first terminal connected to the first node N1, its second terminal connected to the second node N2, and its gate connected to the third port D3 for receiving the first gate control signal S1;

[0071] The data writing transistor T4 has its first terminal connected to the third node N3, its second terminal used to connect to the data voltage DATA, and its gate connected to the fourth port D4 used to connect to the second gate control signal S2.

[0072] The first reset transistor T6 has its first terminal connected to the first reference voltage VREF1, the first terminal connected to the fourth node N4, and its gate connected to the fifth port D5 for connecting to the third gate control signal S3.

[0073] Among them, two or three of the first port D1 to the fifth port D5 are respectively connected to different shift registers in the same driving circuit.

[0074] In the pixel circuit 104 of the display panel provided in this application embodiment, two or three of the first port D1 to the fifth port D5 are respectively connected to different shift registers in the same driving circuit. This allows at least two or three of the ports connected to the gates of the first light-emitting control transistor T1, the second light-emitting control transistor T5, the connecting transistor T2, the first reset transistor T6, and the data writing transistor T4 to be connected to the same driving circuit. This enables two or three of these five transistors to use the same driving circuit to provide gate input signals, which can reduce the number of driving circuits required to drive the pixel circuit, thereby simplifying the design of the driving circuit in the display panel.

[0075] In the same driving circuit, the output signals of each shift register are used as the gate input signals of the corresponding transistors in the pixel circuit, and the output signal of the previous shift register is used as the input signal of the next shift register.

[0076] The gates of identical transistors in the same row of pixel circuits are connected to the outputs of the same stage shift registers in the same driving circuit, just as the gates of the first light-emitting control transistors in the same row of pixel circuits are connected to the outputs of the same stage shift registers in the same driving circuit. Conversely, the gates of identical transistors in different rows of pixel circuits are connected to the outputs of different stages shift registers in the same driving circuit, just as the gates of the first light-emitting control transistors in different rows of pixel circuits are connected to the outputs of different stages shift registers in the same driving circuit.

[0077] Optionally, the connecting transistor T2, driving transistor T3, data writing transistor T4, and first reset transistor T6 are all NMOS transistors, while the first light-emitting control transistor T1 and the second light-emitting control transistor T5 are both PMOS transistors. This allows two or three of these transistors to be connected to the same driving circuit, and the first and second light-emitting control transistors T1 and T5 to be connected to the same driving circuit. The NMOS and PMOS transistors are connected to different driving circuits. This allows a larger number of transistors in the pixel circuit to share a driving circuit, reducing the number of driving circuits required for the pixel circuit.

[0078] Based on other implementation methods, in some implementation methods of this application, the connecting transistor T2, the driving transistor T3, the data writing transistor T4, and the first reset transistor T6 are all oxide (including IGZO) transistors; the first light-emitting control transistor T1 and the second light-emitting control transistor T5 are both low-temperature polycrystalline silicon (LTPS) transistors.

[0079] When the connecting transistor T2, driving transistor T3, data writing transistor T4, and first reset transistor T6 are all oxide transistors, all four transistors can be fabricated as NMOS. Since all four transistors can be NMOS, two or three of these four transistors can be connected to the same driving circuit. This allows a larger number of transistors in the pixel circuit to share the driving circuit, thereby reducing the number of driving circuits required for the pixel circuit.

[0080] When both the first light-emitting control transistor T1 and the second light-emitting control transistor T5 are low-temperature polysilicon transistors, and both transistors can be PMOS, these two transistors can be connected to the same driving circuit. This allows a larger number of transistors in the pixel circuit to share the driving circuit, thereby reducing the number of driving circuits required for the pixel circuit.

[0081] Based on other implementation methods, some implementation methods of the embodiments of this application, such as Figure 4As shown, the connecting transistor T2, the data writing transistor T4, and the first reset transistor T6 are all dual-gate transistors; in the connecting transistor T2, the data writing transistor T4, and the first reset transistor T6, the bottom gate and the top gate of the same dual-gate transistor are connected.

[0082] When the connecting transistor T2, the data writing transistor T4, and the first reset transistor T6 adopt a dual-gate transistor structure, and the bottom gate of each dual-gate transistor is connected to its own top gate, the bottom and top gates of the same dual-gate transistor are connected to the same gate input signal. This allows the transistor to have a higher mobility and on-state current, resulting in a stronger pixel driving capability for the pixel circuit. Higher pixel driving capability allows the pixel circuit to be used in displays with higher brightness and also reduces display power consumption. Higher mobility and on-state current also improve the response speed of the pixel circuit, making it suitable for display panels with high refresh rates. Furthermore, higher mobility and on-state current can alleviate performance drift caused by long-term transistor operation and reduce display unevenness and power consumption caused by transistor aging.

[0083] Optionally, in some embodiments of this application, at least one of the connecting transistor T2, the data writing transistor T4, and the first reset transistor T6 may also be a single-gate transistor.

[0084] In conventional pixel circuits, the driving transistor T3 typically uses a single-gate transistor. However, the threshold voltage of a single-gate transistor is susceptible to threshold drift due to factors such as short-channel effect, bulk bias effect, channel doping fluctuations, and temperature drift. To address the threshold drift problem of the driving transistor T3, based on other implementation methods, some embodiments of this application, such as... Figure 4As shown, the driving transistor T3 is a dual-gate transistor. The bottom gate of the driving transistor T3 is connected to the third node N3. In this way, the dual-gate driving transistor can control the channel through two independent gates. The single-gate transistor can only control the channel from one side. The drain electric field under a short channel can easily penetrate the gate oxide layer. However, the dual-gate transistor can apply an electric field to the channel from both the top and bottom sides of the channel, forming a stronger depletion region, thereby blocking the short-channel effect and reducing the sensitivity of the threshold voltage to the channel length. One of the gates in the dual-gate transistor can act as a body gate, and the body potential can be adjusted independently. This can separate the body potential regulation from the channel conduction, alleviate the body bias effect, and isolate the influence of the source / drain and substrate potentials on the threshold voltage. In addition, the synergistic electric field of the two gates in the dual-gate transistor can distribute the channel potential more evenly, reduce the sensitivity to local doping defects, and reduce the influence of doping fluctuations on the threshold voltage. Moreover, when the temperature changes, the dual-gate transistor can also partially offset the threshold voltage drift through the difference in the carrier mobility response of the two gates. Therefore, this method can improve the threshold voltage stability of the driving transistor T3, and avoid problems such as flickering and uneven display caused by insufficient threshold stability.

[0085] Optionally, in some embodiments of this application, the driving transistor T3 may also be a single-gate transistor.

[0086] Based on other implementations, in some embodiments of this application, the second port D2 and the fifth port D5 are the output terminals of the same shift register, and the third gate control signal S3 and the second light emission control signal EM2 are the same signal, which is the output signal of the shift register. This signal causes one of the first reset transistor T6 and the second light emission control transistor T5 to be turned on, while the other is turned off. In this way, the second port D2 and the fifth port D5 can be connected to the same gate input signal. These two ports can be provided with the same gate input signal by the same shift register in the same driving circuit, which allows a larger number of transistors in the pixel circuit to share the driving circuit, thereby reducing the number of driving circuits connected to the pixel circuit.

[0087] When the pixel circuit controls the light-emitting element 100 to emit light for display, in one driving cycle of the pixel circuit, before the light-emitting element 100 emits light for display, the voltage of the fourth node N4 needs to be reset. That is, the first reset transistor T6 needs to be turned on first to reset the voltage of the fourth node N4, and then the second light-emitting control transistor T5 needs to be turned on to enable the light-emitting element 100 to emit light for display. Therefore, the first reset transistor T6 and the second light-emitting control transistor T5 do not need to be turned on at the same time, and the conduction states of the two transistors can be opposite. Based on this, one of the first reset transistor T6 and the second light-emitting control transistor T5 can be set to NMOS and the other to PMOS, and both of their gates are connected to the same gate input signal. That is, the second port D2 and the fifth port D5 are connected to the output of the same shift register, so that the second light-emitting control transistor T5 and the first reset transistor T6 are connected to the same gate input signal.

[0088] refer to Figure 5 , Figure 5 This is another schematic diagram showing the connection relationship between the pixel circuit and the driving circuit in a display panel, provided as an embodiment of this application. Based on other aspects of this application, Figure 5 In the illustrated configuration, the driving circuit includes a first driving circuit 101 and a second driving circuit 102. The first driving circuit 101 includes multiple cascaded first shift registers VSR1, and the second driving circuit 102 includes multiple cascaded second shift registers VSR2. The first port D1 and the second port D2 are respectively connected to different first shift registers VSR1. The third port D3 and the fourth port D4 are respectively connected to different second shift registers VSR2.

[0089] exist Figure 5 In the illustrated configuration, the first light-emitting control transistor T1 and the second light-emitting control transistor T5 can each receive gate input signals through different first shift registers VSR1 in the first driving circuit 101. Similarly, the connecting transistor T2 and the data writing transistor T4 can each receive gate input signals through different second shift registers VSR2 in the second driving circuit 102. These four transistors only require connection to two driving circuits, corresponding to two sets of shift registers, which reduces the number of driving circuits connected to the pixel circuit and facilitates a narrow bezel design for the display panel.

[0090] In various embodiments of this application, the first shift registers VSR1 at each stage of the first driving circuit 101 output first square wave signals EM with different timings. The second shift registers VSR2 at each stage of the second driving circuit 102 output second square wave signals SP with different timings. The duty cycles of the first square wave signal EM and the second square wave signal SP are different.

[0091] Optionally, in Figure 5In the illustrated configuration, the fifth port D5 can be connected to the same first shift register VSR1 as the second port D2. This means the third gate control signal S3 and the second light-emitting control signal EM2 are the same signal, and the gate input signals of the second light-emitting control transistor T5 and the first reset transistor T6 are the same—both are output signals of the same first shift register VSR1. In this case, the first reset transistor T6, the first light-emitting control transistor T1, and the second light-emitting control transistor T5 can be connected to the same cascaded first shift register VSR1 to form the first driving circuit 101, which can significantly reduce the number of driving circuits connected to the pixel circuit. Figure 5 The pixel circuit shown only requires two driving circuits.

[0092] In this embodiment, the first light-emitting control transistor T1 and the second light-emitting control transistor T5 can both be PMOS for illustration.

[0093] exist Figure 5 In the illustrated configuration, the output signals of the two different stages of the first shift register VSR1 in the first driving circuit 101 are the first light-emitting control signal EM1 and the second light-emitting control signal EM2, respectively. The output signals of the two different stages of the second shift register VSR2 in the second driving circuit 102 are SP1 and SP2, respectively. SP1 serves as the first gate control signal S1, and SP2 serves as the second gate control signal S2. The second light-emitting control signal EM2 also serves as the third gate control signal S3. At this time, Figure 5 The control timing of the pixel circuit shown is as follows: Figure 6 As shown.

[0094] refer to Figure 6 , Figure 6 for Figure 5 The diagram shows a control timing diagram for the pixel circuitry in the display panel. (Combined with...) Figure 5 and Figure 6 As shown, in one driving cycle of the pixel circuit:

[0095] The rising edge of the first light emission control signal EM1 is located between the rising edge and the falling edge of the second light emission control signal EM2;

[0096] Between the rising edge of the second light-emitting control signal EM2 and the falling edge of the first light-emitting control signal EM1, the first gate control signal S1 is turned on to reset the voltage of the first node N1 and the fourth node N4. During this stage, the node voltage is reset. In this stage, the first light-emitting control transistor T1, the connection transistor T2 and the first reset transistor T6 are turned on. The voltage of the first node N1 can be reset by the first power supply signal PVDD and the voltage of the fourth node N4 can be reset by the first reference voltage VREF1.

[0097] At the rising edge of the first light-emitting control signal EM1 and the falling edge of the second light-emitting control signal EM2, the first gate control signal S1 and the second gate control signal S2 are simultaneously turned on, and data voltage DATA is written to the first node N1. During this stage, data voltage DATA is written to the first node N1. The connecting transistor T2 and the data writing transistor T4 are simultaneously turned on, and the data voltage DATA can be transmitted to the first node N1 sequentially through the data writing transistor T4, the driving transistor T3, and the connecting transistor T2. During the data writing stage, both the data writing transistor T4 and the driving transistor T3 are in the on state, so the second node voltage V N2 Equal to the data voltage DATA, after the write is complete, the first node voltage V N1 Second node voltage V N2 Both are equal to the data voltage DATA and the threshold voltage V of the driving transistor T3. th The sum of the voltages at the fourth node, V N4 VREF1 is the first reference voltage after reset.

[0098] After the data voltage DATA is written to the first node N1 and before the falling edge of the second light emission control signal EM2, the second gate control signal S2 is turned on to adjust the on-state bias of the driving transistor T3. This stage is the Operational Bias Stress (OBS) modulation stage, which turns on the connecting transistor T2 to adjust the threshold stability of the oxide transistor that drives the transistor T3 and reduce its threshold voltage hysteresis problem. During the OBS modulation stage, the data voltage DATA from the following rows can be reused to write to the third node N3 to adjust the on-state bias of the driving transistor T3. This helps to adjust the electrical properties of the driving transistor T3 and thus improve the display flicker problem.

[0099] During the period from the falling edge of the first light-emitting control signal EM1 to the next driving cycle, which is the light-emitting phase, both the first gate control signal S1 and the second gate control signal S2 are turned off, controlling the light-emitting element 100 to emit light for display. The gate-source voltage of the driving transistor T3 is set to V. gs During the light-emitting stage, the driving current I transmitted when the driving transistor T3 is turned on can be expressed as follows:

[0100] ;

[0101] In the above formula, k is a constant.

[0102] based on Figure 6As shown in the control timing diagram, the first light-emitting control transistor T1, the second light-emitting control transistor T5, and the first reset transistor T6 in the pixel circuit can be provided with gate input signals through the corresponding first shift register VSR1 in the first driving circuit 101. The connecting transistor T2 and the data writing transistor T4 can be provided with gate input signals through the corresponding second shift register VSR2 in the second driving circuit 102. This reduces the number of driving circuits required for the pixel circuit. The pixel circuit only needs two driving circuits (corresponding to two sets of shift registers) to realize display driving, which simplifies the design of the driving circuit in the display panel and facilitates the implementation of a narrow bezel design in the display panel.

[0103] In this embodiment, each gate control signal is a square wave signal, and its turn-on period is the high-level period of the square wave signal, and its turn-off period is the low-level period of the square wave signal.

[0104] refer to Figure 7 , Figure 7 This is another schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in a display panel, provided in an embodiment of this application. Based on other aspects of this application, Figure 7 In the illustrated configuration, the driving circuit includes a first driving circuit 101 and a second driving circuit 102. The first driving circuit 101 includes multiple cascaded first shift registers VSR1, and the second driving circuit 102 includes multiple cascaded second shift registers VSR2. The first port D1 and the second port D2 are respectively connected to different first shift registers VSR1. The first gate control signal S1 and the second light emission control signal EM2 are the same signal. The third port D3 and the second port D2 are connected to the same first shift register VSR1. The fourth port D4 is connected to the second shift register VSR2.

[0105] exist Figure 7 In the illustrated configuration, the first light-emitting control transistor T1 and the second light-emitting control transistor T5 can each receive gate input signals through different first shift registers VSR1 in the first driving circuit 101. The connecting transistor T2 can be connected to the same first shift register VSR1 as the second light-emitting control transistor T5. The first light-emitting control transistor T1, the second light-emitting control transistor T5, and the connecting transistor T2 can share the first driving circuit 101. The data writing transistor T4 can receive its gate input signal through the second driving circuit 102. These four transistors only need to be connected to two driving circuits, corresponding to two sets of shift registers, which reduces the number of driving circuits connected to the pixel circuit.

[0106] Optionally, in Figure 7In the illustrated configuration, the fifth port D5 can be connected to the same first shift register VSR1 as the second port D2. This means the third gate control signal S3 and the second light-emitting control signal EM2 are the same signal. Consequently, the first reset transistor T6 and the second light-emitting control transistor T5 can be connected to the same first shift register VSR1, and both can share the first drive circuit 101. At this time, Figure 7 The pixel circuit shown only requires two driving circuits.

[0107] exist Figure 7 In the illustrated configuration, the second light-emitting control signal EM2 simultaneously serves as both the first gate control signal S1 and the third gate control signal S3. The output signal of the first-stage second shift register VSR2 in the second driving circuit 102 is used as the second square wave signal SP, and the second square wave signal SP is used as the second gate control signal S2. At this time, Figure 7 The control timing of the pixel circuit shown is as follows: Figure 8 As shown.

[0108] refer to Figure 8 , Figure 8 for Figure 7 The diagram shows a control timing diagram for the pixel circuitry in the display panel. (Combined with...) Figure 8 and Figure 7 As shown, in one driving cycle of the pixel circuit:

[0109] The rising edge of the first light emission control signal EM1 is located between the rising edge and the falling edge of the second light emission control signal EM2;

[0110] At the rising edges of the second light-emitting control signal EM2 and the first light-emitting control signal EM1, the voltages of the first node N1 and the fourth node N4 are reset, and the node voltages are reset during this stage. The first light-emitting control transistor T1 is a PMOS, and the low level of the first light-emitting control signal EM1 during this stage turns on the first light-emitting control transistor T1; the connecting transistor T2 and the first reset transistor T6 are NMOS, and the high level of the second light-emitting control signal EM2 during this stage turns on both the connecting transistor T2 and the first reset transistor T6. Therefore, during this stage, the first power supply signal PVDD can reset the voltage of the first node N1 through the turned-on first light-emitting control transistor T1 and connecting transistor T2, and the first reference voltage VREF1 can reset the voltage of the fourth node N4 through the turned-on first reset transistor T6.

[0111] Between the rising edge of the first light emission control signal EM1 and the falling edge of the second light emission control signal EM2, the second gate control signal S2 is turned on, and a data voltage is written to the first node N1. During this stage, the data voltage DATA is written to the first node N1. The connecting transistor T2 and the data writing transistor T4 are NMOS. During this stage, the high level of the second gate control signal S2 and the second light emission control signal causes the connecting transistor T2 and the data writing transistor T4 to be turned on synchronously. The data voltage DATA can be transmitted to the first node N1 in sequence through the data writing transistor T4, the driving transistor T3 and the connecting transistor T2, thereby writing the data voltage DATA to the first node N1.

[0112] Between the falling edge of the second light emission control signal EM2 and the falling edge of the first light emission control signal EM1, the second gate control signal S2 is turned on, and the on-state bias adjustment is performed on the driving transistor T3. This stage is the conduction bias stress modulation stage. The connecting transistor T2 is turned on, so the data voltage DATA of the following rows can be multiplexed and written to the third node N3 to perform conduction bias stress modulation on the driving transistor T3, so as to adjust the threshold stability of the oxide transistor that serves as the driving transistor T3, reduce its threshold voltage hysteresis problem, and help adjust the electrical properties of the driving transistor T3, thereby improving the flicker problem.

[0113] From the falling edge of the first light-emitting control signal EM1 to the next driving cycle, this period is the light-emitting stage. The first gate control signal S1 and the second gate control signal S2 are both turned off, controlling the light-emitting element 100 to emit light for display.

[0114] based on Figure 8 As shown in the control timing diagram, the first light-emitting control transistor T1, the second light-emitting control transistor T5, the connection transistor T2, and the first reset transistor T6 in the pixel circuit can be provided with gate input signals through the corresponding first shift register VSR1 in the first driving circuit 101, and the data writing transistor T4 can be provided with gate input signals through the corresponding second shift register VSR2 in the second driving circuit 102. This can reduce the number of driving circuits required for the pixel circuit. The pixel circuit only needs two driving circuits (corresponding to two sets of shift registers) to realize display driving, which simplifies the design of driving circuits in the display panel.

[0115] In the above embodiments, the connecting transistor T2 can be used for voltage reset of the first node N1 and writing of the data voltage DATA. In other embodiments, as described below, the voltage reset of the first node N1 can also be achieved through the second reset transistor T7, in which case the connecting transistor T2 is used for writing the data voltage DATA of the first node N1.

[0116] refer to Figure 9 , Figure 9This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in this application embodiment. Based on other implementation methods... Figure 9 The pixel circuit shown also includes: a second reset transistor T7, the first terminal of the second reset transistor T7 is connected to the first node N1 or the second node N2, the second terminal is connected to the second reference voltage VREF2, and the gate is connected to the sixth port D6 for accessing the fourth gate control signal S4; the driving circuit includes a first driving circuit 101 and a second driving circuit 102, the first driving circuit 101 includes multiple cascaded first shift registers VSR1, and the second driving circuit 102 includes multiple cascaded second shift registers VSR2.

[0117] Figure 9 The illustration is based on the example of the first terminal of the second reset transistor T7 being connected to the first node N1. As will be known from the following description of the embodiments, the first terminal of the second reset transistor T7 can be connected to either the first node N1 or the second node N2 as needed.

[0118] exist Figure 9 In the illustrated configuration, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are the same light-emitting control signal. The first port D1 and the second port D2 are connected to the same first shift register VSR1. The first light-emitting control transistor T1 and the second light-emitting control transistor T5 both use the first square wave signal EM output from the first shift register VSR1 as their gate input signal. Thus, the first light-emitting control transistor T1 and the second light-emitting control transistor T5 can share the first driving circuit 101. The sixth port D6 and the fourth port D4 are respectively connected to different second shift registers VSR2. The second reset transistor T7 and the data writing transistor T4 use the second square wave signal SP output from different two-stage second shift registers VSR2 as their gate input signals. Thus, the second reset transistor T7 and the data writing transistor T4 can share the second driving circuit 102.

[0119] Optionally, in Figure 9 In the configuration shown, the third gate control signal S3 and the second light emission control signal EM2 are the same light emission control signal. The fifth port D5 and the second port D2 are connected to the same first shift register VSR1. The first reset transistor T6 and the second light emission control transistor T5 both use the first square wave signal EM output by the first shift register VSR1 as the gate input signal. In this way, the first reset transistor T6 and the second light emission control transistor T5 can share the second driving circuit 102.

[0120] refer to Figure 10 , Figure 10 This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in an embodiment of this application. Figure 9Based on the pixel circuit shown, Figure 10 In the pixel circuit shown, the driving circuit also includes a third driving circuit 103, which includes multiple cascaded third shift registers VSR3; the third port D3 is connected to the third shift register VSR3, meaning that transistor T2 needs to receive its gate input signal separately through the third driving circuit 103. Therefore... Figure 10 The pixel circuit shown requires three driving circuits.

[0121] In the third driving circuit 103, the third shift registers VSR3 at different stages output third wave signals SN with different timings. The duty cycles of the first square wave signal EM, the second square wave signal SP, and the third wave signal SN are different from each other.

[0122] exist Figure 10 In the illustrated configuration, the first square wave signal EM output from the first shift register VSR1 of the same stage in the first driving circuit 101 simultaneously serves as the first light emission control signal EM1, the second light emission control signal EM2, and the third gate control signal S3. The output signals of the two different stages of the second shift register VSR2 in the second driving circuit 102 are SP1 and SP2, respectively. SP1 serves as the fourth gate control signal S4, and SP2 serves as the second gate control signal S2. The third square wave signal SN output from the first stage of the third shift register VSR3 in the third driving circuit 103 serves as the first gate control signal S1. At this time... Figure 10 The control timing of the pixel circuit shown is as follows: Figure 11 or Figure 12 As shown.

[0123] refer to Figure 11 , Figure 11 for Figure 10 The diagram shown is a control timing diagram of the pixel circuit in the display panel, combined with... Figure 10 and Figure 11 As shown, in one driving cycle of the pixel circuit:

[0124] The rising and falling edges of the first gate control signal S1 (third wave signal SN) are located between the rising and falling edges of the light emission control signal;

[0125] Between the rising and falling edges of the first gate control signal S1 (third square wave signal SN), the fourth gate control signal S4 is turned on, resetting the voltage of the first node N1 and the fourth node N4. During this stage, the node voltage is reset, the first light-emitting control transistor T1 is turned off, and both the connecting transistor T2 and the second reset transistor T7 are turned on. The second reference voltage VREF2 can be transmitted to the first node N1 sequentially through the second reset transistor T7, the second node N2, and the connecting transistor T2, resetting the voltage of the first node N1. During this stage, the high-level first square wave signal EM can also control the first reset transistor T6 to turn on, resetting the voltage of the fourth node N4 through the first reference voltage VREF1.

[0126] After voltage reset, before the falling edge of the first gate control signal S1, the second gate control signal S2 is turned on, and data voltage is written to the first node N1. During this stage, data voltage DATA is written to the first node N1. Data writing transistor T4, driving transistor T3 and connecting transistor T2 are all turned on, and data voltage DATA can be transmitted to the first node N1 in sequence through data writing transistor T4, driving transistor T3 and connecting transistor T2.

[0127] From the falling edge of the light-emitting control signal to the next driving cycle, all gate control signals are turned off, controlling the light-emitting element 100 to emit light for display.

[0128] refer to Figure 12 , Figure 12 for Figure 10 The diagram shown is another control timing diagram of the pixel circuit in the display panel, combined with... Figure 10 and Figure 12 As shown, in one driving cycle of the pixel circuit:

[0129] The rising and falling edges of the first gate control signal S1 (third wave signal SN) are located between the rising and falling edges of the light emission control signal;

[0130] Between the rising and falling edges of the first gate control signal S1 (third square wave signal SN), the fourth gate control signal S4 is turned on twice in sequence to reset the voltage of the first node N1 and the fourth node N4. During this phase, the first light-emitting control transistor T1 is turned off, the connecting transistor T2 is turned on, and the second reset transistor T7 is turned on during the on-time of the fourth gate control signal S4 to reset the voltage of the first node N1 using the second reference voltage VREF2. In this method, the second square wave signal SP has two on-time phases in one driving cycle, as described below. The first on-time of the second gate control signal S2 (second square wave signal SP) can be used for data writing, and the second on-time can be used for OBS modulation, relative to... Figure 11The control timing shown can add an OBS modulation stage between the data writing and emission stages.

[0131] After the second activation of the fourth gate control signal S4 and before the falling edge of the first gate control signal S1, the second gate control signal S2 is activated for the first time, and a data voltage is written to the first node N1. During this stage, the data voltage DATA is written to the first node N1. The data writing transistor T4, the driving transistor T3, and the connection transistor T2 are all turned on, and the data voltage DATA can be transmitted to the first node N1 in sequence through the data writing transistor T4, the driving transistor T3, and the connection transistor T2.

[0132] After the falling edge of the first gate control signal S1 (third square wave signal SN) and before the falling edge of the first square wave signal EM, the second gate control signal S2 is turned on for the second time to adjust the on-state bias of the driving transistor T3; during this stage, the OBS modulation is achieved by controlling the data writing transistor to turn on.

[0133] From the falling edge of the light emission control signal to the next driving cycle, all gate control signals are turned off to control the light emission element 100 to emit light for display.

[0134] refer to Figure 13 , Figure 13 This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in an embodiment of this application. Figure 10 The difference shown is that, Figure 13 The first terminal of the second reset transistor T7 in the pixel circuit shown is connected to the first node N1. Figure 13 The control timing of the pixel circuit shown can also be as follows: Figure 11 or Figure 12 As shown, the control timing of a pixel circuit in one driving cycle can be referenced. Figure 11 or Figure 12 The corresponding methods will not be described again in the embodiments of this application.

[0135] refer to Figure 14 , Figure 14 This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in this application embodiment. Based on other implementation methods... Figure 14 In the pixel circuit shown, the first light-emitting control signal EM1, the second light-emitting control signal EM2, and the first gate control signal S1 are the same signal, and the first port D1, the second port D2, and the third port D3 are connected to the same first shift register VSR1. Thus, the first light-emitting control transistor T1, the second light-emitting control transistor T5, and the connecting transistor T2 can share the first driving circuit 101.

[0136] exist Figure 14In the configuration shown, the third gate control signal S3 and the second light-emitting control signal EM2 are the same signal, and the fifth port D5 and the second port D2 are connected to the same first shift register VSR1. Thus, the first reset transistor T6 can share the first drive circuit 101 with the second light-emitting control transistor T5.

[0137] exist Figure 14 In the pixel circuit shown, the first port D1, the second port D2, the third port D3, and the fifth port D5 use the first square wave signal EM output from the same first shift register VSR1 as the gate input signal; the fourth port D4 and the sixth port D6 use the second square wave signal SP output from different second shift registers VSR2 as the gate input signals. At this time, the control timing of the pixel circuit can be as follows: Figure 15 As shown.

[0138] refer to Figure 15 , Figure 15 for Figure 14 The control timing diagram of the pixel circuit in the display panel shown is combined with... Figure 14 and Figure 15 As shown, in one driving cycle of the pixel circuit:

[0139] Between the rising and falling edges of the first square wave signal EM, the fourth gate control signal S4 is turned on, resetting the voltage of the first node N1 and the fourth node N4; during the period when the fourth gate control signal S4 is turned on, the connecting transistor T2 and the second reset transistor T7 are turned on, resetting the voltage of the first node N1 through the second reference voltage VREF2; during the high-level period of the first square wave signal EM, the first reset transistor T6 is turned on, resetting the voltage of the fourth node N4 through the first reference voltage VREF1.

[0140] After voltage reset, before the falling edge of the first square wave signal EM, the second gate control signal S2 is turned on, and the data voltage is written to the first node N1; during this stage, the high-level second gate control signal S2 controls the data writing transistor T4 to be turned on, and the data voltage DATA can be written to the first node N1 in sequence through the data writing transistor T4, the driving transistor T3 and the connecting transistor T2.

[0141] From the falling edge of the first square wave signal EM to the next driving cycle, all gate control signals are turned off, controlling the light-emitting element 100 to emit light for display.

[0142] refer to Figure 16 , Figure 16 This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in an embodiment of this application. Figure 14 The pixel circuit shown is different in that, Figure 16The first terminal of the second reset transistor T7 in the pixel circuit shown is connected to the first node N1. Figure 16 The control timing of the pixel circuit shown can also be as follows: Figure 15 As shown, the control timing of a pixel circuit in one driving cycle can be referenced. Figure 15 The corresponding methods will not be described again in the embodiments of this application.

[0143] refer to Figure 17 , Figure 17 This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in this application embodiment. Based on other implementation methods... Figure 17 In the pixel circuit shown, the third port D3, the fourth port D4, and the sixth port D6 are respectively connected to different second shift registers VSR2. Thus, the connecting transistor T2, the data writing transistor T4, and the second reset transistor T7 each use the second square wave signal SP output from different second shift registers VSR2 as their gate input signals, and all three can share the second driving circuit.

[0144] exist Figure 17 In the illustrated configuration, in the first driving circuit 101, the first square wave signal EM output by the first shift register VSR1 of the same stage simultaneously serves as the first light emission control signal EM1, the second light emission control signal EM2, and the third gate control signal S3. In the second driving circuit 102, the output signals of the three different stages of the second shift register VSR2 are SP1, SP2, and SP3, respectively. SP1 serves as the fourth gate control signal S4, SP2 serves as the first gate control signal S1, and SP3 serves as the second gate control signal S2. At this time, the control timing of the pixel circuit can be as follows: Figure 18 As shown.

[0145] refer to Figure 18 , Figure 18 for Figure 17 The control timing diagram of the pixel circuit in the display panel shown is combined with... Figure 17 and Figure 18 As shown, in one driving cycle of the pixel circuit:

[0146] Between the rising and falling edges of the light emission control signal, the first gate control signal S1, the second gate control signal S2, and the fourth gate control signal S4 are each turned on twice in sequence;

[0147] The second activation of the fourth gate control signal S4 is synchronized with the first activation of the first gate control signal S1, and the voltage of the first node N1 and the fourth node N4 is reset. During this stage, the connecting transistor T2 and the second reset transistor T7 are turned on to reset the voltage of the first node N1 through the second reference voltage VREF2, and the first reset transistor T6 is turned on to reset the voltage of the fourth node N4 through the first reference voltage VREF1.

[0148] The second activation of the first gate control signal S1 is synchronized with the first activation of the second gate control signal S2, and the data voltage DATA is written to the first node N1. During this stage, the data writing transistor T4, the driving transistor T3 and the connection transistor T2 are turned on to write the data voltage DATA to the first node N1.

[0149] When the second gate control signal S2 is turned on for the second time, the on-state bias adjustment of the driving transistor T3 is performed; during this stage, the data writing transistor T4 is turned on, and the on-state bias adjustment of the driving transistor T3 can be performed based on the data voltage DATA of the following rows.

[0150] From the falling edge of the light emission control signal to the next driving cycle, all gate control signals are turned off to control the light emission element 100 to emit light for display.

[0151] refer to Figure 19 , Figure 19 This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in an embodiment of this application. Figure 17 The pixel circuit shown is different in that, Figure 19 The first terminal of the second reset transistor T7 in the pixel circuit shown is connected to the first node N1. Figure 19 The control timing of the pixel circuit shown can also be as follows: Figure 18 As shown, the control timing of the display panel in one drive cycle can be referenced. Figure 18 The corresponding methods will not be described again in the embodiments of this application.

[0152] exist Figures 17-19 In the method shown, not only can the pixel circuit be time-controlled by only two driving circuits, but low-frequency driving can also be achieved while retaining the OBS modulation function.

[0153] refer to Figure 20 , Figure 20 This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in this application embodiment. Based on other methods, Figure 20 In the pixel circuit shown, the first terminal of the second reset transistor T7 is connected to the first node N1; the third port D3 and the fourth port D4 are connected to the same second shift register VSR2.

[0154] exist Figure 20In the illustrated configuration, in the first driving circuit 101, the first square wave signal EM output by the first shift register VSR1 of the same stage simultaneously serves as the first light emission control signal EM1, the second light emission control signal EM2, and the third gate control signal S3. In the second driving circuit 102, the output signals of the two second shift registers VSR2 of different stages are SP1 and SP2, respectively. SP1 serves as the fourth gate control signal S4, and SP2 serves as the first gate control signal S1 and the second gate control signal S2. At this time, the control timing of the pixel circuit can be as follows: Figure 21 As shown.

[0155] refer to Figure 21 , Figure 21 for Figure 20 The control timing diagram of the pixel circuit in the display panel shown is combined with... Figure 20 and Figure 21 As shown, in one driving cycle of the pixel circuit:

[0156] Between the rising and falling edges of the light emission control signal, the fourth gate control signal S4 is turned on to reset the voltage of the first node N1 and the fourth node N4. During this stage, the high-level fourth gate control signal S4 controls the second reset transistor T7 to turn on so as to reset the voltage of the first node N1 through the second reference voltage VREF2.

[0157] After voltage reset and before the falling edge of the light emission control signal, the second gate control signal S2 is turned on, and the data voltage DATA is written to the first node N1. During this stage, the driving transistor T3 is turned on, and the high-level second gate control signal S2 and the first gate control signal S1 control the connection transistor T2 and the data writing transistor T4 to be turned on, so as to write the data voltage DATA to the first node N1.

[0158] From the falling edge of the light emission control signal to the next driving cycle, all gate control signals are turned off to control the light emission element 100 to emit light for display.

[0159] refer to Figure 22 , Figure 22 This is a schematic diagram illustrating the connection relationship between the pixel circuit and the driving circuit in another display panel provided in this application embodiment. Based on other methods, Figure 22 The pixel circuit shown also includes: a bias adjustment transistor T8; the first terminal of the bias adjustment transistor T8 is connected to the second node N2, the second terminal is connected to the bias adjustment signal DVH, and the gate is connected to the seventh port D7 for receiving the fifth gate control signal S5; the first terminal of the second reset transistor T7 is connected to the first node N1; the first gate control signal S1 and the second gate control signal S2 are the same gate control signal, and the third port D3 and the fourth port D4 are connected to the same second shift register VSR2; the third port D3, the sixth port D6, and the seventh port D7 are respectively connected to different second shift registers VSR2. Figure 22 The pixel circuit with the 8T1C structure shown (including eight transistors and one capacitor) only requires two driving circuits for timing control, which reduces the number of driving circuits required for the pixel circuit.

[0160] Optionally, the bias adjustment transistor T8 is a dual-gate transistor with its bottom gate and top gate connected.

[0161] exist Figure 22 In the illustrated configuration, in the first driving circuit 101, the first square wave signal EM output by the first shift register VSR1 of the same stage simultaneously serves as the first light emission control signal EM1, the second light emission control signal EM2, and the third gate control signal S3. In the second driving circuit 102, the output signals of the three different stages of the second shift register VSR2 are SP1, SP2, and SP3, respectively. SP1 serves as the fourth gate control signal S4, SP2 serves as the first gate control signal S1 and the second gate control signal S2, and SP3 serves as the fifth gate control signal S5. At this time, the control timing of the pixel circuit can be as follows: Figure 23 As shown.

[0162] refer to Figure 23 , Figure 23 for Figure 22 The control timing diagram of the pixel circuit in the display panel shown is combined with... Figure 22 and Figure 23 As shown, in one driving cycle of the pixel circuit:

[0163] Between the rising and falling edges of the light emission control signal, the fourth gate control signal S4 is turned on to reset the voltage of the first node N1 and the fourth node N4. During this stage, the high-level light emission control signal and the fourth gate control signal S4 control the first reset transistor T6 and the second reset transistor T7 to be turned on, so as to reset the voltage of the fourth node N4 through the first reference voltage VREF1 and reset the voltage of the first node N1 through the second reference voltage VREF2.

[0164] After voltage reset and before the falling edge of the light emission control signal, the second gate control signal S2 is turned on, and the data voltage DATA is written to the first node N1. During this stage, the high-level second gate control signal S2 controls both the connection transistor T2 and the data writing transistor T4 to be turned on, so that the data voltage DATA can be written to the first node N1.

[0165] After writing the data voltage DATA, before the falling edge of the light emission control signal, the fifth gate control signal S5 is turned on to adjust the on-state bias of the driving transistor T3. During this stage, the high-level fifth gate control signal S5 controls the bias adjustment transistor T8 to be turned on so as to adjust the bias of the driving transistor T3 through the bias adjustment signal DVH.

[0166] From the falling edge of the light emission control signal to the next driving cycle, all gate control signals are turned off to control the light emission element 100 to emit light for display.

[0167] The display panel provided in this application embodiment allows a large number of transistors in the pixel circuit to share the driving circuit, thereby reducing the number of driving circuits required, reducing the bezel width and power consumption of the display panel, and optimizing the pixel layout space inside the display panel.

[0168] The driving phase of one driving cycle of a pixel circuit includes at least a node voltage reset phase, a data voltage writing phase, and a light emission phase, all controlled by timing. In different implementations of the pixel circuit, the control timing principle for the same driving phase is the same, and the control timing of the same driving phase in different implementations can complement and reference each other. Optionally, an OBS phase is also included between the data voltage writing phase and the light emission phase to adjust the bias of the driving transistor T3.

[0169] During the OBS stage, the data writing transistor T4 can be turned on by the second gate control signal S2 to multiplex the data voltage DATA of the following few rows (which can be set to any consecutive data voltage DATA after the barrier scan row according to the modulation requirements) and write it to the third node N3 to adjust the bias of the driving transistor T3.

[0170] Alternatively, during the OBS phase, the bias of the drive transistor T3 can be adjusted using the bias adjustment transistor T8 connected to the second node N2. In this method, the voltage of the first node N1 can also be reset using the second reset transistor T7 connected to the first node N1.

[0171] As can be seen from the above description, in the pixel circuit provided in this application embodiment, the first port D1, the second port D2, and the fifth port D5 can be connected to the same first shift register VSR1, or the first port D1 and the second port D2 can be connected to different first shift registers VSR1 and the second port D2 and the fifth port D5 can be connected to the same first shift register VSR1. The first light-emitting control transistor T1, the second light-emitting control transistor T5, and the first reset transistor T6 can share the first driving circuit 101. At the same time, the gate input signal is provided through the first driving circuit 101 to reduce the number of driving circuits that need to be connected to the pixel circuit.

[0172] When the pixel circuit includes the second reset transistor T7, the sixth port D6 and the fourth port D4 can be connected to different second shift registers VSR2. The second reset transistor T7 and the data write transistor T4 can share the first drive circuit 101, and at the same time, the gate input signal is provided through the second drive circuit 102 to reduce the number of drive circuits that need to be connected to the pixel circuit.

[0173] When bias adjustment transistor T8 is included, the seventh port D7 and the fourth port D4 can be connected to different second shift registers VSR2. The bias adjustment transistor T8 and the data write transistor T4 can share the first drive circuit 101, while providing the gate input signal through the second drive circuit 102 to reduce the number of drive circuits required to be connected to the pixel circuit.

[0174] It should be noted that in the embodiments of the display panel, the connection method between the pixel circuit and the driving circuit in each embodiment mainly reflects the electrical connection relationship between the transistor in the pixel circuit and the driving circuit, and is not the actual layout position of the driving circuit. The driving circuit can be set in one or more bezel areas of the display panel according to design requirements. In display panels with borderless or narrow bezel designs, at least part of the driving circuit can also be set in the display area.

[0175] Based on the display panel provided in the above embodiments, another embodiment of this application also provides a display device, which can perform as follows: Figure 24 As shown.

[0176] refer to Figure 24 , Figure 24 This is a schematic diagram of a display device provided in an embodiment of this application. The display device includes a display panel 106 provided in any of the above-described embodiments. The display panel includes: a light-emitting element 100; a pixel circuit 104 connected to the light-emitting element 100; and a driving circuit 105 connected to the pixel circuit 104.

[0177] The pixel circuit 104 adopts the circuit structure of any of the above embodiments. The pixel circuit 104 includes: a driving transistor T3, the gate of which is connected to a first node N1, the first terminal of which is connected to a second node N2, and the second terminal of which is connected to a third node N3; a first light-emitting control transistor T1, the first terminal of which is used to connect to a first power supply signal PVDD, the second terminal of which is connected to the second node N2, and the gate of which is connected to a first port D1 for connecting to a first light-emitting control signal EM1; a second light-emitting control transistor T5, the first terminal of which is connected to the third node N3, the second terminal of which is connected to a fourth node N4, and the gate of which is connected to a second port D2 for connecting to a second light-emitting control signal EM2; the fourth node N4 is connected to a light-emitting... Component 100; a connecting transistor T2, the first terminal of which is connected to the first node N1, the second terminal of which is connected to the second node N2, and the gate of which is connected to the third port D3 for receiving the first gate control signal S1; a data writing transistor T4, the first terminal of which is connected to the third node N3, the second terminal of which is used to receive the data voltage DATA, and the gate of which is connected to the fourth port D4 for receiving the second gate control signal S2; a first reset transistor T6, the first terminal of which is used to receive the first reference voltage VREF1, the first terminal of which is connected to the fourth node N4, and the gate of which is connected to the fifth port D5 for receiving the third gate control signal S3; wherein, two or three of the first ports D1 to the fifth ports D5 are respectively connected to different shift registers VSR in the same driving circuit 105.

[0178] Display devices include, but are not limited to, displays for mobile phones, wearable display devices, tablets, laptops, and display appliances.

[0179] In this embodiment of the application, the display device uses the above-mentioned display panel, which can reduce the bezel width and power consumption of the display panel, and also optimize the pixel layout space inside the display panel.

[0180] The various embodiments in this application are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. The embodiments provided in this application can be combined with each other without contradiction.

[0181] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0182] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0183] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0184] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized by, The pixel circuit comprises: a pixel circuit and a driving circuit connected with the pixel circuit; The pixel circuit comprises: a driving transistor, a gate of the driving transistor is connected with a first node, a first electrode of the driving transistor is connected with a second node, and a second electrode is connected with a third node; a first light-emitting control transistor, a first electrode of the first light-emitting control transistor is used for accessing a first power supply signal, a second electrode is connected with the second node, and a gate is connected with a first port used for accessing a first light-emitting control signal; a second light-emitting control transistor, a first electrode of the second light-emitting control transistor is connected with the third node, a second electrode is connected with a fourth node, and a gate is connected with a second port used for accessing a second light-emitting control signal; the fourth node is used for connecting a light-emitting element; a communication transistor, a first electrode of the communication transistor is connected with the first node, a second electrode is connected with the second node, and a gate is connected with a third port used for accessing a first gate control signal; a data writing transistor, a first electrode of the data writing transistor is connected with the third node, a second electrode is used for accessing a data voltage, and a gate is connected with a fourth port used for accessing a second gate control signal; a first reset transistor, a first electrode of the first reset transistor is used for accessing a first reference voltage, a first electrode is connected with the fourth node, and a gate is connected with a fifth port used for accessing a third gate control signal; wherein two or three of the first port to the fifth port are respectively connected with different shift registers in the same driving circuit.

2. The display panel of claim 1, wherein, The communication transistor, the driving transistor, the data writing transistor and the first reset transistor are all oxide transistors; The first light-emitting control transistor and the second light-emitting control transistor are both low-temperature polysilicon transistors.

3. The display panel of claim 2, wherein, The communication transistor, the data writing transistor and the first reset transistor are all double-gate transistors; In the communication transistor, the data writing transistor and the first reset transistor, the bottom gate and the top gate of the same double-gate transistor are connected.

4. The display panel of claim 2, wherein, The driving transistor is a double-gate transistor, and the bottom gate of the driving transistor is connected with the third node.

5. The display panel of claim 2, wherein, The second port and the fifth port are output terminals of the same shift register, and the third gate control signal and the second light-emitting control signal are the same signal.

6. The display panel of claim 1, wherein, The driving circuit comprises a first driving circuit and a second driving circuit, the first driving circuit comprises a plurality of cascaded first shift registers, and the second driving circuit comprises a plurality of cascaded second shift registers; The first port and the second port are respectively connected with different first shift registers; The third port and the fourth port are respectively connected with different second shift registers.

7. The display panel of claim 6, wherein, In a driving period of the pixel circuit, the rising edge of the first light-emitting control signal is located between the rising edge and the falling edge of the second light-emitting control signal; Between the rising edge of the second light-emitting control signal and the falling edge of the first light-emitting control signal, the first gate control signal is turned on, and the first node and the fourth node are voltage reset. The first gate control signal and the second gate control signal are synchronously turned on at a rising edge of the first light emitting control signal and a falling edge of the second light emitting control signal, and the data voltage is written into the first node; After the data voltage is written into the first node, the second gate control signal is turned on before the falling edge of the second light emitting control signal, and the drive transistor is subjected to open-state bias adjustment; The first gate control signal and the second gate control signal are both turned off from the falling edge of the first light emitting control signal to the next drive period, and the light emitting element is controlled to emit light for display.

8. The display panel of claim 1, wherein, The drive circuit comprises a first drive circuit and a second drive circuit, the first drive circuit comprises a plurality of cascaded first shift registers, and the second drive circuit comprises a plurality of cascaded second shift registers; The first port and the second port are connected to different first shift registers respectively; the first gate control signal and the second light emitting control signal are the same signal, and the third port and the second port are connected to the same first shift register; The fourth port is connected to the second shift register.

9. The display panel of claim 8, wherein, In one drive period of the pixel circuit, the rising edge of the first gate control signal is located between the rising edge and the falling edge of the light emitting control signal; The first node and the fourth node are subjected to voltage reset at the rising edge of the second light emitting control signal and the rising edge of the first light emitting control signal; The second gate control signal is turned on between the rising edge of the first light emitting control signal and the falling edge of the second light emitting control signal, and the data voltage is written into the first node; The second gate control signal is turned on between the falling edge of the second light emitting control signal and the falling edge of the first light emitting control signal, and the drive transistor is subjected to open-state bias adjustment; The first gate control signal and the second gate control signal are both turned off from the falling edge of the first light emitting control signal to the next drive period, and the light emitting element is controlled to emit light for display.

10. The display panel of claim 1, wherein, Further comprising: A second reset transistor, a first electrode of the second reset transistor being connected to the first node or the second node, a second electrode of the second reset transistor being connected to a second reference voltage, and a gate of the second reset transistor being connected to a sixth port for inputting a fourth gate control signal; The drive circuit comprises a first drive circuit and a second drive circuit, the first drive circuit comprises a plurality of cascaded first shift registers, and the second drive circuit comprises a plurality of cascaded second shift registers; The first light emitting control signal and the second light emitting control signal are the same light emitting control signal, and the first port and the second port are connected to the same first shift register; The sixth port and the fourth port are connected to different second shift registers respectively.

11. The display panel of claim 10, wherein, The drive circuit further comprises a third drive circuit, and the third drive circuit comprises a plurality of cascaded third shift registers; The third port is connected to the third shift register.

12. The display panel of claim 11, wherein, In one drive period of the pixel circuit, the rising edge and the falling edge of the first gate control signal are located between the rising edge and the falling edge of the light emitting control signal; The fourth gate control signal is turned on between the rising edge and the falling edge of the first gate control signal, and the first node and the fourth node are voltage reset; After the voltage reset, the second gate control signal is turned on before the falling edge of the first gate control signal, and the data voltage is written into the first node; The falling edge of the light emitting control signal to the next driving period, each gate control signal is closed, control the light emitting element to emit light display.

13. The display panel of claim 11, wherein, In a driving period of the pixel circuit, the rising edge and the falling edge of the first gate control signal are between the rising edge and the falling edge of the light emitting control signal; The fourth gate control signal is turned on twice in turn between the rising edge and the falling edge of the first gate control signal, and the first node and the fourth node are voltage reset; After the second turning on of the fourth gate control signal, the first turning on of the second gate control signal is before the falling edge of the first gate control signal, and the data voltage is written into the first node; After the falling edge of the first gate control signal, the second turning on of the second gate control signal is before the falling edge of the light emitting control signal, and the on-state bias adjustment of the driving transistor is performed; The falling edge of the light emitting control signal to the next driving period, each gate control signal is closed, to control the light emitting element to emit light display.

14. The display panel of claim 10, wherein, The first light emitting control signal, the second light emitting control signal and the first gate control signal are the same signal, and the first port, the second port and the third port are connected to the same first shift register.

15. The display panel of claim 14, wherein, In a driving period of the pixel circuit: The fourth gate control signal is turned on between the rising edge and the falling edge of the light emitting control signal, and the first node and the fourth node are voltage reset; After the voltage reset, the second gate control signal is turned on before the falling edge of the light emitting control signal, and the data voltage is written into the first node; The falling edge of the light emitting control signal to the next driving period, each gate control signal is closed, to control the light emitting element to emit light display.

16. The display panel of claim 10, wherein, The third port, the fourth port and the sixth port are connected to different second shift registers respectively.

17. The display panel of claim 16, wherein, In a driving period of the pixel circuit: The first gate control signal, the second gate control signal and the fourth gate control signal are turned on twice in turn between the rising edge and the falling edge of the light emitting control signal; The second turning on of the fourth gate control signal is synchronized with the first turning on of the first gate control signal, and the first node and the fourth node are voltage reset; The second turning on of the first gate control signal is synchronized with the first turning on of the second gate control signal, and the data voltage is written into the first node; The second turning on of the second gate control signal is for the on-state bias adjustment of the driving transistor; The falling edge of the light emitting control signal to the next driving period, each gate control signal is closed, to control the light emitting element to emit light display.

18. The display panel of claim 10, wherein, The first electrode of the second reset transistor is connected to the first node; The third port and the fourth port are connected to the same second shift register.

19. The display panel of claim 18, wherein, In one driving period of the pixel circuit: The fourth gate control signal is turned on between the rising edge and the falling edge of the light emitting control signal, and the first node and the fourth node are voltage reset; After the voltage reset, the second gate control signal is turned on before the falling edge of the light emitting control signal, and the data voltage is written to the first node; After the data voltage is written, the fifth gate control signal is turned on before the falling edge of the light emitting control signal, and the driving transistor is turned on for bias adjustment; 20. The display panel of claim 10, wherein, From the falling edge of the light emitting control signal to the next driving period, each gate control signal is turned off to control the light emitting element to emit light for display. Further comprising: a bias adjustment transistor; The first electrode of the bias adjustment transistor is connected to the second node, the second electrode is connected to a bias adjustment signal, and the gate electrode is connected to a seventh port for inputting a fifth gate control signal; The first electrode of the second reset transistor is connected to the first node; The first gate control signal and the second gate control signal are the same gate control signal, and the third port and the fourth port are connected to the same second shift register; 21. The display panel of claim 20, wherein, The third port, the sixth port and the seventh port are respectively connected to different second shift registers. In one driving period of the pixel circuit: The fourth gate control signal is turned on between the rising edge and the falling edge of the light emitting control signal, and the first node and the fourth node are voltage reset; After the voltage reset, the second gate control signal is turned on before the falling edge of the light emitting control signal, and the data voltage is written to the first node; After the data voltage is written, the fifth gate control signal is turned on before the falling edge of the light emitting control signal, and the driving transistor is turned on for bias adjustment; 22. A display device comprising: From the falling edge of the light emitting control signal to the next driving period, each gate control signal is turned off to control the light emitting element to emit light for display. Further comprising: a display panel; The display panel comprises: a light emitting element; a pixel circuit connected to the light emitting element; a driving circuit connected to the pixel circuit; The pixel circuit comprises: a driving transistor, the gate electrode of the driving transistor is connected to a first node, the first electrode of the driving transistor is connected to a second node, and the second electrode is connected to a third node; a first light emitting control transistor, the first electrode of the first light emitting control transistor is used for inputting a first power supply signal, the second electrode is connected to the second node, and the gate electrode is connected to a first port for inputting a first light emitting control signal; a second light emitting control transistor, the first electrode of the second light emitting control transistor is connected to the third node, the second electrode is connected to a fourth node, and the gate electrode is connected to a second port for inputting a second light emitting control signal; the fourth node is connected to the light emitting element; a communication transistor, the first electrode of the communication transistor is connected to the first node, the second electrode is connected to the second node, and the gate electrode is connected to a third port for inputting a first gate control signal; a data writing transistor, the first electrode of the data writing transistor is connected to the third node, the second electrode is used for inputting a data voltage, and the gate electrode is connected to a fourth port for inputting a second gate control signal; A first reset transistor, a first electrode of the first reset transistor is configured to access a first reference voltage, the first electrode is connected to the fourth node, a gate electrode is connected to a fifth port configured to access a third gate control signal; Two or three of the first port to the fifth port are respectively connected to different shift registers in the same driving circuit.

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