A circuit of a serial peripheral interface, a beamforming chip and a radio frequency front end

Abstract

The application provides a circuit based on a beamforming chip serial peripheral interface, a beamforming chip and a radio frequency front end, comprising a shift register and a data output unit; an input end of the shift register is connected with a first device, and an output end of the shift register is connected with the data output unit, which is used for receiving a command field and / or input data from the first device and performing data output; the shift register is controlled by a mode selection input signal to switch between a first mode and a second mode; in the first mode, the first device is a master device, and the shift register outputs the input data from the first device to a target static register corresponding to the command field; in the second mode, the first device is an upstream device, and the shift register outputs the input data from the first device to a downstream device. In the above-mentioned circuit, the shift register can be switched between the first mode and the second mode, and the flexibility is improved.

Description

Technical Field

[0001] This application relates to the field of interfaces, and more specifically, to a circuit, a beamforming chip, and an RF front-end for a serial peripheral interface based on a beamforming chip. Background Technology

[0002] In multi-device electronic systems, such as phased array systems, it is often necessary to configure and control a large number of integrated circuits simultaneously. The Serial Peripheral Interface (SPI) is widely used as the core control interface due to its simple structure and high transmission rate. However, existing SPI implementations have some limitations when scaling up to different system sizes.

[0003] First, in traditional SPI, each device needs to be configured with a dedicated Chip Select (CS) signal. This leads to a corresponding increase in the number of CS lines as the number of devices increases, resulting in a shortage of controller pin resources, complex printed circuit board (PCB) routing, and consequently, limited system scalability.

[0004] In response to this, a daisy-chain pattern exists in related technologies. In the daisy-chain pattern, multiple devices are connected in series, so that the output of an upstream device becomes the input of a downstream device. This pattern can reduce the chip select signals required by multiple devices, simplify the board layout, and is suitable for smaller-scale systems. However, this pattern has the following drawbacks: data must pass through the upstream devices sequentially, thus introducing latency; and if one device in the chain fails, all its downstream devices may be affected, resulting in poor fault tolerance.

[0005] Meanwhile, in related technologies, there is also a physical addressing mode. In physical addressing mode, a unique address is assigned to each device in the SPI command protocol, and the target device is identified by the address. This mode enables direct random access to devices, ensuring that a failure of one device will not block communication with other devices, making it suitable for large systems. However, this mode also has the following drawbacks: it requires more chip select lines and more complex wiring, thereby increasing the use of controller pins and the complexity of printed circuit board design.

[0006] Since daisy-chain mode and physical addressing mode are suitable for different system scales, there is an urgent need to provide a flexible SPI circuit that allows system manufacturers to select either physical addressing mode or daisy-chain mode in the same hardware, thus making it suitable for different system scales. Summary of the Invention

[0007] This application provides at least one circuit, a beamforming chip, and an RF front-end for a serial peripheral interface based on a beamforming chip. In the circuit described above, switching between a first mode and a second mode can be achieved through a first multiplexer MUX1, breaking the limitation in related technologies that serial peripheral interfaces can only support a single mode. This allows for flexible selection between different modes according to the specific system scale, thus improving flexibility.

[0008] In a first aspect, this application provides a circuit for a serial peripheral interface based on a beamforming chip, the circuit including a shift register and a data output unit:

[0009] The input of the shift register is connected to the first device, and the output is connected to the data output unit. It is used to receive command fields and / or input data from the first device and to output data. The shift register is controlled by a mode selection input signal to switch between a first mode and a second mode; In the first mode, the first device is the master device, and the shift register outputs the input data of the future autonomous device to the target static register corresponding to the command field. In the second mode, the first device is the upstream device, and the shift register outputs the input data from the upstream device to the downstream device.

[0010] Secondly, this application also provides a beamforming chip, which includes the circuitry of the serial peripheral interface based on the beamforming chip in the foregoing embodiments.

[0011] Thirdly, this application also provides a radio frequency (RF) front-end, which includes the beamforming chip of the aforementioned embodiments.

[0012] In summary, this application provides a circuit, a beamforming chip, and an RF front-end for a serial peripheral interface based on a beamforming chip. The circuit includes a shift register and a data output unit. The input of the shift register is connected to a first device, and the output is connected to the data output unit. It receives command fields and / or input data from the first device and outputs the data. The shift register is controlled by a mode selection input signal to switch between a first mode and a second mode. In the first mode, the first device is the master device, and the shift register outputs the input data from the master device to the target static register corresponding to the command field. In the second mode, the shift register outputs the input data from the upstream device to the downstream device. In the above circuit, switching between the first and second modes can be achieved through the shift register, breaking the limitation of related technologies where serial peripheral interfaces can only support a single fixed mode. This allows for flexible selection between different modes according to the specific system scale, improving flexibility.

[0013] Other advantages of this application will be explained in more detail in conjunction with the following description and figures.

[0014] It should be understood that the above description is merely an overview of the technical solution of this application, so as to enable a general understanding of the technical means of this application and to implement it in accordance with the contents of the specification. In order to make the above and other objects, features and advantages of this application more apparent and understandable, specific embodiments of this application are illustrated below. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. The accompanying drawings are incorporated in and constitute a part of this specification. These drawings illustrate embodiments conforming to this application and are used together with the specification to explain the technical solutions of this application. It should be understood that the drawings only illustrate certain embodiments of this application and should not be considered as a limitation on the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. Furthermore, the same reference numerals denote the same components throughout the drawings. In the drawings: Figure 1 A circuit diagram of a serial peripheral interface based on a beamforming chip provided in an embodiment of this application; Figure 2 A circuit diagram of a first embodiment of a serial peripheral interface circuit based on a beamforming chip; Figure 3 This is a circuit diagram of a second embodiment of a serial peripheral interface circuit based on a beamforming chip. Figure 4 This is a circuit diagram of a third embodiment of a serial peripheral interface circuit based on a beamforming chip. Figure 5 This is a circuit diagram of a fourth embodiment of a serial peripheral interface circuit based on a beamforming chip. Detailed Implementation

[0016] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0017] In the description of embodiments of this application, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the disclosed features, figures, steps, behaviors, components, portions or combinations thereof in this specification, and do not exclude the possibility of the presence of one or more other features, figures, steps, behaviors, components, portions or combinations thereof.

[0018] Unless otherwise stated, " / " means "or". For example, A / B can mean A or B. In this article, "and / or" is merely a way of describing the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A alone, A and B at the same time, and B alone.

[0019] The terms "first," "second," etc., are used only for ease of description to distinguish identical or similar technical features and should not be construed as indicating or implying the relative importance or number of these technical features. Therefore, a feature defined by "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, the term "multiple" means two or more.

[0020] In multi-device electronic systems, such as phased array systems, it is often necessary to configure and control a large number of integrated circuits simultaneously. SPI is widely used as the core control interface due to its simple structure and high transmission rate. However, existing SPI implementations have some limitations when scaling up to different system sizes.

[0021] First, in traditional SPI, each device needs to be configured with a dedicated chip select signal. This leads to a corresponding increase in the number of CS lines as the number of devices increases, resulting in a shortage of controller pin resources, complex printed circuit board wiring, and thus limiting system scalability.

[0022] In response to this issue, a daisy-chaining model exists in related technologies. In daisy-chaining, multiple devices are connected in series, with the output of an upstream device serving as the input to a downstream device. This model reduces the number of chip select signals required for multiple devices, simplifies board layout, and is suitable for smaller-scale systems. However, this model has the following drawbacks: data must pass through upstream devices sequentially, introducing latency; and if one device in the chain fails, all its downstream devices may be affected, resulting in poor fault tolerance.

[0023] Meanwhile, physical addressing mode also exists in related technologies. In physical addressing mode, a unique address is assigned to each device in the SPI command protocol, and the target device is identified by the address. This mode enables direct random access to devices, ensuring that a failure of one device will not block communication with other devices, making it suitable for large systems. However, this mode also has the following disadvantages: it requires more chip select lines and more complex wiring, thereby increasing the use of controller pins and the complexity of printed circuit board design.

[0024] Since daisy-chain mode and physical addressing mode are suitable for different system scales, there is an urgent need to provide a flexible SPI circuit that allows system manufacturers to select either physical addressing mode or daisy-chain mode in the same hardware, thus making it suitable for different system scales.

[0025] In view of this, this application provides a circuit, a beamforming chip, and an RF front end for a serial peripheral interface based on a beamforming chip. In the circuit described above, switching between a first mode and a second mode can be achieved through a shift register, breaking the limitation of related technologies where serial peripheral interfaces can only support a single mode. This allows for flexible selection between different modes according to the specific system scale, thus improving flexibility.

[0026] The following describes a circuit example of a serial peripheral interface based on a beamforming chip provided in this application. Figure 1 As shown, Figure 1 A circuit diagram of a serial peripheral interface based on a beamforming chip provided in this application embodiment is shown. The circuit includes a shift register and a data output unit. The input of the shift register is connected to the first device, and the output is connected to the data output unit. It is used to receive command fields and / or input data from the first device and to output data. The shift register is controlled by a mode selection input signal to switch between a first mode and a second mode; In the first mode, the first device is the master device, and the shift register outputs the input data of the future autonomous device to the target static register corresponding to the command field. In the second mode, the first device is the upstream device, and the shift register outputs the input data from the upstream device to the downstream device.

[0027] Specifically, the input of the shift register is connected to the first device to receive and temporarily store command fields and / or input data from the first device. The shift register includes control bits and data bits. The control bits of the shift register correspond to the command fields from the first device, and the data bits of the shift register correspond to the input data, such as... Figure 1As shown, the control bits can include "R / W, BC, CHIP_ADDRESS, REGISTER_ADDRESS", and the data bits can include "DATA". These will be explained in detail below: "R / W: A control bit that specifies whether the operation is a write (0) or a read (1). This control bit is only valid in the first mode and is ignored in the second mode."

[0028] BC: A control bit that specifies whether only the target device with the matching address executes the command, or whether all devices on the SPI bus execute the command simultaneously. This control bit is only valid in the first mode and is ignored in the second mode.

[0029] CHIP_ADDRESS: Specifies the physical address of the specific target device to which data needs to be transferred. It is only valid in the first mode and is ignored in the second mode.

[0030] REGISTER_ADDRESS: Specifies the address of the static register to be written to in both modes, or the address of the static register to be read in the first mode, meaning it is valid in both modes.

[0031] DATA: The payload data to be output.

[0032] The data output unit is used to output data.

[0033] The shift register is controlled by a mode select input signal (MODE) to switch between a first mode and a second mode. The mode select input signal determines whether to operate in the first or second mode. In practical applications, the mode select input signal can be set to operate in the first mode when the MODE pin is connected to a logic low level, and in the second mode when it is connected to a logic high level. It should be noted that in practical applications, the logic polarity of the mode select input signal can also be reversed.

[0034] In the first mode, the first device is the master device. During a write operation in the first mode, a shift register shifts in the command field and input data from the master device and transmits the data to the target static register corresponding to the command field. In other possible embodiments, the target static register can also be a storage unit that needs to be read and written. During a read operation in the first mode, the shift register receives the command field from the master device and directly outputs the data from the target static register corresponding to the command field to the master device. In practice, in the first mode, the slave device has a unique hardware identifier (CHIP ID) and compares the address field (CHIP ADDRESS) in the command field with the CHIP ID, performing read and write operations only when the address matches (or a broadcast command is encountered).

[0035] In the second mode, serial commands and data output by the master device are transmitted sequentially along a serial link consisting of multiple slave devices, with the first device referring to the upstream device in the link. Driven by a clock signal, each slave device's shift register simultaneously shifts in serial data from the upstream device and shifts out its currently stored data to the downstream device via a serial output. In the second mode, the shifting process continues until the commands and data sent by the master device have passed through all slave devices in the link, and the master device receives the data shifted out sequentially by each slave device via a serial data return path. In the second mode, the chip ID of each slave device is ignored.

[0036] In the circuit described above, switching between the first and second modes can be achieved through a shift register, breaking the limitation of serial peripheral interfaces in related technologies that can only support a single mode. This allows for flexible selection between different modes based on the specific system scale, thus improving flexibility.

[0037] In one possible implementation, the circuit also includes a static register to be transferred; In the second mode, the data of the static register to be transferred is input to the shift register so that the data of the static register to be transferred can be shifted and output to the downstream device in the next shift operation.

[0038] Specifically, considering that data flows continuously between upstream and downstream devices in the chain in the second mode, a static register (i.e., the read pointer register) is specially set up to store the address pointer value (READ_ADDRESS) in order to meet the data readback requirements in the second mode. When the master device needs to read data from a specific internal register of a slave device in the chain, it first writes the address of the target register to the slave device's dedicated read pointer register through a write operation. Then, the control logic block selects the corresponding internal static register based on the address value in this read pointer register and loads its data content into a shift register so that it can be shifted and output to the downstream device in the next shift operation and finally received by the master device. This achieves non-destructive, addressable reading of any slave device's internal register in the chain.

[0039] In one possible implementation, such as Figure 2 As shown, Figure 2 A first embodiment of a circuit for a serial peripheral interface based on a beamforming chip is provided. In this first embodiment, the circuit further includes a first multiplexer MUX1. The first input of the first multiplexer MUX1 is connected to the output of the shift register, the second input is connected to the output of the static register to be transmitted, and the output is connected to the data output unit. In the first mode read operation, the first multiplexer MUX1 outputs the data of the static register to be transferred; In the second mode, the first multiplexer MUX1 outputs the data from the shift register, where the data portion of the shift register comes from the static register to be transmitted.

[0040] Specifically, the first input of the first multiplexer MUX1 is connected to the output of the shift register, the second input is connected to the output of the static register to be transmitted, and the output is connected to the data output unit. That is, the first input of the first multiplexer MUX1 is connected to the shift register, and the second input is connected to the static register to be transmitted. In the first mode read operation (MODE=0 in this example), the first multiplexer MUX1 directly outputs the data from the static register to be transmitted. In the second mode (MODE=1 in this example), the first multiplexer MUX1 outputs the data from the shift register, where the data portion comes from the static register to be transmitted.

[0041] In one possible implementation, such as Figure 3 As shown, Figure 3 A second embodiment of a circuit for a serial peripheral interface based on a beamforming chip is provided. In this second embodiment, the circuit further includes a second multiplexer MUX2. The first input of the second multiplexer MUX2 is connected to the output of the control bit of the shift register, the second input is connected to the output of the static register to be transmitted, and the output is connected to the input of the data bit of the shift register. In the first mode, the second multiplexer MUX2 outputs the input data of the autonomous device to the data bits of the shift register; In the second mode, the second multiplexer MUX2 first outputs the input data from the upstream device to the data bits of the shift register, and after the shifting process is completed, outputs the data from the static register to be transmitted to the data bits of the shift register.

[0042] Specifically, in this embodiment, a second multiplexer MUX2 is provided between the control bits and the data bits of the shift register.

[0043] In the first mode, the first device is the master device, and the second multiplexer MUX2 outputs the input data from the master device to the data bits of the shift register so that the shift register can output the input data to the target static register corresponding to the command field according to the address matching. In the second mode, the first device is the upstream device, and the second multiplexer MUX2 first outputs the input data from the upstream device to the data bits of the shift register, and after the shift process is completed, outputs the data from the static register to be transmitted to the data bits of the shift register so that it can be shifted into the master device through the downstream device in the next shift operation.

[0044] In one possible implementation, such as Figure 3 As shown, in the first embodiment, the second multiplexer MUX2 is controlled by a mode selection input signal and a chip select signal; the mode selection input signal is used to switch the response of the second multiplexer MUX2 in a first mode and a second mode; the chip select signal is used to control the input of input data in the first mode, and to control the sequential input of input data and data to be transmitted in the static register in the second mode.

[0045] Specifically, in the first mode, the first device is the master device. When the chip select signal (CSB) is valid, the second multiplexer MUX2 shifts the input data of the master device to the data bits of the shift register so that the input data can be output to the target static register according to the address matching.

[0046] In the second mode, the first device is the upstream device. When the chip select signal is valid, the second multiplexer MUX2 first shifts the input data from the upstream device to the data bits of the shift register. After the input data shift is complete, the chip select signal (CSB) changes from valid to invalid. At this time, the data bits of the shift register are output to the target static register. Simultaneously, the second multiplexer MUX2 inputs the data from the static register to be transmitted to the data bits of the shift register. That is, through the transition of the chip select signal (CSB) from valid to invalid, data download from the shift register to the target static register and data upload from the static register to the shift register are simultaneously achieved.

[0047] exist Figure 3 In the illustrated embodiment, the chip select signal (CSB) is active low; however, in an alternative embodiment, it can also be implemented as an active high signal without affecting the functional operation.

[0048] In one possible implementation, such as Figure 4 As shown, Figure 4 A third embodiment of a circuit based on a beamforming chip for a serial peripheral interface is provided. In this third embodiment, the circuit further includes a third multiplexer MUX3. The first input of the third multiplexer MUX3 is connected to the first clock signal, the second input is connected to a high level, and the output is connected to the clock input of the data bits of the shift register; wherein, the first clock signal is the clock signal of the control bits of the shift register; The third multiplexer MUX3 is controlled by the chip select signal and is used to control the clock input of the first clock signal applied to the data bits of the shift register through the third multiplexer MUX3.

[0049] Specifically, such as Figure 4 As shown, when the chip select signal is valid, the first clock signal is applied to the data bits of the shift register through the third multiplexer MUX3 to ensure the correct timing of the input data transmission.

[0050] After the input data shift is complete, the chip select signal transitions from an active to an inactive state, i.e., from low to high. The rising edge of the chip select signal generates a latch signal via the third multiplexer, MUX3. The latch signal achieves different effects in two modes. In the first mode, the latch signal triggers the output of input data from the data bits of the shift register; in the second mode, it triggers both the output of input data from the data bits of the shift register and the upload of data from the static register to be transferred to the data bits of the shift register, preparing for the next shift operation.

[0051] exist Figure 4 In the illustrated embodiment, the chip select signal (CSB) is active low; however, in an alternative embodiment, it can be implemented as active high without affecting the functional operation.

[0052] In one possible implementation, such as Figure 4 As shown, in the second embodiment, the circuit further includes a delay unit: The input of the delay unit is connected to the output of the third multiplexer MUX3, and the output is connected to the clock input of the data bits of the shift register.

[0053] Specifically, a delay unit is set between the third multiplexer MUX3 and the data bits of the shift register. When the chip select signal is valid, the first clock signal is applied to the data bits of the shift register through the third multiplexer MUX3 and the delay unit, so that the first clock signal arrives at the command bit and data bit of the shift register in sequence.

[0054] In one possible implementation, such as Figure 5 As shown, Figure 5 A fourth embodiment of a serial peripheral interface circuit based on a beamforming chip is provided. In this fourth embodiment, the circuit further includes a secondary shift register and a fourth multiplexer MUX4. The input of the secondary shift register is connected to the output of the static register to be transferred, and the output is connected to the second input of the fourth multiplexer MUX4, which is used to store data from the static register to be transferred in the second mode. The first input of the fourth multiplexer MUX4 is connected to the output of the shift register, the second input is connected to the output of the secondary shift register, and the output is connected to the first input of the first multiplexer MUX1. It is used to output the data of the shift register and the data of the secondary shift register in sequence in response to the second mode.

[0055] Specifically, such as Figure 5As shown, the secondary shift register (DATA2) is located between the static register to be transferred and the fourth multiplexer MUX4, and is set in parallel with the shift register. It is used to store data from the static register to be transferred in the second mode.

[0056] In the first mode (MODE=0 in this example), the fourth multiplexer MUX4 has no function. If the master device needs to read static register data from the slave device, the data to be transmitted from the static register will be directly output to the master device through the first multiplexer MUX1.

[0057] In the second mode, the fourth multiplexer MUX4 outputs input data from the upstream device to the downstream device via a shift register, and outputs data from the static register to be transmitted to the downstream device via a secondary shift register. That is, in the second mode, the fourth multiplexer MUX4 selects to output the data from the shift register and the data from the secondary shift register sequentially.

[0058] In one possible implementation, such as Figure 5 As shown, in the fourth embodiment, the fourth multiplexer MUX4 is controlled by an output path control signal to switch between the data in the output shift register and the data in the secondary shift register.

[0059] Specifically, such as Figure 5 As shown, the fourth multiplexer MUX4 is controlled by the output path control signal (READ_SEL_2). Under the control of this output path control signal, the fourth multiplexer MUX4 can output the data of the shift register, and the fourth multiplexer MUX4 can also output the data of the secondary shift register, thereby realizing the selection of the output path.

[0060] In practical applications, such as Figure 5 In the process, when the mode selection input signal (MODE) is in the second mode, the data from the static register to be transmitted stored in the secondary shift register is first output to the downstream device by the fourth multiplexer MUX4. After the data output of the static register to be transmitted is completed, the fourth multiplexer MUX4 switches to the shift register so as to output the input data from the upstream device to the downstream device.

[0061] It should be noted that in practical applications, such as Figure 5 The fourth embodiment shown is similar to... Figure 3 , Figure 4 Compared to the second and third embodiments shown, the fourth embodiment can more easily meet the timing requirements under different processes, voltages, and temperature angles, thereby improving robustness and ensuring stable operation at high clock frequencies. However, due to the additional path corresponding to the secondary shift register in the fourth embodiment, its overall dynamic power consumption is slightly increased compared to the second embodiment.

[0062] In one possible implementation, the first mode is the physical addressing mode, and the second mode is the daisy chain mode.

[0063] Specifically, in this application, the first mode can be the physical addressing mode, and the second mode can be the daisy chain mode.

[0064] Therefore, this application provides a circuit for a serial peripheral interface based on a beamforming chip. This circuit includes a shift register and a data output unit. The input of the shift register is connected to a first device, and the output is connected to the data output unit. It receives command fields and / or input data from the first device and outputs the data. The shift register is controlled by a mode selection input signal to switch between a first mode and a second mode. In the first mode, the shift register outputs the input data from the first device to the target device corresponding to the command field. In the second mode, the shift register outputs the input data from the first device to a downstream device. In the above circuit, switching between the first and second modes can be achieved through the shift register, breaking the limitation of related technologies where serial peripheral interfaces can only support a single mode. This allows for flexible selection between different modes according to the specific system scale, improving flexibility.

[0065] In the description of this specification, references to terms such as "some possible implementations," "some implementations," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with that implementation or example is included in at least one implementation or example of this application, and the aforementioned terms do not necessarily refer to the same implementation or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more implementations or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different implementations or examples described in this specification, as well as the features of different implementations or examples.

[0066] While the spirit and principles of this application have been described above with reference to several specific embodiments, it should be understood that this application is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined. This application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0067] Based on this, embodiments of this application also provide a beamforming chip, which includes any of the serial peripheral interface circuits based on beamforming chips provided above.

[0068] It should be noted that the relevant descriptions of the serial peripheral interface circuit based on the beamforming chip provided above can all be referenced in the beamforming chip, and the embodiments of this application will not be repeated here.

[0069] Based on this, this application embodiment also provides a radio frequency front-end, which includes the beamforming chip provided above.

[0070] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit for a serial peripheral interface based on a beamforming chip, characterized in that, The circuit includes a shift register and a data output unit. The input terminal of the shift register is connected to the first device, and the output terminal is connected to the data output unit, for receiving command fields and / or input data from the first device, and outputting data. The shift register is controlled by a mode selection input signal to switch between a first mode and a second mode; In the first mode, the first device is the master device, and the shift register outputs the input data from the master device to the target static register corresponding to the command field. In the second mode, the first device is the upstream device, and the shift register outputs the input data from the upstream device to the downstream device.

2. The circuit for a serial peripheral interface based on a beamforming chip according to claim 1, characterized in that, The circuit also includes a static register to be transmitted; In the second mode, the data of the static register to be transferred is input to the shift register so that the data of the static register to be transferred can be shifted and output to the downstream device in the next shift operation.

3. The circuit for a serial peripheral interface based on a beamforming chip according to claim 2, characterized in that, The circuit also includes a first multiplexer MUX1: The first input terminal of the first multiplexer MUX1 is connected to the output terminal of the shift register, the second input terminal is connected to the output terminal of the static register to be transmitted, and the output terminal is connected to the data output unit. Under the first mode read operation, the first multiplexer MUX1 outputs the data of the static register to be transmitted; In the second mode, the first multiplexer MUX1 outputs the data from the shift register, wherein the data portion of the shift register comes from the static register to be transmitted.

4. The circuit for a serial peripheral interface based on a beamforming chip according to claim 3, characterized in that, The circuit also includes a second multiplexer MUX2: The first input of the second multiplexer MUX2 is connected to the output of the control bit of the shift register, the second input is connected to the output of the static register to be transmitted, and the output is connected to the input of the data bit of the shift register. In the first mode, the second multiplexer MUX2 outputs the input data from the master device to the data bits of the shift register; In the second mode, the second multiplexer MUX2 first outputs the input data from the upstream device to the data bits of the shift register, and after the shifting process is completed, outputs the data from the static register to be transmitted to the data bits of the shift register.

5. The circuit for a serial peripheral interface based on a beamforming chip according to claim 4, characterized in that, The second multiplexer MUX2 is controlled by the mode selection input signal and the chip select signal; The mode selection input signal is used to switch the response of the second multiplexer MUX2 in the first mode and the second mode; The chip select signal is used to control the input of the input data in the first mode, and to control the sequential input of the input data and the data of the static register to be transferred in the second mode.

6. The circuit for a serial peripheral interface based on a beamforming chip according to claim 5, characterized in that, The circuit also includes a third multiplexer, MUX3: The first input terminal of the third multiplexer MUX3 is connected to a first clock signal, the second input terminal is connected to a high level, and the output terminal is connected to the clock input of the data bits of the shift register; wherein, the first clock signal is the clock signal of the control bits of the shift register; The third multiplexer MUX3 is controlled by the chip select signal and is used to control the clock input of the first clock signal applied to the data bits of the shift register through the third multiplexer MUX3.

7. The circuit for a serial peripheral interface based on a beamforming chip according to claim 6, characterized in that, The circuit also includes a delay unit: The input of the delay unit is connected to the output of the third multiplexer MUX3, and the output is connected to the clock input of the data bits of the shift register.

8. The circuit for a serial peripheral interface based on a beamforming chip according to claim 3, characterized in that, The circuit also includes a secondary shift register and a fourth multiplexer MUX4: The input of the secondary shift register is connected to the output of the static register to be transmitted, and the output is connected to the second input of the fourth multiplexer MUX4, for storing data from the static register to be transmitted in the second mode; The first input of the fourth multiplexer MUX4 is connected to the output of the shift register, the second input is connected to the output of the secondary shift register, and the output is connected to the first input of the first multiplexer MUX1, for responding to the second mode to output the data of the shift register and the data of the secondary shift register sequentially.

9. The circuit for a serial peripheral interface based on a beamforming chip according to claim 8, characterized in that, The fourth multiplexer MUX4 is controlled by an output path control signal to switch between outputting data from the shift register and data from the secondary shift register.

10. The circuit for a serial peripheral interface based on a beamforming chip according to any one of claims 1-9, characterized in that, The first mode is the physical addressing mode, and the second mode is the daisy chain mode.

11. A beamforming chip, characterized in that, The beamforming chip includes a circuit based on a serial peripheral interface as described in any one of claims 1-10.

12. A radio frequency front end, characterized in that, The radio frequency front end includes the beamforming chip as described in claim 11.

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