Bit depth extension circuit for silicon-based liquid crystal display, display device, and driving method

Abstract

The application relates to a bit depth extension circuit capable of improving display effect, a display device and a driving method. The bit depth extension circuit comprises a bit extension control line used for transmitting a normal mode signal or an extension mode signal; a first shift register unit connected with the bit extension control line and used for sequentially outputting 2N first sampling signals when the extension mode signal is received from the bit extension control line; N storage units respectively connected with the shift register unit and a data line; each storage unit is used for corresponding to receive 2 first sampling signals, and obtaining and saving M-bit pixel data from the data line according to each received first sampling signal; N latches are connected with the N storage units one by one and are respectively connected with a latch signal line; each latch is used for combining M-bit pixel data twice saved by the storage unit corresponding to the latch into one 2M-bit pixel data and performing latching when a latch signal is received from the latch signal line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a bit depth extension circuit of a liquid crystal on silicon (LCOS) display, a display device and a driving method. BACKGROUND

[0002] Liquid crystal on silicon (LCOS) is a kind of matrix liquid crystal display device based on reflection mode and very small in size, which is often used in some occasions with strict requirements on volume. Such occasions sometimes need to compress wiring resources, resulting in a decrease in the bit width of transmitted data.

[0003] The driving scheme of LCOS is to store each pixel data in turn, and after storing a row of pixel data, to perform digital-to-analog conversion and output to the corresponding row to drive the pixels of the row to emit light. Different pixel data correspond to different light emitting brightness.

[0004] When the bit width of transmitted data decreases, the image level in brightness and color decreases, the gray scale decreases, and the display effect is poor. SUMMARY

[0005] Therefore, it is necessary to provide a bit depth extension circuit of a liquid crystal on silicon display, a display device and a driving method capable of improving the display effect.

[0006] In a first aspect, a bit depth extension circuit is provided, which comprises:

[0007] a bit extension control line for transmitting a normal mode signal or an extension mode signal;

[0008] a first shift register unit connected with the bit extension control line, for sequentially outputting 2N first sampling signals when the extension mode signal is received from the bit extension control line, N being the number of horizontal pixels of the liquid crystal on silicon display;

[0009] N storage units respectively connected with the shift register unit and a data line; each storage unit is configured to correspondingly receive two first sampling signals, and to obtain and save M-bit pixel data from the data line according to each received first sampling signal, M being the bit width of the data line;

[0010] N latches connected with the N storage units one by one and respectively connected with a latch signal line; each latch is configured to combine and latch 2M-bit pixel data from the two saved M-bit pixel data of the corresponding storage unit of the latch when a latch signal is received from the latch signal line.

[0011] In a second aspect, a display device is provided, which comprises the bit depth extension circuit provided in the first aspect.

[0012] In a third aspect, a driving method is provided, which comprises the following steps:

[0013] transmitting a normal mode signal or an extension mode signal through a bit extension control line;

[0014] outputting 2N first sampling signals in sequence through a first shift register when the extension mode signal is received from the bit extension control line, N being the horizontal pixel number of the liquid crystal on silicon display;

[0015] controlling each of the N storage units to correspondingly receive 2 first sampling signals and to acquire and save M-bit pixel data from a data line according to each of the received first sampling signals, M being the bit width of the data line;

[0016] controlling each of the N latches to combine and latch 2M-bit pixel data from the twice saved M-bit pixel data of the corresponding storage unit of the latch when a latch signal is received from a latch signal line.

[0017] The bit depth extension circuit, the display device and the driving method can transmit a normal mode signal or an extension mode signal through a bit extension control line, output 2*N first sampling signals in sequence through a first shift register when the extension mode signal is received from the bit extension control line, correspondingly receive 2 first sampling signals by each of the N storage units, acquire and save M-bit pixel data from a data line according to each of the received first sampling signals, and combine and latch 2M-bit pixel data from the twice saved M-bit pixel data of the corresponding storage unit of the latch when a latch signal is received from a latch signal line. In this way, the bit width of the pixel data can be doubled without increasing the wiring, for example, the bit width of the data transmitted by the line in one time is M-bit, and the bit width of the pixel data can be extended to 2*M-bit. The data line with a lower bit width is used to realize the transmission of data with a higher bit width, which is particularly suitable for saving the wiring resources of the micro display chip such as LCOS, and can increase the color bit depth of the pixel, improve the level of brightness and color, enrich the gray scale performance of the image, improve the gray scale of the image, and improve the display effect of the image. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0019] Figure 1 A structure diagram of a bit-depth extension circuit provided in an embodiment;

[0020] Figure 2 A structure diagram of a bit-depth extension circuit provided in an embodiment; Figure 1 A connection diagram of a first shift register unit in an extension mode in the embodiment;

[0021] Figure 3 A connection diagram of a first shift register unit in a normal mode in the embodiment; Figure 1

[0022] Figure 4 A structure diagram of a first shift register unit in the embodiment; Figure 1

[0023] Figure 5 A structure diagram of another bit-depth extension circuit provided in an embodiment;

[0024] Figure 6 A structure diagram of another bit-depth extension circuit provided in an embodiment; Figure 5 A structure diagram of a part of the bit-depth extension circuit in the embodiment;

[0025] Figure 7 A structure diagram of another bit-depth extension circuit provided in an embodiment;

[0026] Figure 8 A structure diagram of a timing control circuit in the embodiment; Figure 7

[0027] A flow chart of a driving method provided in an embodiment. Figure 9 Explanation of reference numerals:

[0028] 100-bit width extension circuit;

[0029] 10-first shift register unit, 11-first shift register, 12-second shift register, 13-first multiplexer;

[0030] 20-storage unit, 21-first memory, 22-second memory;

[0031] 30-latch;

[0032] 40-digital-to-analog converter;

[0033] 50-timing control circuit, 51-counter, 52-start signal generator, 53-latch signal generator;

[0034] 60-output buffer circuit;

[0035] 80-second multiplexer;

[0036] ​​​

[0037] 90 - second shift register unit, 91 - third shift register. DETAILED DESCRIPTION

[0038] For the purpose of understanding the present application, the present application will be described in more detail with reference to the attached drawings. The embodiments of the present application are shown in the drawings. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0040] It is to be understood that the terms "first", "second", and etc. can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor can be called a second resistor, and similarly, a second resistor can be called a first resistor, without departing from the scope of the present application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0041] It is to be understood that "connection" in the following embodiments, if the circuits, modules, units, etc. connected to each other have the transmission of electrical signals or data, it should be understood as "electrically connected", "communicatively connected" and the like.

[0042] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It is also to be understood that the term "comprising" or "including" or "having" and the like, specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0043] Reference Figure 1In an embodiment of the present application, a bit depth extension circuit 100 is provided, which comprises a bit extension control line, a first shift register unit 10, N storage units 20 and N latches, N being a positive integer. The bit extension control line is used to transmit a normal mode signal or an extension mode signal. The first shift register unit 10 is connected to the bit extension control line and is used to sequentially output 2N first sampling signals when the extension mode signal is received from the bit extension control line, N being the number of horizontal pixels of a liquid crystal on silicon display. The N storage units 20 are respectively connected to the shift register unit 10 and a data line, and each storage unit 20 is used to correspondingly receive two first sampling signals and to obtain and save M-bit pixel data from the data line when each first sampling signal is received, M being the bit width of the data line. The N latches 30 are respectively connected to the N storage units 20 in one-to-one correspondence and are respectively connected to a latch signal line. Each latch 30 is used to combine the M-bit pixel data twice saved by the storage unit 20 corresponding to the latch 30 into one 2M-bit pixel data and to latch the 2M-bit pixel data when a latch signal is received from the latch signal line.

[0044] The bit depth extension circuit described above transmits a normal mode signal or an extension mode signal through the bit extension control line, the first shift register unit sequentially outputs 2*N first sampling signals when the extension mode signal is received from the bit extension control line, each storage unit correspondingly receives two first sampling signals and obtains and saves M-bit pixel data from the data line according to each first sampling signal received, and each latch combines the M-bit pixel data twice saved by the storage unit corresponding to the latch into one 2M-bit pixel data and latches the 2M-bit pixel data when a latch signal is received from the latch signal line. In this way, the bit width of the pixel data can be doubled without increasing the wiring, for example, if the bit width of the data transmitted by the line at a time is M bits, the bit width of the pixel data can be expanded to 2*M bits, the data line with a lower bit width is used to realize the transmission of data with a higher bit width, which is particularly suitable for saving the wiring resources of a micro display chip such as an LCOS, increasing the color bit depth of the pixels, increasing the level of brightness and color, enriching the gray scale performance of the image, improving the gray scale of the image, and improving the display effect of the image.

[0045] Moreover, the bit depth extension circuit is realized by circuit design, and the implementation cost is low.

[0046] Exemplarily, the high-level signal is the extension mode signal, and the low-level signal is the normal mode signal; or, the high-level signal is the normal mode signal, and the low-level signal is the extension mode signal.

[0047] As Figure 1As shown, in some embodiments, each storage unit 20 includes a first memory 21 and a second memory 22. The first memory 21 is connected to the first shift register unit 10 and the data line, respectively, and is used to receive the first first sampling signal among two first sampling signals, and to acquire and save the first M bits of pixel data from the data line according to the received first sampling signal. The second memory 22 is connected to the first shift register unit 10 and the data line, respectively, and is used to receive the second first sampling signal among two first sampling signals, and to acquire and save the last M bits of pixel data from the data line according to the received first sampling signal.

[0048] Specifically, the first latch is connected to the first memory 21 and the second memory 22 in the first storage unit 20, and combines the data of the first memory 21 and the second memory 22 in the first storage unit 20.

[0049] The second latch is connected to the first memory 21 and the second memory 22 in the second storage unit 20, and combines the data of the first memory 21 and the second memory 22 in the second storage unit 20.

[0050] The i-th latch is connected to the first memory 21 and the second memory 22 in the i-th memory cell 20, and combines the data of the first memory 21 and the second memory 22 in the i-th memory cell 20.

[0051] The Nth latch is connected to the first memory 21 and the second memory 22 in the Nth memory cell 20, and combines the data of the first memory 21 and the second memory 22 in the Nth memory cell 20.

[0052] like Figure 1 As shown, in some embodiments, the first shift register unit 10 includes N first shift registers 11 and N second shift registers 12. The outputs of the N first shift registers 11 are connected one-to-one with the N first memories 21, and the outputs of the N second shift registers 12 are connected one-to-one with the N second shift registers 22. The input of the first first shift register 11 is connected to the start signal line. (See reference...) Figure 2 N first shift registers 11 and N second shift registers 12 are connected alternately in sequence.

[0053] A second shift register 12 is provided between two adjacent first shift registers 11, and a first shift register 11 is provided between two adjacent second shift registers 12.

[0054] Specifically, the input terminal of the i+1th first shift register 11 is connected with the output terminal of the ith second shift register 12, the output terminal of the ith first shift register 11 is connected with the input terminal of the ith second shift register 12, the output terminal of the Nth first shift register 11 is connected with the input terminal of the Nth second shift register 12, 1≤i≤N-1 and i is a positive integer.

[0055] In the extension mode, the start signal on the start signal line inputs the 1st first shift register 11, and the 1st first shift register 11 outputs the 1st sampling signal according to the start signal.

[0056] The 1st sampling signal is input into the 1st second shift register 12 and the first memory 21 in the 1st storage unit 20 respectively. The first memory 21 in the 1st storage unit 20 acquires and stores the pixel data according to the 1st sampling signal. The 1st second shift register 12 outputs the 2nd sampling signal according to the 1st sampling signal.

[0057] The 2nd sampling signal is input into the 2nd first shift register 11 and the first memory 21 in the 2nd storage unit 20 respectively. The first memory 21 in the 2nd storage unit 20 acquires and stores the pixel data according to the 2nd sampling signal, and the 2nd first shift register 11 outputs the 3rd sampling signal according to the 2nd sampling signal.

[0058] The 3rd sampling signal is input into the 2nd second shift register 12 and the first memory 21 in the 2nd storage unit 20 respectively. The first memory 21 in the 2nd storage unit 20 acquires and stores the pixel data according to the 3rd sampling signal. The 2nd second shift register 12 outputs the 4th sampling signal according to the 3rd sampling signal.

[0059] The 2N-1th sampling signal is input into the Nth second shift register 12 and the first memory 21 in the Nth storage unit 20. The first memory 21 in the Nth storage unit 20 acquires and stores the pixel data according to the 2N-1th sampling signal. The Nth second shift register 12 outputs the 2Nth sampling signal according to the 2N-1th sampling signal.

[0060] The 2Nth sampling signal is input into the second memory 22 in the Nth storage unit 20, and the second memory 22 in the Nth storage unit 20 acquires and stores the pixel data according to the 2Nth sampling signal.

[0061] In the first implementation, the N first shift registers 10 are further configured to output N second sampling signals respectively when the normal mode signal is received from the bit expansion control line. Each first memory 21 is further configured to receive one second sampling signal and obtain and save the first M-bit pixel data from the data line according to the received second sampling signal. Each second memory 22 is further configured to store the second M-bit preset data when the first memory 21 receives the second sampling signal. Each latch 30 is further configured to combine the first M-bit pixel data and the second M-bit preset data saved in the same storage unit 20 into one 2M-bit pixel data and latch the 2M-bit pixel data when the latch signal is received from the latch signal line.

[0062] In the first implementation, the N first shift registers 10 are further configured to output N second sampling signals respectively when the normal mode signal is received from the bit expansion control line. Each first memory 21 is further configured to receive one second sampling signal and obtain and save the first M-bit pixel data from the data line according to the received second sampling signal. Each second memory 22 is further configured to store the second M-bit preset data when the first memory 21 receives the second sampling signal. Each latch 30 is further configured to combine the first M-bit pixel data and the second M-bit preset data saved in the same storage unit 20 into one 2M-bit pixel data and latch the 2M-bit pixel data when the latch signal is received from the latch signal line. Figure 3 , the N first shift registers 10 are connected in sequence.

[0063] The preset data can be M-bit 0.

[0064] Specifically, the input end of the i+1th first shift register 11 is connected with the output end of the ith first shift register 11, 1≤i≤N-1 and i is a positive integer.

[0065] In the normal mode, the start signal on the start signal line is input into the 1st first shift register 11. The 1st first shift register 11 outputs the 1st sampling signal.

[0066] The 1st sampling signal is input into the 2nd first shift register 11 and the first memory 21 in the 1st storage unit 20 respectively. The first memory 21 in the 1st storage unit 20 obtains and stores the pixel data according to the 1st sampling signal, and the 2nd first shift register 11 outputs the 2nd sampling signal according to the 1st sampling signal.

[0067] The 2nd sampling signal is input into the 3rd first shift register 11 and the first memory 21 in the 2nd storage unit 20 respectively. The first memory 21 in the 2nd storage unit 20 obtains and stores the pixel data according to the 2nd sampling signal, and the 3rd first shift register 11 outputs the 3rd sampling signal according to the 2nd sampling signal.

[0068] The N-1th sampling signal is input into the Nth first shift register 11 and the first memory 21 in the N-1th storage unit 20 respectively. The first memory 21 in the N-1th storage unit 20 obtains and stores the pixel data according to the N-1th sampling signal, and the Nth first shift register 11 outputs the Nth sampling signal according to the N-1th sampling signal.

[0069] The Nth sampling signal is input to the first memory 21 in the Nth storage unit 20. The first memory 21 in the Nth storage unit 20 acquires pixel data and stores it according to the Nth sampling signal.

[0070] In the above embodiments, the first shift register unit includes N first shift registers and N second shift registers. In normal mode, the N first shift registers are connected sequentially to output N sampled signals sequentially. In extended mode, the N first shift registers and N second shift registers are connected alternately to output 2N sampled signals sequentially. Furthermore, the N first shift registers are connected one-to-one with N first memories, and the N second shift registers are connected one-to-one with N second memories. Thus, in normal mode, the first memories acquire and store pixel data based on the corresponding second sampled signal; in extended mode, the first memories and second memories acquire and store pixel data based on the corresponding first sampled signal, respectively.

[0071] See Figure 4 For example, the first shift register unit 10 further includes N first multiplexers 13. The control terminal A of each first multiplexer 13 is connected to the bit extension control line. The i-th first multiplexer 13 is connected in series between the output terminal of the i-th first shift register 11 and the input terminal of the i-th second shift register 12. The input terminal B of the i-th first multiplexer 13 is connected to the output terminal of the i-th first shift register 11. The first output terminal C of the i-th first multiplexer 13 is connected to the input terminal of the i-th second shift register 12, where i ≤ N and i is a positive integer. When i ≤ N-1, the second output terminal D of the i-th first multiplexer 13 is connected to the input terminal of the (i+1)-th first shift register 11. The N-th first multiplexer 13 is connected in series between the output terminal of the N-th first shift register 11 and the input terminal of the N-th second shift register 12, where 1 ≤ i ≤ N-1 and i is a positive integer.

[0072] Specifically, when the control terminal A of the first multiplexer 13 receives an extended mode signal, the input terminal B of the first multiplexer 13 is connected to the first output terminal C of the first multiplexer 13. When the control terminal A of the first multiplexer 13 receives a normal mode signal, the input terminal B of the first multiplexer 13 is connected to the second output terminal D of the first multiplexer 13.

[0073] For example, the output of the Nth second shift register 12 is left floating and not connected to the input of the first shift register 11.

[0074] Specifically, the output terminal of the first first shift register 11 is connected with the input terminal of the first first multiplexer 13, the first output terminal of the first first multiplexer 13 is connected with the input terminal of the first second shift register 12, the second output terminal of the first first multiplexer 13 is connected with the input terminal of the second first shift register 11, and the output terminal of the first second shift register 12 is also connected with the input terminal of the second first shift register 11.

[0075] The output terminal of the second first shift register 11 is connected with the input terminal of the second first multiplexer 13, the first output terminal of the second first multiplexer 13 is connected with the input terminal of the second second shift register 12, the second output terminal of the second first multiplexer 13 is connected with the input terminal of the third first shift register 11, and the output terminal of the second second shift register 12 is also connected with the input terminal of the third first shift register 11.

[0076] The output terminal of the i-th first shift register 11 is connected with the input terminal of the i-th first multiplexer 13, the first output terminal of the i-th first multiplexer 13 is connected with the input terminal of the i-th second shift register 12, the second output terminal of the i-th first multiplexer 13 is connected with the input terminal of the (i+1)-th first shift register 11, and the output terminal of the i-th second shift register 12 is also connected with the input terminal of the (i+1)-th first shift register 11.

[0077] The output terminal of the N-th first shift register 11 is connected with the input terminal of the N-th first multiplexer 13, the first output terminal of the N-th first multiplexer 13 is connected with the input terminal of the N-th second shift register 12, and the second output terminal of the N-th first multiplexer 13 is not connected.

[0078] In the normal mode, the input terminal and the second output terminal of each first multiplexer 13 are connected, and the N first shift registers 11 are connected in turn. Specifically, the input terminal and the second output terminal of the first first multiplexer 13 are connected, and the output terminal of the first first shift register 11 is connected with the input terminal of the second first shift register 11. The input terminal and the second output terminal of the second first multiplexer 13 are connected, and the output terminal of the second first shift register 11 is connected with the input terminal of the third first shift register 11. The input terminal and the second output terminal of the i-th first multiplexer 13 are connected, and the output terminal of the i-th first shift register 11 is connected with the input terminal of the (i+1)-th first shift register 11. The input terminal and the second output terminal of the N-th first multiplexer 13 are connected, and the output terminal of the N-th first shift register 11 is not connected.

[0079] In the extension mode, the input of each first multiplexer 13 is connected with the first output, at this time, the N first shift registers 11 and the N second shift registers 12 are connected alternately. Specifically, the input of the first first multiplexer 13 is connected with the first output, the output of the first first shift register 11 is connected with the input of the first second shift register 12. The output of the first second shift register 12 is connected with the input of the second first shift register 11. The input of the second first multiplexer 13 is connected with the second output, the output of the second first shift register 11 is connected with the input of the second second shift register 12. The output of the second second shift register 12 is connected with the input of the third first shift register 11. The input of the i-th first multiplexer 13 is connected with the second output, the output of the i-th first shift register 11 is connected with the input of the i-th second shift register 12. The output of the i-th second shift register 12 is connected with the input of the (i+1)-th first shift register 11. The input of the N-th first multiplexer 13 is connected with the second output, the output of the N-th first shift register 11 is connected with the input of the N-th second shift register 12.

[0080] In the above embodiment, the shift register unit further comprises N first multiplexers, the N first multiplexers correspond to the N first shift registers and the N second shift registers one by one, the input of the first multiplexer is connected with the output of the corresponding first shift register, and the first output of the first multiplexer is connected with the input of the corresponding second shift register. In this way, in the extension mode, the input of the first multiplexer is connected with the first output, so that the output of the first shift register is connected with the input of the corresponding second shift register, and the N first shift registers and the N second shift registers can be connected alternately. In the normal mode, the input of the first multiplexer is connected with the second output, so that the output of the first shift register is connected with the input of the adjacent first shift register, and the N first shift registers can be connected in sequence.

[0081] Reference is made to Figure 5In the second implementation, the bit depth extension circuit 100 further comprises a second shift register unit 90, which corresponds to output N second sampling signals when receiving a normal mode signal from the bit extension control line. Each first memory 21 is further connected to the second shift register unit 90, for receiving 1 second sampling signal, and obtaining and storing the first M-bit pixel data from the data line according to the received second sampling signal. Each second memory 22 is further configured to store the second M-bit preset data when the first memory 21 receives the second sampling signal. Each latch 30 is further configured to combine the first M-bit pixel data and the second M-bit preset data stored in the same storage unit 20 into one 2M-bit pixel data and latch when receiving the latch signal from the latch signal line.

[0082] As shown in the example, Figure 5 The second shift register unit 90 comprises N third shift registers 91, the output ends of the N third shift registers 91 are connected to the N first memories 21 one by one, and the N third shift registers 91 are connected in sequence.

[0083] Referring to Figure 6 The bit depth extension circuit 100 further comprises a second multiplexer 80, the control end E of the second multiplexer 80 is connected to the bit extension control line, the second multiplexer 80 is connected in series between the start signal line and the input end of the first first shift register 11, the input end F of the second multiplexer 80 is connected to the start signal line, the first output end G of the second multiplexer 80 is connected to the input end of the first first shift register 11, and the second output end H of the second multiplexer 80 is connected to the input end of the first third shift register 91.

[0084] When the control end E of the second multiplexer 80 receives the extension mode signal, the input end F of the second multiplexer 80 is connected to the first output end G of the second multiplexer 80. When the control end E of the second multiplexer 80 receives the normal mode signal, the input end F of the second multiplexer 80 is connected to the second output end H of the second multiplexer 80.

[0085] In the normal mode, the start signal on the start signal line is input to the first third shift register 14. The first third shift register 14 outputs the first sampling signal.

[0086] The first sampling signal is input to the second third shift register 14 and the first memory 21 in the first storage unit 20, respectively. The first memory 21 in the first storage unit 20 obtains and stores the pixel data according to the first sampling signal, and the second third shift register 14 outputs the second sampling signal according to the first sampling signal.

[0087] The second sampling signal is inputted into the third shift register 14 and the first memory 21 in the second storage unit 20 respectively, the first memory 21 in the second storage unit 20 acquires and stores the pixel data according to the second sampling signal, and the third shift register 14 outputs the third sampling signal according to the second sampling signal.

[0088] The N-1th sampling signal is inputted into the Nth first shift register 11 and the first memory 21 in the N-1th storage unit 20 respectively, the first memory 21 in the N-1th storage unit 20 acquires and stores the pixel data according to the N-1th sampling signal, and the Nth first shift register 11 outputs the Nth sampling signal according to the N-1th sampling signal.

[0089] The Nth sampling signal is inputted into the first memory 21 in the Nth storage unit 20, and the first memory 21 in the Nth storage unit 20 acquires and stores the pixel data according to the Nth sampling signal.

[0090] In the extended mode, the start signal on the start signal line is inputted into the first first shift register 11, and the subsequent process is as described above, which will not be described in detail here.

[0091] In the above embodiment, the bit depth expansion circuit further comprises a second multiplexer and a second shift register unit, the first output end of the second multiplexer is connected with the input end of the first third shift register, the start signal line can be connected with the second shift register unit in the normal mode, the second shift register unit outputs N second sampling signals in sequence, so that the N first memories acquire and store the pixel data according to the corresponding second sampling signals. The second output end of the second multiplexer is connected with the input end of the first first shift register, the start signal line can be connected with the first shift register unit in the extended mode, the first shift register unit outputs 2N first sampling signals in sequence, so that the N first memories and the N second memories acquire and store the pixel data according to the corresponding first sampling signals.

[0092] In summary, the second memory stores the preset data in the normal mode, so that the data combination range of the first memory and the second memory stored in the normal mode and the extended mode is relatively small, which can always maintain a high brightness and contrast, and further improve the display effect of the image.

[0093] In practical applications, the data stored in the first memory 21 and the second memory 22 can be cleared first, and then the corresponding memory is selected for updating according to the sampling signal. Specifically, in the normal mode, the corresponding first memory 21 is selected to update the stored data according to the sampling signal; the second memory 22 has no corresponding sampling signal, and the stored data is not updated and remains cleared. In the extended mode, the corresponding first memory 21 or the second memory 22 is selected to update the stored data according to the sampling signal.

[0094] Referring to Figure 7 In some embodiments, the bit depth extension circuit 100 further comprises a digital-to-analog converter 40 connected with the N latches 30 respectively, for converting the pixel data latched by the N latches 30 into analog signals simultaneously.

[0095] Referring to Figure 8 In some embodiments, the bit depth extension circuit 100 further comprises a timing control circuit 50 connected with the row synchronization signal line, the clock signal line, the start signal line and the latch signal line respectively, for generating the start signal and outputting to the start signal line, and generating the latch signal and outputting to the latch signal line according to the clock signal on the clock signal line and the row synchronization signal on the row synchronization signal line.

[0096] The row synchronization signal represents the beginning of a row of data.

[0097] In the above embodiments, the bit depth extension circuit further comprises a timing control circuit, which outputs a start signal to the shift register unit according to the clock signal and the row synchronization signal, and the shift register unit can output a sampling signal according to the start signal. The timing control circuit also outputs a latch signal to the N latches according to the clock signal and the row synchronization signal, and the latches can obtain the data stored in the first memory and the second memory in the corresponding storage unit and latch according to the latch signal.

[0098] Referring to Figure 8 For example, the timing control circuit 50 comprises a counter 51, a start signal generator 52 and a latch signal generator 53. The counter 51 is connected with the row synchronization signal line and the clock signal line respectively, for clearing when receiving the row synchronization signal, and adding 1 when receiving the clock signal. The start signal generator 52 is connected with the counter 51, the clock signal line and the start signal line respectively, for generating the start signal and outputting to the start signal line when receiving the clock signal, if the counter 51 is 0. The latch signal generator 53 is connected with the counter 51, the clock signal line and the latch signal line respectively, for generating the latch signal and outputting to the latch signal line when receiving the clock signal, if the value of the counter 51 is N or 2N.

[0099] Specifically, when the bit extension control line receives the normal mode signal, the latch signal generator 53 generates the latch signal when the value of the counter 51 is N; when the bit extension control line receives the extension mode signal, the latch signal generator 53 generates the latch signal when the value of the counter 51 is 2N. That is, N is a preset count value corresponding to the normal mode signal received by the bit extension control line, and 2N is a preset count value corresponding to the bit extension mode signal received by the bit extension control line.

[0100] In the above embodiment, the timing control circuit includes a counter, a start signal generator and a latch signal generator. The counter is cleared when receiving the line synchronization signal and is incremented by one when receiving the clock signal. The value of the counter can be used to determine the stages of data processing of a row, for example, the value of the counter being 0 indicates the start of data processing, and the value of the counter being N or 2N indicates the end of data processing. The start signal generator is connected to the counter and can output a start signal when the value of the counter is 0 to control the shift register unit to output a sampling signal. The latch signal generator is connected to the counter and can output a latch signal when the value of the counter is N or 2N to control the latch to obtain and latch the data stored in the first memory and the second memory of the corresponding storage unit.

[0101] Referring to Figure 7 In some embodiments, the bit depth extension circuit 100 further includes an output buffer circuit 60 connected to the digital-to-analog converter 40 for buffering the analog signal.

[0102] In the above embodiment, the display driving apparatus further includes an output buffer circuit connected to the digital-to-analog converter, which can buffer the analog signal to increase the load capacity of the analog signal.

[0103] Based on the same inventive concept, an embodiment of the present application further provides a display device (not shown in the figure) comprising the bit depth extension circuit 100 provided by the above embodiment.

[0104] Referring to Figure 9 Based on the same inventive concept, an embodiment of the present application further provides a driving method, comprising the following steps:

[0105] In step S902, a normal mode signal or an extension mode signal is transmitted through a bit extension control line. When the normal mode signal is transmitted, steps S908 and S910 are performed; when the extension mode signal is transmitted, steps S904 and S906 are performed.

[0106] In step S904, 2N first sampling signals are sequentially output by the first shift register when the extension mode signal is received through the bit extension control line, N being the number of horizontal pixels of the liquid crystal display.

[0107] Step S906, each of the N storage units is controlled to correspondingly receive two first sampling signals, and to acquire and save M-bit pixel data from the data line according to each of the received first sampling signals, M being the bit width of the data line.

[0108] Step S908, the first shift register or the second shift register is controlled to sequentially output the N first sampling signals when the normal mode signal is received from the bit expansion control line.

[0109] Step S910, each of the N storage units is controlled to correspondingly receive one second sampling signal, and to acquire and save M-bit pixel data from the data line according to the received second sampling signal, and to store M-bit preset data.

[0110] Step S912, each of the N latches is controlled to combine the twice saved M-bit pixel data of the corresponding storage unit into one 2M-bit pixel data and latch when the latch signal is received from the latch signal line. The step S912 is performed after the step S906 or the step S910.

[0111] Step S914, the digital-to-analog converter is controlled to simultaneously convert the N latched data into analog signals.

[0112] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0113] Each of the technical features of the above-described embodiments can be combined arbitrarily. In order to make the description simple, each of the technical features in the above-described embodiments is not described in all possible combinations, however, as long as the combination of the technical features does not contradict, it should be considered as the scope of the present specification.

[0114] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the patent scope of the present application. It should be noted that, for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A bit depth extension circuit for a silicon-based liquid crystal display, characterized in that, The bit depth extension circuit includes: Bit extension control lines are used to transmit normal mode signals or extended mode signals; The first shift register unit is connected to the bit extension control line and is used to sequentially output 2N first sampling signals when the extended mode signal is received from the bit extension control line, where N is the number of horizontal pixels of the silicon-based liquid crystal display. N storage units are respectively connected to the shift register unit and the data line; each storage unit is used to receive two first sampling signals, and to obtain and save M bits of pixel data from the data line according to each received first sampling signal, where M is the bit width of the data line; N latches are connected one-to-one with the N storage units and are respectively connected to the latch signal line; each latch is used to combine the M-bit pixel data stored twice in the storage unit corresponding to the latch into a 2M-bit pixel data and latch it when it receives a latch signal from the latch signal line. Each of the aforementioned storage units includes: a first memory, connected to the first shift register unit and the data line respectively, for receiving the first of two first sampling signals, and acquiring and storing the first M pixel data from the data line according to the received first sampling signal; and a second memory, connected to the first shift register unit and the data line respectively, for receiving the second of two first sampling signals, and acquiring and storing the last M pixel data from the data line according to the received first sampling signal. The first shift register unit includes: N first shift registers, the outputs of which are connected one-to-one with the N first memories; and N second shift registers, the outputs of which are connected one-to-one with the N second memories; wherein, the input of the first first shift register is connected to the start signal line, and the N first shift registers and the N second shift registers are connected alternately in sequence; The first shift register unit further includes: N first multiplexers, the control terminal of each first multiplexer being connected to the bit extension control line, the i-th first multiplexer being connected in series between the output terminal of the i-th first shift register and the input terminal of the i-th second shift register, the input terminal of the i-th first multiplexer being connected to the output terminal of the i-th first shift register, the first output terminal of the i-th first multiplexer being connected to the input terminal of the i-th second shift register, and the second output terminal of the i-th first multiplexer being connected to the (i+1)-th bit extension control line. The input terminal of the first shift register is connected, and the Nth first multiplexer is connected in series between the output terminal of the Nth first shift register and the input terminal of the Nth second shift register, where 1≤i≤N-1 and i is a positive integer; wherein, when the control terminal of the first multiplexer receives the extended mode signal, the input terminal of the first multiplexer is connected to the first output terminal of the first multiplexer; when the control terminal of the first multiplexer receives the normal mode signal, the input terminal of the first multiplexer is connected to the second output terminal of the first multiplexer.

2. The bit depth extension circuit according to claim 1, characterized in that, The N first shift registers are also used to output N second sampling signals respectively when the normal mode signal is received from the bit extension control line; Each of the first memories is further configured to receive one of the second sampling signals, and to acquire and save the first M pixel data from the data line according to the received second sampling signal; Each of the second memories is further configured to store the next M bits of preset data when the first memory receives the second sampling signal; Each of the latches is further configured to, upon receiving a latch signal from the latch signal line, combine the first M bits of pixel data and the last M bits of preset data stored in the same storage unit into a 2M-bit pixel data and latch it.

3. The bit depth extension circuit according to claim 1, characterized in that, The bit depth extension circuit also includes: The second shift register unit is connected to the bit extension control line and is used to output N second sampling signals respectively when the normal mode signal is received from the bit extension control line. Each of the first memories is also connected to a second shift register unit, for receiving one second sampling signal and for acquiring and storing the first M pixel data from the data line according to the received second sampling signal; Each of the second memories is further configured to store the next M bits of preset data when the first memory receives the second sampling signal; Each of the latches is further configured to, upon receiving a latch signal from the latch signal line, combine the first M bits of pixel data and the last M bits of preset data stored in the same storage unit into a 2M-bit pixel data and latch it.

4. The bit depth extension circuit according to claim 3, characterized in that, The second shift register unit includes: N third shift registers, the outputs of the N third shift registers are connected one-to-one with the N first memories, and the N third shift registers are connected sequentially; The bit depth extension circuit also includes: A second multiplexer, the control terminal of which is connected to the bit extension control line, is connected in series between the start signal line and the input of the first first shift register, the input of which is connected to the start signal line, the first output of which is connected to the input of the first first shift register, and the second output of which is connected to the input of the first third shift register; Specifically, when the control terminal of the second multiplexer receives the extended mode signal, the input terminal of the second multiplexer is connected to the first output terminal of the second multiplexer; when the control terminal of the second multiplexer receives the normal mode signal, the input terminal of the second multiplexer is connected to the second output terminal of the second multiplexer.

5. The bit depth extension circuit according to claim 1, characterized in that, The bit depth extension circuit also includes: The timing control circuit is connected to the horizontal synchronization signal line, the clock signal line, the start signal line and the latch signal line respectively. It is used to generate a start signal and output it to the start signal line according to the clock signal on the clock signal line and the horizontal synchronization signal on the horizontal synchronization signal line, and to generate the latch signal and output it to the latch signal line. The timing control circuit includes: A counter, connected to the horizontal synchronization signal line and the clock signal line respectively, is used to clear the counter when the horizontal synchronization signal is received and to increment the counter when the clock signal is received. A start signal generator is connected to the counter, the clock signal line, and the start signal line respectively, and is used to generate the start signal and output it to the start signal line when the clock signal is received and the counter is 0. A latch signal generator is connected to the counter, the clock signal line, and the latch signal line respectively. When the clock signal is received, if the value of the counter reaches the same preset count value corresponding to the normal mode signal or bit extension mode signal received by the bit extension control line, the latch signal is generated and output to the latch signal line.

6. A display device, characterized in that, The display device includes a bit depth extension circuit as described in any one of claims 1 to 5.

7. A driving method, characterized in that, Implemented based on the bit depth extension circuit according to any one of claims 1-5; the driving method includes: Transmit normal mode signals or extended mode signals via bit extension control lines; When the extended mode signal is received from the bit extension control line, the first shift register sequentially outputs 2N first sampling signals, where N is the number of horizontal pixels of the silicon-based liquid crystal display. Each of the N storage units is controlled to receive two of the first sampling signals, and to acquire and save M bits of pixel data from the data line according to each of the received first sampling signals, where M is the bit width of the data line; Each of the N latches is controlled to combine the M-bit pixel data stored twice in the storage unit corresponding to the latch into a 2M-bit pixel data and latch it when the latch signal line receives a latch signal.

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