Analog-to-digital conversion system and conversion method using the same

Abstract

An analog-to-digital (ADC) conversion system and a conversion method using the ADC system are provided. The system's slicing unit generates a sliced ​​signal. When the sliced ​​signal is in a first logic state, the system's Σ-Δ modulator converts a first summed signal into a first digital signal. The system's digital adder sums the first digital signal and multiple first carry signals to produce a first output result. The first summed signal is a superposition of the analog input signal and multiple first pseudo-random signals. When the sliced ​​signal is in a second logic state, the Σ-Δ modulator converts the inverted second summed signal into a second digital signal. The digital adder sums the inverted second digital signal and multiple second carry signals to produce a second output result. The second summed signal is a superposition of the analog input signal and multiple second pseudo-random signals. The system's digital decimation filter sums the first and second output results and averages them to obtain a digital output signal indicating the analog input signal.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to an analog-to-digital conversion system and method thereof. Background Technology

[0002] When a slowly varying analog signal is received at the input of a delta-axis analog-to-digital converter (ADC), such as a low-frequency or DC signal, a idle tone may be generated at the output. This idle tone sounds like a hissing noise, which is audible and unpleasant. Furthermore, the noise spikes that generate these idle tones may be incorrectly converted into digital values ​​by the delta-axis ADC, further increasing the conversion error. To eliminate or reduce the idle tone, traditional methods add a random signal to the analog signal. Since this random signal is random relative to the analog signal, it breaks the periodicity of the idle tone, thus eliminating or reducing it. However, due to the non-ideal nature of the delta-axis ADC and the effects of later layout parasitics, this random signal cannot be completely eliminated at the output of the delta-axis ADC, thus affecting the output result. Summary of the Invention

[0003] This invention provides a method for converting an analog input signal into a digital output signal using an analog-to-digital converter (ADC). The ADC includes a slicing unit, a multi-Δ modulator, a digital adder, and a digital decimation filter. The method includes: the slicing unit generating a slicing signal having a first logic state and a second logic state; and when the slicing signal is in the first logic state: the ADC generates multiple first pseudo-random signals; the ADC generates a first summation signal based on the multiple first pseudo-random signals and the analog input signal; the multi-Δ modulator converts the first summation signal into a first digital signal; the ADC generates multiple first carry signals, wherein the superposition signal of the multiple analog signals indicated by the multiple first carry signals is inverted with the superposition signal of the multiple first pseudo-random signals; and the digital adder sums the first digital signal and the multiple first carry signals to generate a first output result. The method further includes, when the chopped signal is in the second logic state: an analog-to-digital converter (ADC) generates multiple second pseudo-random signals; the ADC generates a second summation signal based on the multiple second pseudo-random signals and the analog input signal; a Σ-Δ modulator converts the inverted second summation signal into a second digital signal; the ADC generates multiple second carry signals, wherein the superposition signal of the multiple analog signals indicated by the multiple second carry signals is inverted from the superposition signal of the multiple second pseudo-random signals; and a digital adder sums the inverted second digital signal and the multiple second carry signals to generate a second output result. The method also includes a digital decimation filter averaging the sum of the first output result and the second output result to obtain a digital output signal indicating the analog input signal.

[0004] The present invention also provides an analog-to-digital conversion system. The system includes: a slicing unit for generating a slicing signal having a first logic state and a second logic state; and a Σ-Δ modulator for converting a first summed signal into a first digital signal when the slicing signal is in the first logic state; and converting an inverted second summed signal into a second digital signal when the slicing signal is in the second logic state, wherein the first summed signal is a superposition of an analog input signal and multiple first pseudo-random signals, and the second summed signal is a superposition of an analog input signal and multiple second pseudo-random signals, wherein both the multiple first pseudo-random signals and the multiple second pseudo-random signals are generated by the analog-to-digital conversion system. The system also includes a digital adder coupled to the digital adder, used to sum the first digital signal and multiple first carry signals to produce a first output result when the cut signal is in a first logic state; and to sum the inverted second digital signal and multiple second carry signals to produce a second output result when the cut signal is in a second logic state. The superimposed signal of multiple analog signals indicated by the multiple first carry signals is inverted by the superimposed signal of multiple first pseudo-random signals, and the superimposed signal of analog signals indicated by the multiple second carry signals is inverted by the superimposed signal of multiple second pseudo-random signals. Both the multiple first carry signals and the multiple second carry signals are generated by the analog-to-digital conversion system. The system also includes a digital decimation filter coupled to the digital adder, used to sum and average the first and second output results to obtain a digital output signal indicating the analog input signal.

[0005] This invention utilizes multiple carry signals to eliminate multiple pseudo-random signals introduced when the cut signal is in the first and second logic states. Furthermore, when the cut signal is in the second logic state, a series of inversion operations are performed on each signal, and the signals in the two logic states are summed and averaged to eliminate the inherent offset signal in the analog-to-digital conversion system. Therefore, this analog-to-digital conversion method can eliminate multiple pseudo-random signals and offset signals, improving conversion accuracy. Attached Figure Description

[0006] The objectives, specific structural features, and advantages of the present invention can be further understood through the following description in conjunction with some embodiments and accompanying drawings.

[0007] Figure 1 The diagram shown is a block diagram of an analog-to-digital conversion system according to an embodiment of the present invention.

[0008] Figure 2 The diagram shown is a block diagram of a Σ-Δ modulator according to an embodiment of the present invention; and

[0009] Figure 3 The diagram shows a method for converting analog signals into digital signals using an analog-to-digital converter system according to an embodiment of the present invention. Detailed Implementation

[0010] The embodiments of the present invention will be described in detail below. Although the present invention has been described and illustrated through these embodiments, it should be noted that the present invention is not limited to these embodiments. Rather, the present invention covers all alternatives, variations, and equivalents within the spirit and scope of the invention as defined in the appended claims.

[0011] Furthermore, to better illustrate the invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail in order to highlight the spirit of the invention.

[0012] This invention provides a method for converting analog input signals into digital output signals using an analog-to-digital converter (ADC). This method utilizes multiple carry signals to eliminate multiple pseudo-random signals input when the cutter signal is in the first and second logic states. Furthermore, when the cutter signal is in the second logic state, a series of inversion operations are performed on each signal, and the signals in the two logic states are summed and averaged to eliminate the inherent offset signal in the ADC. Therefore, this ADC method can eliminate multiple pseudo-random signals and offset signals, improving conversion accuracy.

[0013] Figure 1 The diagram shown is a block diagram of an analog-to-digital conversion system 100 according to an embodiment of the present invention. The analog-to-digital conversion system 100 includes a chopper unit 101, an analog adder 102, a first inverter 103, a multiplexer MUX1, a Σ-Δ modulator 104, a second inverter 105, a multiplexer MUX2, a digital adder 106, a digital decimation filter 107, a decision unit 112, a pseudo-random signal generator 113, and a digital accumulator 111. For connection relationships, please refer to... Figure 1 The analog-to-digital converter system 100 converts an analog input signal SIN into a digital output signal DIG3 that indicates the analog input signal SIN. For ease of explanation, in this invention, the resolution of the analog-to-digital converter system 100 is N. In one embodiment, the analog input signal SIN may be an analog voltage VIN. In one embodiment, the digital output signal DIG3 may be an N-bit digital code stream composed of "0"s and "1"s.

[0014] The analog-to-digital conversion system 100 also includes a clock ( Figure 1 (Not shown). This clock is used to generate a clock signal CLK that cycles through clock periods T1. The components within the analog-to-digital conversion system 100 operate in a coordinated and orderly manner according to this clock signal CLK.

[0015] The chopped signal unit 101 is used to generate a chopped signal CHOP. The chopped signal CHOP has a first logic state (e.g., logic low) and a second logic state (e.g., logic high). The chopped signal CHOP cycles with a period T2. In the first half-cycle (T2 / 2), the chopped signal CHOP is in the first logic state, and in the second half-cycle (T2 / 2), the chopped signal CHOP is in the second logic state. Where T2 / 2 = 2... N T1. The CHOP signal is used to control the multiplexers MUX1 and MUX2 and the stream generator 108 described below, which will be described in detail below.

[0016] The judgment unit 112, coupled to the digital decimation filter 107, is used to determine whether the voltage indicated by the digital output signal DIG3 is within a preset voltage range. If the voltage indicated by the digital output signal DIG3 is within the preset voltage range, the judgment unit 112 generates an enable signal EN to enable the pseudo-random signal generator 113. The preset voltage range can be set according to actual conditions, and this invention does not limit it.

[0017] A pseudo-random signal generator 113, coupled to the judgment unit 112, is used to generate a first pseudo-random sequence when the slicing signal CHOP is in a first logic state after being enabled by the enable signal EN, and to generate a second pseudo-random sequence when the slicing signal CHOP is in a second logic state. The first pseudo-random sequence includes multiple first pseudo-random signals S. DHA The second pseudo-random sequence includes multiple second pseudo-random signals S. DHB In one embodiment, at each rising edge of the clock signal CLK, the pseudo-random signal generator 113 generates a pseudo-random signal S. DHA or S DHB Specifically, in the first half of the cycle (T2 / 2), the pseudo-random signal generator 113 generates 2 N A pseudo-random signal S DHA The 2 N A pseudo-random signal S DHA This forms the first pseudo-random sequence. In the latter half of the cycle (T2 / 2), the pseudo-random signal generator 113 generates 2... N A pseudo-random signal S DHB The 2 N A pseudo-random signal S DHB This forms the second pseudo-random sequence.

[0018] In one embodiment, the pseudo-random signal generator 113 includes a code stream generator 108, a first digital-to-analog converter 109, and a coefficient unit 110. The connections are as follows: Figure 1 As shown.

[0019] The bitstream generator 108, coupled to the chopper unit 101, is used to generate 2 when the chopper signal CHOP is in the first logic state after being enabled. N The first bit of the code stream; when the chopped signal CHOP is in the second logic state, it generates 2 bits. N The second bitstream. In one embodiment, the bitstream generator 108 is enabled by the enable signal EN. In the first half-cycle (T2 / 2), the bitstream generator 108 generates a 2-bit second bitstream. N The first bit of the bitstream; in the second half of the cycle (T2 / 2), the bitstream generator 108 generates 2 bits. N The second bit of the bitstream.

[0020] In one embodiment, the first bitstream and the second bitstream are inverses of each other. For example, the first bitstream is "1010" and the second bitstream is "0101".

[0021] A first digital-to-analog converter 109, coupled to a bitstream generator 108, is used to convert each bit in the first bitstream into multiple (e.g., 2) corresponding bits when the chopping signal CHOP is in the first logic state. N (a) pseudo-random signal S DHA One of them; when the chopper signal CHOP is in the second logic state, each bit in the second bitstream is converted into multiple (e.g., 2) N (a) pseudo-random signal S DHB One of them. A pseudo-random signal can indicate the first reference voltage V. REF Or the second reference voltage -V REF Among them, the first reference voltage V REF Second reference voltage -V REF They are opposites, i.e., V REF +(-V REF ) = 0.

[0022] In one embodiment, at each rising edge of the clock signal CLK, the first digital-to-analog converter 109 converts one bit of either the first or second bit stream into a pseudo-random signal. Specifically, in the first half-cycle (T2 / 2), the first digital-to-analog converter 109 converts 2... N The first bit of the bitstream is converted to 2. N A pseudo-random signal S DHA In the second half of the cycle (T2 / 2), the first digital-to-analog converter 109 will convert 2 N The second bit of the bitstream is converted to 2. N A pseudo-random signal S DHB .

[0023] 2 NBoth the first and second bitstreams include a first digit (“1”) and a second digit (“0”). The first digital-to-analog converter 109 converts the first digit (“1”) in the first bitstream into an indicator of the first reference voltage V. REF Multiple (e.g., 2) N The first pseudo-random signal S DHA One of them converts the second digit ("0") in the first bitstream into an indicator of the second reference voltage -V. REF Multiple (e.g., 2) N The first pseudo-random signal S DHA One of them. For example, when the first bit stream is "01", the first digital-to-analog converter 109 first converts the first bit "0" into an indicator of the second reference voltage -V. REF A pseudo-random signal S DHA Then, the second bit "1" is converted to indicate the first reference voltage V. REF A pseudo-random signal S DHA .

[0024] The first digital-to-analog converter 109 converts the first digit ("1") in the second code stream into an indicator of the first reference voltage V. REF Multiple (e.g., 2) N The second pseudo-random signal S DHB One of them converts the second digit ("0") in the second bitstream into an indicator of the second reference voltage -V. REF Multiple (e.g., 2) N The second pseudo-random signal S DHB one of the.

[0025] Coefficient unit 110, coupled to the first digital-to-analog converter 109, is used to reduce the pseudo-random signal S by a preset coefficient 1 / m. DHA S DHB The amplitude. In one embodiment, the preset coefficient 1 / m can be 1 / 4. Setting the preset coefficient 1 / m can prevent pseudo-random signals S DHA S DHB The indicated analog voltage is too high, causing data overflow.

[0026] Analog adder 102, coupled to pseudo-random signal generator 113, is used to sequentially add a pseudo-random signal to analog input signal S at each rising edge of clock signal CLK. IN This generates a corresponding summation signal. Based on the logic state of the chopped signal CHOP, the summation signal can be divided into a first summation signal and a second summation signal. If the chopped signal CHOP is in the first logic state, the first summation signal is the analog input signal S. IN With multiple pseudo-random signals S DHAThe superimposed signals. For example, after two rising edges of the clock signal CLK, the first summation signal is (S IN +2S DHA If the chopped signal CHOP is in the second logic state, the second summation signal is the analog input signal S. IN With multiple pseudo-random signals S DHB The superimposed signals. For example, after two rising edges of the clock signal CLK, the second summation signal is (S IN +2S DHB ).

[0027] The first inverter 103, coupled between the analog adder 102 and the "1" input of the multiplexer MUX1, is used to invert the second summing signal to obtain the inverted second summing signal (e.g., -S). IN -2S DHB ).

[0028] When the chopped signal CHOP is in the first logic state, the "0" input of the multiplexer MUX1 receives and transmits the first summation signal (e.g., S). IN +2S DHA When the chopped signal CHOP is in the second logic state, the "1" input of the multiplexer MUX1 receives and transmits the inverted second summation signal (e.g., -S). IN -2S DHB ).

[0029] Offset signal S OS This is introduced by the non-ideality of the Σ-Δ modulator 104. In this Σ-Δ modulator 104, the offset signal S OS There are many sources of this offset, such as offset caused by the amplifier itself, offset caused by the injection of charge into the sampling capacitor when the sampling switch is closed, or offset caused by electromagnetic interference. These offsets all exist within the Σ-Δ modulator 104 due to its non-ideality, thus reducing conversion accuracy. For ease of explanation, we assume that this offset signal S... OS The offset signal S is input at the input terminal of the Σ-Δ modulator 104. OS It can be an analog voltage V OS .

[0030] The Σ-Δ modulator 104, coupled to the multiplexer MUX1, is used to convert the first summation signal into a first digital signal DIG1 when the chopped signal CHOP is in the first logic state; and to convert the inverted second summation signal into a second digital signal DIG2 when the chopped signal CHOP is in the second logic state. Due to the offset signal S... OS If it exists in a Σ-Δ modulator, then the analog signal indicated by the digital signal DIG1 is the sum of the first summation signal and the offset signal S.OS The superimposed signal, i.e. (S IN +2 N S DHA +S OS The analog signal indicated by the digital signal DIG2 is the inverted second summation signal and the offset signal S. OS The superimposed signal, i.e. -(S IN +2 N S DHB )+S OS , among which, (S IN +2 N S DHA (S) is the first summation signal. IN +2 N S DHB () represents the second summation signal, which here has undergone 2... N The rising edge of the clock signal CLK. In one embodiment, at each rising edge of the clock signal CLK, the Σ-Δ modulator 104 converts one bit of digital signal. In the first half of the cycle (T2 / 2), the Σ-Δ modulator 104 generates 2... N The digital signal DIG1 is 2 bits; in the second half of the cycle (T2 / 2), the Σ-Δ modulator 104 generates 2 bits. N The digital signal DIG2 is 1 bit.

[0031] In one embodiment, please refer to Figure 2 The Σ-Δ modulator 104 includes an analog subtractor 201, a gain unit g1, an integrator H(z), a voltage comparator 202, and a second digital-to-analog converter 203. The connections are as follows: Figure 2 As shown.

[0032] Analog subtractor 201, coupled to multiplexer MUX1, is used to subtract an analog feedback signal S from the output of multiplexer MUX1 (either the first summation signal or the second summation signal) on each rising edge of clock signal CLK. FB (Generated by the second digital-to-analog converter 203) to generate an analog differential signal S DIF .

[0033] Gain unit g1, coupled to analog subtractor 201, is used to amplify the analog differential signal S. DIF .

[0034] The integrator H(z), coupled to the gain unit g1, is used to amplify the analog differential signal S. DIF Integrate and generate a changing signal S VARY The changing signal S VARY The slope and amplitude depend on the amplified analog differential signal S DIF The symbols and amplitudes.

[0035] Voltage comparator 202, coupled to integrator H(z), is used to apply the voltage to the changing signal V at each rising edge of clock signal CLK. VARY A sampled signal is obtained by sampling once, and this sampled signal is compared with a reference signal to generate one bit of the digital signals DIG1 and DIG2. If the sampled signal is not less than the reference signal, the bit is logic high ("1"); otherwise, the bit is logic low ("0"). This voltage comparator 202 performs 2... N Second sampling and generate 2 N The 2-bit digital signal DIG1 is processed in the second half of the cycle (T2 / 2). N Second sampling and generate 2 N The digital signal DIG2 is 1 bit.

[0036] The second digital-to-analog converter 203, coupled to the voltage comparator 202, is used to convert the digital signals DIG1 and DIG2 bit by bit into the analog feedback signal S. FB In one embodiment, at each rising edge of the clock signal CLK, the second digital-to-analog converter 203 converts one bit of the digital signal DIG1 or DIG2 into an analog feedback signal S. FB Therefore, the second digital-to-analog converter 203 converts 2 N The 2-bit digital signal DIG1 is converted to 2 N A simulated feedback signal S FB , will 2 N The bit digital signal DIG2 is converted to 2 bits. N A simulated feedback signal S FB An analog feedback signal S FB It can indicate the first reference voltage V REF Or the second reference voltage -V REF For example, when the digital signal DIG1 is "01", the second digital-to-analog converter 203 first converts the first bit "0" to an indicator of the second reference voltage -V at a rising edge of the clock signal CLK. REF The analog feedback signal S FB On the next rising edge of the clock signal CLK, the second bit "1" is converted to indicate the first reference voltage V. REF The analog feedback signal S FB .

[0037] Furthermore, if one bit in digital signals DIG1 or DIG2 is the same digit (e.g., "0"), the second digital-to-analog converter 203 converts it to the same reference voltage. For example, when one bit in digital signals DIG1 or DIG2 is "0", the second digital-to-analog converter 203 converts it to indicate the second reference voltage -V. REFWhen the analog feedback signal is "1", the second digital-to-analog converter 203 converts it into an indication of the first reference voltage V. REF The analog feedback signal. As discussed above, both the first digital-to-analog converter 109 and the second digital-to-analog converter 203 convert "0" to the second reference voltage -V. REF Convert "1" to the first reference voltage V REF This allows for the subsequent use of multiple carry signals S CY1 S CY2 Cancel multiple pseudo-random signals S DHA S DHB This laid the foundation, and the specific details will be described in detail below.

[0038] The second inverter 105, coupled between the Σ-Δ modulator 104 and the "1" input of the multiplexer MUX2, is used to invert the digital signal DIG2 to obtain the inverted digital signal DIG2 (indicator S). IN +2 N S DHB -S OS ).

[0039] When the chopped signal CHOP is in the first logic state, the "0" input of the multiplexer MUX2 receives and transmits the digital signal DIG1. When the chopped signal CHOP is in the second logic state, the "1" input of the multiplexer MUX2 receives and transmits the inverted digital signal DIG2.

[0040] Digital accumulator 111, coupled to bitstream generator 108, is used to generate multiple (2) bits corresponding to the first bitstream. N The first carry signal S) CY1 and multiple (2) corresponding to the second bitstream N The second carry signal S CY2 Among them, multiple (2) N The first carry signal S) CY1 The superposition of multiple analog signals and multiple (2) N The first pseudo-random signal S DHA The superimposed signals are mutually out of phase. Multiple (2 N The second carry signal S CY2 The superimposed signal of the indicated analog signal and multiple (2 N The second pseudo-random signal S DHB The superimposed signals are mutually out of phase.

[0041] In one embodiment, when the pseudo-random signal generator 113 does not include the coefficient unit 110, the digital accumulator 111 converts the first digit ("1") in the first code stream into an indication of the second reference voltage -V. REF Multiple (2)N The first carry signal S) CY1 One of them converts the second digit ("0") in the first bitstream into an indicator of the first reference voltage V. REF Multiple (2) N The first carry signal S) CY1 One of them. Digital accumulator 111 converts the first digit ("1") in the second code stream into an indicator of the second reference voltage -V. REF Multiple (2) N The second carry signal S CY2 One of them converts the second digit ("0") in the second bitstream into an indicator of the first reference voltage V. REF Multiple (2) N The second carry signal S CY2 One of them. Among them, the first reference voltage V REF Second reference voltage -V REF They are opposites. For example, when the first bit stream is "01", the digital accumulator 111 first converts the "0" in the first bit to an indicator of the first reference voltage V on a rising edge of the clock signal CLK. REF A carry signal S CY1 On the next rising edge of the clock signal CLK, the "1" in the second bit is converted to indicate the second reference voltage -V. REF A carry signal S CY1 For the second bitstream, the function of the digital accumulator 111 is similar to that described above, and will not be repeated here.

[0042] As can be seen from the above, when one bit in the first or second bit stream is "0", the first digital-to-analog converter 109 converts it into an indication reference voltage -V. REF A pseudo-random signal is converted by digital accumulator 111 into an indication reference voltage V. REF A carry signal. When it is "1", the first digital-to-analog converter 109 converts it into an indication of the reference voltage V. REF A pseudo-random signal is converted by digital accumulator 111 into an indication reference voltage -V REF A carry signal. It can be seen that for the same bit in the first or second bit stream, the voltage indicated by a carry signal converted by the digital accumulator 111 is the opposite of the voltage indicated by a pseudo-random signal converted by the first digital-to-analog converter 109. The two can be completely canceled out by the summation of the digital adder 106 described below, thereby eliminating the problem of reduced conversion accuracy caused by the introduction of pseudo-random signals.

[0043] In another embodiment, when the pseudo-random signal generator 113 includes a coefficient unit 110, the digital accumulator 111 counts the number of the first digit ("1") and the second digit ("0") in the first or second code stream at each rising edge of the clock signal CLK, calculates the ratio of the difference between the two to the reciprocal of a preset coefficient 1 / m, and generates multiple (2) digits based on this ratio. N (one) carry signal S CY1 One of them or multiple (2) are generated based on the ratio. N (one) carry signal S CY2 One of them. Among them, the multiple (2) N (one) carry signal S CY1 The sum of the indicated voltages and multiple (2) N (a) pseudo-random signal S DHA The sums of the indicated voltages are opposites, and multiple (2) N (one) carry signal S CY2 The sum of the indicated voltages and multiple (2) N (a) pseudo-random signal S DHB If the sum of the indicated voltages are opposites, they can be completely canceled out by the digital adder 106 described below, thus eliminating the problem of reduced conversion accuracy caused by the introduction of pseudo-random signals.

[0044] Specifically, when the ratio is between -1 and 1, the corresponding multiple carry signals S CY1 One of the zero indicators corresponds to multiple carry signals S. CY2 One of the indicators is zero. When this ratio equals -1, the corresponding multiple carry signals S CY1 One of the indicators is the first reference voltage V. REF The corresponding multiple carry signals S CY2 One of the indicators is the first reference voltage V. REF When this ratio equals 1, the corresponding multiple carry signals S CY1 One of the indicators is the second reference voltage -V REF The corresponding multiple carry signals S CY2 One of the indicators is the second reference voltage -V REF .

[0045] For example, with a preset coefficient 1 / m of 1 / 4, the first bitstream is "01011111". The digital accumulator 111 counts the number of digits "1" and "0" at each rising edge of the clock signal CLK, and calculates the difference between them (the number of digits "1" minus the number of digits "0") and the ratio to 4. For the first seven bits, this ratio is between -1 and 1, so the first seven carry signals S... CY1 All indicate zero. For the eighth bit, this ratio equals 1, then the eighth carry signal S CY1Indicates the second reference voltage -V REF So, these eight carry signals S CY1 The sum of the indicated voltages is the second reference voltage -V REF The corresponding eight pseudo-random signals S DHA The sum of the indicated voltages is the first reference voltage V. REF Finally, through the summation by the digital adder 106 described below, the eight carry signals S are obtained. CY1 The sum of the indicated voltages can completely cancel out the eight pseudo-random signals S DHA The sum of the indicated voltages eliminates the problem of reduced conversion accuracy caused by the introduction of pseudo-random signals.

[0046] Digital adder 106, coupled to multiplexer MUX2, is used to add the first digital signal DIG1 and multiple (2) multiplexers when the choke signal CHOP is in the first logic state. N The first carry signal S) CY1 Summing and generating the first output result OUT1. When the chopping signal CHOP is in the second logic state, the inverted second digital signal DIG2 and multiple second carry signals S are summed to produce the first output result OUT1. CY2 Summing and producing a second output result OUT2.

[0047] In one embodiment, 2 N The voltage indicated by the first digital signal DIG1 is the sum of the first summation signal and the offset signal S. OS The superimposed signal, i.e. (S IN +2 N S DHA +S OS ). As can be seen from the above, 2 N The first carry signal S CY1 The sum of the indicated voltages can cancel out 2 N A pseudo-random signal S DHA The sum of the indicated voltages, then the analog signal indicated by the first output result OUT1 is the analog input signal S. IN With offset signal S OS The superimposed signal (i.e., S) IN +S OS ). Inverter 105 to 2 N Inverting the second digital signal DIG2 of bit 2 yields the inverted second digital signal DIG2. N The analog signal indicated by the second digital signal DIG2 is the second summation signal and the inverted offset signal S. OS The superimposed signal, i.e. (S IN +2 N S DHB )-S OS As can be seen from the above, 2N The second carry signal S CY2 The sum of the indicated voltages can cancel out 2 N A pseudo-random signal S DHB The sum of the indicated voltages, then the analog signal indicated by the second output result OUT2 is the analog input signal S. IN The offset signal S after inversion OS The superimposed signal (i.e., S) IN -S OS As can be seen, after the digital adder 106 sums, under one logic state of the chopped signal CHOP, 2 N The sum of the voltages indicated by the pseudo-random signals and 2 N The sum of the voltages indicated by the carry signals can cancel each other out, thereby improving the conversion accuracy.

[0048] The digital decimation filter 107, coupled to the digital adder 106, is used to sum and average the first output result OUT1 and the second output result OUT2 to obtain the analog input signal S. IN The digital output signal DIG3 is N bits. As mentioned above, the offset signal S is also eliminated by summing and averaging. OS This yielded only the analog input signal S. IN The digital output signal DIG3 further improves the conversion accuracy.

[0049] In one embodiment, the combination Figure 1 The entire analog-to-digital conversion process is described in detail. In this embodiment, 2 N The first bit of the bit stream and 2 N The second bitstream is identical, consisting entirely of "1"s, with a preset coefficient 1 / m of 1 / 4, and the resolution N of the analog-to-digital conversion system 100 ≥ 2. In other embodiments, the first and second bitstreams may be different, and the preset coefficient 1 / m and resolution N may be other values; this invention does not limit these values. The chopping unit 101 generates a chopping signal CHOP. This chopping signal CHOP is in a first logic state during the first half-cycle (T2 / 2) and in a second logic state during the second half-cycle (T2 / 2). The judgment unit 112 generates an enable signal EN when it determines that the voltage indicated by the digital output signal DIG3 is within a preset voltage range. Based on this enable signal EN, the bitstream generator 108 is enabled.

[0050] During the first half of the cycle (T2 / 2), the operation of each component is as follows:

[0051] The 108 bitstream generator produces 2 N The first bit of the bitstream.

[0052] The first digital-to-analog converter 109 converts one bit of the first bitstream into a pseudo-random signal S at each rising edge of the clock signal CLK. DHA Therefore, in the first half of the cycle (T2 / 2), the first digital-to-analog converter 109 will convert the 2 N The first bit of the bitstream is converted to 2. N A pseudo-random signal S DHA Since the first bitstream consists entirely of "1"s, each pseudo-random signal S DHA All indicate reference voltage V REF .

[0053] Coefficient unit 110 will 2 N A pseudo-random signal S DHA The amplitude is reduced to 1 / 4 of its original value. For ease of explanation, the reduced pseudo-random signal S... DHA It is still called a pseudo-random signal S DHA Each pseudo-random signal S DHA The indicated voltage becomes V REF / 4.2 N A pseudo-random signal S DHA The sum of the indicated voltages is 2 N V REF / 4.

[0054] The analog adder 102 adds a pseudo-random signal S on each rising edge of the clock signal CLK. DHA Accumulated to analog input signal S IN It then outputs a first summation signal. Thus, in the first half of the cycle (T2 / 2), the analog adder 102 generates a total of 2... N The first summation signal. According to the order in which they are generated, the 2... N The voltages indicated by the first summation signal are (V) IN +V REF / 4), (V IN +2V REF / 4), ..., (V IN +2 N V REF / 4).

[0055] The "0" input of the multiplexer MUX1 transmits a first summation signal on each rising edge of the clock signal CLK.

[0056] The Σ-Δ modulator 104 sequentially sums a first summation signal and an offset signal S at each rising edge of the clock signal CLK. OS Convert to one bit in the digital signal DIG1 until 2 is completed. N This transformation produces 2 NThe digital signal DIG1 is 2 bits. During the first half of this cycle (T2 / 2), the Σ-Δ modulator 104 generates a total of 2 bits. N A digital signal DIG1 (including a 1-bit digital signal DIG1, ​​a 2-bit digital signal DIG1, ​​..., 2... N A 1-bit digital signal DIG1 indicates the voltage (V). IN +V REF / 4+V OS The 2-bit digital signal DIG1 indicates the voltage (V). IN +2V REF / 4+V OS ), and so on, 2 N The digital signal DIG1 indicates the voltage (V) IN +2 N V REF / 4+V OS ).

[0057] The "0" input of the multiplexer MUX2 receives and transmits a digital signal DIG1 on each rising edge of the clock signal CLK.

[0058] The digital accumulator 111 counts the number of "1"s and "0"s in the first bitstream at each rising edge of the clock signal CLK, calculates the ratio of the difference between the two (the number of "1"s minus the number of "0"s) to the reciprocal of a preset coefficient of 1 / 4, and generates a corresponding carry signal S based on this ratio. CY1 For example, when counting the first, second, and third "1"s in the first bitstream, the ratios correspond to 1 / 4, 2 / 4, and 3 / 4, respectively, and the three carry signals S corresponding to these ratios are... CY1 All values ​​indicate zero; when counting the fourth "1", the ratio is 1, and a carry signal S corresponds to this ratio. CY1 Indicating reference voltage -V REF And so on. In this embodiment, 2 N One carry signal S CY1 The sum of the indicated voltages is (-2) N V REF / 4).

[0059] The digital adder 106 adds a digital signal DIG1 and a corresponding carry signal S on each rising edge of the clock signal CLK. CY1 Summation, until 2 is completed. N This summation is performed twice, producing the output result OUT1. That is, the output result OUT1 is 2. N The digital signals DIG1 and 2 are 2 bits. N One carry signal S CY1 The sum. Because 2 NThe voltage indicated by the first digital signal DIG1 of the bit is (V IN +2 N V REF / 4+V OS ), 2 N One carry signal S CY1 The sum of the indicated voltages is (-2) N V REF / 4), then after summing, the voltage indicated by the output OUT1 is (V IN +V OS As can be seen, by summing, 2 N One carry signal S CY1 The sum of the indicated voltages (-2) N V REF / 4) can completely offset 2 N A pseudo-random signal S DHA The sum of the indicated voltages (2) N V REF / 4) to improve conversion accuracy.

[0060] During the second half of the cycle (T2 / 2), the operation of each component is as follows:

[0061] The 108 bitstream generator produces 2 N The second bit of the bitstream.

[0062] The first digital-to-analog converter 109 converts one bit of the second bit stream into a pseudo-random signal S at each rising edge of the clock signal CLK. DHB Therefore, in the second half of the cycle (T2 / 2), the first digital-to-analog converter 109 will convert the 2... N The second bit of the bitstream is converted to 2. N A pseudo-random signal S DHB Since the second bitstream consists entirely of "1"s, each pseudo-random signal S DHB All indicate reference voltage V REF .

[0063] Coefficient unit 110 will use the pseudo-random signal S DHB The amplitude is reduced to 1 / 4 of its original value. For ease of explanation, the reduced pseudo-random signal S... DHB It is still called a pseudo-random signal S DHB Each pseudo-random signal S DHB The indicated voltage becomes V REF / 4. The 2 N A pseudo-random signal S DHB The sum of the indicated analog voltages is 2 N V REF / 4.

[0064] The analog adder 102 adds a pseudo-random signal S on each rising edge of the clock signal CLK. DHB Accumulated to analog input signal S IN It then outputs a second summation signal. Thus, in the second half of the cycle (T2 / 2), the analog adder 102 generates a total of 2... N The second summation signal. According to the order of their generation, 2... N The voltages indicated by the second summation signal are (V) IN +V REF / 4), (V IN +2V REF / 4), ..., (V IN +2 N V REF / 4).

[0065] The first inverter 103 inverts the phase 2. N The second summation signal yields 2. N The second summation signal after inversion.

[0066] The "1" input of the multiplexer MUX2 receives and transmits the 2 N The second summation signal after inversion.

[0067] The Σ-Δ modulator 104 sequentially converts an inverted second summation signal and an offset signal S at each rising edge of the clock signal CLK. OS Convert to one bit in the digital signal DIG2 until 2 is completed. N This transformation produces 2 N The digital signal DIG2 is 2 bits. Therefore, in the latter half of the cycle (T2 / 2), the Σ-Δ modulator 104 generates a total of 2 bits. N A digital signal DIG2 (including a 1-bit digital signal DIG2, a 2-bit digital signal DIG2, ..., 2... N The 1-bit digital signal DIG2 indicates the voltage [-(V]]. IN +V REF / 4)+V OS The 2-bit digital signal DIG2 indicates the voltage [-(V]]. IN +2V REF / 4)+V OS ], and so on, 2 N The digital signal DIG2 indicates the voltage [-(V] IN +2 N V REF / 4)+V OS ].

[0068] The second inverter 105 sequentially... NInverting the digital signal DIG2 yields 2 N The inverted digital signal DIG2.2 N The voltages indicated by the inverted digital signal DIG2 are (V) IN +V REF / 4-V OS ), (V IN +2V REF / 4-V OS ), ..., (V IN +2 N V REF / 4-V OS ).

[0069] The "1" input of the multiplexer MUX2 receives and transmits the two inputs sequentially. N The inverted digital signal DIG2.

[0070] The digital accumulator 111 counts the number of "1"s and "0"s in the second code stream at each rising edge of the clock signal CLK, calculates the ratio of the difference between the two (the number of "1"s minus the number of "0"s) to the reciprocal of a preset coefficient of 1 / 4, and generates a corresponding carry signal S based on this ratio. CY2 The specific generation process is similar to that of the carry signal S. CY1 The details will not be elaborated further. In this embodiment, 2 N One carry signal S CY2 The sum of the indicated voltages is (-2) N V REF / 4).

[0071] The digital adder 106 adds the inverted digital signal DIG2 and a corresponding carry signal S at each rising edge of the clock signal CLK. CY2 Summation, until 2 is completed. N This summation is performed twice, producing the output result OUT2. That is, the output result OUT2 is the inverted 2^ ... N The digital signal DIG2 and 2 bits N One carry signal S CY2 The sum. Due to the inversion of 2 N The voltage indicated by the bit-digital signal DIG2 is (V) IN +2 N V REF / 4-V OS ), 2 N One carry signal S CY2 The sum of the indicated voltages is (-2) N V REF / 4), then after summing, the output result OUT2 indicates the voltage (V) IN -V OSAs can be seen, by summing, 2 N One carry signal S CY2 The sum of the indicated voltages (-2) N V REF / 4) can offset 2 N A pseudo-random signal S DHB The sum of the indicated voltages (2) N V REF / 4) to improve conversion accuracy.

[0072] The digital decimation filter 107 sums and averages the outputs OUT1 and OUT2 to obtain the analog input signal S. IN The digital output signal DIG3. The voltage indicated by the digital output signal DIG3 is [(V IN +V OS )+(V IN -V OS )] / 2=V IN It is evident that by summing and averaging, the offset signal S is eliminated. OS This further improves the conversion accuracy.

[0073] In other embodiments, the first and second bitstreams can also be inverses of each other. Therefore, based on the above, 2 N A pseudo-random signal S DHA Each of the two is related to 2. N A pseudo-random signal S DHB If the corresponding phases are opposite, then 2 N A pseudo-random signal S DHA Each of the indicated voltages is related to 2 N A pseudo-random signal S DHB The corresponding voltages indicated in the two numbers are opposites. Also, 2 N One carry signal S CY1 Each of the indicated voltages is related to 2 N One carry signal S CY2 The corresponding indicated voltages are also opposites. Finally, the values ​​are summed and averaged through a digital decimation filter 107, resulting in 2... N A pseudo-random signal S DHA The sum of the indicated voltages and 2 N A pseudo-random signal S DHB The sum of the indicated voltages cancels each other out, 2 N One carry signal S CY1 The sum of the indicated voltages and 2 N One carry signal S CY2 The sum of the indicated voltages cancels out, which can also completely eliminate the pseudo-random signal S. DHA S DHB and offset signal SOS This improves the accuracy of analog-to-digital conversion.

[0074] When the judgment unit 112 determines that the analog voltage indicated by the digital output signal DIG3 exceeds the preset voltage range, it does not generate an enable signal EN. Therefore, the code stream generator 108 is disabled, and multiple pseudo-random signals S... DHA S DHB It will not be generated. Other processes are similar to those described above and will not be repeated.

[0075] Figure 3 The diagram illustrates the use of an analog-to-digital converter 100 to convert an analog input signal S according to an embodiment of the present invention. IN A flowchart of a method 300 for converting an analog-to-digital converter (ADC) signal S into a digital output signal DIG3. The analog-to-digital converter system 100 includes a chopper unit 101, a Σ-Δ modulator 104, a digital adder 106, and a digital decimation filter 107. In this invention, the resolution of the ADC system 100 is N. The ADC system 100 can convert an analog input signal S into a digital output signal DIG3. IN Converted to indicate the analog input signal S IN 2 N The digital output signal DIG3 is 3 bits. Figure 3 Combining Figure 1 This method 300 includes:

[0076] Step 301: The chopped signal unit 101 generates a chopped signal CHOP having a first logic state and a second logic state. Figure 3 The embodiment describes the case where the chopped signal CHOP changes from a first logic state to a second logic state.

[0077] When the choke signal CHOP is in the first logic state, the operation of each component is as follows:

[0078] Step 302, the analog-to-digital conversion system 100 generates multiple (2 N The first pseudo-random signal S DHA .

[0079] Step 303, the analog-to-digital conversion system 100 according to multiple (2 N The first pseudo-random signal S DHA and analog input signal S IN Generate the first summation signal. The first summation signal consists of multiple (2) signals. N The first pseudo-random signal S DHA and analog input signal S IN The superimposed signal, i.e. (S IN +2 N S DHA ).

[0080] Step 304, the Σ-Δ modulator 104 converts the first summed signal into a first digital signal DIG1. In one embodiment, the first digital signal DIG1 has 2 N Bit. Due to the offset signal S OS If it exists within the Σ-Δ modulator 104, then the 2 N The first digital signal DIG1 indicates the analog signals, which are the first summation signal and the offset signal S. OS The superimposed signal, i.e. (S IN +2 N S DHA +S OS ).

[0081] Step 305, the analog-to-digital conversion system 100 generates multiple (2 N The first carry signal S) CY1 Among them, multiple (2) N The first carry signal S) CY1 Multiple indications (2) N The superposition of one (2) analog signals and multiple (2) analog signals N The first pseudo-random signal S DHA The superimposed signals are mutually out of phase.

[0082] Step 306, digital adder 106 adds the first digital signal DIG1 and multiple (2 N The first carry signal S) CY1 Sum the results and produce the first output result OUT1.

[0083] In one embodiment, due to 2 N The first carry signal S CY1 Instruction 2 N The superposition of two analog signals and 2 N The first pseudo-random signal S DHA Superimposed signal (2) N S DHA If the phases are mutually inverted, then after summing by the digital adder 106, 2 N The first carry signal S CY1 Instruction 2 N The superposition of two analog signals canceled out 2 N The portion of the signal indicated by the first digital signal DIG1 (i.e., 2 bits) N The first pseudo-random signal S DHA The superimposed signal makes the analog signal indicated by the output result OUT1 equal to the analog input signal S. IN With offset signal S OS The superimposed signal, i.e. (S IN +S OSThis step eliminates the problem of reduced conversion accuracy caused by the introduction of pseudo-random signals.

[0084] When the choke signal CHOP is in the second logic state, the steps are as follows:

[0085] Step 307, the analog-to-digital conversion system 100 generates multiple (2 N The second pseudo-random signal S DHB .

[0086] Step 308, the analog-to-digital conversion system 100 according to multiple (2 N The second pseudo-random signal S DHB and analog input signal S IN Generate a second summation signal. The second summation signal consists of multiple (2) signals. N The second pseudo-random signal S DHB and analog input signal S IN The superimposed signal, i.e. (S IN +2 N S DHB ).

[0087] Step 309, the Σ-Δ modulator 104 converts the inverted second summed signal into a second digital signal DIG2. In one embodiment, the second digital signal DIG2 has 2 N Bit. Due to the offset signal S OS If it exists within the Σ-Δ modulator 104, then the 2 N The second digital signal DIG2 indicates the analog signal, which is the inverted second summation signal and the offset signal S. OS The superimposed signal, i.e. (-S IN -2 N S DHA +S OS ).

[0088] Step 310, the analog-to-digital conversion system 100 generates multiple (2 N The second carry signal S CY2 Multiple (2) N The second carry signal S CY2 Multiple indications (2) N The superposition of one (2) analog signals and multiple (2) analog signals N The second pseudo-random signal S DHB The superimposed signals are mutually out of phase.

[0089] Step 311, the digital adder 106 adds the inverted second digital signal DIG2 and multiple (2 N The second carry signal S CY2 Summing and producing a second output result OUT2.

[0090] In one embodiment, due to 2 N The second carry signal S CY2 Instruction 2 N The superposition of two analog signals and 2 N The second pseudo-random signal S DHB Superimposed signal (2) N S DHB If the phases are mutually inverted, then after summing by the digital adder 106, 2 N The second carry signal S CY2 Instruction 2 N The superposition of two analog signals cancels out the inverted 2 N The portion of the signal indicated by the second digital signal DIG2 (i.e., 2 bits) N The second pseudo-random signal S DHB The superimposed signal (of the two signals) makes the analog signal indicated by the output result OUT2 the analog input signal S. IN The offset signal S after inversion OS The superimposed signal, i.e. (S IN -S OS This step eliminates the problem of reduced conversion accuracy caused by the introduction of pseudo-random signals.

[0091] Step 312: The digital decimation filter 107 sums and averages the first output result OUT1 and the second output result OUT2 to obtain the analog input signal S. IN The digital output signal DIG3. In one embodiment, the digital output signal DIG3 is N bits. As can be seen from the above, the offset signal S is also eliminated by summing and averaging. OS This yielded only the analog input signal S. IN The digital output signal DIG3 improves the conversion accuracy.

[0092] As previously stated, this invention discloses a method and system for converting analog input signals into digital output signals using an analog-to-digital converter. This invention eliminates offset signals while completely eliminating pseudo-random signals, thus improving conversion accuracy.

[0093] The specific embodiments and accompanying drawings described above are merely common examples of the present invention. Obviously, various additions, modifications, and substitutions can be made without departing from the spirit and scope of the invention as defined in the claims. Those skilled in the art should understand that the present invention can be varied in form, structure, layout, proportion, materials, elements, components, and other aspects in practical applications according to specific environments and working requirements, without departing from the inventive principles. Therefore, the embodiments disclosed herein are for illustrative purposes only and not for limitation. The scope of the present invention is defined by the appended claims and their legal equivalents, and is not limited to the preceding description.

Claims

1. A method for converting an analog input signal into a digital output signal using an analog-to-digital converter system, characterized in that, The analog-to-digital conversion system includes a wave-cutting unit, a Σ-Δ modulator, a digital adder, and a digital decimation filter; the method includes: The slicing unit generates a sliced ​​signal having a first logic state and a second logic state; When the chopper signal is in the first logic state: The analog-to-digital conversion system generates multiple first pseudo-random signals; The analog-to-digital conversion system generates a first summation signal based on the plurality of first pseudo-random signals and the analog input signal; The Σ-Δ modulator converts the first summation signal into a first digital signal; The analog-to-digital conversion system generates multiple first carry signals, wherein the superimposed signal of the multiple analog signals indicated by the multiple first carry signals is out of phase with the superimposed signal of the multiple first pseudo-random signals; The digital adder sums the first digital signal and the plurality of first carry signals and generates a first output result; When the chopper signal is in the second logic state: The analog-to-digital conversion system generates multiple second pseudo-random signals; The analog-to-digital conversion system generates a second summation signal based on the plurality of second pseudo-random signals and the analog input signal; The Σ-Δ modulator converts the inverted second summation signal into a second digital signal; The analog-to-digital conversion system generates multiple second carry signals, wherein the superimposed signal of the multiple analog signals indicated by the multiple second carry signals is out of phase with the superimposed signal of the multiple second pseudo-random signals; The digital adder sums the inverted second digital signal and the plurality of second carry signals and generates a second output result; and The digital decimation filter sums and averages the first output result and the second output result to obtain the digital output signal that indicates the analog input signal.

2. The method of claim 1, wherein, Each of the plurality of first pseudo-random signals is the opposite phase of its corresponding one of the plurality of second pseudo-random signals.

3. The method of claim 1, wherein, The analog-to-digital conversion system further includes a pseudo-random signal generator, and the method further includes: after the pseudo-random signal generator is enabled... The pseudo-random signal generator generates the plurality of first pseudo-random signals when the slicing signal is in the first logic state, and generates the plurality of second pseudo-random signals when the slicing signal is in the second logic state.

4. The method of claim 3, wherein, The method further includes: When the voltage indicated by the digital output signal is within a preset voltage range, the pseudo-random signal generator is enabled.

5. The method of claim 3, wherein, The pseudo-random signal generator includes a code stream generator and a digital-to-analog converter coupled to the code stream generator, and the method further includes: When the chopping signal is in the first logic state, the bitstream generator generates a first bitstream, and the digital-to-analog converter converts each bit in the first bitstream into one of the plurality of first pseudo-random signals; and When the chopped signal is in the second logic state, the code stream generator generates a second code stream, and the digital-to-analog converter converts each bit in the second code stream into one of the plurality of second pseudo-random signals.

6. The method of claim 5, wherein, Both the first bitstream and the second bitstream include a first number and a second number, and the method further includes: The digital-to-analog converter converts the first digit in the first bitstream into one of the plurality of first pseudo-random signals indicating a first reference voltage, and converts the second digit in the first bitstream into one of the plurality of first pseudo-random signals indicating a second reference voltage; and The analog-to-digital converter converts the first number in the second bitstream into one of the plurality of second pseudo-random signals indicating the first reference voltage, and converts the second number in the second bitstream into one of the plurality of second pseudo-random signals indicating the second reference voltage, wherein the first reference voltage and the second reference voltage are opposites of each other.

7. The method of claim 5, wherein, The first bitstream and the second bitstream are inverses of each other.

8. The method of claim 6, wherein, The analog-to-digital conversion system further includes a digital accumulator coupled to the bitstream generator, and the method further includes: The digital accumulator converts the first number in the first bitstream into one of the plurality of first carry signals indicating the second reference voltage, and converts the second number in the first bitstream into one of the plurality of first carry signals indicating the first reference voltage; and The digital accumulator converts the first number in the second bitstream into one of the plurality of second carry signals indicating the second reference voltage, and converts the second number in the second bitstream into one of the plurality of second carry signals indicating the first reference voltage. Wherein, the sum of the voltages indicated by the plurality of first carry signals is the opposite of the sum of the voltages indicated by the plurality of first pseudo-random signals, and the sum of the voltages indicated by the plurality of second carry signals is the opposite of the sum of the voltages indicated by the plurality of second pseudo-random signals.

9. The method of claim 6, wherein, The pseudo-random signal generator further includes a coefficient unit coupled to the digital-to-analog converter, and the method further includes: The coefficient unit reduces the amplitude of the plurality of first pseudo-random signals and the amplitude of the plurality of second pseudo-random signals according to a preset coefficient.

10. The method of claim 9, wherein, The analog-to-digital conversion system further includes a digital accumulator coupled to the bitstream generator, and the method further includes: The digital accumulator counts the number of the first digit and the second digit in the first bitstream or the second bitstream, calculates the ratio of the difference between the counted number of the first digit and the second digit to the reciprocal of the preset coefficient, and generates one of the plurality of first carry signals or one of the plurality of second carry signals according to the ratio.

11. The method according to claim 10, characterized in that, When the ratio is between -1 and 1, one of the plurality of first carry signals or one of the plurality of second carry signals indicates zero; When the ratio is equal to -1, one of the plurality of first carry signals or one of the plurality of second carry signals indicates the first reference voltage; When the ratio is equal to 1, one of the plurality of first carry signals or one of the plurality of second carry signals indicates the second reference voltage.

12. An analog-to-digital conversion system, characterized by The analog-to-digital conversion system includes: A slicing unit is used to generate a sliced ​​signal having a first logic state and a second logic state; A Σ-Δ modulator is used to: convert a first summed signal into a first digital signal when the chopped signal is in the first logic state; and convert an inverted second summed signal into a second digital signal when the chopped signal is in the second logic state, wherein the first summed signal is a superposition of an analog input signal and a plurality of first pseudo-random signals, and the second summed signal is a superposition of the analog input signal and a plurality of second pseudo-random signals, wherein the plurality of first pseudo-random signals and the plurality of second pseudo-random signals are both generated by the analog-to-digital conversion system; A digital adder, coupled to the Σ-Δ modulator, is configured to: when the slicing signal is in the first logic state, sum the first digital signal and a plurality of first carry signals and generate a first output result; when the slicing signal is in the second logic state, sum the inverted second digital signal and a plurality of second carry signals and generate a second output result, wherein the superimposed signal of the plurality of analog signals indicated by the plurality of first carry signals is inverted with the superimposed signal of the plurality of first pseudo-random signals, and the superimposed signal of the plurality of analog signals indicated by the plurality of second carry signals is inverted with the superimposed signal of the plurality of second pseudo-random signals, and both the plurality of first carry signals and the plurality of second carry signals are generated by the analog-to-digital conversion system; and A digital decimation filter, coupled to the digital adder, is used to sum and average the first output result and the second output result to obtain a digital output signal indicating the analog input signal.

13. The analog-to-digital conversion system of claim 12, wherein, Each of the plurality of first pseudo-random signals is the opposite phase of its corresponding one of the plurality of second pseudo-random signals.

14. The analog-to-digital conversion system of claim 12, wherein, The analog-to-digital conversion system also includes: A pseudo-random signal generator, coupled to the Σ-Δ modulator, is configured to generate the plurality of first pseudo-random signals when the slicing signal is in the first logic state, and to generate the plurality of second pseudo-random signals when the slicing signal is in the second logic state, after being enabled.

15. The analog-to-digital conversion system of claim 14, wherein, The analog-to-digital conversion system also includes: The judgment unit, coupled to the pseudo-random signal generator, is used to generate an enable signal to enable the pseudo-random signal generator when the voltage indicated by the digital output signal is within a preset voltage range.

16. The analog-to-digital conversion system of claim 14, wherein, The pseudo-random signal generator includes: A bitstream generator, configured to, when enabled, generate a first bitstream when the chopped signal is in the first logic state, and generate a second bitstream when the chopped signal is in the second logic state; and A digital-to-analog converter, coupled to the bitstream generator, is used to: when the slicing signal is in the first logic state, convert each bit in the first bitstream into one of the plurality of first pseudo-random signals; and when the slicing signal is in the second logic state, convert each bit in the second bitstream into one of the plurality of second pseudo-random signals.

17. The analog-to-digital conversion system according to claim 16, characterized in that, Both the first bitstream and the second bitstream include a first number and a second number; The digital-to-analog converter converts the first number in the first bitstream into one of the plurality of first pseudo-random signals indicating a first reference voltage, and converts the second number in the first bitstream into one of the plurality of first pseudo-random signals indicating a second reference voltage; and The analog-to-digital converter converts the first number in the second bitstream into one of the plurality of second pseudo-random signals indicating the first reference voltage, and converts the second number in the second bitstream into one of the plurality of second pseudo-random signals indicating the second reference voltage, wherein the first reference voltage and the second reference voltage are opposites of each other.

18. The analog-to-digital conversion system of claim 16, wherein, The first bitstream and the second bitstream are inverses of each other.

19. The analog-to-digital conversion system of claim 18, wherein, The analog-to-digital conversion system also includes: A digital accumulator, coupled to the bitstream generator, is configured to: convert a first number in the first bitstream into one of the plurality of first carry signals indicating a second reference voltage; convert a second number in the first bitstream into one of the plurality of first carry signals indicating a first reference voltage; convert the first number in the second bitstream into one of the plurality of second carry signals indicating a second reference voltage; and convert the second number in the second bitstream into one of the plurality of second carry signals indicating a first reference voltage. Wherein, the sum of the voltages indicated by the plurality of first carry signals is the opposite of the sum of the voltages indicated by the plurality of first pseudo-random signals, and the sum of the voltages indicated by the plurality of second carry signals is the opposite of the sum of the voltages indicated by the plurality of second pseudo-random signals.

20. The analog-to-digital conversion system of claim 17, wherein, The pseudo-random signal generator also includes: The coefficient unit, coupled to the digital-to-analog converter, is used to reduce the amplitude of the plurality of first pseudo-random signals and the amplitude of the plurality of second pseudo-random signals according to a preset coefficient.

21. The analog-to-digital conversion system of claim 20, wherein, The analog-to-digital conversion system also includes: A digital accumulator, coupled to the bitstream generator, is used to count the number of the first digit and the second digit in the first bitstream or the second bitstream, calculate the ratio of the difference between the counted number of the first digit and the second digit to the reciprocal of the preset coefficient, and generate one of the plurality of first carry signals or one of the plurality of second carry signals according to the ratio.

22. The analog-to-digital conversion system according to claim 21, characterized in that, When the ratio is between -1 and 1, one of the plurality of first carry signals or one of the plurality of second carry signals indicates zero; When the ratio is equal to -1, one of the plurality of first carry signals or one of the plurality of second carry signals indicates the first reference voltage; When the ratio is equal to 1, one of the plurality of first carry signals or one of the plurality of second carry signals indicates the second reference voltage.

Images