Array substrate, display panel and display device

Abstract

The present invention discloses an array substrate, a display panel, and a display device. The array substrate includes: a base substrate and a plurality of pixel units located on the base substrate. Each pixel unit includes a thin film transistor and a pixel electrode; the pixel electrode is located on the side of the thin film transistor facing away from the base substrate; a passivation insulating layer is provided between the pixel electrode and the thin film transistor, and the pixel electrode is electrically connected to the drain electrode of the thin film transistor via a via penetrating the passivation insulating layer. The array substrate also includes a common electrode line located on the side of the drain electrode facing away from the pixel electrode; the portion where the common electrode line overlaps with the pixel electrode forms a storage capacitor; the orthographic projection of the via on the base substrate does not overlap with the orthographic projection of the common electrode line on the base substrate, thereby avoiding a short circuit between the drain electrode and the common electrode line and reducing the probability of dot line defects.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] A liquid crystal display (LCD) panel includes an array substrate, a color filter substrate, and a liquid crystal layer located between the array and color filter substrates. The array substrate includes thin-film transistors (TFTs) and pixel electrodes located above the TFTs. The TFTs include a gate electrode, a source electrode, a drain electrode, and an active layer. The drain electrode and pixel electrode are separated by a passivation insulating layer, and the drain electrode and pixel electrode are connected via vias in the passivation insulating layer. When displaying an image, an image signal voltage is input to the pixel electrode through the drain electrode, forming an electric field between the array substrate and the color filter substrate that deflects the liquid crystal molecules in the liquid crystal layer, thereby displaying the image.

[0003] During image display, a storage capacitor (CS) is required to maintain the image signal voltage on the pixel electrode during a frame. Currently, some solutions use common electrode lines and pixel electrodes to form storage capacitors. To increase the storage capacitance, some solutions place the common electrode line on the side of the drain electrode facing away from the pixel electrode, with the drain electrode's orthographic projection on the array substrate located within the common electrode line's orthographic projection on the array substrate. This results in a high incidence of dot-line defects. Summary of the Invention

[0004] The present invention provides an array substrate, a display panel and a display device, which are used to reduce the occurrence probability of defective dots and lines.

[0005] According to a first aspect of the present invention, an array substrate is provided, comprising:

[0006] substrate;

[0007] A plurality of pixel units are located on a substrate; each pixel unit includes a thin film transistor and a pixel electrode; the pixel electrode is located on a side of the thin film transistor facing away from the substrate; a passivation insulating layer is provided between the pixel electrode and the thin film transistor, and the pixel electrode is electrically connected to a drain electrode of the thin film transistor via a via hole penetrating the passivation insulating layer;

[0008] The common electrode line is located on the side of the drain electrode away from the pixel electrode; the overlapping portion of the common electrode line and the pixel electrode forms a storage capacitor; the orthographic projection of the via hole on the base substrate does not overlap with the orthographic projection of the common electrode line on the base substrate.

[0009] In the array substrate provided by the present invention, the orthographic projection of the drain electrode on the base substrate does not overlap with the orthographic projection of the common electrode line on the array substrate.

[0010] The array substrate provided by the present invention further comprises data lines and gate lines that cross each other horizontally and vertically; the gate lines are connected to the gate electrodes, and the data lines are connected to the source electrodes;

[0011] The gate lines and the data lines are arranged to form a plurality of pixel areas arranged in an array, and the pixel electrodes are located within each pixel area;

[0012] The common electrode line is located in each pixel area and extends in a direction parallel to the periphery of the pixel electrode; the orthographic projection of the common electrode line on the base substrate at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate.

[0013] In the array substrate provided by the present invention, the orthographic projections of the data lines on the base substrate do not overlap with the orthographic projections of the common electrode lines on the base substrate, and the orthographic projections of the gate lines on the base substrate do not overlap with the orthographic projections of the common electrode lines on the base substrate.

[0014] In the array substrate provided by the present invention, the common electrode line includes a first portion extending in a direction parallel to the data line; the width of the first portion is greater than the width of the data line.

[0015] In the array substrate provided by the present invention, the width of the first part is 5.0μm to 5.5μm; the width of the data line is 4.50μm to 5.0μm; the width of the overlapping area between the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the first part on the base substrate is 3.25μm to 3.75μm.

[0016] In the array substrate provided by the present invention, the common electrode lines located on both sides of the data line are electrically connected through the connecting line.

[0017] In the array substrate provided by the present invention, the distance between the orthographic projection of the via hole on the base substrate and the orthographic projection of the common electrode line on the base substrate is greater than 5 μm.

[0018] In the array substrate provided by the present invention, the common electrode line is provided in the same layer as the gate electrode and is spaced apart from the gate electrode.

[0019] The second aspect of the present invention further provides a display panel comprising the array substrate of any one of the above items, an opposing substrate and a liquid crystal layer located between the array substrate and the opposing substrate; the opposing substrate further comprises a common electrode layer for forming a deflection electric field with the pixel electrode.

[0020] According to a third aspect of the present invention, a display device is provided, comprising any one of the display panels described above.

[0021] The beneficial effects of the present invention are as follows:

[0022] The present invention provides an array substrate, a display panel, and a display device, wherein the array substrate includes a base substrate and a plurality of pixel units located on the base substrate. Each pixel unit includes a thin film transistor and a pixel electrode; the pixel electrode is located on the side of the thin film transistor facing away from the base substrate; a passivation insulating layer is provided between the pixel electrode and the thin film transistor, and the pixel electrode is electrically connected to the drain electrode of the thin film transistor via a via penetrating the passivation insulating layer. The array substrate also includes a common electrode line located on the side of the drain electrode facing away from the pixel electrode; the portion where the common electrode line overlaps with the pixel electrode forms a storage capacitor; the orthographic projection of the via on the base substrate does not overlap with the orthographic projection of the common electrode line on the base substrate, thereby preventing a short circuit between the drain electrode and the common electrode line and reducing the probability of defective dots and lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings introduced below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A top view of an array substrate in the related art;

[0025] Figure 2 is a cross-sectional view of an array substrate in the related art;

[0026] Figure 3 One of the top views of the array substrate provided in an embodiment of the present invention;

[0027] Figure 4 This is a cross-sectional view of an array substrate provided in an embodiment of the present invention;

[0028] Figure 5 A second cross-sectional view of the array substrate provided in an embodiment of the present invention;

[0029] Figure 6 A second top view of the array substrate provided in an embodiment of the present invention;

[0030] Figure 7 A third cross-sectional view of an array substrate provided in an embodiment of the present invention;

[0031] Figure 8 A partial schematic diagram of an array substrate provided by an embodiment of the present invention;

[0032] Figure 9 A partial enlarged view provided for an embodiment of the present invention;

[0033] Figure 10A signal crosstalk simulation diagram provided by an embodiment of the present invention;

[0034] Figure 11 A third cross-sectional view of an array substrate provided in an embodiment of the present invention;

[0035] Figure 12 This is a schematic cross-sectional structural diagram of a display device provided by an embodiment of the present invention.

[0036] Among them, 1-base substrate, 2-gate line, 21-gate, 3-data line, 31-source electrode, 32-drain electrode, K-opening, 4-active layer, 5-common electrode line, 51-first part, 52-second part, 6-pixel electrode, 7-passivation insulating layer, T-thin film transistor, S-pixel area, H-via, 100-display panel, 110-array substrate, 120-opposite substrate, 130-liquid crystal layer, 200-backlight module. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained with reference to the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportion.

[0038] Figure 1 A top view of an array substrate in the related art; Figure 2 It is a cross-sectional view of an array substrate in the related art.

[0039] A liquid crystal display (LCD) panel includes an array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate. Figure 1 and Figure 2As shown, the array substrate includes a thin film transistor T and a pixel electrode 6 located above the thin film transistor T. The thin film transistor includes a gate 21, a source electrode 31, a drain electrode 32, and an active layer 4. The drain electrode 32 is separated from the pixel electrode 6 by a passivation insulating layer 7, and the drain electrode 32 and the pixel electrode 6 are connected via a via H penetrating the passivation insulating layer 7. When displaying an image, an image signal voltage is input to the pixel electrode 6 through the drain electrode 32, thereby forming an electric field between the array substrate and the color filter substrate that deflects the liquid crystal molecules in the liquid crystal layer, thereby displaying the image.

[0040] During image display, in order to maintain the image signal voltage of the pixel electrode 6 during a frame period, a storage capacitor (CS) needs to be formed in the array substrate to maintain the image signal voltage of the pixel electrode. Currently, there is a solution based on forming a storage capacitor based on a common electrode line and a pixel electrode.

[0041] For example, if Figure 1 and Figure 2 As shown, in a related solution, in order to increase the storage capacitance, a common electrode line 5 is provided on the side of the drain electrode 32 away from the pixel electrode 6, and the portion where the common electrode line 5 overlaps with the pixel electrode 6 forms a storage capacitance. And because the drain electrode of a thin film transistor is usually made of an opaque material, such as gold, silver, chromium or titanium, a common electrode line 5 is usually also provided directly below the drain electrode 32 to further increase the storage capacitance without reducing the aperture ratio of the pixel. However, after adopting this solution, the incidence of poor dot and line problems is high, resulting in dark spots or dark lines on the display screen, affecting the display effect.

[0042] Based on extensive experiments and analysis, the present invention discovered that the main reason for the poor dot line performance in the above-mentioned solution is that, during the fabrication of the common electrode line 5, foreign matter (paticle) is easily introduced into the film layer of the common electrode line 5, resulting in an uneven surface of the common electrode line 5. Where the foreign matter is present, the surface of the common electrode line 5 bulges toward the side of the drain electrode 32. This results in a thinner insulating layer when depositing the insulating layer between the common electrode line 5 and the drain electrode 32 and when fabricating the drain electrode 32. When the passivation insulating layer 7 is subsequently etched to form the via H for connecting the pixel electrode 6 to the drain electrode 32, if the via H coincides with the location of the foreign matter, perforation of the drain electrode 32 and the insulating layer is easily caused. Ultimately, after the pixel electrode 6 is deposited, the drain electrode 32 and the common electrode line 5 are short-circuited, resulting in poor dot line performance. The incidence of poor dot line performance in the related art is approximately 3% to 6%, resulting in significant economic losses.

[0043] In view of this, an embodiment of the present invention provides an array substrate that can solve the above problems.

[0044] Figure 3 One of the top views of the array substrate provided in an embodiment of the present invention; Figure 4 This is a cross-sectional view of an array substrate provided in an embodiment of the present invention; Figure 5 This is the second cross-sectional view of the array substrate provided in the embodiment of the present invention.

[0045] In the embodiment of the present invention, Figures 3 to 5 As shown, the array substrate includes: a base substrate 1 , a plurality of pixel units and a common electrode line 5 .

[0046] The base substrate 1 is located at the bottom of the array substrate and is used to support the various film layers on the array substrate. The shape of the base substrate 1 adapts to the shape of the array substrate and can be square, rectangular, or circular, etc., in specific implementations, but this is not limited here. The base substrate 1 can be made of a transparent material, specifically glass or resin, etc., but this is not limited here.

[0047] Multiple pixel units are located on a substrate 1. Each pixel unit includes a thin film transistor T and a pixel electrode 6. The thin film transistor T acts as a drive switch, inputting an image signal voltage to the pixel electrode 6. The pixel electrode 6 is used to form an electric field that deflects the liquid crystal molecules in the liquid crystal layer, thereby displaying an image.

[0048] The thin film transistor T is located between the pixel electrode 6 and the base substrate 1, and includes a gate, an active layer, a source electrode, and a drain electrode. Figure 4 As shown, the gate 21 is located between the active layer 4 and the base substrate 1, and the orthographic projection of the gate 21 on the base substrate 1 at least partially overlaps with the orthographic projection of the active layer 4 on the base substrate. The source electrode 31 and the drain electrode 32 are respectively located on both sides of the active layer 4 and are electrically connected to the active layer 4. By applying a voltage to the gate 21, a conductive channel is formed between the source electrode 31 and the drain electrode 32, thereby turning on the thin film transistor T. In a specific implementation, as shown in FIG. Figure 4 As shown, the source electrode 31 can be a "U"-shaped structure, and the drain electrode 32 is partially located within the groove of the "U"-shaped structure, thereby increasing the channel length and improving the gate control capability. The source electrode 31 can also be other shapes, which are not limited here.

[0049] A passivation insulating layer 7 is further provided between the pixel electrode 6 and the thin film transistor T. The passivation insulating layer 7 can play the role of insulation and planarization. In specific implementation, the passivation insulating layer 7 can be made of materials such as silicon oxide, silicon nitride, silicon oxynitride and transparent resin, which are not limited here. Figure 4 As shown, the pixel electrode 6 is electrically connected to the drain electrode 32 of the thin film transistor T through a via hole H penetrating the passivation insulating layer 7 .

[0050] The common electrode line 5 is located on the side of the drain electrode 32 away from the pixel electrode 6. There is at least a partial overlap between the common electrode line 5 and the pixel electrode 6. The overlapping portion of the common electrode line 5 and the pixel electrode 6 forms a storage capacitor.

[0051] In the embodiment of the present invention, Figure 4 As shown, the orthographic projection of the via hole H on the base substrate 1 does not overlap with the orthographic projection of the common electrode line 5 on the base substrate. Figure 4 As shown, an insulating layer is further provided between the drain electrode 32 and the common electrode line 5, and the orthographic projection of the via hole H on the base substrate 1 does not overlap with the orthographic projection of the common electrode line 5 on the base substrate, thereby preventing the insulating layer and the drain electrode 32 from being thinner due to the presence of foreign matter in the common electrode line 5 directly below the via hole H. When the passivation insulating layer 7 is etched, the insulating layer and the drain electrode 32 are prevented from being perforated, thereby preventing the drain electrode 32 and the common electrode line 5 from being short-circuited, thereby reducing the probability of point and line defects.

[0052] In some embodiments, as Figure 4 As shown, the distance D between the orthographic projection of the via hole H on the base substrate 1 and the orthographic projection of the common electrode line 5 on the base substrate 1 is greater than 5 μm. In actual implementation, since the size of foreign matter introduced when manufacturing the common electrode line 5 is generally around 5 μm, setting the distance D between the orthographic projection of the via hole H on the base substrate 1 and the common electrode line 5 on the base substrate 1 to be greater than 5 μm can avoid dot and line defects caused by foreign matter introduced by the common electrode line 5.

[0053] When implementing it specifically, Figure 5 As shown, in the process of etching the passivation insulating layer 7 to form the via hole H, since the side of the passivation insulating layer 7 away from the base substrate 1 is etched first, and the side of the passivation insulating layer 7 close to the base substrate 1 is etched later, the opening size of the finally formed via hole H gradually decreases from the side away from the base substrate 1 to the side close to the base substrate 1. In the embodiment of the present invention, the distance D between the orthographic projection of the via hole H on the base substrate 1 and the orthographic projection of the common electrode line 5 on the base substrate 1 can specifically be the distance between the orthographic projection of the bottom of the via hole H on the base substrate 1 and the orthographic projection of the common electrode line 5 on the base substrate 1.

[0054] In some embodiments, as Figures 3 and 4 As shown, the orthographic projection of the drain electrode 32 on the base substrate 1 and the orthographic projection of the common electrode line 5 on the base substrate 1 have a partially overlapping area. Figures 3 and 4As shown, a common electrode line 5 is provided below the drain electrode 32, and an opening K is provided on the common electrode line 5. The orthographic projection of the via H on the base substrate 1 is located within the orthographic projection of the opening K on the base substrate 1. In the area outside the opening K, the orthographic projection of the drain electrode 32 on the base substrate 1 overlaps with the orthographic projection of the common electrode line 5 on the base substrate 1, so that the size of the storage capacitor can be increased by utilizing the overlapping area.

[0055] Figure 6 A second top view of the array substrate provided in an embodiment of the present invention; Figure 7 A third cross-sectional view of an array substrate provided in an embodiment of the present invention; Figure 8 A partial schematic diagram of an array substrate provided by an embodiment of the present invention.

[0056] In some embodiments, as Figure 6 and Figure 7 As shown, the orthographic projection of the drain electrode 32 on the base substrate 1 does not overlap with the orthographic projection of the common electrode line 5 on the array substrate 1, thereby minimizing the impact of foreign matter introduced during the manufacture of the common electrode line 5 on the thickness of the drain electrode 32 and avoiding the problem of short circuit between the drain electrode 32 and the common electrode line 5.

[0057] like Figure 8 As shown, typically, the drain electrode 32 has a length of approximately 20 μm in the horizontal direction v and a length of approximately 25 μm in the vertical direction h. When manufacturing the common electrode line 5, an opening having a length of 20 μm to 25 μm in the horizontal direction v and a length of approximately 25 μm to 30 μm in the vertical direction h can be formed below the drain electrode 32. In specific implementations, the size of the opening of the common electrode line 5 can be determined based on the actual size of the drain electrode 32 and is not limited here.

[0058] In the embodiment of the present invention, Figure 3 and Figure 6 As shown, the array substrate further includes data lines 3 and gate lines 2 that intersect horizontally and vertically. The gate line 2 is connected to the gate electrode 21 and is used to apply a gate control voltage to the gate electrode 21 to conduct between the source electrode 31 and the drain electrode 32. The data line 3 is connected to the source electrode 31 and is used to input an image signal voltage to the thin film transistor T and then input to the pixel electrode through the drain electrode 32.

[0059] In a specific implementation, the gate line 2 and the gate electrode 21 can be provided in the same layer and manufactured at the same time, and the data line 3 and the source electrode 31 can be provided in the same layer and manufactured at the same time, which is not limited here.

[0060] The gate lines 2 and data lines 3 are arranged to form a plurality of pixel regions S in an array, and the pixel electrodes 6 are located in each pixel region S. The common electrode lines 5 are located in each pixel region and extend in a direction parallel to the periphery of the pixel electrodes 6 to form a ring structure.

[0061] In some embodiments, as Figure 3 and Figure 6 As shown, the common electrode line 5 includes a first portion 51 extending in a direction parallel to the data line 3 and a second portion 52 perpendicular to the first portion 51. The common electrode line 5 surrounds the pixel electrode 6. The orthographic projection of the edge of the pixel electrode 6 on the substrate 1 at least partially overlaps with the orthographic projection of the first portion 51 on the substrate 1 and the orthographic projection of the second portion 52 on the substrate 1. In a specific implementation, the orthographic projection of the common electrode line 5 on the substrate 1 can completely fall within the orthographic projection of the pixel electrode 6 on the substrate 1, and a large storage capacitance exists between the common electrode line 5 and the pixel electrode 6. Due to the limitations of process accuracy and aperture ratio, the orthographic projection of the common electrode line 5 on the substrate 1 can be partially located outside the orthographic projection of the pixel electrode 6 on the substrate 1, which is not limited here.

[0062] In some embodiments, as Figure 3 and Figure 6 As shown, the orthographic projection of the data line 3 on the substrate 1 does not overlap with the orthographic projection of the common electrode line 5 on the substrate 1 and the orthographic projection of the pixel electrode 6 on the substrate 1, and the orthographic projection of the gate line 2 on the substrate 1 does not overlap with the orthographic projection of the common electrode line 5 on the substrate 1 and the orthographic projection of the pixel electrode 6 on the substrate 1. In specific implementations, it is necessary to ensure that a certain distance exists between the data line 3 and the common electrode line 5 and the pixel electrode 6, as well as between the gate line 2 and the common electrode line 5 and the pixel electrode 6, so as to avoid disturbance of the storage capacitor between the common electrode line 5 and the pixel electrode 6 when the gate line 2 and the data line 3 input a signal voltage, thereby avoiding flicker.

[0063] Figure 9 A partial enlarged view provided for an embodiment of the present invention; Figure 10 This is a signal crosstalk simulation diagram provided by an embodiment of the present invention.

[0064] exist Figures 6-7 In the illustrated embodiment, because the orthographic projection of the drain electrode 32 on the base substrate 1 does not overlap with the orthographic projection of the common electrode line 5 on the array substrate 1, the overlapping area between the pixel electrode 6 and the common electrode 5 is reduced, and the storage capacitance formed between the pixel electrode 6 and the common electrode 5 is reduced. In some embodiments, the first portion 51 of the pixel electrode 6 and the common electrode 5 can be simultaneously expanded outward toward the side closer to the data line 3 to increase the area of ​​the overlapping area between the orthographic projection of the pixel electrode 6 on the base substrate 1 and the orthographic projection of the common electrode 5 on the base substrate 1, thereby compensating for the decrease in storage capacitance caused by the reduction in the area of ​​the common electrode line 5 below the drain electrode 32.

[0065] For example, if Figure 9As shown, in the related art, on both sides of the data line 3, the width W1 of the first portion 51 of the common electrode line 5 is usually about 4.5μm, and the width W2 of the data line 3 is usually about 5.5μm. The width of the overlapping area of ​​the orthographic projection of the first portion 51 of the common electrode line 5 on the base substrate 1 and the orthographic projection of the data line 3 on the base substrate 1 is W, and the value of W depends on the process accuracy. In the embodiment of the present invention, the width of the first portion 51 of the common electrode line 5 can be expanded outward to one side of the data line 3 by 0.5μm to 1μm. After the expansion, the width W of the first portion 51 of the common electrode line 5 is 11 The width of the overlapped area between the orthographic projection of the first portion 51 of the common electrode line 5 on the base substrate 1 and the orthographic projection of the data line 3 on the base substrate 1 is 5.0μm to 5.5μm, and the width of W′ is increased by 0.5μm to 1μm compared to W, and the range is 3.25μm to 3.75μm, thereby ensuring that the size of the storage capacitor meets the requirements. In the embodiment of the present invention, the common electrode line 5 and the pixel electrode 6 are simultaneously expanded toward the side close to the data line 3, thereby increasing the storage capacitance while avoiding a decrease in the pixel aperture ratio.

[0066] While the common electrode line 5 and the pixel electrode 6 are expanded, the data line 3 can be retracted. Figure 9 As shown, the data line 3 can be retracted by 0.5 μm to 1 μm, and the width W of the retracted data line 3 is 22 The distance between the pixel electrode 6 and the data line 3 is 4.5 μm to 5.0 μm to ensure that there is a sufficient distance between the pixel electrode 6 and the data line 3 to avoid signal crosstalk. In specific implementation, after the common electrode line 5 and the pixel electrode 6 are expanded and the data line 3 is retracted, it is necessary to ensure that the distance between the orthographic projection of the pixel electrode 6 on the substrate 1 and the orthographic projection of the data line 3 on the substrate 1 is greater than 4.05 μm to avoid signal crosstalk. Figure 10 As shown, the horizontal axis represents the offset of the actual distance between the orthographic projection of the pixel electrode 6 on the substrate 1 and the orthographic projection of the data line 3 on the substrate 1 compared to the designed distance, and the vertical axis represents the value of (Cpd-Cpd′) / CST, wherein Cpd represents the coupling capacitance generated when the distance between the pixel electrode 6 and the data line 3 is the designed distance, Cpd′ represents the change in coupling capacitance caused by the distance deviation between the pixel electrode 6 and the data line 3 compared to the designed distance, and CST represents the storage capacitance. The embodiment of the present invention simulates the signal crosstalk situation after the common electrode line 5 and the pixel electrode 6 are expanded by 1μm and the data line 3 is retracted by 1μm. The simulation curve of the embodiment of the present application (dashed line in the figure) has a high degree of overlap with the standard curve (solid line in the figure) obtained by simulating the signal crosstalk of the mass-produced product, and the error is within 0.1%. The risk of signal crosstalk is small, meeting the mass production requirements.

[0067] In the embodiment of the present invention, Figure 9As shown, while the common electrode line 5 and the pixel electrode 6 are expanded, the data line 3 is retracted, and the width of the first portion 51 of the common electrode line 5 is greater than the width of the data line 3. The width direction of the first portion 51 and the width direction of the data line 3 are perpendicular to the extension direction of the first portion 51.

[0068] In some embodiments, the common electrode line 5 can also be expanded inward toward the inside of the pixel area S to increase the area of ​​the overlapping region between the pixel electrode 6 and the common electrode 5, compensating for the decrease in storage capacitance caused by the reduction in the area of ​​the common electrode line 5 below the drain electrode 32. For example, in the related art, the width W1 of the common electrode line 5 is usually about 4.5μm. In the embodiment of the present invention, the width of the data line 3 and the size of the pixel electrode 6 can be kept unchanged, and the width W1 of the common electrode line 5 can be expanded by 0.5μm to 1μm toward the inside of the pixel area S, thereby increasing the width of the overlapping region between the common electrode line 5 and the data line 3 and improving the storage capacitance. The use of the internal expansion method can avoid changes to the width of the data line 3 and the size of the pixel electrode 6, ensuring process stability.

[0069] When forming a display panel, to prevent the metal traces in the array substrate from reflecting external light and affecting the display effect, the data lines 3, gate lines 2, common electrode lines 5, etc. in the array substrate are typically shielded by a black matrix in the counter substrate. In specific implementation, after the width W1 of the common electrode lines 5 is expanded inwardly of the pixel area S, the area of ​​the black matrix in the counter substrate needs to be correspondingly expanded so that the orthographic projection of the black matrix on the array substrate covers the expanded common electrode lines 5 to prevent light reflection.

[0070] In some embodiments, as Figure 3 and Figure 6 As shown, the common electrode lines 5 on both sides of the data line 3 are electrically connected by connecting wires, thereby preventing a common voltage difference between two adjacent pixel regions S on both sides of the data line 3, improving the uniformity of the common voltage, and preventing flicker. In specific implementations, the common electrode lines 5 and the connecting wires can be formed simultaneously through a patterning process, which is not limited here.

[0071] In some embodiments, the common electrode lines 5 located on both sides of the data line 3 may also be disconnected, which is not limited here.

[0072] In some embodiments, as Figure 4 and Figure 7 As shown, the common electrode line 5 and the gate 2 are arranged in different film layers. Figure 4As shown, the common electrode line 5 can be disposed between the film layer where the gate 2 is located and the film layer where the drain electrode 32 is located, and the common electrode line 5 and the gate 2, as well as the common electrode line 5 and the drain electrode 32, are separated by an insulating layer. Placing the common electrode line 5 and the gate 2 in different film layers can increase the distance between the common electrode line 5 and the gate 2, reduce the risk of signal crosstalk, and simplify the circuit design difficulty of the film layer where the gate 2 is located.

[0073] Figure 11 This is the third cross-sectional view of the array substrate provided in an embodiment of the present invention.

[0074] In some embodiments, as Figure 11 As shown, the common electrode line 5 is provided in the same layer as the gate 2 and is spaced apart from the gate 2. In specific implementation, the common electrode line 5 and the gate 2 can be formed simultaneously in the same film layer through a patterning process to reduce the thickness of the array substrate and simplify the manufacturing process.

[0075] The array substrate provided by the embodiment of the present invention can reduce the probability of occurrence of point line defects to 0% by setting the orthographic projection of the drain electrode 32 on the base substrate 1 not to overlap with the orthographic projection of the common electrode line 5 on the array substrate 1, and simultaneously performing an outward expansion process on the common electrode line 5 and the pixel electrode 6 and an inward contraction process on the data line 3. At the same time, it can ensure the size of the storage capacitor formed by the common electrode line 5 and the pixel electrode 6, and avoid signal crosstalk between the common electrode line 5 and the data line 3.

[0076] Figure 12 This is a schematic cross-sectional structural diagram of a display device provided by an embodiment of the present invention.

[0077] An embodiment of the present invention further provides a display panel.

[0078] The display panel provided by the embodiment of the present invention may be a liquid crystal display panel. Specifically, it may be a twisted nematic (TN) type liquid crystal display panel. Figure 12 As shown, the liquid crystal display panel includes the array substrate 110 provided in any of the above embodiments, an opposite substrate 120, and a liquid crystal layer 130 located between the array substrate 110 and the opposite substrate 120. The opposite substrate 120 also includes a common electrode layer for forming a deflection electric field with the pixel electrodes in the array substrate 110 to drive the deflection of liquid crystal molecules in the liquid crystal layer 130 to display images.

[0079] During specific implementation, the display panel may also be other types of display panels, which is not limited here.

[0080] The display panel provided by the embodiment of the present invention includes the array substrate provided by any of the above embodiments. In specific implementation, it has the same technical effects as the array substrate provided by any of the above embodiments, which will not be described in detail here.

[0081] An embodiment of the present invention further provides a display device, which includes the display panel provided by any of the above embodiments.

[0082] Specifically, if Figure 12 As shown, when the display panel is a liquid crystal display panel, the display device further includes a backlight module 200. The display panel 100 is located on the light-emitting side of the backlight module 200, and is used to receive light emitted by the backlight module 200 and modulate the incident light to display an image.

[0083] In specific implementation, the display device may also be other display devices, which is not limited here. The display device provided by the embodiment of the present invention includes the display panel provided by any of the above embodiments, and in specific implementation, has the same technical effects as the display panel provided by any of the above embodiments, which is not described in detail here.

[0084] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0085] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of pixel units are located on the base substrate; Each of the pixel units includes a thin film transistor and a pixel electrode; The pixel electrode is located on a side of the thin film transistor facing away from the substrate; a passivation insulating layer is provided between the pixel electrode and the thin film transistor, and the pixel electrode is electrically connected to the drain electrode of the thin film transistor via a via hole penetrating the passivation insulating layer; the source electrode and the drain electrode of the thin film transistor are respectively located on both sides of the active layer of the thin film transistor; a common electrode line located on a side of the drain electrode away from the pixel electrode; a storage capacitor is formed at a portion where the common electrode line overlaps the pixel electrode; The orthographic projection of the via hole on the base substrate does not overlap with the orthographic projection of the common electrode line on the base substrate; An orthographic projection of the drain electrode on the base substrate and an orthographic projection of the common electrode line on the array substrate have a partially overlapping area.

2. The array substrate according to claim 1, wherein: It also includes data lines and gate lines that cross each other horizontally and vertically; the gate lines are connected to the gate electrodes, and the data lines are connected to the source electrodes; The gate lines and the data lines are arranged to form a plurality of pixel areas arranged in an array, and the pixel electrodes are located within each of the pixel areas; The common electrode line is located in each pixel area and extends in a direction parallel to the periphery of the pixel electrode; The orthographic projection of the common electrode line on the base substrate at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate.

3. The array substrate according to claim 2, wherein: The orthographic projection of the data line on the base substrate does not overlap with the orthographic projection of the common electrode line on the base substrate, and the orthographic projection of the gate line on the base substrate does not overlap with the orthographic projection of the common electrode line on the base substrate.

4. The array substrate according to claim 3, wherein: The common electrode line includes a first portion extending in a direction parallel to the data line; a width of the first portion is greater than a width of the data line.

5. The array substrate according to claim 4, wherein: The width of the first portion is 5.0 5.5 ; The width of the data line is 4.50 5.0 ; The width of the overlapping area between the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the first part on the substrate is .

6. The array substrate according to claim 2, wherein: The common electrode lines located on both sides of the data line are electrically connected through a connecting line.

7. The array substrate according to any one of claims 1 to 6, wherein: The distance between the orthographic projection of the via hole on the substrate and the orthographic projection of the common electrode line on the substrate is greater than 5 .

8. The array substrate according to any one of claims 1 to 6, wherein: The common electrode line is arranged in the same layer as the gate electrode and is spaced apart from the gate electrode.

9. A display panel, characterized in that: The device comprises an array substrate according to any one of claims 1 to 6, an opposite substrate, and a liquid crystal layer located between the array substrate and the opposite substrate; the opposite substrate further comprises a common electrode layer for forming a deflection electric field with the pixel electrode.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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