Display panel and display device

Abstract

The present application discloses a display panel and a display device. Among them, an output control module and a first main output module are connected in series between a first signal terminal and a main output terminal, and are used for transmitting the signal of the first signal terminal to the main output terminal. The input end of a second main output module is connected to a second signal terminal and is used for transmitting the signal of the second signal terminal to the main output terminal. The frame refresh rate of the first display area of the display panel is a first refresh rate, and the frame refresh rate of the second display area is a second refresh rate. The output control module in the shift register corresponding to the first display area is turned on, and the output control module in the shift register corresponding to the second display area is turned off in at least some time periods. According to the embodiments of the present application, it is beneficial to realize the partitioned and frequency-divided display of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technologies, and more particularly to a display panel and a display device. Background Art

[0002] With the continuous update of display technologies, the refresh rate of display panels has reached new highs. For example, the refresh rate can reach 165 Hz or even exceed 240 Hz. In addition, reducing the power consumption of display panels is also a pursuit goal in this field. Therefore, low-refresh-rate displays have also continued to break through. For example, the low refresh rate can reach 1 Hz.

[0003] In addition, in order to achieve a certain balance between the picture display quality and power consumption, the display panel can support a dynamic refresh rate. For example, the display panel can support a refresh rate of 1 to 120 Hz. In related technologies, only the entire display area of the display panel can be switched simultaneously. For example, the entire display area is switched from one frame rate to another frame rate at the same time. However, this cannot meet the possibility that there are multiple display scenarios in the entire display area of the display panel. For example, a part of the entire display area is displayed at a high refresh rate, and a part of the display area is displayed at a low refresh rate.

[0004] How to enable the display panel to display with different frequencies in different regions has become a technical problem faced by those skilled in the art. Summary of the Invention

[0005] Embodiments of this application provide a display panel and a display device, which are conducive to realizing the display with different frequencies in different regions of the display panel.

[0006] In a first aspect, an embodiment of this application provides a display panel, including a gate driving circuit. The gate driving circuit includes multiple cascaded shift registers. The shift register includes: an output unit, including a first main output module, a second main output module, and an output control module. Among them, the output control module is connected in series with the first main output module between the first signal terminal and the main output terminal, and is used to transmit the signal of the first signal terminal to the main output terminal. The control terminal of the first main output module is connected to the first node, the control terminal of the second main output module is connected to the second node, and the input terminal of the second main output module is connected to the second signal terminal, and is used to transmit the signal of the second signal terminal to the main output terminal. The signals of the first signal terminal and the second signal terminal are both transmitted to the main output terminal through the third node. The display area of the display panel includes a first display area and a second display area. The picture refresh rate of the first display area is the first refresh rate, and the picture refresh rate of the second display area is the second refresh rate. The output control module in the shift register corresponding to the first display area is turned on, and the output control module in the shift register corresponding to the second display area is turned off in at least some periods. The first refresh rate is greater than the second refresh rate. The first signal terminal is used to provide alternating conduction levels and cut-off levels, and the second signal terminal is used to provide cut-off levels.

[0007] In a possible embodiment of the first aspect, the shift register further includes:

[0008] A first node control module, the input end of the first node control module is connected to the start signal end, and the output end of the first node control module is connected to the first node;

[0009] A start signal generation unit, including a first auxiliary output module and a second auxiliary output module. Wherein, the control end of the first auxiliary output module is connected to the first node, the input end of the first auxiliary output module is connected to the first signal end, the control end of the second auxiliary output module is connected to the second node, the input end of the second auxiliary output module is connected to the second signal end, and the output ends of the first auxiliary output module and the second auxiliary output module are connected to the auxiliary output end of the start signal generation unit;

[0010] The auxiliary output end of the start signal generation unit in the i-th stage shift register serves as the start signal end connected to the first node control module in the (i + 1)-th stage shift register.

[0011] In a possible embodiment of the first aspect, both the first auxiliary output module and the first main output module include a transistor controlled by the first node, and both the second auxiliary output module and the second main output module include a transistor controlled by the second node.

[0012] In a possible embodiment of the first aspect, the shift register further includes a first capacitor, one end of the first capacitor is connected to the first node, and the other end is connected to the auxiliary output end.

[0013] In a possible embodiment of the first aspect, the shift register further includes a second capacitor, one end of the second capacitor is connected to the second node, and the other end is connected to the second signal end.

[0014] In a possible embodiment of the first aspect, the output control module is connected between the first signal end and the input end of the first main output module;

[0015] Alternatively, the output control module is connected between the output end of the first main output module and the third node;

[0016] Alternatively, the output control module is connected between the third node and the main output end.

[0017] In a possible embodiment of the first aspect, the main output end is connected to the pixel circuit of the display panel. The shift register includes multiple transistors, and the output control module includes a first transistor, and the channel width-to-length ratio of the first transistor is greater than or equal to the channel width-to-length ratio of other transistors in the shift register.

[0018] In a possible embodiment of the first aspect, the output control module includes a first transistor, and the first transistor is turned on or off under the control of a control signal;

[0019] The first transistor is a P-type transistor, and the sum of the low level of the first signal terminal and the threshold voltage of the first transistor is greater than the conduction level of the control signal;

[0020] Alternatively, the first transistor is an N-type transistor, and the sum of the high level of the first signal terminal and the threshold voltage of the first transistor is less than the conduction level of the control signal.

[0021] In a possible embodiment of the first aspect, the working process of the pixel circuit in the display panel includes a data writing sub-frame, and in the data writing sub-frame, the output control module is turned on;

[0022] The working process of the pixel circuit in the second display area further includes a holding sub-frame, and in the holding sub-frame, the output control module is turned off.

[0023] In a possible embodiment of the first aspect, the display area includes an edge extending in the first direction, the first display area and the second display area are adjacent in the second direction, and the first direction and the second direction intersect;

[0024] The working scenarios of the display panel include a first scenario and a second scenario. In the first scenario, the minimum distance between the boundary line between the first display area and the second display area and the edge is d1, and in the second scenario, the minimum distance between the boundary line between the first display area and the second display area and the edge is d2, and d1≠d2.

[0025] In a possible embodiment of the first aspect, the shift register further includes:

[0026] A second node control module, configured to transmit the signal received at its input terminal to the second node;

[0027] A mutual control module, configured to enable mutual control between the first node and the second node.

[0028] Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a display device, including the display panel described in any one of the embodiments of the first aspect.

[0029] According to the display panel and the display device provided by the embodiments of the present application, the output control module can control whether the conduction level of the first signal terminal can be transmitted to the main output terminal. That is to say, the output control module can control the conduction level output of the main output terminal. Since the output control module corresponding to the first display area with a relatively high refresh frequency is turned on, the conduction level of the first signal terminal can be output at a relatively high refresh frequency, so that the first display area can be displayed at a relatively high refresh frequency. And the output control module corresponding to the second display area with a relatively low refresh frequency is turned off in at least some time periods, so that the conduction level of the first signal terminal can be output at a relatively low refresh frequency, so that the second display area can be displayed at a relatively low refresh frequency. It can be seen that the embodiments of the present application can achieve the effect of dividing the display panel into areas and displaying at different refresh frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] By reading the following detailed description of the non-limiting embodiments with reference to the accompanying drawings, other features, objects and advantages of the present application will become more obvious. Among them, the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0031] Figure 1 FIG. shows a top view structural schematic diagram of the display panel provided by the embodiments of the present application;

[0032] Figure 2 FIG. shows a circuit structural schematic diagram of a pixel circuit in the display panel provided by the embodiments of the present application;

[0033] Figure 3 FIG. shows a circuit structural schematic diagram of a shift register in the display panel provided by the embodiments of the present application;

[0034] Figure 4 FIG. shows another circuit structural schematic diagram of a shift register in the display panel provided by the embodiments of the present application;

[0035] Figure 5 FIG. shows yet another circuit structural schematic diagram of a shift register in the display panel provided by the embodiments of the present application;

[0036] Figure 6 FIG. shows yet another circuit structural schematic diagram of a shift register in the display panel provided by the embodiments of the present application;

[0037] Figure 7 FIG. shows yet another circuit structural schematic diagram of a shift register in the display panel provided by the embodiments of the present application;

[0038] Figure 8 FIG. shows yet another circuit structural schematic diagram of a shift register in the display panel provided by the embodiments of the present application;

[0039] Figure 9 Shows a frame refresh schematic diagram of a display panel provided by an embodiment of the present application;

[0040] Figure 10 Shows a schematic diagram of a partition structure of a display area of a display panel provided by an embodiment of the present application;

[0041] Figure 11 Shows a timing schematic diagram of two refresh frequencies of a display panel provided by an embodiment of the present application;

[0042] Figure 12 Shows a timing schematic diagram of the refresh frequency switching of a display panel provided by an embodiment of the present application;

[0043] Figure 13 Shows another schematic diagram of a partition structure of a display area of a display panel provided by an embodiment of the present application;

[0044] Figure 14 Shows Figure 3 A timing schematic diagram of the shown circuit structure;

[0045] Figure 15 Shows Figure 3 Another timing schematic diagram of the shown circuit structure;

[0046] Figure 16 Shows Figure 3 A simulation timing schematic diagram of the shown circuit structure;

[0047] Figure 17 Shows another circuit structure schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0048] Figure 18 Shows another circuit structure schematic diagram of a shift register in a display panel provided by an embodiment of the present application;

[0049] Figure 19 Shows Figure 18 A timing schematic diagram of the shown circuit structure;

[0050] Figure 20 Shows Figure 18 Another timing schematic diagram of the shown circuit structure;

[0051] Figure 21 Shows a top view structure schematic diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0052] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only provided to provide a better understanding of the present application by showing examples of the present application.

[0053] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, elements defined by the statement "comprising..." do not preclude the existence of additional identical elements in the process, method, article or device comprising the said elements.

[0054] It should be understood that the term "and / or" used herein is only a relationship description of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0055] It should be noted that when an element is expressed as "connected" or "electrically connected" to another element, it can be directly connected to the other element, or there may be one or more intermediate elements therebetween.

[0056] Without departing from the spirit or scope of the present application, various modifications and changes can be made to the present application, which are obvious to those skilled in the art. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0057] Embodiments of the present application provide a display panel and a display device. The embodiments of the display panel and the display device will be described below with reference to the accompanying drawings.

[0058] An embodiment of the present application provides a display panel, which may be an Organic Light Emitting Diode (OLED) display panel or other types of display panels.

[0059] As Figure 1 shown, the display panel 100 provided by the embodiment of the present application may include a gate driving circuit 10, and the gate driving circuit 10 may include a plurality of cascaded shift registers VSR. Exemplarily, the display panel 100 may further include a pixel circuit 20 and a gate signal line 30, and the gate signal line 30 is connected to the shift register VSR and the pixel circuit 20. The signal output by the shift register VSR can control at least some transistors in the pixel circuit 20 to turn on or off, and the pixel circuit 20 can be used to drive a light-emitting element ( Figure 1 not shown in the figure) to emit light for display.

[0060] The gate driving circuit 10 may be located in the non-display area NA of the display panel, and the pixel circuit 20 may be located in the display area AA of the display panel. The pixel circuits 20 may be arranged in an array in a first direction X and a second direction Y, and a plurality of shift registers VSR may be arranged in the second direction Y. The first direction X may be the row direction, and the second direction Y may be the column direction.

[0061] The pixel circuit 20 may have structures such as 7T1C, 8T1C, 2T1C, 4T2C, etc. As an example, the pixel circuit 20 may include transistors T1 to T7 and a storage capacitor Cst as Figure 2 shown, where Figure 2 transistors T1 to T7 are shown as P-type transistors in the figure, VDD represents a first power supply terminal, VSS represents a second power supply terminal, Vref1 represents a first initialization signal, Vref2 represents a second initialization signal, Vdata represents a data signal, S1 and S2 represent scan signals, and EM represents a light emission control signal. For example, the gate driving circuit 10 can be used to output scan signals S1 and S2.

[0062] Figure 2 The 7T1C structure of the pixel circuit shown as

[0063] As Figures 3 to 5 shown, the shift register may include an output unit 11, and the output unit 11 may include a first main output module 111, a second main output module 112, and an output control module 113.

[0064] The output control module 113 and the first main output module 111 are connected in series between a first signal terminal V1 and a main output terminal Gout. The output control module 113 and the first main output module 111 are used to transmit the signal of the first signal terminal V1 to the main output terminal Gout.

[0065] The control terminal of the first main output module 111 is connected to the first node N1.

[0066] The control terminal of the second main output module 112 is connected to the second node N2. The input terminal of the second main output module 112 is connected to the second signal terminal V2. The second main output module 112 is configured to transmit the signal of the second signal terminal V2 to the main output terminal Gout.

[0067] The signals of the first signal terminal V1 and the second signal terminal V2 are both transmitted to the main output terminal Gout through the third node N3.

[0068] The main output terminal Gout can be connected to the gates of at least some of the transistors in the pixel circuit 20 to control the conduction or cutoff of at least some of the transistors in the pixel circuit.

[0069] The first signal terminal V1 can be used to alternately provide a conduction level and a cutoff level, and the second signal terminal V2 can be used to provide a cutoff level.

[0070] One of the conduction level and the cutoff level is a low level, and the other is a high level. For example, for a P-type transistor, the conduction level is a low level and the cutoff level is a high level. Another example is that for an N-type transistor, the conduction level is a high level and the cutoff level is a low level.

[0071] If the signal output from the main output terminal Gout is used to control the P-type transistor in the pixel circuit, the cutoff level provided by the second signal terminal V2 can be a high level, and the conduction level provided by the first signal terminal V1 can be a low level. On the contrary, if the signal output from the main output terminal Gout is used to control the N-type transistor in the pixel circuit, the cutoff level provided by the second signal terminal V2 can be a low level, and the conduction level provided by the first signal terminal V1 can be a high level.

[0072] Provided by this application Figures 3 to 8 Taking the signal output from the main output terminal Gout to control the P-type transistor in the pixel circuit as an example, the first signal terminal V1 may include a clock signal terminal SCK2, and the second signal terminal V2 may include a high-level signal terminal VGH. The clock signal terminal SCK2 is used to provide alternating high and low levels. The high-level signal terminal VGH is used to provide a high level. The high level can be a level of about +7V, and the low level can be a level of about -7V. Here, for the convenience of distinguishing other clock signal terminals, the first signal terminal V1 is denoted as the second clock signal terminal SCK2.

[0073] Please continue to refer to Figure 1, the display area AA of the display panel 100 may include a first display area AA1 and a second display area AA2. The frame refresh rate of the first display area AA1 is a first refresh rate F1, and the frame refresh rate of the second display area AA2 is a second refresh rate F2, where F1 > F2.

[0074] The output control module 113 in the shift register VSR corresponding to the first display area AA1 may remain conductive, and the output control module 113 in the shift register VSR corresponding to the second display area AA2 may be cut off during at least some periods.

[0075] The refresh rate represents the number of images that the display panel can display per second. For example, if a certain display area of the display panel has a first refresh rate F1 of 120 Hz, then the number of images that this display area can display per second is 120 times. If another display area of the display panel has a second refresh rate F2 of 1 Hz, then the number of images that this display area can display per second is 1 time. The higher the refresh rate of the display panel, the better the stability of the displayed image (picture), that is, the better the display quality. The lower the refresh rate of the display panel, the lower the power consumption.

[0076] It can be understood that the shift register VSR corresponding to the first display area AA1 is the shift register among multiple shift registers that can control the frame refresh rate of the first display area AA1. Similarly, the shift register VSR corresponding to the second display area AA2 is the shift register among multiple shift registers that can control the frame refresh rate of the second display area AA2.

[0077] According to the display panel provided by the embodiments of the present application, the output control module 113 can control whether the low level of the first signal terminal V1 can be transmitted to the main output terminal Gout, that is, the output control module 113 can control the low-level output of the main output terminal Gout. Since the output control module 113 corresponding to the first display area with a relatively high refresh rate is conductive, the low level of the first signal terminal V1 can be output at a relatively high refresh rate, so that the first display area can be displayed at a relatively high refresh rate. And the output control module 113 corresponding to the second display area with a relatively low refresh rate is cut off during at least some periods, so that the low level of the first signal terminal V1 can be output at a relatively low refresh rate, so that the second display area can be displayed at a relatively low refresh rate. Thus, it can be seen that the embodiments of the present application can achieve the effect of partitioning the display panel and displaying at different refresh rates.

[0078] As long as the output control module 113 and the first main output unit 111 are connected in series between the first signal terminal V1 and the main output terminal Gout, the output control module 113 can control whether the low level of the first signal terminal V1 can be transmitted to the main output terminal Gout.

[0079] As an example, as Figure 3 shown, the output control module 113 can be connected between the first signal terminal V1 and the input terminal of the first main output module 111.

[0080] As another example, as Figure 4 shown, the output control module 113 can be connected between the output terminal of the first main output module 111 and the third node N3.

[0081] As yet another example, as Figure 5 shown, the output control module 113 can be connected between the third node N3 and the main output terminal Gout. In this case, when the output control module 113 is turned on, the main output terminal Gout can output the signal of the first signal terminal V1 or the signal of the second signal terminal V2; when the output control module 113 is turned off, neither the signal of the first signal terminal V1 nor the signal of the second signal terminal V2 can be transmitted to the main output terminal Gout, and the main output terminal Gout can maintain the signal it received in the previous stage.

[0082] Under the control of the output control module 113, the switching from a high refresh frequency to a low refresh frequency can be achieved. To achieve the switching from a low refresh frequency to a high refresh frequency, as Figures 3 to 5 shown, the shift register may further include a first node control module 12 and a start signal generation unit 13.

[0083] The first node control module 12 can be connected between the start signal terminal SIN and the first node N1. When the first node control module 12 is turned on, the first node control module 12 can transmit the start signal provided by the start signal terminal SIN to the first node N1 to start the shift register to work. As an example, the control terminal of the first node control module 12 can be connected to the first clock signal terminal SCK1.

[0084] The start signal generation unit 13 may include a first auxiliary output module 131 and a second auxiliary output module 132.

[0085] The control terminal of the first auxiliary output module 131 is connected to the first node N1, the input terminal of the first auxiliary output module 131 is connected to the first signal terminal V1, and the output terminal of the first auxiliary output module 131 is connected to the auxiliary output terminal Carry of the start signal generation unit 13.

[0086] The control terminal of the second auxiliary output module 132 is connected to the second node N2, the input terminal of the second auxiliary output module 132 is connected to the second signal terminal V2, and the output terminal of the second auxiliary output module 132 is connected to the auxiliary output terminal Carry of the start signal generation unit 13.

[0087] As Figure 1 shown, the auxiliary output terminal Carry of the start signal generation unit in the i-th stage shift register VSR can be used as the start signal terminal SIN connected to the first node control module in the (i + 1)-th stage shift register VSR. That is to say, the signal output from the auxiliary output terminal Carry of the start signal generation unit in the i-th stage shift register VSR can be used as the start signal of the (i + 1)-th stage shift register VSR.

[0088] In the embodiment of the present application, the difference between the start signal generation unit 13 and the output unit 11 is that the start signal generation unit 13 no longer sets the output control module 113 for controlling whether the signal of the first signal terminal V1 can be transmitted to the auxiliary output terminal Carry. In this way, when the first auxiliary output unit 131 is turned on, the conduction level of the first signal terminal V1 can be transmitted to the auxiliary output terminal Carry. Therefore, the auxiliary output terminal Carry of the start signal generation unit 13 can output a signal with a high refresh frequency. The signal with a high refresh frequency output from the auxiliary output terminal Carry of the start signal generation unit 13 in the i-th stage shift register VSR is used as the start signal of the (i + 1)-th stage shift register VSR. Therefore, when the output control module 113 of the i-th stage shift register VSR is turned off and the output control module 113 of the (i + 1)-th stage shift register VSR is turned on, the main output terminal Gout of the i-th stage shift register VSR can output a signal with a low refresh frequency, and the main output terminal Gout of the (i + 1)-th stage shift register VSR can output a signal with a high refresh frequency. Thus, the switching from a low refresh frequency to a high refresh frequency can be realized.

[0089] It can be understood that the auxiliary output terminal Carry of the start signal generation unit 13 in each stage shift register VSR can output a signal with a high refresh frequency. For example, if the switching is from the second refresh frequency to the first refresh frequency, the auxiliary output terminal Carry of the start signal generation unit 13 in each stage shift register VSR can output a signal with the first refresh frequency.

[0090] Exemplarily, as Figure 1 shown, the start signal terminal connected to the input terminal of the first node control module in the first stage shift register is the pad 41 of the display panel. The pad 41 can be arranged in the non-display area of the display panel. The pad 41 can be connected to the driving chip, and the driving chip can be used to provide an initial start signal and transmit it to the first stage shift register through the pad 41 and the connection line to start the first stage shift register to work.

[0091] The refresh frequency of the signal output from the auxiliary output terminal Carry of the start signal generation unit 13 is equal to the refresh frequency of the start signal provided by terminal 41.

[0092] In some embodiments, as Figures 3 to 5 shown in any of the drawings, the first auxiliary output module 131 and the first main output module 111 each include a transistor controlled by the first node N1. That is to say, the first auxiliary output module 131 and the first main output module 111 have the same structure. For example, the first main output module 111 includes transistor M7, and the first auxiliary output module 131 includes transistor M11. The gates of transistor M7 and transistor M11 are both connected to the first node N1, and the first poles of transistor M7 and transistor M11 are both connected to the first signal terminal V1. The second pole of transistor M7 is electrically connected to the main output terminal Gout, and the second pole of transistor M11 is connected to the auxiliary output terminal Carry.

[0093] The second auxiliary output module 132 and the second main output module 112 each include a transistor controlled by the second node N2. That is to say, the second auxiliary output module 132 and the second main output module 112 have the same structure. For example, the second main output module 112 includes transistor M6, and the second auxiliary output module 132 includes transistor M10. The gates of transistor M6 and transistor M10 are both connected to the second node N2, and the first poles of transistor M6 and transistor M10 are both connected to the second signal terminal V2. The second pole of transistor M6 is electrically connected to the main output terminal Gout, and the second pole of transistor M10 is connected to the auxiliary output terminal Carry.

[0094] In the embodiments of the present application, each output module can realize the output control of the output terminal by including only one transistor, and the output modules with the control terminals connected to the same node and the input terminals connected to the same signal terminal all include transistors, which is beneficial to making the high-level magnitudes output from different output terminals basically the same or the low-level magnitudes output basically the same.

[0095] In some embodiments, as Figure 3 shown, the shift register may further include a first capacitor C1. One end of the first capacitor C1 is connected to the first node N1, and the other end is connected to the auxiliary output terminal Carry. The first capacitor C1 can help stabilize the potential of the first node N1.

[0096] In some embodiments, as Figure 3 shown, the shift register may further include a second capacitor C2. One end of the second capacitor C2 is connected to the second node N2, and the other end is connected to the second signal terminal V2. The second capacitor C2 can help stabilize the potential of the second node N1.

[0097] In some embodiments, as Figure 3As shown, the shift register may further include a second node control module 14 and a mutual control module 15.

[0098] The second node control module 14 may be configured to transmit the signal received at its input terminal to the second node N2. For example, when the potential of the second node N2 is at a low level and the second main output module 112 and the second auxiliary output module 132 can be turned on, the input terminal of the second node control module 14 may be connected to the low-level signal terminal VGL. The low-level signal terminal VGL may provide a signal of about -7V.

[0099] The mutual control module 15 may be configured to enable mutual control between the first node N1 and the second node N2.

[0100] For example, the mutual control module 15 may include a pull-up sub-module composed of transistors M2 and M3 and a pull-down sub-module composed of transistors M41 and M42. The pull-up sub-module may be configured to pull up the potential of the first node N1 under the control of the second node N2, and the pull-down sub-module may be configured to pull down the potential of the second node N2 under the control of the first node N1.

[0101] The shift register may include a plurality of transistors. As an example, as Figure 3 shown, the first node control module 12 may include a transistor M1, the mutual control module 15 includes transistors M2, M3, M41, and M42, the second node control module 14 includes a transistor M5, the second main output module 112 includes a transistor M6, the first main output module 111 includes a transistor M7, the output control module 113 includes a transistor M9, the second auxiliary output module 132 includes a transistor M10, and the first auxiliary output module 131 includes a transistor M11. The shift register may further include a transistor M8.

[0102] The gate of the transistor M1 serves as the control terminal of the first node control module 12, the first pole of the transistor M1 serves as the input terminal of the first node control module 12, and the second pole of the transistor M1 serves as the output terminal of the first node control module 12.

[0103] The gate of the transistor M2 is connected to the second clock signal terminal SCK2, the first pole of the transistor M2 is electrically connected to the first node N1, the second pole of the transistor M2 is connected to the first pole of the transistor M3, the gate of the transistor M3 is connected to the second node N2, and the second pole of the transistor M3 is connected to the high-level signal terminal VGH.

[0104] The gate of the transistor M41 is electrically connected to the first node N1, the first pole of the transistor M41 is connected to the first clock signal terminal SCK1, the second pole of the transistor M41 is connected to the first pole of the transistor M42, the gate of the transistor M42 is connected to the second clock signal terminal SCK2, and the second pole of the transistor M42 is connected to the second node N2.

[0105] The gate of transistor M5 serves as the control terminal of the second node control module 14, the first pole of transistor M5 serves as the input terminal of the second node control module 14, and the second pole of transistor M5 serves as the output terminal of the second node control module 14.

[0106] The gate of transistor M6 serves as the control terminal of the second main output module 112, the first pole of transistor M6 serves as the input terminal of the second main output module 112, and the second pole of transistor M6 serves as the output terminal of the second main output module 112.

[0107] The gate of transistor M7 serves as the control terminal of the first main output module 111, the first pole of transistor M7 serves as the input terminal of the first main output module 111, and the second pole of transistor M7 serves as the output terminal of the first main output module 111.

[0108] The gate of transistor M8 is connected to the low-level signal terminal VGL. The first pole of transistor M8 is connected to the second pole of transistor M1, the first pole of transistor M41, and the first pole of transistor M2. The second pole of transistor M8 is connected to the first node N1.

[0109] The gate of transistor M9 serves as the control terminal of the output control module 113, the first pole of transistor M9 serves as the input terminal of the output control module 113, and the second pole of transistor M9 serves as the output terminal of the output control module 113.

[0110] The gate of transistor M10 serves as the control terminal of the second auxiliary output module 132, the first pole of transistor M10 serves as the input terminal of the second auxiliary output module 132, and the second pole of transistor M10 serves as the output terminal of the second auxiliary output module 132.

[0111] The gate of transistor M11 serves as the control terminal of the first auxiliary output module 131, the first pole of transistor M11 serves as the input terminal of the first auxiliary output module 131, and the second pole of transistor M11 serves as the output terminal of the first auxiliary output module 131.

[0112] It should be noted that when the shift register includes transistor M42, it is more conducive to the working stability of the shift register. If considering the overall size of the shift register, transistor M42 may not be provided, and the second pole of transistor M41 is connected to the second node N2.

[0113] For the convenience of description below, the transistor M9 included in the output control module 113 is referred to as the first transistor M9. The channel width-to-length ratio (W / L) of the first transistor M9 can be greater than or equal to the channel width-to-length ratio of any other transistor in the shift register.

[0114] Since the main output terminal Gout is connected to the pixel circuit of the display panel, the main output terminal Gout has a relatively large load (loading). If the channel width-to-length ratio of the first transistor M9 is relatively large, the driving ability of the signal output by the main output terminal Gout can be improved.

[0115] Exemplarily, in addition to the first transistor M9 and the transistors M10 and M11, the channel width-to-length ratios of the transistors M6 and M7 can be greater than those of the other transistors in the shift register. In addition to the first transistor M9 and the transistors M6 and M7, the channel width-to-length ratios of the transistors M10 and M11 can be greater than those of the other transistors in the shift register.

[0116] In addition, the auxiliary output terminal Carry is not connected to the pixel circuit, and the signal output by the auxiliary output terminal Carry only serves as the start signal for the next-stage shift register. Therefore, the load of the auxiliary output terminal Carry is smaller than that of the main output terminal Gout. Therefore, the channel width-to-length ratios of the transistors M6 and M7 can be greater than those of the transistors M10 and M11.

[0117] As an example, as Figures 3 to 5 shown, the first transistor M9 can be a P-type transistor, and the first transistor M9 is turned on or off under the control of the control signal SW. It can be understood that when the first transistor M9 is a P-type transistor, the first transistor M9 is turned on when the control signal SW is at a low level, and the first transistor M9 is turned off when the control signal SW is at a high level.

[0118] Since there is a voltage loss (loss) in the process of the transistor transmitting the signal, the sum of the low level of the first signal terminal V1 and the threshold voltage Vth of the first transistor M9 is greater than the conduction level of the control signal SW. For example, when the first transistor M9 is a P-type transistor, the low level of the first signal terminal V1 is denoted as vgl, and the conduction level of SW is denoted as SW1, then SW1 < vgl + Vth. In this way, it can be ensured that the first transistor M9 can be turned on.

[0119] As another example, as Figures 6 to 8 shown, the first transistor M9 can be an N-type transistor, and the first transistor M9 is turned on or off under the control of the control signal SW. It can be understood that when the first transistor M9 is an N-type transistor, the first transistor M9 is turned on when the control signal SW is at a high level, and the first transistor M9 is turned off when the control signal SW is at a low level.

[0120] Similarly, due to the voltage loss during the signal transmission of the transistor, the sum of the high level of the first signal terminal V1 and the threshold voltage Vth of the first transistor M9 is less than the conduction level of the control signal SW. For example, when the first transistor M9 is an N-type transistor, the high level of the first signal terminal V1 is denoted as vgh, and the conduction level of SW is denoted as SW2, then SW2 > vgh + Vth. In this way, it can be ensured that the first transistor M9 can be turned on.

[0121] Exemplarily, the control terminal of the output control module 113 in the multi-stage shift register can be connected to the same control signal terminal, and the same control signal terminal can output control signals SW with different levels at different times. For example, the i-th stage shift register to the j-th stage shift register correspond to the first refresh frequency F1, the j + 1-th stage shift register to the p-th stage shift register correspond to the second refresh frequency F2, F1 > F2, i < j, j + 1 < p, then the control signal SW output by the control signal terminal can be the conduction level first and then the cut-off level.

[0122] In some embodiments, the working process of each pixel circuit in the display panel can include a data writing sub-frame (active frame). The working process of the pixel circuit in the second display area can further include a holding sub-frame (Idle Frame). Exemplarily, the working process of the pixel circuit in the first display area can only include a data writing sub-frame, and the working process of the pixel circuit in the second display area can include a data writing sub-frame and a holding sub-frame. In the data writing sub-frame, the data signal (Vdata) can be written into the gate of the driving transistor of the pixel circuit. In the holding sub-frame, the data signal (Vdata) is no longer written into the gate of the driving transistor of the pixel circuit.

[0123] As Figure 9 shown, the data writing sub-frame (active frame) and the holding sub-frame (Idle Frame) are introduced first with a refresh frequency of 60Hz.

[0124] When the refresh frequency is 60Hz, 60 frames are refreshed within 1 second, and the time of each frame = 1s / 60 = 16.67ms.

[0125] When the refresh frequency is reduced, the skip frame method is used for scanning and driving. Taking 30Hz as an example, the refresh is still 60 times per second, but the data signal (Vdata) is written in the 1st / 3rd / 5th / 7th...57th / 59th odd frames as the data writing sub-frame (active frame); the data signal (Vdata) is not written in the 2nd / 4th / 6th / 8th...58th / 60th even frames as the holding sub-frame (Idle Frame). In this way, the line scanning time of 30Hz is the same as that of 60Hz. Additionally, Figure 9The VSYNC in the middle represents the vertical synchronization signal.

[0126] In some embodiments, such as Figure 10 shown, taking the display panel including two first display areas AA1 and one second display area AA2 as an example, the second display area AA2 is located between the two first display areas AA1. The frame refresh rate of the first display area AA1 is the first refresh rate F1, and the frame refresh rate of the second display area AA2 is the second refresh rate F2. For example, if F1 is 120HZ and F2 is 1HZ, then the refresh rate switching sequence of the entire display area is 120HZ~1HZ~120HZ.

[0127] Such as Figure 11 shown, the frame refresh rate of the first display area AA1 is 120HZ, and the working process of the pixel circuit in the first display area AA1 may only include the data writing sub-frame (Active frame). The frame refresh rate of the second display area AA2 is 1HZ, and the working process of the pixel circuit in the second display area AA2 may include the data writing sub-frame (Active frame) and the holding sub-frame (Idle Frame). The refresh rate switching sequence is 120HZ~1HZ~120HZ, and the gate driving circuit needs to output a timing as Figure 12 shown. It can be understood that the main output terminal Gout of the shift register for driving the first display area AA1 needs to output the timing corresponding to 120HZ, and the main output terminal Gout of the shift register for driving the second display area AA2 needs to output the timing corresponding to 1HZ.

[0128] As introduced above, during the data writing sub-frame, the data signal (Vdata) needs to be written. During the holding sub-frame, the data signal (Vdata) is no longer written. To avoid affecting the writing of the data signal during the refresh rate switching process, during the data writing sub-frame, the output control module 113 can remain conducting, and during the holding sub-frame, the output control module 113 can be cut off.

[0129] For example, the output control module 113 is cut off when the control signal SW is at a high level and is conducting when at a low level. The high level can be equal to the level of the high level signal terminal VGH, and the low level can be equal to the level of the low level signal terminal VGL. Such as Figure 10 shown, the two first display areas AA1 may only include the data writing sub-frame, and the control signal SW received by the output control module 113 of the shift register corresponding to the two first display areas AA1 can be at a low level. The second display area AA2 may include the data writing sub-frame and the holding sub-frame, and the control signal SW received by the output control module 113 of the shift register corresponding to the second display area AA2 can be at a high level during the holding sub-frame.

[0130] In the embodiment of the present application, during the data writing sub-frame, the output control module 113 can remain conducting, and during the holding sub-frame, the output control module 113 can be cut off. In this way, during the data writing sub-frame, the waveforms of the main output terminals Gout of the shift registers corresponding to the high refresh rate display area and the low refresh rate display area are normally output, and the transformation of the output waveforms of the main output terminals Gout of the shift registers corresponding to the refresh rate switching all occurs during the holding sub-frame, so that both frequency switching can be realized and the writing of data signals can be prevented from being affected during the refresh rate switching process.

[0131] In some embodiments, please refer to Figure 10 , the display area AA includes a first edge a1 extending along the first direction X. The first display area AA1 and the second display area AA2 are adjacent in the second direction Y, and the first direction and the second direction intersect. For example, the dividing line between one of the first display areas AA1 and the second display area AA2 is L.

[0132] The working scenarios of the display panel may include a first scenario and a second scenario. In the first scenario, the minimum distance between the dividing line L and the first edge a1 is d1, and in the second scenario, the minimum distance between the dividing line L and the first edge a1 is d2, and d1≠d2.

[0133] In this way, the partition position can be not fixed, and the partition positions of the display areas with different refresh rates can be dynamically adjusted according to the scenario requirements and / or the display screen.

[0134] Exemplarily, the control signal SW of the output control module 113 can be synchronized with the scenario requirements or the picture requirements. For example, according to the scenario requirements or the picture requirements, the positions of the display areas with different refresh rates can be determined, and then according to the positions of the display areas with different refresh rates, the level of the control signal SW can be determined.

[0135] To better understand that the shift register provided in the embodiment of the present application can realize the switching of the refresh rate, the working process of the shift register will be described below with Figure 3 the circuit structure shown.

[0136] Please refer to Figure 3 and Figure 14 , during the stages t11 to t14, the control signal SW is at a high level, and the first transistor M9 is cut off.

[0137] During the stage t11, the start signal terminal SIN and the first clock signal terminal SCK1 provide low levels, the second clock signal terminal SCK2 provides a high level, the transistors M1 and M5 are conducting, the potentials of the first node N1 and the second node N2 are both at low levels, the transistors M10, M11, M6, and M7 are conducting, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

[0138] At stage t12, the start signal terminal SIN and the first clock signal terminal SCK1 provide high levels, the second clock signal terminal SCK2 provides a low level, the potential of the first node N1 remains low, the potential of the second node N2 becomes high, the transistors M11 and M7 are turned on, and the auxiliary output terminal Carry outputs a low level. However, since the first transistor M9 is cut off, the main output terminal Gout remains high.

[0139] At stage t13, the start signal terminal SIN and the second clock signal terminal SCK2 provide high levels, the first clock signal terminal SCK1 provides a low level, the potential of the first node N1 becomes high, the potential of the second node N2 becomes low, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

[0140] At stage t14, the start signal terminal SIN and the first clock signal terminal SCK1 provide high levels, the second clock signal terminal SCK2 provides a low level, the potential of the first node N1 remains high, the potential of the second node N2 remains low, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

[0141] In the following, regardless of the level of the control signal SW, since the transistor M7 is cut off, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level. Therefore, except for the control signal SW, the following is a cycle of stages t13 and t14.

[0142] It can be seen that when the control signal SW is at a high level, the auxiliary output terminal Carry outputs a normal waveform, and the signal of the main output terminal Gout is high.

[0143] It should be noted that Figure 14 in the figure, the control signal SW is shown as a low level in the stage after stage t14, which is not used to limit this application. For example, in other examples, the control signal SW can be at a high level in the stage after stage t14.

[0144] Please refer to Figure 3 and Figure 15 , from stage t15 to stage t18, the control signal SW is at a low level, and the first transistor M9 is turned on.

[0145] At stage t15, the start signal terminal SIN and the first clock signal terminal SCK1 provide low levels, the second clock signal terminal SCK2 provides a high level, the transistors M1 and M5 are turned on, the potentials of the first node N1 and the second node N2 are both low, the transistors M10, M11, M6, and M7 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

[0146] At stage t16, the start signal terminal SIN and the first clock signal terminal SCK1 provide high levels, the second clock signal terminal SCK2 provides a low level, the potential of the first node N1 remains low, the potential of the second node N2 becomes high, the transistors M11 and M7 are turned on, the auxiliary output terminal Carry outputs a low level, and since the first transistor M9 is turned on, the main output terminal Gout outputs a low level.

[0147] At stage t17, the start signal terminal SIN and the second clock signal terminal SCK2 provide high levels, the first clock signal terminal SCK1 provides a low level, the potential of the first node N1 becomes high, the potential of the second node N2 becomes low, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

[0148] At stage t18, the start signal terminal SIN and the first clock signal terminal SCK1 provide high levels, the second clock signal terminal SCK2 provides a low level, the potential of the first node N1 remains high, the potential of the second node N2 remains low, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

[0149] Subsequently, it is a cycle of stages t17 and t18.

[0150] It can be seen that when the control signal SW is at a low level, both the auxiliary output terminal Carry and the main output terminal Gout can output waveforms normally.

[0151] It can be seen that by controlling the conduction or cutoff of the output control module (the first transistor M9), and cooperating with the start signal generation unit (the transistors M10 and M11), the switching from a high refresh rate to a low refresh rate and the switching from a low refresh rate to a high refresh rate can be achieved.

[0152] To further verify the function of the shift register provided in the embodiment of the present application, please refer to Figure 16 the simulation diagram shown. It can be clearly obtained that when the control signal SW is at a high level, the auxiliary output terminal Carry outputs a waveform normally, and the signal of the main output terminal Gout is at a high level; when the control signal SW is at a low level, both the auxiliary output terminal Carry and the main output terminal Gout can output waveforms normally.

[0153] In the above embodiments, the signal output from the main output terminal Gout is used to control the P-type transistor in the pixel circuit as an example. The signal output from the main output terminal Gout of the gate driving circuit provided in the embodiment of the present application can also be used to control the N-type transistor in the pixel circuit.

[0154] AsFigure 17 As shown Figure 17 The same as that of Figure 2 will not be elaborated here. The differences are that transistors T4 and T5 are N-type transistors, and other transistors are P-type transistors. Scanning signals S1N and S2N are used to control the conduction or cutoff of N-type transistors, and scanning signals S1P and S2P are used to control the conduction or cutoff of P-type transistors. The signals output from the main output terminal Gout of the gate driving circuit provided in the embodiment of the present application may include scanning signals S1N and S2N.

[0155] When the signal output from the main output terminal Gout is used to control the N-type transistors in the pixel circuit, as Figure 18 shown, the first signal terminal V1 may include a clock signal terminal SCK2, and the second signal terminal V2 may include a low-level signal terminal VGL. The cutoff level provided by the second signal terminal V2 may be a low level, and the conduction level provided by the first signal terminal V1 may be a high level.

[0156] In addition Figure 18 the difference from Figure 3 is that Figure 18 the transistors shown may all be N-type transistors. The first pole of transistor M5 is connected to the high-level signal terminal VGH, and the second pole of transistor M3 is connected to the low-level signal terminal VGL. The gate of transistor M8 is connected to the high-level signal terminal.

[0157] When the signal output from the shift register is used to control the N-type transistors in the pixel circuit, its working process may be as follows:

[0158] Please refer to Figure 18 and Figure 19 . In the stages from t21 to t24, the control signal SW is at a low-high level, and the first transistor M9 is cutoff.

[0159] In the t21 stage, the start signal terminal SIN and the first clock signal terminal SCK1 provide high levels, the second clock signal terminal SCK2 provides a low level, transistors M1 and M5 are conductive, the potentials of the first node N1 and the second node N2 are both high levels, transistors M10, M11, M6, and M7 are conductive, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

[0160] In the t22 stage, the start signal terminal SIN and the first clock signal terminal SCK1 provide low levels, the second clock signal terminal SCK2 provides a high level, the potential of the first node N1 remains at a high level, the potential of the second node N2 becomes a low level, transistors M11 and M7 are conductive, the auxiliary output terminal Carry outputs a high level, but since the first transistor M9 is cutoff, the main output terminal Gout remains at a low level.

[0161] In the t23 stage, the start signal terminal SIN and the second clock signal terminal SCK2 provide low levels, the first clock signal terminal SCK1 provides a high level, the potential of the first node N1 becomes low, the potential of the second node N2 becomes high, the transistors M10 and M6 are turned on, and the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

[0162] In the t24 stage, the start signal terminal SIN and the first clock signal terminal SCK1 provide low levels, the second clock signal terminal SCK2 provides a high level, the potential of the first node N1 remains low, the potential of the second node N2 remains high, the transistors M10 and M6 are turned on, and the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a high level.

[0163] In the following, regardless of the level of the control signal SW, since the transistor M7 is cut off, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level. Therefore, except for the control signal SW, the following is a cycle of the t23 stage and the t24 stage.

[0164] It can be seen that when the control signal SW is at a low level, the auxiliary output terminal Carry outputs a normal waveform, and the signal of the main output terminal Gout is at a low level.

[0165] It should be noted that Figure 19 in the figure, the control signal SW is shown as a high level in the stage after the t24 stage, which is not used to limit this application. For example, in other examples, the control signal SW may be at a low level in the stage after the t24 stage.

[0166] Please refer to Figure 18 and Figure 20 , in the t25 stage to the t28 stage, the control signal SW is at a high level, and the first transistor M9 is turned on.

[0167] In the t25 stage, the start signal terminal SIN and the first clock signal terminal SCK1 provide high levels, the second clock signal terminal SCK2 provides a low level, the transistors M1 and M5 are turned on, the potentials of the first node N1 and the second node N2 are both high, the transistors M10, M11, M6, and M7 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

[0168] In the t26 stage, the start signal terminal SIN and the first clock signal terminal SCK1 provide low levels, the second clock signal terminal SCK2 provides a high level, the potential of the first node N1 remains high, the potential of the second node N2 becomes low, the transistors M11 and M7 are turned on, the auxiliary output terminal Carry outputs a high level, and since the first transistor M9 is turned on, the main output terminal Gout outputs a high level.

[0169] At stage t27, the start signal terminal SIN and the second clock signal terminal SCK2 provide low levels, the first clock signal terminal SCK1 provides a high level, the potential of the first node N1 becomes low, the potential of the second node N2 becomes high, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

[0170] At stage t28, the start signal terminal SIN and the first clock signal terminal SCK1 provide low levels, the second clock signal terminal SCK2 provides a high level, the potential of the first node N1 remains low, the potential of the second node N2 remains high, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

[0171] Subsequently, it is a cycle of t27 stage and t28 stage.

[0172] It can be seen that when the control signal SW is at a high level, both the auxiliary output terminal Carry and the main output terminal Gout can output waveforms normally.

[0173] It should be noted that the specific structure of the shift register provided in the embodiments of the present application is only some examples and is not used to limit the present application. The technical concept of realizing the refresh frequency switching based on the output control module and / or the start signal generation unit provided in the embodiments of the present application can also be applied to shift registers with other structures, which will not be listed one by one here.

[0174] It should also be noted that the transistors in the embodiments of the present application can be N-type transistors or P-type transistors. For N-type transistors, the conduction level is high and the cut-off level is low. That is, when the gate potential of the N-type transistor is high, it conducts between its first pole and second pole, and when the gate potential of the N-type transistor is low, it turns off between its first pole and second pole. For P-type transistors, the conduction level is low and the cut-off level is high. That is, when the gate potential of the P-type transistor is low, it conducts between its first pole and second pole, and when the gate potential of the P-type transistor is high, it turns off between its first pole and second pole. In specific implementation, the gate of each of the above transistors is used as its control pole, and according to the signal of the gate of each transistor and its type, its first pole can be used as the source pole and the second pole as the drain pole, or its first pole can be used as the drain pole and the second pole as the source pole, which will not be distinguished here. In addition, the conduction level and the cut-off level in the embodiments of the present application are general references. The conduction level refers to any level that can make the transistor conduct, and the cut-off level refers to any level that can make the transistor cut off / turn off.

[0175] Based on the same inventive concept, the present application also provides a display device, including the display panel provided by the present application. Please refer toFigure 21 , Figure 21 is a schematic structural diagram of a display device provided by an embodiment of the present application. Figure 21 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Figure 21 Taking a mobile phone as an example only in the embodiment, the display device 1000 is described. It can be understood that the display device provided by the embodiment of the present application can be other display devices with a display function such as wearable products, computers, televisions, in-vehicle display devices, etc. The present application does not make specific limitations thereto. The display device provided by the embodiment of the present application has the beneficial effects of the display panel provided by the embodiment of the present application. For specific descriptions of the display panel, reference can be made to the above embodiments. Details are not described herein again in this embodiment.

[0176] In accordance with the embodiments of the present application as described above, these embodiments do not describe all details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, Comprising: A gate driving circuit, the gate driving circuit including multiple cascaded shift registers; The shift register includes: An output unit, including a first main output module, a second main output module, and an output control module; Wherein, the output control module and the first main output module are connected in series between a first signal terminal and a main output terminal, for transmitting the signal of the first signal terminal to the main output terminal, the control terminal of the first main output module is connected to a first node, the control terminal of the second main output module is connected to a second node, the input terminal of the second main output module is connected to a second signal terminal, for transmitting the signal of the second signal terminal to the main output terminal, and the signals of the first signal terminal and the second signal terminal are both transmitted to the main output terminal through a third node; The display area of the display panel includes a first display area and a second display area, the frame refresh rate of the first display area is a first refresh rate, the frame refresh rate of the second display area is a second refresh rate, the output control module in the shift register corresponding to the first display area is turned on, the output control module in the shift register corresponding to the second display area is turned off in at least some time periods, the first refresh rate is greater than the second refresh rate, the first signal terminal is used to provide an alternating conduction level and a cut-off level, and the second signal terminal is used to provide a cut-off level; The shift register further includes: A first node control module, the input terminal of the first node control module is connected to a start signal terminal, and the output terminal of the first node control module is connected to the first node; A start signal generation unit, including a first auxiliary output module and a second auxiliary output module, wherein, the control terminal of the first auxiliary output module is connected to the first node, the input terminal of the first auxiliary output module is connected to the first signal terminal, the control terminal of the second auxiliary output module is connected to the second node, the input terminal of the second auxiliary output module is connected to the second signal terminal, and the output terminals of the first auxiliary output module and the second auxiliary output module are connected to the auxiliary output terminal of the start signal generation unit; The auxiliary output terminal of the start signal generation unit in the i-th stage shift register serves as the start signal terminal to which the first node control module in the (i + 1)-th stage shift register is connected.

2. The display panel according to claim 1, wherein Both the first auxiliary output module and the first main output module include a transistor controlled by the first node, and both the second auxiliary output module and the second main output module include a transistor controlled by the second node.

3. The display panel according to claim 1, wherein The shift register further includes a first capacitor, one end of the first capacitor is connected to the first node, and the other end is connected to the auxiliary output terminal.

4. The display panel according to claim 1, wherein The shift register further includes a second capacitor, one end of the second capacitor is connected to the second node, and the other end is connected to the second signal terminal.

5. The display panel according to claim 1, characterized in that, The output control module is connected between the first signal terminal and the input terminal of the first main output module; Alternatively, the output control module is connected between the output terminal of the first main output module and the third node; Alternatively, the output control module is connected between the third node and the main output terminal.

6. The display panel according to claim 1, wherein The main output terminal is connected to the pixel circuit of the display panel. The shift register includes a plurality of transistors. The output control module includes a first transistor, and the channel width-to-length ratio of the first transistor is greater than or equal to the channel width-to-length ratio of the other transistors in the shift register.

7. The display panel according to claim 1, characterized in that The output control module includes a first transistor, and the first transistor is turned on or off under the control of a control signal. The first transistor is a P-type transistor, and the sum of the low level of the first signal terminal and the threshold voltage of the first transistor is greater than the conduction level of the control signal. Alternatively, the first transistor is an N-type transistor, and the sum of the high level of the first signal terminal and the threshold voltage of the first transistor is less than the conduction level of the control signal.

8. The display panel according to claim 1, wherein The operation process of the pixel circuit in the display panel includes a data writing sub-frame, and in the data writing sub-frame, the output control module is turned on. The operation process of the pixel circuit in the second display area further includes a holding sub-frame, and in the holding sub-frame, the output control module is turned off.

9. The display panel according to claim 1, wherein The display area includes an edge extending in a first direction. The first display area and the second display area are adjacent in a second direction, and the first direction and the second direction intersect. The working scenarios of the display panel include a first scenario and a second scenario. In the first scenario, the minimum distance between the boundary line of the first display area and the second display area and the edge is d1. In the second scenario, the minimum distance between the boundary line of the first display area and the second display area and the edge is d2, and d1≠d2.

10. The display panel according to any one of claims 1 to 9, characterized in that, The shift register further includes: A second node control module for transmitting the signal received at its input terminal to the second node. A mutual control module for enabling mutual control between the first node and the second node.

11. A display device, characterized in that, A display panel according to any one of claims 1 to 10.

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